4 * $Log: if_edreg.h,v $
5 * Revision 1.5 93/08/25 20:38:34 davidg
6 * added define for card type WD8013WC (10BaseT)
7 *
8 * Revision 1.4 93/08/14 20:07:55 davidg
9 * fix board type definition for 8013EP
10 *
11 * Revision 1.3 93/07/20 15:25:25 davidg
12 * added config flags for forcing 8/16bit mode and disabling double
13 * xmit buffers.
14 *
15 * Revision 1.2 93/06/23 03:03:05 davidg
16 * added some additional definitions for the 83C584 bus interface
17 * chip (SMC/WD boards)
18 *
19 * Revision 1.1 93/06/23 03:01:07 davidg
20 * Initial revision
21 *
22 */
23
24/*
25 * Page 0 register offsets
26 */
27#define ED_P0_CR 0x00 /* Command Register */
28
29#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
30#define ED_P0_PSTART 0x01 /* Page Start register (write) */
31
32#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
33#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
34
35#define ED_P0_BNRY 0x03 /* Boundary Pointer */
36
37#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
38#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
39
40#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
41#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
42
43#define ED_P0_FIFO 0x06 /* FIFO register (read) */
44#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
45
46#define ED_P0_ISR 0x07 /* Interrupt Status Register */
47
48#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
49#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
50
51#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
52#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
53
54#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
55
56#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
57
58#define ED_P0_RSR 0x0c /* Receive Status (read) */
59#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
60
61#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
62#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
63
64#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
65#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
66
67#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
68#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
69
70/*
71 * Page 1 register offsets
72 */
73#define ED_P1_CR 0x00 /* Command Register */
74#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
75#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
76#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
77#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
78#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
79#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
80#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
81#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
82#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
83#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
84#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
85#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
86#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
87#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
88#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
89
90/*
91 * Page 2 register offsets
92 */
93#define ED_P2_CR 0x00 /* Command Register */
94#define ED_P2_PSTART 0x01 /* Page Start (read) */
95#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
96#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
97#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
98#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
99#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
100#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
101#define ED_P2_ACU 0x06 /* Address Counter Upper */
102#define ED_P2_ACL 0x07 /* Address Counter Lower */
103#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
104#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
105#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
106#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
107
108/*
109 * Command Register (CR) definitions
110 */
111
112/*
113 * STP: SToP. Software reset command. Takes the controller offline. No
114 * packets will be received or transmitted. Any reception or
115 * transmission in progress will continue to completion before
116 * entering reset state. To exit this state, the STP bit must
117 * reset and the STA bit must be set. The software reset has
118 * executed only when indicated by the RST bit in the ISR being
119 * set.
120 */
121#define ED_CR_STP 0x01
122
123/*
124 * STA: STArt. This bit is used to activate the NIC after either power-up,
125 * or when the NIC has been put in reset mode by software command
126 * or error.
127 */
128#define ED_CR_STA 0x02
129
130/*
131 * TXP: Transmit Packet. This bit must be set to indicate transmission of
132 * a packet. TXP is internally reset either after the transmission is
133 * completed or aborted. This bit should be set only after the Transmit
134 * Byte Count and Transmit Page Start register have been programmed.
135 */
136#define ED_CR_TXP 0x04
137
138/*
139 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
140 * of the remote DMA channel. RD2 can be set to abort any remote DMA
141 * command in progress. The Remote Byte Count registers should be cleared
142 * when a remote DMA has been aborted. The Remote Start Addresses are not
143 * restored to the starting address if the remote DMA is aborted.
144 *
145 * RD2 RD1 RD0 function
146 * 0 0 0 not allowed
147 * 0 0 1 remote read
148 * 0 1 0 remote write
149 * 0 1 1 send packet
150 * 1 X X abort
151 */
152#define ED_CR_RD0 0x08
153#define ED_CR_RD1 0x10
154#define ED_CR_RD2 0x20
155
156/*
157 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
158 * access.
159 *
160 * PS1 PS0 page
161 * 0 0 0
162 * 0 1 1
163 * 1 0 2
164 * 1 1 reserved
165 */
166#define ED_CR_PS0 0x40
167#define ED_CR_PS1 0x80
168/* bit encoded aliases */
169#define ED_CR_PAGE_0 0x00 /* (for consistency) */
170#define ED_CR_PAGE_1 0x40
171#define ED_CR_PAGE_2 0x80
172
173/*
174 * Interrupt Status Register (ISR) definitions
175 */
176
177/*
178 * PRX: Packet Received. Indicates packet received with no errors.
179 */
180#define ED_ISR_PRX 0x01
181
182/*
183 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
184 */
185#define ED_ISR_PTX 0x02
186
187/*
188 * RXE: Receive Error. Indicates that a packet was received with one or more
189 * the following errors: CRC error, frame alignment error, FIFO overrun,
190 * missed packet.
191 */
192#define ED_ISR_RXE 0x04
193
194/*
195 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
196 * resulted in one or more of the following errors: excessive
197 * collisions, FIFO underrun.
198 */
199#define ED_ISR_TXE 0x08
200
201/*
202 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
203 * would exceed (has exceeded?) the boundry pointer, resulting in data
204 * that was previously received and not yet read from the buffer to be
205 * overwritten.
206 */
207#define ED_ISR_OVW 0x10
208
209/*
210 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
211 * Counters has been set.
212 */
213#define ED_ISR_CNT 0x20
214
215/*
216 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
217 */
218#define ED_ISR_RDC 0x40
219
220/*
221 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
222 * Start Command is issued to the CR. This bit is also set when a receive
223 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
224 * packets have been removed from the ring. This is a read-only bit.
225 */
226#define ED_ISR_RST 0x80
227
228/*
229 * Interrupt Mask Register (IMR) definitions
230 */
231
232/*
233 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
234 * an interrupt.
235 */
236#define ED_IMR_PRXE 0x01
237
238/*
239 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
240 * a packet transmission completes.
241 */
242#define ED_IMR_PTXE 0x02
243
244/*
245 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
246 * packet is received with an error.
247 */
248#define ED_IMR_RXEE 0x04
249
250/*
251 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
252 * a transmission results in an error.
253 */
254#define ED_IMR_TXEE 0x08
255
256/*
257 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
258 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
259 */
260#define ED_IMR_OVWE 0x10
261
262/*
263 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
264 * the MSB of one or more of the Network Statistics counters has been set.
265 */
266#define ED_IMR_CNTE 0x20
267
268/*
269 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
270 * when a remote DMA transfer has completed.
271 */
272#define ED_IMR_RDCE 0x40
273
274/*
275 * bit 7 is unused/reserved
276 */
277
278/*
279 * Data Configuration Register (DCR) definitions
280 */
281
282/*
283 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
284 * both remote and local DMA transfers
285 */
286#define ED_DCR_WTS 0x01
287
288/*
289 * BOS: Byte Order Select. BOS sets the byte order for the host.
290 * Should be 0 for 80x86, and 1 for 68000 series processors
291 */
292#define ED_DCR_BOS 0x02
293
294/*
295 * LAS: Long Address Select. When LAS is 1, the contents of the remote
296 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
297 */
298#define ED_DCR_LAS 0x04
299
300/*
301 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
302 * of the TCR must also be programmed for loopback operation.
303 * When 1, normal operation is selected.
304 */
305#define ED_DCR_LS 0x08
306
307/*
308 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
309 * under program control. When 1, remote DMA is automatically initiated
310 * and the boundry pointer is automatically updated
311 */
312#define ED_DCR_AR 0x10
313
314/*
315 * FT0, FT1: Fifo Threshold select.
316 * FT1 FT0 Word-width Byte-width
317 * 0 0 1 word 2 bytes
318 * 0 1 2 words 4 bytes
319 * 1 0 4 words 8 bytes
320 * 1 1 8 words 12 bytes
321 *
322 * During transmission, the FIFO threshold indicates the number of bytes
323 * or words that the FIFO has filled from the local DMA before BREQ is
324 * asserted. The transmission threshold is 16 bytes minus the receiver
325 * threshold.
326 */
327#define ED_DCR_FT0 0x20
328#define ED_DCR_FT1 0x40
329
330/*
331 * bit 7 (0x80) is unused/reserved
332 */
333
334/*
335 * Transmit Configuration Register (TCR) definitions
336 */
337
338/*
339 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
340 * is not appended by the transmitter.
341 */
342#define ED_TCR_CRC 0x01
343
344/*
345 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
346 * to be performed.
347 *
348 * LB1 LB0 mode
349 * 0 0 0 - normal operation (DCR_LS = 0)
350 * 0 1 1 - internal loopback (DCR_LS = 0)
351 * 1 0 2 - external loopback (DCR_LS = 1)
352 * 1 1 3 - external loopback (DCR_LS = 0)
353 */
354#define ED_TCR_LB0 0x02
355#define ED_TCR_LB1 0x04
356
357/*
358 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
359 * another station to disable the NIC's transmitter by transmitting to
360 * a multicast address hashing to bit 62. Reception of a multicast address
361 * hashing to bit 63 enables the transmitter.
362 */
363#define ED_TCR_ATD 0x08
364
365/*
366 * OFST: Collision Offset enable. This bit when set modifies the backoff
367 * algorithm to allow prioritization of nodes.
368 */
369#define ED_TCR_OFST 0x10
370
371/*
372 * bits 5, 6, and 7 are unused/reserved
373 */
374
375/*
376 * Transmit Status Register (TSR) definitions
377 */
378
379/*
380 * PTX: Packet Transmitted. Indicates successful transmission of packet.
381 */
382#define ED_TSR_PTX 0x01
383
384/*
385 * bit 1 (0x02) is unused/reserved
386 */
387
388/*
389 * COL: Transmit Collided. Indicates that the transmission collided at least
390 * once with another station on the network.
391 */
392#define ED_TSR_COL 0x04
393
394/*
395 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
396 * excessive collisions.
397 */
398#define ED_TSR_ABT 0x08
399
400/*
401 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
402 * transmission of the packet. (Transmission is not aborted because
403 * of a loss of carrier)
404 */
405#define ED_TSR_CRS 0x10
406
407/*
408 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
409 * transmission memory before the FIFO emptied. Transmission of the
410 * packet was aborted.
411 */
412#define ED_TSR_FU 0x20
413
414/*
415 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
416 * isn't working correctly during a collision heartbeat test.
417 */
418#define ED_TSR_CDH 0x40
419
420/*
421 * OWC: Out of Window Collision: Indicates that a collision occurred after
422 * a slot time (51.2us). The transmission is rescheduled just as in
423 * normal collisions.
424 */
425#define ED_TSR_OWC 0x80
426
427/*
428 * Receiver Configuration Register (RCR) definitions
429 */
430
431/*
432 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
433 * packets with CRC and frame errors are not discarded.
434 */
435#define ED_RCR_SEP 0x01
436
437/*
438 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
439 * If set to 1, packets with less than 64 byte are not discarded.
440 */
441#define ED_RCR_AR 0x02
442
443/*
444 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
445 * accepted.
446 */
447#define ED_RCR_AB 0x04
448
449/*
450 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
451 * for a match in the hashing array. If clear, multicast packets are ignored.
452 */
453#define ED_RCR_AM 0x08
454
455/*
456 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
457 * accepted. If clear, a physical destination address must match this
458 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
459 * must also be set. In addition, the multicast hashing array must be set
460 * to all 1's so that all multicast addresses are accepted.
461 */
462#define ED_RCR_PRO 0x10
463
464/*
465 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
466 * but are not stored in the ring-buffer. If clear, packets are stored (normal
467 * operation).
468 */
469#define ED_RCR_MON 0x20
470
471/*
472 * bits 6 and 7 are unused/reserved.
473 */
474
475/*
476 * Receiver Status Register (RSR) definitions
477 */
478
479/*
480 * PRX: Packet Received without error.
481 */
482#define ED_RSR_PRX 0x01
483
484/*
485 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
486 * alignment errors.
487 */
488#define ED_RSR_CRC 0x02
489
490/*
491 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
492 * a byte boundry and the CRC did not match at the last byte boundry.
493 */
494#define ED_RSR_FAE 0x04
495
496/*
497 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
498 * causing it to overrun. Reception of the packet is aborted.
499 */
500#define ED_RSR_FO 0x08
501
502/*
503 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
504 * the ring-buffer because of insufficient buffer space (exceeding the
505 * boundry pointer), or because the transfer to the ring-buffer was inhibited
506 * by RCR_MON - monitor mode.
507 */
508#define ED_RSR_MPA 0x10
509
510/*
511 * PHY: Physical address. If 0, the packet received was sent to a physical address.
512 * If 1, the packet was accepted because of a multicast/broadcast address
513 * match.
514 */
515#define ED_RSR_PHY 0x20
516
517/*
518 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
519 * mode. Cleared when the receiver exits monitor mode.
520 */
521#define ED_RSR_DIS 0x40
522
523/*
524 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
525 * are active, and the transceiver has set the CD line as a result of the
526 * jabber.
527 */
528#define ED_RSR_DFR 0x80
529
530/*
531 * receive ring discriptor
532 *
533 * The National Semiconductor DS8390 Network interface controller uses
534 * the following receive ring headers. The way this works is that the
535 * memory on the interface card is chopped up into 256 bytes blocks.
536 * A contiguous portion of those blocks are marked for receive packets
537 * by setting start and end block #'s in the NIC. For each packet that
538 * is put into the receive ring, one of these headers (4 bytes each) is
539 * tacked onto the front.
540 */
541struct ed_ring {
542 struct edr_status { /* received packet status */
543 u_char rs_prx:1, /* packet received intack */
544 rs_crc:1, /* crc error */
545 rs_fae:1, /* frame alignment error */
546 rs_fo:1, /* fifo overrun */
547 rs_mpa:1, /* packet received intack */
548 rs_phy:1, /* packet received intack */
549 rs_dis:1, /* packet received intack */
550 rs_dfr:1; /* packet received intack */
551 } ed_rcv_status; /* received packet status */
552 u_char next_packet; /* pointer to next packet */
553 u_short count; /* bytes in packet (length + 4) */
554};
555
556/*
557 * Common constants
558 */
559#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
560#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
561
562/*
563 * Vendor types
564 */
565#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
566#define ED_VENDOR_3COM 0x01 /* 3Com */
567
568/*
569 * Compile-time config flags
570 */
571/*
572 * this sets the default for enabling/disablng the tranceiver
573 */
574#define ED_FLAGS_DISABLE_TRANCEIVER 0x01
575
576/*
577 * This forces the board to be used in 8/16bit mode even if it
578 * autoconfigs differently
579 */
580#define ED_FLAGS_FORCE_8BIT_MODE 0x02
581#define ED_FLAGS_FORCE_16BIT_MODE 0x04
582
583/*
584 * This disables the use of double transmit buffers.
585 */
586#define ED_FLAGS_NO_DOUBLE_BUFFERING 0x08
587
588/*
589 * Definitions for Western digital/SMC WD80x3 series ASIC
590 */
591/*
592 * Memory Select Register (MSR)
593 */
594#define ED_WD_MSR 0
595
596#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
597#define ED_WD_MSR_MENB 0x40 /* Memory enable */
598#define ED_WD_MSR_RST 0x80 /* Reset board */
599
600/*
601 * Interface Configuration Register (ICR)
602 */
603#define ED_WD_ICR 1
604
605#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
606#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
607#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
608#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
609#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
610#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
611#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
612#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
613
614/*
615 * IO Address Register (IAR)
616 */
617#define ED_WD_IAR 2
618
619/*
620 * EEROM Address Register
621 */
622#define ED_WD_EAR 3
623
624/*
625 * Interrupt Request Register (IRR)
626 */
627#define ED_WD_IRR 4
628
629#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
630#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
631#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
632#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
633#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
634
635/*
636 * The three bit of the encoded IRQ are decoded as follows:
637 *
638 * IR2 IR1 IR0 IRQ
639 * 0 0 0 2/9
640 * 0 0 1 3
641 * 0 1 0 5
642 * 0 1 1 7
643 * 1 0 0 10
644 * 1 0 1 11
645 * 1 1 0 15
646 * 1 1 1 4
647 */
648#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
649#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
650#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
651
652/*
653 * LA Address Register (LAAR)
654 */
655#define ED_WD_LAAR 5
656
657#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
658#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
659#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
660#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
661
662/* i/o base offset to station address/card-ID PROM */
663#define ED_WD_PROM 8
664
665/* i/o base offset to CARD ID */
666#define ED_WD_CARD_ID ED_WD_PROM+6
667
668#define ED_TYPE_WD8003S 0x02
669#define ED_TYPE_WD8003E 0x03
670#define ED_TYPE_WD8013EBT 0x05
671#define ED_TYPE_WD8013EP 0x27
672#define ED_TYPE_WD8013WC 0x28
673#define ED_TYPE_WD8013EBP 0x2c
674#define ED_TYPE_WD8013EPC 0x29
675
676/* Bit definitions in card ID */
677#define ED_WD_REV_MASK 0x1f /* Revision mask */
678#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
679#define ED_WD_LARGERAM 0x40 /* Large RAM */
680#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
681
682/*
683 * Checksum total. All 8 bytes in station address PROM will add up to this
684 */
685#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
686
687#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
688#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
689#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
690
691#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
692
693/*
694 * Definitions for 3Com 3c503
695 */
696#define ED_3COM_NIC_OFFSET 0
697#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
698
699/*
700 * XXX - The I/O address range is fragmented in the 3c503; this is the
701 * number of regs at iobase.
702 */
703#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
704
705#define ED_3COM_PAGE_OFFSET 0x20 /* memory starts in second bank */
706
707/*
708 * Page Start Register. Must match PSTART in NIC
709 */
710#define ED_3COM_PSTR 0
711
712/*
713 * Page Stop Register. Must match PSTOP in NIC
714 */
715#define ED_3COM_PSPR 1
716
717/*
718 * Drq Timer Register. Determines number of bytes to be transfered during
719 * a DMA burst.
720 */
721#define ED_3COM_DQTR 2
722
723/*
724 * Base Configuration Register. Read-only register which contains the
725 * board-configured I/O base address of the adapter. Bit encoded.
726 */
727#define ED_3COM_BCFR 3
728
729#define ED_3COM_BCFR_2E0 0x01
730#define ED_3COM_BCFR_2A0 0x02
731#define ED_3COM_BCFR_280 0x04
732#define ED_3COM_BCFR_250 0x08
733#define ED_3COM_BCFR_350 0x10
734#define ED_3COM_BCFR_330 0x20
735#define ED_3COM_BCFR_310 0x40
736#define ED_3COM_BCFR_300 0x80
737
738/*
739 * EPROM Configuration Register. Read-only register which contains the
740 * board-configured memory base address. Bit encoded.
741 */
742#define ED_3COM_PCFR 4
743
744#define ED_3COM_PCFR_C8000 0x10
745#define ED_3COM_PCFR_CC000 0x20
746#define ED_3COM_PCFR_D8000 0x40
747#define ED_3COM_PCFR_DC000 0x80
748
749/*
750 * GA Configuration Register. Gate-Array Configuration Register.
751 */
752#define ED_3COM_GACFR 5
753
754/*
755 * mbs2 mbs1 mbs0 start address
756 * 0 0 0 0x0000
757 * 0 0 1 0x2000
758 * 0 1 0 0x4000
759 * 0 1 1 0x6000
760 *
761 * Note that with adapters with only 8K, the setting for 0x2000 must
762 * always be used.
763 */
764#define ED_3COM_GACFR_MBS0 0x01
765#define ED_3COM_GACFR_MBS1 0x02
766#define ED_3COM_GACFR_MBS2 0x04
767
768#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
769#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
770#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
771#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
772#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
773
774/*
775 * Control Register. Miscellaneous control functions.
776 */
777#define ED_3COM_CR 6
778
779#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
780#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
781#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
782#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
783#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
784#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
785#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
786#define ED_3COM_CR_START 0x80 /* Start DMA controller */
787
788/*
789 * Status Register. Miscellaneous status information.
790 */
791#define ED_3COM_STREG 7
792
793#define ED_3COM_STREG_REV 0x07 /* GA revision */
794#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
795#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
796#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
797#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
798#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
799
800/*
801 * Interrupt/DMA Configuration Register
802 */
803#define ED_3COM_IDCFR 8
804
805#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
806#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
807#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
808#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
809#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
810#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
811#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
812#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
813
814/*
815 * DMA Address Register MSB
816 */
817#define ED_3COM_DAMSB 9
818
819/*
820 * DMA Address Register LSB
821 */
822#define ED_3COM_DALSB 0x0a
823
824/*
825 * Vector Pointer Register 2
826 */
827#define ED_3COM_VPTR2 0x0b
828
829/*
830 * Vector Pointer Register 1
831 */
832#define ED_3COM_VPTR1 0x0c
833
834/*
835 * Vector Pointer Register 0
836 */
837#define ED_3COM_VPTR0 0x0d
838
839/*
840 * Register File Access MSB
841 */
842#define ED_3COM_RFMSB 0x0e
843
844/*
845 * Register File Access LSB
846 */
847#define ED_3COM_RFLSB 0x0f
| 8 * $Log: if_edreg.h,v $
9 * Revision 1.5 93/08/25 20:38:34 davidg
10 * added define for card type WD8013WC (10BaseT)
11 *
12 * Revision 1.4 93/08/14 20:07:55 davidg
13 * fix board type definition for 8013EP
14 *
15 * Revision 1.3 93/07/20 15:25:25 davidg
16 * added config flags for forcing 8/16bit mode and disabling double
17 * xmit buffers.
18 *
19 * Revision 1.2 93/06/23 03:03:05 davidg
20 * added some additional definitions for the 83C584 bus interface
21 * chip (SMC/WD boards)
22 *
23 * Revision 1.1 93/06/23 03:01:07 davidg
24 * Initial revision
25 *
26 */
27
28/*
29 * Page 0 register offsets
30 */
31#define ED_P0_CR 0x00 /* Command Register */
32
33#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
34#define ED_P0_PSTART 0x01 /* Page Start register (write) */
35
36#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
37#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
38
39#define ED_P0_BNRY 0x03 /* Boundary Pointer */
40
41#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
42#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
43
44#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
45#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
46
47#define ED_P0_FIFO 0x06 /* FIFO register (read) */
48#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
49
50#define ED_P0_ISR 0x07 /* Interrupt Status Register */
51
52#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
53#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
54
55#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
56#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
57
58#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
59
60#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
61
62#define ED_P0_RSR 0x0c /* Receive Status (read) */
63#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
64
65#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
66#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
67
68#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
69#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
70
71#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
72#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
73
74/*
75 * Page 1 register offsets
76 */
77#define ED_P1_CR 0x00 /* Command Register */
78#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
79#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
80#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
81#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
82#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
83#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
84#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
85#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
86#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
87#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
88#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
89#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
90#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
91#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
92#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
93
94/*
95 * Page 2 register offsets
96 */
97#define ED_P2_CR 0x00 /* Command Register */
98#define ED_P2_PSTART 0x01 /* Page Start (read) */
99#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
100#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
101#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
102#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
103#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
104#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
105#define ED_P2_ACU 0x06 /* Address Counter Upper */
106#define ED_P2_ACL 0x07 /* Address Counter Lower */
107#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
108#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
109#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
110#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
111
112/*
113 * Command Register (CR) definitions
114 */
115
116/*
117 * STP: SToP. Software reset command. Takes the controller offline. No
118 * packets will be received or transmitted. Any reception or
119 * transmission in progress will continue to completion before
120 * entering reset state. To exit this state, the STP bit must
121 * reset and the STA bit must be set. The software reset has
122 * executed only when indicated by the RST bit in the ISR being
123 * set.
124 */
125#define ED_CR_STP 0x01
126
127/*
128 * STA: STArt. This bit is used to activate the NIC after either power-up,
129 * or when the NIC has been put in reset mode by software command
130 * or error.
131 */
132#define ED_CR_STA 0x02
133
134/*
135 * TXP: Transmit Packet. This bit must be set to indicate transmission of
136 * a packet. TXP is internally reset either after the transmission is
137 * completed or aborted. This bit should be set only after the Transmit
138 * Byte Count and Transmit Page Start register have been programmed.
139 */
140#define ED_CR_TXP 0x04
141
142/*
143 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
144 * of the remote DMA channel. RD2 can be set to abort any remote DMA
145 * command in progress. The Remote Byte Count registers should be cleared
146 * when a remote DMA has been aborted. The Remote Start Addresses are not
147 * restored to the starting address if the remote DMA is aborted.
148 *
149 * RD2 RD1 RD0 function
150 * 0 0 0 not allowed
151 * 0 0 1 remote read
152 * 0 1 0 remote write
153 * 0 1 1 send packet
154 * 1 X X abort
155 */
156#define ED_CR_RD0 0x08
157#define ED_CR_RD1 0x10
158#define ED_CR_RD2 0x20
159
160/*
161 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
162 * access.
163 *
164 * PS1 PS0 page
165 * 0 0 0
166 * 0 1 1
167 * 1 0 2
168 * 1 1 reserved
169 */
170#define ED_CR_PS0 0x40
171#define ED_CR_PS1 0x80
172/* bit encoded aliases */
173#define ED_CR_PAGE_0 0x00 /* (for consistency) */
174#define ED_CR_PAGE_1 0x40
175#define ED_CR_PAGE_2 0x80
176
177/*
178 * Interrupt Status Register (ISR) definitions
179 */
180
181/*
182 * PRX: Packet Received. Indicates packet received with no errors.
183 */
184#define ED_ISR_PRX 0x01
185
186/*
187 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
188 */
189#define ED_ISR_PTX 0x02
190
191/*
192 * RXE: Receive Error. Indicates that a packet was received with one or more
193 * the following errors: CRC error, frame alignment error, FIFO overrun,
194 * missed packet.
195 */
196#define ED_ISR_RXE 0x04
197
198/*
199 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
200 * resulted in one or more of the following errors: excessive
201 * collisions, FIFO underrun.
202 */
203#define ED_ISR_TXE 0x08
204
205/*
206 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
207 * would exceed (has exceeded?) the boundry pointer, resulting in data
208 * that was previously received and not yet read from the buffer to be
209 * overwritten.
210 */
211#define ED_ISR_OVW 0x10
212
213/*
214 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
215 * Counters has been set.
216 */
217#define ED_ISR_CNT 0x20
218
219/*
220 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
221 */
222#define ED_ISR_RDC 0x40
223
224/*
225 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
226 * Start Command is issued to the CR. This bit is also set when a receive
227 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
228 * packets have been removed from the ring. This is a read-only bit.
229 */
230#define ED_ISR_RST 0x80
231
232/*
233 * Interrupt Mask Register (IMR) definitions
234 */
235
236/*
237 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
238 * an interrupt.
239 */
240#define ED_IMR_PRXE 0x01
241
242/*
243 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
244 * a packet transmission completes.
245 */
246#define ED_IMR_PTXE 0x02
247
248/*
249 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
250 * packet is received with an error.
251 */
252#define ED_IMR_RXEE 0x04
253
254/*
255 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
256 * a transmission results in an error.
257 */
258#define ED_IMR_TXEE 0x08
259
260/*
261 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
262 * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
263 */
264#define ED_IMR_OVWE 0x10
265
266/*
267 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
268 * the MSB of one or more of the Network Statistics counters has been set.
269 */
270#define ED_IMR_CNTE 0x20
271
272/*
273 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
274 * when a remote DMA transfer has completed.
275 */
276#define ED_IMR_RDCE 0x40
277
278/*
279 * bit 7 is unused/reserved
280 */
281
282/*
283 * Data Configuration Register (DCR) definitions
284 */
285
286/*
287 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
288 * both remote and local DMA transfers
289 */
290#define ED_DCR_WTS 0x01
291
292/*
293 * BOS: Byte Order Select. BOS sets the byte order for the host.
294 * Should be 0 for 80x86, and 1 for 68000 series processors
295 */
296#define ED_DCR_BOS 0x02
297
298/*
299 * LAS: Long Address Select. When LAS is 1, the contents of the remote
300 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
301 */
302#define ED_DCR_LAS 0x04
303
304/*
305 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
306 * of the TCR must also be programmed for loopback operation.
307 * When 1, normal operation is selected.
308 */
309#define ED_DCR_LS 0x08
310
311/*
312 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
313 * under program control. When 1, remote DMA is automatically initiated
314 * and the boundry pointer is automatically updated
315 */
316#define ED_DCR_AR 0x10
317
318/*
319 * FT0, FT1: Fifo Threshold select.
320 * FT1 FT0 Word-width Byte-width
321 * 0 0 1 word 2 bytes
322 * 0 1 2 words 4 bytes
323 * 1 0 4 words 8 bytes
324 * 1 1 8 words 12 bytes
325 *
326 * During transmission, the FIFO threshold indicates the number of bytes
327 * or words that the FIFO has filled from the local DMA before BREQ is
328 * asserted. The transmission threshold is 16 bytes minus the receiver
329 * threshold.
330 */
331#define ED_DCR_FT0 0x20
332#define ED_DCR_FT1 0x40
333
334/*
335 * bit 7 (0x80) is unused/reserved
336 */
337
338/*
339 * Transmit Configuration Register (TCR) definitions
340 */
341
342/*
343 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
344 * is not appended by the transmitter.
345 */
346#define ED_TCR_CRC 0x01
347
348/*
349 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
350 * to be performed.
351 *
352 * LB1 LB0 mode
353 * 0 0 0 - normal operation (DCR_LS = 0)
354 * 0 1 1 - internal loopback (DCR_LS = 0)
355 * 1 0 2 - external loopback (DCR_LS = 1)
356 * 1 1 3 - external loopback (DCR_LS = 0)
357 */
358#define ED_TCR_LB0 0x02
359#define ED_TCR_LB1 0x04
360
361/*
362 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
363 * another station to disable the NIC's transmitter by transmitting to
364 * a multicast address hashing to bit 62. Reception of a multicast address
365 * hashing to bit 63 enables the transmitter.
366 */
367#define ED_TCR_ATD 0x08
368
369/*
370 * OFST: Collision Offset enable. This bit when set modifies the backoff
371 * algorithm to allow prioritization of nodes.
372 */
373#define ED_TCR_OFST 0x10
374
375/*
376 * bits 5, 6, and 7 are unused/reserved
377 */
378
379/*
380 * Transmit Status Register (TSR) definitions
381 */
382
383/*
384 * PTX: Packet Transmitted. Indicates successful transmission of packet.
385 */
386#define ED_TSR_PTX 0x01
387
388/*
389 * bit 1 (0x02) is unused/reserved
390 */
391
392/*
393 * COL: Transmit Collided. Indicates that the transmission collided at least
394 * once with another station on the network.
395 */
396#define ED_TSR_COL 0x04
397
398/*
399 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
400 * excessive collisions.
401 */
402#define ED_TSR_ABT 0x08
403
404/*
405 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
406 * transmission of the packet. (Transmission is not aborted because
407 * of a loss of carrier)
408 */
409#define ED_TSR_CRS 0x10
410
411/*
412 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
413 * transmission memory before the FIFO emptied. Transmission of the
414 * packet was aborted.
415 */
416#define ED_TSR_FU 0x20
417
418/*
419 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
420 * isn't working correctly during a collision heartbeat test.
421 */
422#define ED_TSR_CDH 0x40
423
424/*
425 * OWC: Out of Window Collision: Indicates that a collision occurred after
426 * a slot time (51.2us). The transmission is rescheduled just as in
427 * normal collisions.
428 */
429#define ED_TSR_OWC 0x80
430
431/*
432 * Receiver Configuration Register (RCR) definitions
433 */
434
435/*
436 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
437 * packets with CRC and frame errors are not discarded.
438 */
439#define ED_RCR_SEP 0x01
440
441/*
442 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
443 * If set to 1, packets with less than 64 byte are not discarded.
444 */
445#define ED_RCR_AR 0x02
446
447/*
448 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
449 * accepted.
450 */
451#define ED_RCR_AB 0x04
452
453/*
454 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
455 * for a match in the hashing array. If clear, multicast packets are ignored.
456 */
457#define ED_RCR_AM 0x08
458
459/*
460 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
461 * accepted. If clear, a physical destination address must match this
462 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
463 * must also be set. In addition, the multicast hashing array must be set
464 * to all 1's so that all multicast addresses are accepted.
465 */
466#define ED_RCR_PRO 0x10
467
468/*
469 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
470 * but are not stored in the ring-buffer. If clear, packets are stored (normal
471 * operation).
472 */
473#define ED_RCR_MON 0x20
474
475/*
476 * bits 6 and 7 are unused/reserved.
477 */
478
479/*
480 * Receiver Status Register (RSR) definitions
481 */
482
483/*
484 * PRX: Packet Received without error.
485 */
486#define ED_RSR_PRX 0x01
487
488/*
489 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
490 * alignment errors.
491 */
492#define ED_RSR_CRC 0x02
493
494/*
495 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
496 * a byte boundry and the CRC did not match at the last byte boundry.
497 */
498#define ED_RSR_FAE 0x04
499
500/*
501 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
502 * causing it to overrun. Reception of the packet is aborted.
503 */
504#define ED_RSR_FO 0x08
505
506/*
507 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
508 * the ring-buffer because of insufficient buffer space (exceeding the
509 * boundry pointer), or because the transfer to the ring-buffer was inhibited
510 * by RCR_MON - monitor mode.
511 */
512#define ED_RSR_MPA 0x10
513
514/*
515 * PHY: Physical address. If 0, the packet received was sent to a physical address.
516 * If 1, the packet was accepted because of a multicast/broadcast address
517 * match.
518 */
519#define ED_RSR_PHY 0x20
520
521/*
522 * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
523 * mode. Cleared when the receiver exits monitor mode.
524 */
525#define ED_RSR_DIS 0x40
526
527/*
528 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
529 * are active, and the transceiver has set the CD line as a result of the
530 * jabber.
531 */
532#define ED_RSR_DFR 0x80
533
534/*
535 * receive ring discriptor
536 *
537 * The National Semiconductor DS8390 Network interface controller uses
538 * the following receive ring headers. The way this works is that the
539 * memory on the interface card is chopped up into 256 bytes blocks.
540 * A contiguous portion of those blocks are marked for receive packets
541 * by setting start and end block #'s in the NIC. For each packet that
542 * is put into the receive ring, one of these headers (4 bytes each) is
543 * tacked onto the front.
544 */
545struct ed_ring {
546 struct edr_status { /* received packet status */
547 u_char rs_prx:1, /* packet received intack */
548 rs_crc:1, /* crc error */
549 rs_fae:1, /* frame alignment error */
550 rs_fo:1, /* fifo overrun */
551 rs_mpa:1, /* packet received intack */
552 rs_phy:1, /* packet received intack */
553 rs_dis:1, /* packet received intack */
554 rs_dfr:1; /* packet received intack */
555 } ed_rcv_status; /* received packet status */
556 u_char next_packet; /* pointer to next packet */
557 u_short count; /* bytes in packet (length + 4) */
558};
559
560/*
561 * Common constants
562 */
563#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
564#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
565
566/*
567 * Vendor types
568 */
569#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
570#define ED_VENDOR_3COM 0x01 /* 3Com */
571
572/*
573 * Compile-time config flags
574 */
575/*
576 * this sets the default for enabling/disablng the tranceiver
577 */
578#define ED_FLAGS_DISABLE_TRANCEIVER 0x01
579
580/*
581 * This forces the board to be used in 8/16bit mode even if it
582 * autoconfigs differently
583 */
584#define ED_FLAGS_FORCE_8BIT_MODE 0x02
585#define ED_FLAGS_FORCE_16BIT_MODE 0x04
586
587/*
588 * This disables the use of double transmit buffers.
589 */
590#define ED_FLAGS_NO_DOUBLE_BUFFERING 0x08
591
592/*
593 * Definitions for Western digital/SMC WD80x3 series ASIC
594 */
595/*
596 * Memory Select Register (MSR)
597 */
598#define ED_WD_MSR 0
599
600#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
601#define ED_WD_MSR_MENB 0x40 /* Memory enable */
602#define ED_WD_MSR_RST 0x80 /* Reset board */
603
604/*
605 * Interface Configuration Register (ICR)
606 */
607#define ED_WD_ICR 1
608
609#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
610#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
611#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
612#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
613#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
614#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
615#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
616#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
617
618/*
619 * IO Address Register (IAR)
620 */
621#define ED_WD_IAR 2
622
623/*
624 * EEROM Address Register
625 */
626#define ED_WD_EAR 3
627
628/*
629 * Interrupt Request Register (IRR)
630 */
631#define ED_WD_IRR 4
632
633#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
634#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
635#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
636#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
637#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
638
639/*
640 * The three bit of the encoded IRQ are decoded as follows:
641 *
642 * IR2 IR1 IR0 IRQ
643 * 0 0 0 2/9
644 * 0 0 1 3
645 * 0 1 0 5
646 * 0 1 1 7
647 * 1 0 0 10
648 * 1 0 1 11
649 * 1 1 0 15
650 * 1 1 1 4
651 */
652#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
653#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
654#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
655
656/*
657 * LA Address Register (LAAR)
658 */
659#define ED_WD_LAAR 5
660
661#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
662#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
663#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
664#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
665
666/* i/o base offset to station address/card-ID PROM */
667#define ED_WD_PROM 8
668
669/* i/o base offset to CARD ID */
670#define ED_WD_CARD_ID ED_WD_PROM+6
671
672#define ED_TYPE_WD8003S 0x02
673#define ED_TYPE_WD8003E 0x03
674#define ED_TYPE_WD8013EBT 0x05
675#define ED_TYPE_WD8013EP 0x27
676#define ED_TYPE_WD8013WC 0x28
677#define ED_TYPE_WD8013EBP 0x2c
678#define ED_TYPE_WD8013EPC 0x29
679
680/* Bit definitions in card ID */
681#define ED_WD_REV_MASK 0x1f /* Revision mask */
682#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
683#define ED_WD_LARGERAM 0x40 /* Large RAM */
684#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
685
686/*
687 * Checksum total. All 8 bytes in station address PROM will add up to this
688 */
689#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
690
691#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
692#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
693#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
694
695#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
696
697/*
698 * Definitions for 3Com 3c503
699 */
700#define ED_3COM_NIC_OFFSET 0
701#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
702
703/*
704 * XXX - The I/O address range is fragmented in the 3c503; this is the
705 * number of regs at iobase.
706 */
707#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
708
709#define ED_3COM_PAGE_OFFSET 0x20 /* memory starts in second bank */
710
711/*
712 * Page Start Register. Must match PSTART in NIC
713 */
714#define ED_3COM_PSTR 0
715
716/*
717 * Page Stop Register. Must match PSTOP in NIC
718 */
719#define ED_3COM_PSPR 1
720
721/*
722 * Drq Timer Register. Determines number of bytes to be transfered during
723 * a DMA burst.
724 */
725#define ED_3COM_DQTR 2
726
727/*
728 * Base Configuration Register. Read-only register which contains the
729 * board-configured I/O base address of the adapter. Bit encoded.
730 */
731#define ED_3COM_BCFR 3
732
733#define ED_3COM_BCFR_2E0 0x01
734#define ED_3COM_BCFR_2A0 0x02
735#define ED_3COM_BCFR_280 0x04
736#define ED_3COM_BCFR_250 0x08
737#define ED_3COM_BCFR_350 0x10
738#define ED_3COM_BCFR_330 0x20
739#define ED_3COM_BCFR_310 0x40
740#define ED_3COM_BCFR_300 0x80
741
742/*
743 * EPROM Configuration Register. Read-only register which contains the
744 * board-configured memory base address. Bit encoded.
745 */
746#define ED_3COM_PCFR 4
747
748#define ED_3COM_PCFR_C8000 0x10
749#define ED_3COM_PCFR_CC000 0x20
750#define ED_3COM_PCFR_D8000 0x40
751#define ED_3COM_PCFR_DC000 0x80
752
753/*
754 * GA Configuration Register. Gate-Array Configuration Register.
755 */
756#define ED_3COM_GACFR 5
757
758/*
759 * mbs2 mbs1 mbs0 start address
760 * 0 0 0 0x0000
761 * 0 0 1 0x2000
762 * 0 1 0 0x4000
763 * 0 1 1 0x6000
764 *
765 * Note that with adapters with only 8K, the setting for 0x2000 must
766 * always be used.
767 */
768#define ED_3COM_GACFR_MBS0 0x01
769#define ED_3COM_GACFR_MBS1 0x02
770#define ED_3COM_GACFR_MBS2 0x04
771
772#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
773#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
774#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
775#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
776#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
777
778/*
779 * Control Register. Miscellaneous control functions.
780 */
781#define ED_3COM_CR 6
782
783#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
784#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
785#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
786#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
787#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
788#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
789#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
790#define ED_3COM_CR_START 0x80 /* Start DMA controller */
791
792/*
793 * Status Register. Miscellaneous status information.
794 */
795#define ED_3COM_STREG 7
796
797#define ED_3COM_STREG_REV 0x07 /* GA revision */
798#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
799#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
800#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
801#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
802#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
803
804/*
805 * Interrupt/DMA Configuration Register
806 */
807#define ED_3COM_IDCFR 8
808
809#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
810#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
811#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
812#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
813#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
814#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
815#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
816#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
817
818/*
819 * DMA Address Register MSB
820 */
821#define ED_3COM_DAMSB 9
822
823/*
824 * DMA Address Register LSB
825 */
826#define ED_3COM_DALSB 0x0a
827
828/*
829 * Vector Pointer Register 2
830 */
831#define ED_3COM_VPTR2 0x0b
832
833/*
834 * Vector Pointer Register 1
835 */
836#define ED_3COM_VPTR1 0x0c
837
838/*
839 * Vector Pointer Register 0
840 */
841#define ED_3COM_VPTR0 0x0d
842
843/*
844 * Register File Access MSB
845 */
846#define ED_3COM_RFMSB 0x0e
847
848/*
849 * Register File Access LSB
850 */
851#define ED_3COM_RFLSB 0x0f
|