381 case ED_TYPE_WD8013EP: /* also WD8003EP */
382 if (inb(sc->asic_addr + ED_WD_ICR)
383 & ED_WD_ICR_16BIT) {
384 isa16bit = 1;
385 memsize = 16384;
386 sc->type_str = "WD8013EP";
387 } else {
388 isa16bit = 0;
389 memsize = 8192;
390 sc->type_str = "WD8003EP";
391 }
392 break;
393 case ED_TYPE_WD8013WC:
394 sc->type_str = "WD8013WC";
395 memsize = 16384;
396 isa16bit = 1;
397 break;
398 case ED_TYPE_WD8013EBP:
399 sc->type_str = "WD8013EBP";
400 memsize = 16384;
401 isa16bit = 1;
402 break;
403 case ED_TYPE_WD8013EPC:
404 sc->type_str = "WD8013EPC";
405 memsize = 16384;
406 isa16bit = 1;
407 break;
408 case ED_TYPE_SMC8216C:
409 sc->type_str = "SMC8216/SMC8216C";
410 memsize = 16384;
411 isa16bit = 1;
412 sc->is790 = 1;
413 break;
414 case ED_TYPE_SMC8216T:
415 sc->type_str = "SMC8216T";
416 memsize = 16384;
417 isa16bit = 1;
418 sc->is790 = 1;
419 break;
420 default:
421 sc->type_str = "";
422 memsize = 8192;
423 isa16bit = 0;
424 break;
425 }
426 /*
427 * Make some adjustments to initial values depending on what is
428 * found in the ICR.
429 */
430 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
431 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
432 isa16bit = 0;
433 memsize = 8192;
434 }
435
436#if ED_DEBUG
437 printf("type=%s isa16bit=%d memsize=%d id_msize=%d\n",
438 sc->type_str,isa16bit,memsize,isa_dev->id_msize);
439 for (i=0; i<8; i++)
440 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
441#endif
442 /*
443 * Allow the user to override the autoconfiguration
444 */
445 if (isa_dev->id_msize)
446 memsize = isa_dev->id_msize;
447 /*
448 * (note that if the user specifies both of the following flags
449 * that '8bit' mode intentionally has precedence)
450 */
451 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
452 isa16bit = 1;
453 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
454 isa16bit = 0;
455
456 /*
457 * Check 83C584 interrupt configuration register if this board has one
458 * XXX - we could also check the IO address register. But why
459 * bother...if we get past this, it *has* to be correct.
460 */
461 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
462 /*
463 * Assemble together the encoded interrupt number.
464 */
465 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
466 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
467 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
468 /*
469 * Translate it using translation table, and check for correctness.
470 */
471 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
472 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
473 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
474 return(0);
475 }
476 /*
477 * Enable the interrupt.
478 */
479 outb(isa_dev->id_iobase + ED_WD_IRR,
480 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
481 }
482 if (sc->is790) {
483 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
484 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
485 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
486 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
487
488 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
489 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
490 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
491 return 0;
492 }
493 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
494 }
495
496 sc->isa16bit = isa16bit;
497
498#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
499 /*
500 * The following allows the WD/SMC boards to be used in Programmed I/O
501 * mode - without mapping the NIC memory shared. ...Not the prefered
502 * way, but it might be the only way.
503 */
504 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
505 sc->mem_shared = 0;
506 isa_dev->id_maddr = 0;
507 } else {
508 sc->mem_shared = 1;
509 }
510#else
511 sc->mem_shared = 1;
512#endif
513 isa_dev->id_msize = memsize;
514
515 sc->mem_start = (caddr_t)isa_dev->id_maddr;
516
517 /*
518 * allocate one xmit buffer if < 16k, two buffers otherwise
519 */
520 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
521 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
522 sc->txb_cnt = 1;
523 sc->rec_page_start = ED_TXBUF_SIZE;
524 } else {
525 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
526 sc->txb_cnt = 2;
527 sc->rec_page_start = ED_TXBUF_SIZE * 2;
528 }
529 sc->mem_size = memsize;
530 sc->mem_end = sc->mem_start + memsize;
531 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
532 sc->tx_page_start = ED_WD_PAGE_OFFSET;
533
534 /*
535 * Get station address from on-board ROM
536 */
537 for (i = 0; i < ETHER_ADDR_LEN; ++i)
538 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
539
540 if (sc->mem_shared) {
541 /*
542 * Set address and enable interface shared memory.
543 */
544 if(!sc->is790) {
545 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
546 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
547 } else {
548 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
549 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
550 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
551 ((kvtop(sc->mem_start) >> 11) & 0x40) |
552 (inb(sc->asic_addr + 0x0b) & 0xb0));
553 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
554 }
555
556 /*
557 * Set upper address bits and 8/16 bit access to shared memory
558 */
559 if (isa16bit) {
560 if (sc->is790) {
561 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
562 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
563 } else {
564 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
565 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
566 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
567 }
568 } else {
569 if ((sc->type & ED_WD_SOFTCONFIG) || (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
570 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
571 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
572 }
573 }
574
575 /*
576 * Now zero memory and verify that it is clear
577 */
578 bzero(sc->mem_start, memsize);
579
580 for (i = 0; i < memsize; ++i)
581 if (sc->mem_start[i]) {
582 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
583 isa_dev->id_unit, kvtop(sc->mem_start + i));
584
585 /*
586 * Disable 16 bit access to shared memory
587 */
588 if (isa16bit)
589 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
590 ~ED_WD_LAAR_M16EN));
591
592 return(0);
593 }
594
595 /*
596 * Disable 16bit access to shared memory - we leave it disabled so
597 * that 1) machines reboot properly when the board is set
598 * 16 bit mode and there are conflicting 8bit devices/ROMS
599 * in the same 128k address space as this boards shared
600 * memory. and 2) so that other 8 bit devices with shared
601 * memory can be used in this 128k region, too.
602 */
603 if (isa16bit)
604 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
605 ~ED_WD_LAAR_M16EN));
606
607 }
608
609 return (ED_WD_IO_PORTS);
610}
611
612/*
613 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
614 */
615int
616ed_probe_3Com(isa_dev)
617 struct isa_device *isa_dev;
618{
619 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
620 int i;
621 u_int memsize;
622 u_char isa16bit, sum;
623
624 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
625 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
626
627 /*
628 * Verify that the kernel configured I/O address matches the board
629 * configured address
630 */
631 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
632 case ED_3COM_BCFR_300:
633 if (isa_dev->id_iobase != 0x300)
634 return(0);
635 break;
636 case ED_3COM_BCFR_310:
637 if (isa_dev->id_iobase != 0x310)
638 return(0);
639 break;
640 case ED_3COM_BCFR_330:
641 if (isa_dev->id_iobase != 0x330)
642 return(0);
643 break;
644 case ED_3COM_BCFR_350:
645 if (isa_dev->id_iobase != 0x350)
646 return(0);
647 break;
648 case ED_3COM_BCFR_250:
649 if (isa_dev->id_iobase != 0x250)
650 return(0);
651 break;
652 case ED_3COM_BCFR_280:
653 if (isa_dev->id_iobase != 0x280)
654 return(0);
655 break;
656 case ED_3COM_BCFR_2A0:
657 if (isa_dev->id_iobase != 0x2a0)
658 return(0);
659 break;
660 case ED_3COM_BCFR_2E0:
661 if (isa_dev->id_iobase != 0x2e0)
662 return(0);
663 break;
664 default:
665 return(0);
666 }
667
668 /*
669 * Verify that the kernel shared memory address matches the
670 * board configured address.
671 */
672 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
673 case ED_3COM_PCFR_DC000:
674 if (kvtop(isa_dev->id_maddr) != 0xdc000)
675 return(0);
676 break;
677 case ED_3COM_PCFR_D8000:
678 if (kvtop(isa_dev->id_maddr) != 0xd8000)
679 return(0);
680 break;
681 case ED_3COM_PCFR_CC000:
682 if (kvtop(isa_dev->id_maddr) != 0xcc000)
683 return(0);
684 break;
685 case ED_3COM_PCFR_C8000:
686 if (kvtop(isa_dev->id_maddr) != 0xc8000)
687 return(0);
688 break;
689 default:
690 return(0);
691 }
692
693
694 /*
695 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
696 * sequence because it'll lock up if the cable isn't connected
697 * if we don't.
698 */
699 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
700
701 /*
702 * Wait for a while, then un-reset it
703 */
704 DELAY(50);
705 /*
706 * The 3Com ASIC defaults to rather strange settings for the CR after
707 * a reset - it's important to set it again after the following
708 * outb (this is done when we map the PROM below).
709 */
710 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
711
712 /*
713 * Wait a bit for the NIC to recover from the reset
714 */
715 DELAY(5000);
716
717 sc->vendor = ED_VENDOR_3COM;
718 sc->type_str = "3c503";
719
720 sc->mem_shared = 1;
721
722 /*
723 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
724 * window to it.
725 */
726 memsize = 8192;
727
728 /*
729 * Get station address from on-board ROM
730 */
731 /*
732 * First, map ethernet address PROM over the top of where the NIC
733 * registers normally appear.
734 */
735 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
736
737 for (i = 0; i < ETHER_ADDR_LEN; ++i)
738 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
739
740 /*
741 * Unmap PROM - select NIC registers. The proper setting of the
742 * tranceiver is set in ed_init so that the attach code
743 * is given a chance to set the default based on a compile-time
744 * config option
745 */
746 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
747
748 /*
749 * Determine if this is an 8bit or 16bit board
750 */
751
752 /*
753 * select page 0 registers
754 */
755 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
756
757 /*
758 * Attempt to clear WTS bit. If it doesn't clear, then this is a
759 * 16bit board.
760 */
761 outb(sc->nic_addr + ED_P0_DCR, 0);
762
763 /*
764 * select page 2 registers
765 */
766 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
767
768 /*
769 * The 3c503 forces the WTS bit to a one if this is a 16bit board
770 */
771 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
772 isa16bit = 1;
773 else
774 isa16bit = 0;
775
776 /*
777 * select page 0 registers
778 */
779 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
780
781 sc->mem_start = (caddr_t)isa_dev->id_maddr;
782 sc->mem_size = memsize;
783 sc->mem_end = sc->mem_start + memsize;
784
785 /*
786 * We have an entire 8k window to put the transmit buffers on the
787 * 16bit boards. But since the 16bit 3c503's shared memory
788 * is only fast enough to overlap the loading of one full-size
789 * packet, trying to load more than 2 buffers can actually
790 * leave the transmitter idle during the load. So 2 seems
791 * the best value. (Although a mix of variable-sized packets
792 * might change this assumption. Nonetheless, we optimize for
793 * linear transfers of same-size packets.)
794 */
795 if (isa16bit) {
796 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
797 sc->txb_cnt = 1;
798 else
799 sc->txb_cnt = 2;
800
801 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
802 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
803 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
804 ED_3COM_RX_PAGE_OFFSET_16BIT;
805 sc->mem_ring = sc->mem_start;
806 } else {
807 sc->txb_cnt = 1;
808 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
809 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
810 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
811 ED_3COM_TX_PAGE_OFFSET_8BIT;
812 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
813 }
814
815 sc->isa16bit = isa16bit;
816
817 /*
818 * Initialize GA page start/stop registers. Probably only needed
819 * if doing DMA, but what the hell.
820 */
821 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
822 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
823
824 /*
825 * Set IRQ. 3c503 only allows a choice of irq 2-5.
826 */
827 switch (isa_dev->id_irq) {
828 case IRQ2:
829 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
830 break;
831 case IRQ3:
832 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
833 break;
834 case IRQ4:
835 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
836 break;
837 case IRQ5:
838 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
839 break;
840 default:
841 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
842 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
843 return(0);
844 }
845
846 /*
847 * Initialize GA configuration register. Set bank and enable shared mem.
848 */
849 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
850 ED_3COM_GACFR_MBS0);
851
852 /*
853 * Initialize "Vector Pointer" registers. These gawd-awful things
854 * are compared to 20 bits of the address on ISA, and if they
855 * match, the shared memory is disabled. We set them to
856 * 0xffff0...allegedly the reset vector.
857 */
858 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
859 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
860 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
861
862 /*
863 * Zero memory and verify that it is clear
864 */
865 bzero(sc->mem_start, memsize);
866
867 for (i = 0; i < memsize; ++i)
868 if (sc->mem_start[i]) {
869 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
870 isa_dev->id_unit, kvtop(sc->mem_start + i));
871 return(0);
872 }
873
874 isa_dev->id_msize = memsize;
875 return(ED_3COM_IO_PORTS);
876}
877
878/*
879 * Probe and vendor-specific initialization routine for NE1000/2000 boards
880 */
881int
882ed_probe_Novell(isa_dev)
883 struct isa_device *isa_dev;
884{
885 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
886 u_int memsize, n;
887 u_char romdata[16], isa16bit = 0, tmp;
888 static char test_pattern[32] = "THIS is A memory TEST pattern";
889 char test_buffer[32];
890
891 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
892 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
893
894 /* XXX - do Novell-specific probe here */
895
896 /* Reset the board */
897 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
898
899#if 0
900 /*
901 * This total and completely screwy thing is to work around braindamage
902 * in some NE compatible boards. Why it works, I have *no* idea.
903 * It appears that the boards watch the ISA bus for an outb, and
904 * will lock up the ISA bus if they see an inb first. Weird.
905 */
906 outb(0x84, 0);
907#endif
908
909 /*
910 * I don't know if this is necessary; probably cruft leftover from
911 * Clarkson packet driver code. Doesn't do a thing on the boards
912 * I've tested. -DG [note that a outb(0x84, 0) seems to work
913 * here, and is non-invasive...but some boards don't seem to reset
914 * and I don't have complete documentation on what the 'right'
915 * thing to do is...so we do the invasive thing for now. Yuck.]
916 */
917 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
918 DELAY(5000);
919
920 /*
921 * This is needed because some NE clones apparently don't reset the
922 * NIC properly (or the NIC chip doesn't reset fully on power-up)
923 * XXX - this makes the probe invasive! ...Done against my better
924 * judgement. -DLG
925 */
926 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
927
928 DELAY(5000);
929
930 /* Make sure that we really have an 8390 based board */
931 if (!ed_probe_generic8390(sc))
932 return(0);
933
934 sc->vendor = ED_VENDOR_NOVELL;
935 sc->mem_shared = 0;
936 isa_dev->id_maddr = 0;
937
938 /*
939 * Test the ability to read and write to the NIC memory. This has
940 * the side affect of determining if this is an NE1000 or an NE2000.
941 */
942
943 /*
944 * This prevents packets from being stored in the NIC memory when
945 * the readmem routine turns on the start bit in the CR.
946 */
947 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
948
949 /* Temporarily initialize DCR for byte operations */
950 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
951
952 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
953 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
954
955 sc->isa16bit = 0;
956
957 /*
958 * Write a test pattern in byte mode. If this fails, then there
959 * probably isn't any memory at 8k - which likely means
960 * that the board is an NE2000.
961 */
962 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
963 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
964
965 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
966 /* not an NE1000 - try NE2000 */
967
968 outb(sc->nic_addr + ED_P0_DCR,
969 ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
970 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
971 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
972
973 sc->isa16bit = 1;
974 /*
975 * Write a test pattern in word mode. If this also fails, then
976 * we don't know what this board is.
977 */
978 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
979 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
980
981 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
982 return(0); /* not an NE2000 either */
983
984 sc->type = ED_TYPE_NE2000;
985 sc->type_str = "NE2000";
986 } else {
987 sc->type = ED_TYPE_NE1000;
988 sc->type_str = "NE1000";
989 }
990
991 /* 8k of memory plus an additional 8k if 16bit */
992 memsize = 8192 + sc->isa16bit * 8192;
993
994#if 0 /* probably not useful - NE boards only come two ways */
995 /* allow kernel config file overrides */
996 if (isa_dev->id_msize)
997 memsize = isa_dev->id_msize;
998#endif
999
1000 sc->mem_size = memsize;
1001
1002 /* NIC memory doesn't start at zero on an NE board */
1003 /* The start address is tied to the bus width */
1004 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1005 sc->mem_end = sc->mem_start + memsize;
1006 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1007
1008 /*
1009 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1010 * otherwise).
1011 */
1012 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
1013 sc->txb_cnt = 1;
1014 else
1015 sc->txb_cnt = 2;
1016
1017 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1018 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1019
1020 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1021
1022 ed_pio_readmem(sc, 0, romdata, 16);
1023 for (n = 0; n < ETHER_ADDR_LEN; n++)
1024 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
1025
1026 /* clear any pending interrupts that might have occurred above */
1027 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1028
1029 return(ED_NOVELL_IO_PORTS);
1030}
1031
1032/*
1033 * Install interface into kernel networking data structures
1034 */
1035int
1036ed_attach(isa_dev)
1037 struct isa_device *isa_dev;
1038{
1039 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1040 struct ifnet *ifp = &sc->arpcom.ac_if;
1041 struct ifaddr *ifa;
1042 struct sockaddr_dl *sdl;
1043
1044 /*
1045 * Set interface to stopped condition (reset)
1046 */
1047 ed_stop(isa_dev->id_unit);
1048
1049 /*
1050 * Initialize ifnet structure
1051 */
1052 ifp->if_unit = isa_dev->id_unit;
1053 ifp->if_name = "ed" ;
1054 ifp->if_mtu = ETHERMTU;
1055 ifp->if_init = ed_init;
1056 ifp->if_output = ether_output;
1057 ifp->if_start = ed_start;
1058 ifp->if_ioctl = ed_ioctl;
1059 ifp->if_reset = ed_reset;
1060 ifp->if_watchdog = ed_watchdog;
1061
1062 /*
1063 * Set default state for ALTPHYS flag (used to disable the tranceiver
1064 * for AUI operation), based on compile-time config option.
1065 */
1066 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1067 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS
1068 | IFF_ALTPHYS);
1069 else
1070 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1071
1072 /*
1073 * Attach the interface
1074 */
1075 if_attach(ifp);
1076
1077 /*
1078 * Search down the ifa address list looking for the AF_LINK type entry
1079 */
1080 ifa = ifp->if_addrlist;
1081 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1082 (ifa->ifa_addr->sa_family != AF_LINK))
1083 ifa = ifa->ifa_next;
1084 /*
1085 * If we find an AF_LINK type entry we fill in the hardware address.
1086 * This is useful for netstat(1) to keep track of which interface
1087 * is which.
1088 */
1089 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1090 /*
1091 * Fill in the link-level address for this interface
1092 */
1093 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1094 sdl->sdl_type = IFT_ETHER;
1095 sdl->sdl_alen = ETHER_ADDR_LEN;
1096 sdl->sdl_slen = 0;
1097 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1098 }
1099
1100 /*
1101 * Print additional info when attached
1102 */
1103 printf("ed%d: address %s, ", isa_dev->id_unit,
1104 ether_sprintf(sc->arpcom.ac_enaddr));
1105
1106 if (sc->type_str && (*sc->type_str != 0))
1107 printf("type %s ", sc->type_str);
1108 else
1109 printf("type unknown (0x%x) ", sc->type);
1110
1111 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1112
1113 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1114 (ifp->if_flags & IFF_ALTPHYS)) ? "tranceiver disabled" : "");
1115
1116 /*
1117 * If BPF is in the kernel, call the attach for it
1118 */
1119#if NBPFILTER > 0
1120 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1121#endif
1122 return 1;
1123}
1124
1125/*
1126 * Reset interface.
1127 */
1128void
1129ed_reset(unit, uban)
1130 int unit;
1131 int uban; /* XXX */
1132{
1133 int s;
1134
1135 s = splimp();
1136
1137 /*
1138 * Stop interface and re-initialize.
1139 */
1140 ed_stop(unit);
1141 ed_init(unit);
1142
1143 (void) splx(s);
1144}
1145
1146/*
1147 * Take interface offline.
1148 */
1149void
1150ed_stop(unit)
1151 int unit;
1152{
1153 struct ed_softc *sc = &ed_softc[unit];
1154 int n = 5000;
1155
1156 /*
1157 * Stop everything on the interface, and select page 0 registers.
1158 */
1159 if (sc->is790) {
1160 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1161 } else {
1162 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1163 }
1164 /*
1165 * Wait for interface to enter stopped state, but limit # of checks
1166 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1167 * DS8390's, but just in case it's an old one.
1168 */
1169 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1170
1171}
1172
1173/*
1174 * Device timeout/watchdog routine. Entered if the device neglects to
1175 * generate an interrupt after a transmit has been started on it.
1176 */
1177void
1178ed_watchdog(unit)
1179 int unit;
1180{
1181 struct ed_softc *sc = &ed_softc[unit];
1182
1183 log(LOG_ERR, "ed%d: device timeout\n", unit);
1184 ++sc->arpcom.ac_if.if_oerrors;
1185
1186 ed_reset(unit, 0);
1187}
1188
1189/*
1190 * Initialize device.
1191 */
1192void
1193ed_init(unit)
1194 int unit;
1195{
1196 struct ed_softc *sc = &ed_softc[unit];
1197 struct ifnet *ifp = &sc->arpcom.ac_if;
1198 int i, s;
1199 u_char command;
1200
1201
1202 /* address not known */
1203 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1204
1205 /*
1206 * Initialize the NIC in the exact order outlined in the NS manual.
1207 * This init procedure is "mandatory"...don't change what or when
1208 * things happen.
1209 */
1210 s = splimp();
1211
1212 /* reset transmitter flags */
1213 sc->xmit_busy = 0;
1214 sc->arpcom.ac_if.if_timer = 0;
1215
1216 sc->txb_inuse = 0;
1217 sc->txb_new = 0;
1218 sc->txb_next_tx = 0;
1219
1220 /* This variable is used below - don't move this assignment */
1221 sc->next_packet = sc->rec_page_start + 1;
1222
1223 /*
1224 * Set interface for page 0, Remote DMA complete, Stopped
1225 */
1226 if (sc->is790) {
1227 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1228 } else {
1229 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1230 }
1231 if (sc->isa16bit) {
1232 /*
1233 * Set FIFO threshold to 8, No auto-init Remote DMA,
1234 * byte order=80x86, word-wide DMA xfers,
1235 */
1236 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1237 } else {
1238 /*
1239 * Same as above, but byte-wide DMA xfers
1240 */
1241 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1242 }
1243
1244 /*
1245 * Clear Remote Byte Count Registers
1246 */
1247 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1248 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1249
1250 /*
1251 * Enable reception of broadcast packets
1252 */
1253 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1254
1255 /*
1256 * Place NIC in internal loopback mode
1257 */
1258 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1259
1260 /*
1261 * Initialize transmit/receive (ring-buffer) Page Start
1262 */
1263 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1264 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1265 /* Set lower bits of byte addressable framing to 0 */
1266 if (sc->is790)
1267 outb(sc->nic_addr + 0x09, 0);
1268
1269 /*
1270 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1271 */
1272 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1273 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1274
1275 /*
1276 * Clear all interrupts. A '1' in each bit position clears the
1277 * corresponding flag.
1278 */
1279 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1280
1281 /*
1282 * Enable the following interrupts: receive/transmit complete,
1283 * receive/transmit error, and Receiver OverWrite.
1284 *
1285 * Counter overflow and Remote DMA complete are *not* enabled.
1286 */
1287 outb(sc->nic_addr + ED_P0_IMR,
1288 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1289
1290 /*
1291 * Program Command Register for page 1
1292 */
1293 if (sc->is790) {
1294 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1295 } else {
1296 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1297 }
1298 /*
1299 * Copy out our station address
1300 */
1301 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1302 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1303
1304#if NBPFILTER > 0
1305 /*
1306 * Initialize multicast address hashing registers to accept
1307 * all multicasts (only used when in promiscuous mode)
1308 */
1309 for (i = 0; i < 8; ++i)
1310 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1311#endif
1312
1313 /*
1314 * Set Current Page pointer to next_packet (initialized above)
1315 */
1316 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1317
1318 /*
1319 * Set Command Register for page 0, Remote DMA complete,
1320 * and interface Start.
1321 */
1322 if (sc->is790) {
1323 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1324 } else {
1325 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1326 }
1327 /*
1328 * Take interface out of loopback
1329 */
1330 outb(sc->nic_addr + ED_P0_TCR, 0);
1331
1332 /*
1333 * If this is a 3Com board, the tranceiver must be software enabled
1334 * (there is no settable hardware default).
1335 */
1336 if (sc->vendor == ED_VENDOR_3COM) {
1337 if (ifp->if_flags & IFF_ALTPHYS) {
1338 outb(sc->asic_addr + ED_3COM_CR, 0);
1339 } else {
1340 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1341 }
1342 }
1343
1344 /*
1345 * Set 'running' flag, and clear output active flag.
1346 */
1347 ifp->if_flags |= IFF_RUNNING;
1348 ifp->if_flags &= ~IFF_OACTIVE;
1349
1350 /*
1351 * ...and attempt to start output
1352 */
1353 ed_start(ifp);
1354
1355 (void) splx(s);
1356}
1357
1358/*
1359 * This routine actually starts the transmission on the interface
1360 */
1361static inline void ed_xmit(ifp)
1362 struct ifnet *ifp;
1363{
1364 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1365 unsigned short len;
1366
1367 len = sc->txb_len[sc->txb_next_tx];
1368
1369 /*
1370 * Set NIC for page 0 register access
1371 */
1372 if (sc->is790) {
1373 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1374 } else {
1375 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1376 }
1377 /*
1378 * Set TX buffer start page
1379 */
1380 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1381 sc->txb_next_tx * ED_TXBUF_SIZE);
1382
1383 /*
1384 * Set TX length
1385 */
1386 outb(sc->nic_addr + ED_P0_TBCR0, len);
1387 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1388
1389 /*
1390 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1391 */
1392 if (sc->is790) {
1393 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1394 } else {
1395 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1396 }
1397 sc->xmit_busy = 1;
1398
1399 /*
1400 * Point to next transmit buffer slot and wrap if necessary.
1401 */
1402 sc->txb_next_tx++;
1403 if (sc->txb_next_tx == sc->txb_cnt)
1404 sc->txb_next_tx = 0;
1405
1406 /*
1407 * Set a timer just in case we never hear from the board again
1408 */
1409 ifp->if_timer = 2;
1410}
1411
1412/*
1413 * Start output on interface.
1414 * We make two assumptions here:
1415 * 1) that the current priority is set to splimp _before_ this code
1416 * is called *and* is returned to the appropriate priority after
1417 * return
1418 * 2) that the IFF_OACTIVE flag is checked before this code is called
1419 * (i.e. that the output part of the interface is idle)
1420 */
1421void
1422ed_start(ifp)
1423 struct ifnet *ifp;
1424{
1425 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1426 struct mbuf *m0, *m;
1427 caddr_t buffer;
1428 int len;
1429
1430outloop:
1431 /*
1432 * First, see if there are buffered packets and an idle
1433 * transmitter - should never happen at this point.
1434 */
1435 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1436 printf("ed: packets buffers, but transmitter idle\n");
1437 ed_xmit(ifp);
1438 }
1439
1440 /*
1441 * See if there is room to put another packet in the buffer.
1442 */
1443 if (sc->txb_inuse == sc->txb_cnt) {
1444 /*
1445 * No room. Indicate this to the outside world
1446 * and exit.
1447 */
1448 ifp->if_flags |= IFF_OACTIVE;
1449 return;
1450 }
1451
1452 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1453 if (m == 0) {
1454 /*
1455 * We are using the !OACTIVE flag to indicate to the outside
1456 * world that we can accept an additional packet rather than
1457 * that the transmitter is _actually_ active. Indeed, the
1458 * transmitter may be active, but if we haven't filled all
1459 * the buffers with data then we still want to accept more.
1460 */
1461 ifp->if_flags &= ~IFF_OACTIVE;
1462 return;
1463 }
1464
1465 /*
1466 * Copy the mbuf chain into the transmit buffer
1467 */
1468
1469 m0 = m;
1470
1471 /* txb_new points to next open buffer slot */
1472 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1473
1474 if (sc->mem_shared) {
1475 /*
1476 * Special case setup for 16 bit boards...
1477 */
1478 if (sc->isa16bit) {
1479 switch (sc->vendor) {
1480 /*
1481 * For 16bit 3Com boards (which have 16k of memory),
1482 * we have the xmit buffers in a different page
1483 * of memory ('page 0') - so change pages.
1484 */
1485 case ED_VENDOR_3COM:
1486 outb(sc->asic_addr + ED_3COM_GACFR,
1487 ED_3COM_GACFR_RSEL);
1488 break;
1489 /*
1490 * Enable 16bit access to shared memory on WD/SMC boards
1491 * Don't update wd_laar_proto because we want to restore the
1492 * previous state (because an arp reply in the input code
1493 * may cause a call-back to ed_start)
1494 * XXX - the call-back to 'start' is a bug, IMHO.
1495 */
1496 case ED_VENDOR_WD_SMC:
1497 outb(sc->asic_addr + ED_WD_LAAR,
1498 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1499 }
1500 }
1501
1502 for (len = 0; m != 0; m = m->m_next) {
1503 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1504 buffer += m->m_len;
1505 len += m->m_len;
1506 }
1507
1508 /*
1509 * Restore previous shared memory access
1510 */
1511 if (sc->isa16bit) {
1512 switch (sc->vendor) {
1513 case ED_VENDOR_3COM:
1514 outb(sc->asic_addr + ED_3COM_GACFR,
1515 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1516 break;
1517 case ED_VENDOR_WD_SMC:
1518 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1519 break;
1520 }
1521 }
1522 } else {
1523 len = ed_pio_write_mbufs(sc, m, buffer);
1524 }
1525
1526 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1527
1528 sc->txb_inuse++;
1529
1530 /*
1531 * Point to next buffer slot and wrap if necessary.
1532 */
1533 sc->txb_new++;
1534 if (sc->txb_new == sc->txb_cnt)
1535 sc->txb_new = 0;
1536
1537 if (sc->xmit_busy == 0)
1538 ed_xmit(ifp);
1539 /*
1540 * If there is BPF support in the configuration, tap off here.
1541 * The following has support for converting trailer packets
1542 * back to normal.
1543 * XXX - support for trailer packets in BPF should be moved into
1544 * the bpf code proper to avoid code duplication in all of
1545 * the drivers.
1546 */
1547#if NBPFILTER > 0
1548 if (sc->bpf) {
1549 u_short etype;
1550 int off, datasize, resid;
1551 struct ether_header *eh;
1552 struct trailer_header trailer_header;
1553 char ether_packet[ETHER_MAX_LEN];
1554 char *ep;
1555
1556 ep = ether_packet;
1557
1558 /*
1559 * We handle trailers below:
1560 * Copy ether header first, then residual data,
1561 * then data. Put all this in a temporary buffer
1562 * 'ether_packet' and send off to bpf. Since the
1563 * system has generated this packet, we assume
1564 * that all of the offsets in the packet are
1565 * correct; if they're not, the system will almost
1566 * certainly crash in m_copydata.
1567 * We make no assumptions about how the data is
1568 * arranged in the mbuf chain (i.e. how much
1569 * data is in each mbuf, if mbuf clusters are
1570 * used, etc.), which is why we use m_copydata
1571 * to get the ether header rather than assume
1572 * that this is located in the first mbuf.
1573 */
1574 /* copy ether header */
1575 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1576 eh = (struct ether_header *) ep;
1577 ep += sizeof(struct ether_header);
1578 etype = ntohs(eh->ether_type);
1579 if (etype >= ETHERTYPE_TRAIL &&
1580 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1581 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1582 off = datasize + sizeof(struct ether_header);
1583
1584 /* copy trailer_header into a data structure */
1585 m_copydata(m0, off, sizeof(struct trailer_header),
1586 &trailer_header.ether_type);
1587
1588 /* copy residual data */
1589 m_copydata(m0, off+sizeof(struct trailer_header),
1590 resid = ntohs(trailer_header.ether_residual) -
1591 sizeof(struct trailer_header), ep);
1592 ep += resid;
1593
1594 /* copy data */
1595 m_copydata(m0, sizeof(struct ether_header),
1596 datasize, ep);
1597 ep += datasize;
1598
1599 /* restore original ether packet type */
1600 eh->ether_type = trailer_header.ether_type;
1601
1602 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1603 } else
1604 bpf_mtap(sc->bpf, m0);
1605 }
1606#endif
1607
1608 m_freem(m0);
1609
1610 /*
1611 * Loop back to the top to possibly buffer more packets
1612 */
1613 goto outloop;
1614}
1615
1616/*
1617 * Ethernet interface receiver interrupt.
1618 */
1619static inline void
1620ed_rint(unit)
1621 int unit;
1622{
1623 register struct ed_softc *sc = &ed_softc[unit];
1624 u_char boundry, current;
1625 u_short len;
1626 struct ed_ring packet_hdr;
1627 char *packet_ptr;
1628
1629 /*
1630 * Set NIC to page 1 registers to get 'current' pointer
1631 */
1632 if (sc->is790) {
1633 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1634 } else {
1635 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1636 }
1637 /*
1638 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1639 * it points to where new data has been buffered. The 'CURR'
1640 * (current) register points to the logical end of the ring-buffer
1641 * - i.e. it points to where additional new data will be added.
1642 * We loop here until the logical beginning equals the logical
1643 * end (or in other words, until the ring-buffer is empty).
1644 */
1645 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1646
1647 /* get pointer to this buffer's header structure */
1648 packet_ptr = sc->mem_ring +
1649 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1650
1651 /*
1652 * The byte count includes the FCS - Frame Check Sequence (a
1653 * 32 bit CRC).
1654 */
1655 if (sc->mem_shared)
1656 packet_hdr = *(struct ed_ring *)packet_ptr;
1657 else
1658 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1659 sizeof(packet_hdr));
1660 len = packet_hdr.count;
1661 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1662 /*
1663 * Go get packet. len - 4 removes CRC from length.
1664 */
1665 ed_get_packet(sc, packet_ptr + 4, len - 4);
1666 ++sc->arpcom.ac_if.if_ipackets;
1667 } else {
1668 /*
1669 * Really BAD...probably indicates that the ring pointers
1670 * are corrupted. Also seen on early rev chips under
1671 * high load - the byte order of the length gets switched.
1672 */
1673 log(LOG_ERR,
1674 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1675 unit, len);
1676 ++sc->arpcom.ac_if.if_ierrors;
1677 ed_reset(unit, 0);
1678 return;
1679 }
1680
1681 /*
1682 * Update next packet pointer
1683 */
1684 sc->next_packet = packet_hdr.next_packet;
1685
1686 /*
1687 * Update NIC boundry pointer - being careful to keep it
1688 * one buffer behind. (as recommended by NS databook)
1689 */
1690 boundry = sc->next_packet - 1;
1691 if (boundry < sc->rec_page_start)
1692 boundry = sc->rec_page_stop - 1;
1693
1694 /*
1695 * Set NIC to page 0 registers to update boundry register
1696 */
1697 if (sc->is790) {
1698 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1699 } else {
1700 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1701 }
1702 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1703
1704 /*
1705 * Set NIC to page 1 registers before looping to top (prepare to
1706 * get 'CURR' current pointer)
1707 */
1708 if (sc->is790) {
1709 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1710 } else {
1711 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1712 }
1713 }
1714}
1715
1716/*
1717 * Ethernet interface interrupt processor
1718 */
1719void
1720edintr(unit)
1721 int unit;
1722{
1723 struct ed_softc *sc = &ed_softc[unit];
1724 u_char isr;
1725
1726 /*
1727 * Set NIC to page 0 registers
1728 */
1729 if (sc->is790) {
1730 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1731 } else {
1732 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1733 }
1734 /*
1735 * loop until there are no more new interrupts
1736 */
1737 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1738
1739 /*
1740 * reset all the bits that we are 'acknowledging'
1741 * by writing a '1' to each bit position that was set
1742 * (writing a '1' *clears* the bit)
1743 */
1744 outb(sc->nic_addr + ED_P0_ISR, isr);
1745
1746 /*
1747 * Handle transmitter interrupts. Handle these first
1748 * because the receiver will reset the board under
1749 * some conditions.
1750 */
1751 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1752 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1753
1754 /*
1755 * Check for transmit error. If a TX completed with an
1756 * error, we end up throwing the packet away. Really
1757 * the only error that is possible is excessive
1758 * collisions, and in this case it is best to allow the
1759 * automatic mechanisms of TCP to backoff the flow. Of
1760 * course, with UDP we're screwed, but this is expected
1761 * when a network is heavily loaded.
1762 */
1763 (void) inb(sc->nic_addr + ED_P0_TSR);
1764 if (isr & ED_ISR_TXE) {
1765
1766 /*
1767 * Excessive collisions (16)
1768 */
1769 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1770 && (collisions == 0)) {
1771 /*
1772 * When collisions total 16, the
1773 * P0_NCR will indicate 0, and the
1774 * TSR_ABT is set.
1775 */
1776 collisions = 16;
1777 }
1778
1779 /*
1780 * update output errors counter
1781 */
1782 ++sc->arpcom.ac_if.if_oerrors;
1783 } else {
1784 /*
1785 * Update total number of successfully
1786 * transmitted packets.
1787 */
1788 ++sc->arpcom.ac_if.if_opackets;
1789 }
1790
1791 /*
1792 * reset tx busy and output active flags
1793 */
1794 sc->xmit_busy = 0;
1795 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1796
1797 /*
1798 * clear watchdog timer
1799 */
1800 sc->arpcom.ac_if.if_timer = 0;
1801
1802 /*
1803 * Add in total number of collisions on last
1804 * transmission.
1805 */
1806 sc->arpcom.ac_if.if_collisions += collisions;
1807
1808 /*
1809 * Decrement buffer in-use count if not zero (can only
1810 * be zero if a transmitter interrupt occured while
1811 * not actually transmitting).
1812 * If data is ready to transmit, start it transmitting,
1813 * otherwise defer until after handling receiver
1814 */
1815 if (sc->txb_inuse && --sc->txb_inuse)
1816 ed_xmit(&sc->arpcom.ac_if);
1817 }
1818
1819 /*
1820 * Handle receiver interrupts
1821 */
1822 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1823 /*
1824 * Overwrite warning. In order to make sure that a lockup
1825 * of the local DMA hasn't occurred, we reset and
1826 * re-init the NIC. The NSC manual suggests only a
1827 * partial reset/re-init is necessary - but some
1828 * chips seem to want more. The DMA lockup has been
1829 * seen only with early rev chips - Methinks this
1830 * bug was fixed in later revs. -DG
1831 */
1832 if (isr & ED_ISR_OVW) {
1833 ++sc->arpcom.ac_if.if_ierrors;
1834#ifdef DIAGNOSTIC
1835 log(LOG_WARNING,
1836 "ed%d: warning - receiver ring buffer overrun\n",
1837 unit);
1838#endif
1839 /*
1840 * Stop/reset/re-init NIC
1841 */
1842 ed_reset(unit, 0);
1843 } else {
1844
1845 /*
1846 * Receiver Error. One or more of: CRC error, frame
1847 * alignment error FIFO overrun, or missed packet.
1848 */
1849 if (isr & ED_ISR_RXE) {
1850 ++sc->arpcom.ac_if.if_ierrors;
1851#ifdef ED_DEBUG
1852 printf("ed%d: receive error %x\n", unit,
1853 inb(sc->nic_addr + ED_P0_RSR));
1854#endif
1855 }
1856
1857 /*
1858 * Go get the packet(s)
1859 * XXX - Doing this on an error is dubious
1860 * because there shouldn't be any data to
1861 * get (we've configured the interface to
1862 * not accept packets with errors).
1863 */
1864
1865 /*
1866 * Enable 16bit access to shared memory first
1867 * on WD/SMC boards.
1868 */
1869 if (sc->isa16bit &&
1870 (sc->vendor == ED_VENDOR_WD_SMC)) {
1871
1872 outb(sc->asic_addr + ED_WD_LAAR,
1873 (sc->wd_laar_proto |=
1874 ED_WD_LAAR_M16EN));
1875 }
1876
1877 ed_rint (unit);
1878
1879 /* disable 16bit access */
1880 if (sc->isa16bit &&
1881 (sc->vendor == ED_VENDOR_WD_SMC)) {
1882
1883 outb(sc->asic_addr + ED_WD_LAAR,
1884 (sc->wd_laar_proto &=
1885 ~ED_WD_LAAR_M16EN));
1886 }
1887 }
1888 }
1889
1890 /*
1891 * If it looks like the transmitter can take more data,
1892 * attempt to start output on the interface.
1893 * This is done after handling the receiver to
1894 * give the receiver priority.
1895 */
1896 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1897 ed_start(&sc->arpcom.ac_if);
1898
1899 /*
1900 * return NIC CR to standard state: page 0, remote DMA complete,
1901 * start (toggling the TXP bit off, even if was just set
1902 * in the transmit routine, is *okay* - it is 'edge'
1903 * triggered from low to high)
1904 */
1905 if (sc->is790) {
1906 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1907 } else {
1908 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1909 }
1910 /*
1911 * If the Network Talley Counters overflow, read them to
1912 * reset them. It appears that old 8390's won't
1913 * clear the ISR flag otherwise - resulting in an
1914 * infinite loop.
1915 */
1916 if (isr & ED_ISR_CNT) {
1917 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1918 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1919 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1920 }
1921 }
1922}
1923
1924/*
1925 * Process an ioctl request. This code needs some work - it looks
1926 * pretty ugly.
1927 */
1928int
1929ed_ioctl(ifp, command, data)
1930 register struct ifnet *ifp;
1931 int command;
1932 caddr_t data;
1933{
1934 register struct ifaddr *ifa = (struct ifaddr *)data;
1935 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1936 struct ifreq *ifr = (struct ifreq *)data;
1937 int s, error = 0;
1938
1939 s = splimp();
1940
1941 switch (command) {
1942
1943 case SIOCSIFADDR:
1944 ifp->if_flags |= IFF_UP;
1945
1946 switch (ifa->ifa_addr->sa_family) {
1947#ifdef INET
1948 case AF_INET:
1949 ed_init(ifp->if_unit); /* before arpwhohas */
1950 /*
1951 * See if another station has *our* IP address.
1952 * i.e.: There is an address conflict! If a
1953 * conflict exists, a message is sent to the
1954 * console.
1955 */
1956 ((struct arpcom *)ifp)->ac_ipaddr =
1957 IA_SIN(ifa)->sin_addr;
1958 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1959 break;
1960#endif
1961#ifdef NS
1962 /*
1963 * XXX - This code is probably wrong
1964 */
1965 case AF_NS:
1966 {
1967 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1968
1969 if (ns_nullhost(*ina))
1970 ina->x_host =
1971 *(union ns_host *)(sc->arpcom.ac_enaddr);
1972 else {
1973 /*
1974 *
1975 */
1976 bcopy((caddr_t)ina->x_host.c_host,
1977 (caddr_t)sc->arpcom.ac_enaddr,
1978 sizeof(sc->arpcom.ac_enaddr));
1979 }
1980 /*
1981 * Set new address
1982 */
1983 ed_init(ifp->if_unit);
1984 break;
1985 }
1986#endif
1987 default:
1988 ed_init(ifp->if_unit);
1989 break;
1990 }
1991 break;
1992
1993 case SIOCSIFFLAGS:
1994 /*
1995 * If interface is marked down and it is running, then stop it
1996 */
1997 if (((ifp->if_flags & IFF_UP) == 0) &&
1998 (ifp->if_flags & IFF_RUNNING)) {
1999 ed_stop(ifp->if_unit);
2000 ifp->if_flags &= ~IFF_RUNNING;
2001 } else {
2002 /*
2003 * If interface is marked up and it is stopped, then start it
2004 */
2005 if ((ifp->if_flags & IFF_UP) &&
2006 ((ifp->if_flags & IFF_RUNNING) == 0))
2007 ed_init(ifp->if_unit);
2008 }
2009#if NBPFILTER > 0
2010 if (ifp->if_flags & IFF_PROMISC) {
2011 /*
2012 * Set promiscuous mode on interface.
2013 * XXX - for multicasts to work, we would need to
2014 * write 1's in all bits of multicast
2015 * hashing array. For now we assume that
2016 * this was done in ed_init().
2017 */
2018 outb(sc->nic_addr + ED_P0_RCR,
2019 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
2020 } else {
2021 /*
2022 * XXX - for multicasts to work, we would need to
2023 * rewrite the multicast hashing array with the
2024 * proper hash (would have been destroyed above).
2025 */
2026 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
2027 }
2028#endif
2029 /*
2030 * An unfortunate hack to provide the (required) software control
2031 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
2032 * the tranceiver if set.
2033 */
2034 if (sc->vendor == ED_VENDOR_3COM) {
2035 if (ifp->if_flags & IFF_ALTPHYS) {
2036 outb(sc->asic_addr + ED_3COM_CR, 0);
2037 } else {
2038 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2039 }
2040 }
2041
2042 break;
2043
2044 default:
2045 error = EINVAL;
2046 }
2047 (void) splx(s);
2048 return (error);
2049}
2050
2051/*
2052 * Macro to calculate a new address within shared memory when given an offset
2053 * from an address, taking into account ring-wrap.
2054 */
2055#define ringoffset(sc, start, off, type) \
2056 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2057 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2058 + (sc)->mem_ring: \
2059 ((caddr_t)(start)+(off)) ))
2060
2061/*
2062 * Retreive packet from shared memory and send to the next level up via
2063 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2064 */
2065static void
2066ed_get_packet(sc, buf, len)
2067 struct ed_softc *sc;
2068 char *buf;
2069 u_short len;
2070{
2071 struct ether_header *eh;
2072 struct mbuf *m, *head = 0, *ed_ring_to_mbuf();
2073 u_short off;
2074 int resid;
2075 u_short etype;
2076 struct trailer_header trailer_header;
2077
2078 /* Allocate a header mbuf */
2079 MGETHDR(m, M_DONTWAIT, MT_DATA);
2080 if (m == 0)
2081 goto bad;
2082 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2083 m->m_pkthdr.len = len;
2084 m->m_len = 0;
2085 head = m;
2086
2087 /* The following sillines is to make NFS happy */
2088#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2089#define EOFF (EROUND - sizeof(struct ether_header))
2090
2091 /*
2092 * The following assumes there is room for
2093 * the ether header in the header mbuf
2094 */
2095 head->m_data += EOFF;
2096 eh = mtod(head, struct ether_header *);
2097
2098 if (sc->mem_shared)
2099 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2100 else
2101 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2102 sizeof(struct ether_header));
2103 buf += sizeof(struct ether_header);
2104 head->m_len += sizeof(struct ether_header);
2105 len -= sizeof(struct ether_header);
2106
2107 etype = ntohs((u_short)eh->ether_type);
2108
2109 /*
2110 * Deal with trailer protocol:
2111 * If trailer protocol, calculate the datasize as 'off',
2112 * which is also the offset to the trailer header.
2113 * Set resid to the amount of packet data following the
2114 * trailer header.
2115 * Finally, copy residual data into mbuf chain.
2116 */
2117 if (etype >= ETHERTYPE_TRAIL &&
2118 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2119
2120 off = (etype - ETHERTYPE_TRAIL) << 9;
2121 if ((off + sizeof(struct trailer_header)) > len)
2122 goto bad; /* insanity */
2123
2124 /*
2125 * If we have shared memory, we can get info directly from the
2126 * stored packet, otherwise we must get a local copy
2127 * of the trailer header using PIO.
2128 */
2129 if (sc->mem_shared) {
2130 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2131 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2132 } else {
2133 struct trailer_header trailer_header;
2134 ed_pio_readmem(sc,
2135 ringoffset(sc, buf, off, caddr_t),
2136 (char *) &trailer_header,
2137 sizeof(trailer_header));
2138 eh->ether_type = trailer_header.ether_type;
2139 resid = trailer_header.ether_residual;
2140 }
2141
2142 if ((off + resid) > len) goto bad; /* insanity */
2143
2144 resid -= sizeof(struct trailer_header);
2145 if (resid < 0) goto bad; /* insanity */
2146
2147 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid);
2148 if (m == 0) goto bad;
2149
2150 len = off;
2151 head->m_pkthdr.len -= 4; /* subtract trailer header */
2152 }
2153
2154 /*
2155 * Pull packet off interface. Or if this was a trailer packet,
2156 * the data portion is appended.
2157 */
2158 m = ed_ring_to_mbuf(sc, buf, m, len);
2159 if (m == 0) goto bad;
2160
2161#if NBPFILTER > 0
2162 /*
2163 * Check if there's a BPF listener on this interface.
2164 * If so, hand off the raw packet to bpf.
2165 */
2166 if (sc->bpf) {
2167 bpf_mtap(sc->bpf, head);
2168
2169 /*
2170 * Note that the interface cannot be in promiscuous mode if
2171 * there are no BPF listeners. And if we are in promiscuous
2172 * mode, we have to check if this packet is really ours.
2173 *
2174 * XXX This test does not support multicasts.
2175 */
2176 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2177 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2178 sizeof(eh->ether_dhost)) != 0 &&
2179 bcmp(eh->ether_dhost, etherbroadcastaddr,
2180 sizeof(eh->ether_dhost)) != 0) {
2181
2182 m_freem(head);
2183 return;
2184 }
2185 }
2186#endif
2187
2188 /*
2189 * Fix up data start offset in mbuf to point past ether header
2190 */
2191 m_adj(head, sizeof(struct ether_header));
2192
2193 /*
2194 * silly ether_input routine needs 'type' in host byte order
2195 */
2196 eh->ether_type = ntohs(eh->ether_type);
2197
2198 ether_input(&sc->arpcom.ac_if, eh, head);
2199 return;
2200
2201bad: if (head)
2202 m_freem(head);
2203 return;
2204}
2205
2206/*
2207 * Supporting routines
2208 */
2209
2210/*
2211 * Given a NIC memory source address and a host memory destination
2212 * address, copy 'amount' from NIC to host using Programmed I/O.
2213 * The 'amount' is rounded up to a word - okay as long as mbufs
2214 * are word sized.
2215 * This routine is currently Novell-specific.
2216 */
2217void
2218ed_pio_readmem(sc,src,dst,amount)
2219 struct ed_softc *sc;
2220 unsigned short src;
2221 unsigned char *dst;
2222 unsigned short amount;
2223{
2224 unsigned short tmp_amount;
2225
2226 /* select page 0 registers */
2227 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2228
2229 /* round up to a word */
2230 tmp_amount = amount;
2231 if (amount & 1) ++amount;
2232
2233 /* set up DMA byte count */
2234 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2235 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2236
2237 /* set up source address in NIC mem */
2238 outb(sc->nic_addr + ED_P0_RSAR0, src);
2239 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2240
2241 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2242
2243 if (sc->isa16bit) {
2244 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2245 } else
2246 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2247
2248}
2249
2250/*
2251 * Stripped down routine for writing a linear buffer to NIC memory.
2252 * Only used in the probe routine to test the memory. 'len' must
2253 * be even.
2254 */
2255void
2256ed_pio_writemem(sc,src,dst,len)
2257 struct ed_softc *sc;
2258 char *src;
2259 unsigned short dst;
2260 unsigned short len;
2261{
2262 int maxwait=100; /* about 120us */
2263
2264 /* select page 0 registers */
2265 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2266
2267 /* reset remote DMA complete flag */
2268 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2269
2270 /* set up DMA byte count */
2271 outb(sc->nic_addr + ED_P0_RBCR0, len);
2272 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2273
2274 /* set up destination address in NIC mem */
2275 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2276 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2277
2278 /* set remote DMA write */
2279 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2280
2281 if (sc->isa16bit)
2282 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2283 else
2284 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2285 /*
2286 * Wait for remote DMA complete. This is necessary because on the
2287 * transmit side, data is handled internally by the NIC in bursts
2288 * and we can't start another remote DMA until this one completes.
2289 * Not waiting causes really bad things to happen - like the NIC
2290 * irrecoverably jamming the ISA bus.
2291 */
2292 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2293}
2294
2295/*
2296 * Write an mbuf chain to the destination NIC memory address using
2297 * programmed I/O.
2298 */
2299u_short
2300ed_pio_write_mbufs(sc,m,dst)
2301 struct ed_softc *sc;
2302 struct mbuf *m;
2303 unsigned short dst;
2304{
2305 unsigned short len, mb_offset;
2306 struct mbuf *mp;
2307 unsigned char residual[2];
2308 int maxwait=100; /* about 120us */
2309
2310 /* First, count up the total number of bytes to copy */
2311 for (len = 0, mp = m; mp; mp = mp->m_next)
2312 len += mp->m_len;
2313
2314 /* select page 0 registers */
2315 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2316
2317 /* reset remote DMA complete flag */
2318 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2319
2320 /* set up DMA byte count */
2321 outb(sc->nic_addr + ED_P0_RBCR0, len);
2322 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2323
2324 /* set up destination address in NIC mem */
2325 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2326 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2327
2328 /* set remote DMA write */
2329 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2330
2331 mb_offset = 0;
2332 /*
2333 * Transfer the mbuf chain to the NIC memory.
2334 * The following code isn't too pretty. The problem is that we can only
2335 * transfer words to the board, and if an mbuf has an odd number
2336 * of bytes in it, this is a problem. It's not a simple matter of
2337 * just removing a byte from the next mbuf (adjusting data++ and
2338 * len--) because this will hose-over the mbuf chain which might
2339 * be needed later for BPF. Instead, we maintain an offset
2340 * (mb_offset) which let's us skip over the first byte in the
2341 * following mbuf.
2342 */
2343 while (m) {
2344 if (m->m_len - mb_offset) {
2345 if (sc->isa16bit) {
2346 if ((m->m_len - mb_offset) > 1)
2347 outsw(sc->asic_addr + ED_NOVELL_DATA,
2348 mtod(m, caddr_t) + mb_offset,
2349 (m->m_len - mb_offset) / 2);
2350
2351 /*
2352 * if odd number of bytes, get the odd byte from
2353 * the next mbuf with data
2354 */
2355 if ((m->m_len - mb_offset) & 1) {
2356 /* first the last byte in current mbuf */
2357 residual[0] = *(mtod(m, caddr_t)
2358 + m->m_len - 1);
2359
2360 /* advance past any empty mbufs */
2361 while (m->m_next && (m->m_next->m_len == 0))
2362 m = m->m_next;
2363
2364 if (m->m_next) {
2365 /* remove first byte in next mbuf */
2366 residual[1] = *(mtod(m->m_next, caddr_t));
2367 mb_offset = 1;
2368 }
2369
2370 outw(sc->asic_addr + ED_NOVELL_DATA,
2371 *((unsigned short *) residual));
2372 } else
2373 mb_offset = 0;
2374 } else
2375 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2376
2377 }
2378 m = m->m_next;
2379 }
2380
2381 /*
2382 * Wait for remote DMA complete. This is necessary because on the
2383 * transmit side, data is handled internally by the NIC in bursts
2384 * and we can't start another remote DMA until this one completes.
2385 * Not waiting causes really bad things to happen - like the NIC
2386 * irrecoverably jamming the ISA bus.
2387 */
2388 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2389
2390 if (!maxwait) {
2391 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2392 sc->arpcom.ac_if.if_unit);
2393 ed_reset(sc->arpcom.ac_if.if_unit, 0);
2394 }
2395
2396 return(len);
2397}
2398
2399/*
2400 * Given a source and destination address, copy 'amount' of a packet from
2401 * the ring buffer into a linear destination buffer. Takes into account
2402 * ring-wrap.
2403 */
2404static inline char *
2405ed_ring_copy(sc,src,dst,amount)
2406 struct ed_softc *sc;
2407 char *src;
2408 char *dst;
2409 u_short amount;
2410{
2411 u_short tmp_amount;
2412
2413 /* does copy wrap to lower addr in ring buffer? */
2414 if (src + amount > sc->mem_end) {
2415 tmp_amount = sc->mem_end - src;
2416
2417 /* copy amount up to end of NIC memory */
2418 if (sc->mem_shared)
2419 bcopy(src,dst,tmp_amount);
2420 else
2421 ed_pio_readmem(sc,src,dst,tmp_amount);
2422
2423 amount -= tmp_amount;
2424 src = sc->mem_ring;
2425 dst += tmp_amount;
2426 }
2427
2428 if (sc->mem_shared)
2429 bcopy(src, dst, amount);
2430 else
2431 ed_pio_readmem(sc, src, dst, amount);
2432
2433 return(src + amount);
2434}
2435
2436/*
2437 * Copy data from receive buffer to end of mbuf chain
2438 * allocate additional mbufs as needed. return pointer
2439 * to last mbuf in chain.
2440 * sc = ed info (softc)
2441 * src = pointer in ed ring buffer
2442 * dst = pointer to last mbuf in mbuf chain to copy to
2443 * amount = amount of data to copy
2444 */
2445struct mbuf *
2446ed_ring_to_mbuf(sc,src,dst,total_len)
2447 struct ed_softc *sc;
2448 char *src;
2449 struct mbuf *dst;
2450 u_short total_len;
2451{
2452 register struct mbuf *m = dst;
2453
2454 while (total_len) {
2455 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2456
2457 if (amount == 0) { /* no more data in this mbuf, alloc another */
2458 /*
2459 * If there is enough data for an mbuf cluster, attempt
2460 * to allocate one of those, otherwise, a regular
2461 * mbuf will do.
2462 * Note that a regular mbuf is always required, even if
2463 * we get a cluster - getting a cluster does not
2464 * allocate any mbufs, and one is needed to assign
2465 * the cluster to. The mbuf that has a cluster
2466 * extension can not be used to contain data - only
2467 * the cluster can contain data.
2468 */
2469 dst = m;
2470 MGET(m, M_DONTWAIT, MT_DATA);
2471 if (m == 0)
2472 return (0);
2473
2474 if (total_len >= MINCLSIZE)
2475 MCLGET(m, M_DONTWAIT);
2476
2477 m->m_len = 0;
2478 dst->m_next = m;
2479 amount = min(total_len, M_TRAILINGSPACE(m));
2480 }
2481
2482 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2483
2484 m->m_len += amount;
2485 total_len -= amount;
2486
2487 }
2488 return (m);
2489}
2490#endif
| 394 case ED_TYPE_WD8013EP: /* also WD8003EP */
395 if (inb(sc->asic_addr + ED_WD_ICR)
396 & ED_WD_ICR_16BIT) {
397 isa16bit = 1;
398 memsize = 16384;
399 sc->type_str = "WD8013EP";
400 } else {
401 isa16bit = 0;
402 memsize = 8192;
403 sc->type_str = "WD8003EP";
404 }
405 break;
406 case ED_TYPE_WD8013WC:
407 sc->type_str = "WD8013WC";
408 memsize = 16384;
409 isa16bit = 1;
410 break;
411 case ED_TYPE_WD8013EBP:
412 sc->type_str = "WD8013EBP";
413 memsize = 16384;
414 isa16bit = 1;
415 break;
416 case ED_TYPE_WD8013EPC:
417 sc->type_str = "WD8013EPC";
418 memsize = 16384;
419 isa16bit = 1;
420 break;
421 case ED_TYPE_SMC8216C:
422 sc->type_str = "SMC8216/SMC8216C";
423 memsize = 16384;
424 isa16bit = 1;
425 sc->is790 = 1;
426 break;
427 case ED_TYPE_SMC8216T:
428 sc->type_str = "SMC8216T";
429 memsize = 16384;
430 isa16bit = 1;
431 sc->is790 = 1;
432 break;
433 default:
434 sc->type_str = "";
435 memsize = 8192;
436 isa16bit = 0;
437 break;
438 }
439 /*
440 * Make some adjustments to initial values depending on what is
441 * found in the ICR.
442 */
443 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
444 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
445 isa16bit = 0;
446 memsize = 8192;
447 }
448
449#if ED_DEBUG
450 printf("type=%s isa16bit=%d memsize=%d id_msize=%d\n",
451 sc->type_str,isa16bit,memsize,isa_dev->id_msize);
452 for (i=0; i<8; i++)
453 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
454#endif
455 /*
456 * Allow the user to override the autoconfiguration
457 */
458 if (isa_dev->id_msize)
459 memsize = isa_dev->id_msize;
460 /*
461 * (note that if the user specifies both of the following flags
462 * that '8bit' mode intentionally has precedence)
463 */
464 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
465 isa16bit = 1;
466 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
467 isa16bit = 0;
468
469 /*
470 * Check 83C584 interrupt configuration register if this board has one
471 * XXX - we could also check the IO address register. But why
472 * bother...if we get past this, it *has* to be correct.
473 */
474 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
475 /*
476 * Assemble together the encoded interrupt number.
477 */
478 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
479 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
480 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
481 /*
482 * Translate it using translation table, and check for correctness.
483 */
484 if (ed_intr_mask[iptr] != isa_dev->id_irq) {
485 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n",
486 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1);
487 return(0);
488 }
489 /*
490 * Enable the interrupt.
491 */
492 outb(isa_dev->id_iobase + ED_WD_IRR,
493 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
494 }
495 if (sc->is790) {
496 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80);
497 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) |
498 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4);
499 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80);
500
501 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) {
502 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n",
503 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr);
504 return 0;
505 }
506 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01);
507 }
508
509 sc->isa16bit = isa16bit;
510
511#ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */
512 /*
513 * The following allows the WD/SMC boards to be used in Programmed I/O
514 * mode - without mapping the NIC memory shared. ...Not the prefered
515 * way, but it might be the only way.
516 */
517 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) {
518 sc->mem_shared = 0;
519 isa_dev->id_maddr = 0;
520 } else {
521 sc->mem_shared = 1;
522 }
523#else
524 sc->mem_shared = 1;
525#endif
526 isa_dev->id_msize = memsize;
527
528 sc->mem_start = (caddr_t)isa_dev->id_maddr;
529
530 /*
531 * allocate one xmit buffer if < 16k, two buffers otherwise
532 */
533 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
534 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
535 sc->txb_cnt = 1;
536 sc->rec_page_start = ED_TXBUF_SIZE;
537 } else {
538 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2);
539 sc->txb_cnt = 2;
540 sc->rec_page_start = ED_TXBUF_SIZE * 2;
541 }
542 sc->mem_size = memsize;
543 sc->mem_end = sc->mem_start + memsize;
544 sc->rec_page_stop = memsize / ED_PAGE_SIZE;
545 sc->tx_page_start = ED_WD_PAGE_OFFSET;
546
547 /*
548 * Get station address from on-board ROM
549 */
550 for (i = 0; i < ETHER_ADDR_LEN; ++i)
551 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
552
553 if (sc->mem_shared) {
554 /*
555 * Set address and enable interface shared memory.
556 */
557 if(!sc->is790) {
558 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
559 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
560 } else {
561 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
562 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
563 outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
564 ((kvtop(sc->mem_start) >> 11) & 0x40) |
565 (inb(sc->asic_addr + 0x0b) & 0xb0));
566 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
567 }
568
569 /*
570 * Set upper address bits and 8/16 bit access to shared memory
571 */
572 if (isa16bit) {
573 if (sc->is790) {
574 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
575 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
576 } else {
577 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
578 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
579 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
580 }
581 } else {
582 if ((sc->type & ED_WD_SOFTCONFIG) || (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) {
583 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
584 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
585 }
586 }
587
588 /*
589 * Now zero memory and verify that it is clear
590 */
591 bzero(sc->mem_start, memsize);
592
593 for (i = 0; i < memsize; ++i)
594 if (sc->mem_start[i]) {
595 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
596 isa_dev->id_unit, kvtop(sc->mem_start + i));
597
598 /*
599 * Disable 16 bit access to shared memory
600 */
601 if (isa16bit)
602 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
603 ~ED_WD_LAAR_M16EN));
604
605 return(0);
606 }
607
608 /*
609 * Disable 16bit access to shared memory - we leave it disabled so
610 * that 1) machines reboot properly when the board is set
611 * 16 bit mode and there are conflicting 8bit devices/ROMS
612 * in the same 128k address space as this boards shared
613 * memory. and 2) so that other 8 bit devices with shared
614 * memory can be used in this 128k region, too.
615 */
616 if (isa16bit)
617 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
618 ~ED_WD_LAAR_M16EN));
619
620 }
621
622 return (ED_WD_IO_PORTS);
623}
624
625/*
626 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
627 */
628int
629ed_probe_3Com(isa_dev)
630 struct isa_device *isa_dev;
631{
632 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
633 int i;
634 u_int memsize;
635 u_char isa16bit, sum;
636
637 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
638 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
639
640 /*
641 * Verify that the kernel configured I/O address matches the board
642 * configured address
643 */
644 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
645 case ED_3COM_BCFR_300:
646 if (isa_dev->id_iobase != 0x300)
647 return(0);
648 break;
649 case ED_3COM_BCFR_310:
650 if (isa_dev->id_iobase != 0x310)
651 return(0);
652 break;
653 case ED_3COM_BCFR_330:
654 if (isa_dev->id_iobase != 0x330)
655 return(0);
656 break;
657 case ED_3COM_BCFR_350:
658 if (isa_dev->id_iobase != 0x350)
659 return(0);
660 break;
661 case ED_3COM_BCFR_250:
662 if (isa_dev->id_iobase != 0x250)
663 return(0);
664 break;
665 case ED_3COM_BCFR_280:
666 if (isa_dev->id_iobase != 0x280)
667 return(0);
668 break;
669 case ED_3COM_BCFR_2A0:
670 if (isa_dev->id_iobase != 0x2a0)
671 return(0);
672 break;
673 case ED_3COM_BCFR_2E0:
674 if (isa_dev->id_iobase != 0x2e0)
675 return(0);
676 break;
677 default:
678 return(0);
679 }
680
681 /*
682 * Verify that the kernel shared memory address matches the
683 * board configured address.
684 */
685 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
686 case ED_3COM_PCFR_DC000:
687 if (kvtop(isa_dev->id_maddr) != 0xdc000)
688 return(0);
689 break;
690 case ED_3COM_PCFR_D8000:
691 if (kvtop(isa_dev->id_maddr) != 0xd8000)
692 return(0);
693 break;
694 case ED_3COM_PCFR_CC000:
695 if (kvtop(isa_dev->id_maddr) != 0xcc000)
696 return(0);
697 break;
698 case ED_3COM_PCFR_C8000:
699 if (kvtop(isa_dev->id_maddr) != 0xc8000)
700 return(0);
701 break;
702 default:
703 return(0);
704 }
705
706
707 /*
708 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
709 * sequence because it'll lock up if the cable isn't connected
710 * if we don't.
711 */
712 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
713
714 /*
715 * Wait for a while, then un-reset it
716 */
717 DELAY(50);
718 /*
719 * The 3Com ASIC defaults to rather strange settings for the CR after
720 * a reset - it's important to set it again after the following
721 * outb (this is done when we map the PROM below).
722 */
723 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
724
725 /*
726 * Wait a bit for the NIC to recover from the reset
727 */
728 DELAY(5000);
729
730 sc->vendor = ED_VENDOR_3COM;
731 sc->type_str = "3c503";
732
733 sc->mem_shared = 1;
734
735 /*
736 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k
737 * window to it.
738 */
739 memsize = 8192;
740
741 /*
742 * Get station address from on-board ROM
743 */
744 /*
745 * First, map ethernet address PROM over the top of where the NIC
746 * registers normally appear.
747 */
748 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
749
750 for (i = 0; i < ETHER_ADDR_LEN; ++i)
751 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
752
753 /*
754 * Unmap PROM - select NIC registers. The proper setting of the
755 * tranceiver is set in ed_init so that the attach code
756 * is given a chance to set the default based on a compile-time
757 * config option
758 */
759 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
760
761 /*
762 * Determine if this is an 8bit or 16bit board
763 */
764
765 /*
766 * select page 0 registers
767 */
768 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
769
770 /*
771 * Attempt to clear WTS bit. If it doesn't clear, then this is a
772 * 16bit board.
773 */
774 outb(sc->nic_addr + ED_P0_DCR, 0);
775
776 /*
777 * select page 2 registers
778 */
779 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP);
780
781 /*
782 * The 3c503 forces the WTS bit to a one if this is a 16bit board
783 */
784 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
785 isa16bit = 1;
786 else
787 isa16bit = 0;
788
789 /*
790 * select page 0 registers
791 */
792 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP);
793
794 sc->mem_start = (caddr_t)isa_dev->id_maddr;
795 sc->mem_size = memsize;
796 sc->mem_end = sc->mem_start + memsize;
797
798 /*
799 * We have an entire 8k window to put the transmit buffers on the
800 * 16bit boards. But since the 16bit 3c503's shared memory
801 * is only fast enough to overlap the loading of one full-size
802 * packet, trying to load more than 2 buffers can actually
803 * leave the transmitter idle during the load. So 2 seems
804 * the best value. (Although a mix of variable-sized packets
805 * might change this assumption. Nonetheless, we optimize for
806 * linear transfers of same-size packets.)
807 */
808 if (isa16bit) {
809 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
810 sc->txb_cnt = 1;
811 else
812 sc->txb_cnt = 2;
813
814 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
815 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
816 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
817 ED_3COM_RX_PAGE_OFFSET_16BIT;
818 sc->mem_ring = sc->mem_start;
819 } else {
820 sc->txb_cnt = 1;
821 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
822 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
823 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
824 ED_3COM_TX_PAGE_OFFSET_8BIT;
825 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
826 }
827
828 sc->isa16bit = isa16bit;
829
830 /*
831 * Initialize GA page start/stop registers. Probably only needed
832 * if doing DMA, but what the hell.
833 */
834 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
835 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
836
837 /*
838 * Set IRQ. 3c503 only allows a choice of irq 2-5.
839 */
840 switch (isa_dev->id_irq) {
841 case IRQ2:
842 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
843 break;
844 case IRQ3:
845 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
846 break;
847 case IRQ4:
848 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
849 break;
850 case IRQ5:
851 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
852 break;
853 default:
854 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n",
855 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
856 return(0);
857 }
858
859 /*
860 * Initialize GA configuration register. Set bank and enable shared mem.
861 */
862 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
863 ED_3COM_GACFR_MBS0);
864
865 /*
866 * Initialize "Vector Pointer" registers. These gawd-awful things
867 * are compared to 20 bits of the address on ISA, and if they
868 * match, the shared memory is disabled. We set them to
869 * 0xffff0...allegedly the reset vector.
870 */
871 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
872 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
873 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
874
875 /*
876 * Zero memory and verify that it is clear
877 */
878 bzero(sc->mem_start, memsize);
879
880 for (i = 0; i < memsize; ++i)
881 if (sc->mem_start[i]) {
882 printf("ed%d: failed to clear shared memory at %x - check configuration\n",
883 isa_dev->id_unit, kvtop(sc->mem_start + i));
884 return(0);
885 }
886
887 isa_dev->id_msize = memsize;
888 return(ED_3COM_IO_PORTS);
889}
890
891/*
892 * Probe and vendor-specific initialization routine for NE1000/2000 boards
893 */
894int
895ed_probe_Novell(isa_dev)
896 struct isa_device *isa_dev;
897{
898 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
899 u_int memsize, n;
900 u_char romdata[16], isa16bit = 0, tmp;
901 static char test_pattern[32] = "THIS is A memory TEST pattern";
902 char test_buffer[32];
903
904 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET;
905 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET;
906
907 /* XXX - do Novell-specific probe here */
908
909 /* Reset the board */
910 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
911
912#if 0
913 /*
914 * This total and completely screwy thing is to work around braindamage
915 * in some NE compatible boards. Why it works, I have *no* idea.
916 * It appears that the boards watch the ISA bus for an outb, and
917 * will lock up the ISA bus if they see an inb first. Weird.
918 */
919 outb(0x84, 0);
920#endif
921
922 /*
923 * I don't know if this is necessary; probably cruft leftover from
924 * Clarkson packet driver code. Doesn't do a thing on the boards
925 * I've tested. -DG [note that a outb(0x84, 0) seems to work
926 * here, and is non-invasive...but some boards don't seem to reset
927 * and I don't have complete documentation on what the 'right'
928 * thing to do is...so we do the invasive thing for now. Yuck.]
929 */
930 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
931 DELAY(5000);
932
933 /*
934 * This is needed because some NE clones apparently don't reset the
935 * NIC properly (or the NIC chip doesn't reset fully on power-up)
936 * XXX - this makes the probe invasive! ...Done against my better
937 * judgement. -DLG
938 */
939 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
940
941 DELAY(5000);
942
943 /* Make sure that we really have an 8390 based board */
944 if (!ed_probe_generic8390(sc))
945 return(0);
946
947 sc->vendor = ED_VENDOR_NOVELL;
948 sc->mem_shared = 0;
949 isa_dev->id_maddr = 0;
950
951 /*
952 * Test the ability to read and write to the NIC memory. This has
953 * the side affect of determining if this is an NE1000 or an NE2000.
954 */
955
956 /*
957 * This prevents packets from being stored in the NIC memory when
958 * the readmem routine turns on the start bit in the CR.
959 */
960 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
961
962 /* Temporarily initialize DCR for byte operations */
963 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
964
965 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
966 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
967
968 sc->isa16bit = 0;
969
970 /*
971 * Write a test pattern in byte mode. If this fails, then there
972 * probably isn't any memory at 8k - which likely means
973 * that the board is an NE2000.
974 */
975 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
976 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
977
978 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
979 /* not an NE1000 - try NE2000 */
980
981 outb(sc->nic_addr + ED_P0_DCR,
982 ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS);
983 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
984 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
985
986 sc->isa16bit = 1;
987 /*
988 * Write a test pattern in word mode. If this also fails, then
989 * we don't know what this board is.
990 */
991 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
992 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
993
994 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
995 return(0); /* not an NE2000 either */
996
997 sc->type = ED_TYPE_NE2000;
998 sc->type_str = "NE2000";
999 } else {
1000 sc->type = ED_TYPE_NE1000;
1001 sc->type_str = "NE1000";
1002 }
1003
1004 /* 8k of memory plus an additional 8k if 16bit */
1005 memsize = 8192 + sc->isa16bit * 8192;
1006
1007#if 0 /* probably not useful - NE boards only come two ways */
1008 /* allow kernel config file overrides */
1009 if (isa_dev->id_msize)
1010 memsize = isa_dev->id_msize;
1011#endif
1012
1013 sc->mem_size = memsize;
1014
1015 /* NIC memory doesn't start at zero on an NE board */
1016 /* The start address is tied to the bus width */
1017 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1018 sc->mem_end = sc->mem_start + memsize;
1019 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1020
1021 /*
1022 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1023 * otherwise).
1024 */
1025 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING))
1026 sc->txb_cnt = 1;
1027 else
1028 sc->txb_cnt = 2;
1029
1030 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1031 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1032
1033 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1034
1035 ed_pio_readmem(sc, 0, romdata, 16);
1036 for (n = 0; n < ETHER_ADDR_LEN; n++)
1037 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)];
1038
1039 /* clear any pending interrupts that might have occurred above */
1040 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1041
1042 return(ED_NOVELL_IO_PORTS);
1043}
1044
1045/*
1046 * Install interface into kernel networking data structures
1047 */
1048int
1049ed_attach(isa_dev)
1050 struct isa_device *isa_dev;
1051{
1052 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1053 struct ifnet *ifp = &sc->arpcom.ac_if;
1054 struct ifaddr *ifa;
1055 struct sockaddr_dl *sdl;
1056
1057 /*
1058 * Set interface to stopped condition (reset)
1059 */
1060 ed_stop(isa_dev->id_unit);
1061
1062 /*
1063 * Initialize ifnet structure
1064 */
1065 ifp->if_unit = isa_dev->id_unit;
1066 ifp->if_name = "ed" ;
1067 ifp->if_mtu = ETHERMTU;
1068 ifp->if_init = ed_init;
1069 ifp->if_output = ether_output;
1070 ifp->if_start = ed_start;
1071 ifp->if_ioctl = ed_ioctl;
1072 ifp->if_reset = ed_reset;
1073 ifp->if_watchdog = ed_watchdog;
1074
1075 /*
1076 * Set default state for ALTPHYS flag (used to disable the tranceiver
1077 * for AUI operation), based on compile-time config option.
1078 */
1079 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER)
1080 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS
1081 | IFF_ALTPHYS);
1082 else
1083 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
1084
1085 /*
1086 * Attach the interface
1087 */
1088 if_attach(ifp);
1089
1090 /*
1091 * Search down the ifa address list looking for the AF_LINK type entry
1092 */
1093 ifa = ifp->if_addrlist;
1094 while ((ifa != 0) && (ifa->ifa_addr != 0) &&
1095 (ifa->ifa_addr->sa_family != AF_LINK))
1096 ifa = ifa->ifa_next;
1097 /*
1098 * If we find an AF_LINK type entry we fill in the hardware address.
1099 * This is useful for netstat(1) to keep track of which interface
1100 * is which.
1101 */
1102 if ((ifa != 0) && (ifa->ifa_addr != 0)) {
1103 /*
1104 * Fill in the link-level address for this interface
1105 */
1106 sdl = (struct sockaddr_dl *)ifa->ifa_addr;
1107 sdl->sdl_type = IFT_ETHER;
1108 sdl->sdl_alen = ETHER_ADDR_LEN;
1109 sdl->sdl_slen = 0;
1110 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
1111 }
1112
1113 /*
1114 * Print additional info when attached
1115 */
1116 printf("ed%d: address %s, ", isa_dev->id_unit,
1117 ether_sprintf(sc->arpcom.ac_enaddr));
1118
1119 if (sc->type_str && (*sc->type_str != 0))
1120 printf("type %s ", sc->type_str);
1121 else
1122 printf("type unknown (0x%x) ", sc->type);
1123
1124 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)");
1125
1126 printf("%s\n", ((sc->vendor == ED_VENDOR_3COM) &&
1127 (ifp->if_flags & IFF_ALTPHYS)) ? "tranceiver disabled" : "");
1128
1129 /*
1130 * If BPF is in the kernel, call the attach for it
1131 */
1132#if NBPFILTER > 0
1133 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
1134#endif
1135 return 1;
1136}
1137
1138/*
1139 * Reset interface.
1140 */
1141void
1142ed_reset(unit, uban)
1143 int unit;
1144 int uban; /* XXX */
1145{
1146 int s;
1147
1148 s = splimp();
1149
1150 /*
1151 * Stop interface and re-initialize.
1152 */
1153 ed_stop(unit);
1154 ed_init(unit);
1155
1156 (void) splx(s);
1157}
1158
1159/*
1160 * Take interface offline.
1161 */
1162void
1163ed_stop(unit)
1164 int unit;
1165{
1166 struct ed_softc *sc = &ed_softc[unit];
1167 int n = 5000;
1168
1169 /*
1170 * Stop everything on the interface, and select page 0 registers.
1171 */
1172 if (sc->is790) {
1173 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1174 } else {
1175 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1176 }
1177 /*
1178 * Wait for interface to enter stopped state, but limit # of checks
1179 * to 'n' (about 5ms). It shouldn't even take 5us on modern
1180 * DS8390's, but just in case it's an old one.
1181 */
1182 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1183
1184}
1185
1186/*
1187 * Device timeout/watchdog routine. Entered if the device neglects to
1188 * generate an interrupt after a transmit has been started on it.
1189 */
1190void
1191ed_watchdog(unit)
1192 int unit;
1193{
1194 struct ed_softc *sc = &ed_softc[unit];
1195
1196 log(LOG_ERR, "ed%d: device timeout\n", unit);
1197 ++sc->arpcom.ac_if.if_oerrors;
1198
1199 ed_reset(unit, 0);
1200}
1201
1202/*
1203 * Initialize device.
1204 */
1205void
1206ed_init(unit)
1207 int unit;
1208{
1209 struct ed_softc *sc = &ed_softc[unit];
1210 struct ifnet *ifp = &sc->arpcom.ac_if;
1211 int i, s;
1212 u_char command;
1213
1214
1215 /* address not known */
1216 if (ifp->if_addrlist == (struct ifaddr *)0) return;
1217
1218 /*
1219 * Initialize the NIC in the exact order outlined in the NS manual.
1220 * This init procedure is "mandatory"...don't change what or when
1221 * things happen.
1222 */
1223 s = splimp();
1224
1225 /* reset transmitter flags */
1226 sc->xmit_busy = 0;
1227 sc->arpcom.ac_if.if_timer = 0;
1228
1229 sc->txb_inuse = 0;
1230 sc->txb_new = 0;
1231 sc->txb_next_tx = 0;
1232
1233 /* This variable is used below - don't move this assignment */
1234 sc->next_packet = sc->rec_page_start + 1;
1235
1236 /*
1237 * Set interface for page 0, Remote DMA complete, Stopped
1238 */
1239 if (sc->is790) {
1240 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP);
1241 } else {
1242 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP);
1243 }
1244 if (sc->isa16bit) {
1245 /*
1246 * Set FIFO threshold to 8, No auto-init Remote DMA,
1247 * byte order=80x86, word-wide DMA xfers,
1248 */
1249 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS);
1250 } else {
1251 /*
1252 * Same as above, but byte-wide DMA xfers
1253 */
1254 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS);
1255 }
1256
1257 /*
1258 * Clear Remote Byte Count Registers
1259 */
1260 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1261 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1262
1263 /*
1264 * Enable reception of broadcast packets
1265 */
1266 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
1267
1268 /*
1269 * Place NIC in internal loopback mode
1270 */
1271 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1272
1273 /*
1274 * Initialize transmit/receive (ring-buffer) Page Start
1275 */
1276 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1277 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1278 /* Set lower bits of byte addressable framing to 0 */
1279 if (sc->is790)
1280 outb(sc->nic_addr + 0x09, 0);
1281
1282 /*
1283 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1284 */
1285 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1286 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1287
1288 /*
1289 * Clear all interrupts. A '1' in each bit position clears the
1290 * corresponding flag.
1291 */
1292 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1293
1294 /*
1295 * Enable the following interrupts: receive/transmit complete,
1296 * receive/transmit error, and Receiver OverWrite.
1297 *
1298 * Counter overflow and Remote DMA complete are *not* enabled.
1299 */
1300 outb(sc->nic_addr + ED_P0_IMR,
1301 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE);
1302
1303 /*
1304 * Program Command Register for page 1
1305 */
1306 if (sc->is790) {
1307 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP);
1308 } else {
1309 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP);
1310 }
1311 /*
1312 * Copy out our station address
1313 */
1314 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1315 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1316
1317#if NBPFILTER > 0
1318 /*
1319 * Initialize multicast address hashing registers to accept
1320 * all multicasts (only used when in promiscuous mode)
1321 */
1322 for (i = 0; i < 8; ++i)
1323 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
1324#endif
1325
1326 /*
1327 * Set Current Page pointer to next_packet (initialized above)
1328 */
1329 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1330
1331 /*
1332 * Set Command Register for page 0, Remote DMA complete,
1333 * and interface Start.
1334 */
1335 if (sc->is790) {
1336 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA);
1337 } else {
1338 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA);
1339 }
1340 /*
1341 * Take interface out of loopback
1342 */
1343 outb(sc->nic_addr + ED_P0_TCR, 0);
1344
1345 /*
1346 * If this is a 3Com board, the tranceiver must be software enabled
1347 * (there is no settable hardware default).
1348 */
1349 if (sc->vendor == ED_VENDOR_3COM) {
1350 if (ifp->if_flags & IFF_ALTPHYS) {
1351 outb(sc->asic_addr + ED_3COM_CR, 0);
1352 } else {
1353 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1354 }
1355 }
1356
1357 /*
1358 * Set 'running' flag, and clear output active flag.
1359 */
1360 ifp->if_flags |= IFF_RUNNING;
1361 ifp->if_flags &= ~IFF_OACTIVE;
1362
1363 /*
1364 * ...and attempt to start output
1365 */
1366 ed_start(ifp);
1367
1368 (void) splx(s);
1369}
1370
1371/*
1372 * This routine actually starts the transmission on the interface
1373 */
1374static inline void ed_xmit(ifp)
1375 struct ifnet *ifp;
1376{
1377 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1378 unsigned short len;
1379
1380 len = sc->txb_len[sc->txb_next_tx];
1381
1382 /*
1383 * Set NIC for page 0 register access
1384 */
1385 if (sc->is790) {
1386 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1387 } else {
1388 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1389 }
1390 /*
1391 * Set TX buffer start page
1392 */
1393 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
1394 sc->txb_next_tx * ED_TXBUF_SIZE);
1395
1396 /*
1397 * Set TX length
1398 */
1399 outb(sc->nic_addr + ED_P0_TBCR0, len);
1400 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
1401
1402 /*
1403 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1404 */
1405 if (sc->is790) {
1406 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA);
1407 } else {
1408 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA);
1409 }
1410 sc->xmit_busy = 1;
1411
1412 /*
1413 * Point to next transmit buffer slot and wrap if necessary.
1414 */
1415 sc->txb_next_tx++;
1416 if (sc->txb_next_tx == sc->txb_cnt)
1417 sc->txb_next_tx = 0;
1418
1419 /*
1420 * Set a timer just in case we never hear from the board again
1421 */
1422 ifp->if_timer = 2;
1423}
1424
1425/*
1426 * Start output on interface.
1427 * We make two assumptions here:
1428 * 1) that the current priority is set to splimp _before_ this code
1429 * is called *and* is returned to the appropriate priority after
1430 * return
1431 * 2) that the IFF_OACTIVE flag is checked before this code is called
1432 * (i.e. that the output part of the interface is idle)
1433 */
1434void
1435ed_start(ifp)
1436 struct ifnet *ifp;
1437{
1438 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1439 struct mbuf *m0, *m;
1440 caddr_t buffer;
1441 int len;
1442
1443outloop:
1444 /*
1445 * First, see if there are buffered packets and an idle
1446 * transmitter - should never happen at this point.
1447 */
1448 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1449 printf("ed: packets buffers, but transmitter idle\n");
1450 ed_xmit(ifp);
1451 }
1452
1453 /*
1454 * See if there is room to put another packet in the buffer.
1455 */
1456 if (sc->txb_inuse == sc->txb_cnt) {
1457 /*
1458 * No room. Indicate this to the outside world
1459 * and exit.
1460 */
1461 ifp->if_flags |= IFF_OACTIVE;
1462 return;
1463 }
1464
1465 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
1466 if (m == 0) {
1467 /*
1468 * We are using the !OACTIVE flag to indicate to the outside
1469 * world that we can accept an additional packet rather than
1470 * that the transmitter is _actually_ active. Indeed, the
1471 * transmitter may be active, but if we haven't filled all
1472 * the buffers with data then we still want to accept more.
1473 */
1474 ifp->if_flags &= ~IFF_OACTIVE;
1475 return;
1476 }
1477
1478 /*
1479 * Copy the mbuf chain into the transmit buffer
1480 */
1481
1482 m0 = m;
1483
1484 /* txb_new points to next open buffer slot */
1485 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
1486
1487 if (sc->mem_shared) {
1488 /*
1489 * Special case setup for 16 bit boards...
1490 */
1491 if (sc->isa16bit) {
1492 switch (sc->vendor) {
1493 /*
1494 * For 16bit 3Com boards (which have 16k of memory),
1495 * we have the xmit buffers in a different page
1496 * of memory ('page 0') - so change pages.
1497 */
1498 case ED_VENDOR_3COM:
1499 outb(sc->asic_addr + ED_3COM_GACFR,
1500 ED_3COM_GACFR_RSEL);
1501 break;
1502 /*
1503 * Enable 16bit access to shared memory on WD/SMC boards
1504 * Don't update wd_laar_proto because we want to restore the
1505 * previous state (because an arp reply in the input code
1506 * may cause a call-back to ed_start)
1507 * XXX - the call-back to 'start' is a bug, IMHO.
1508 */
1509 case ED_VENDOR_WD_SMC:
1510 outb(sc->asic_addr + ED_WD_LAAR,
1511 (sc->wd_laar_proto | ED_WD_LAAR_M16EN));
1512 }
1513 }
1514
1515 for (len = 0; m != 0; m = m->m_next) {
1516 bcopy(mtod(m, caddr_t), buffer, m->m_len);
1517 buffer += m->m_len;
1518 len += m->m_len;
1519 }
1520
1521 /*
1522 * Restore previous shared memory access
1523 */
1524 if (sc->isa16bit) {
1525 switch (sc->vendor) {
1526 case ED_VENDOR_3COM:
1527 outb(sc->asic_addr + ED_3COM_GACFR,
1528 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
1529 break;
1530 case ED_VENDOR_WD_SMC:
1531 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
1532 break;
1533 }
1534 }
1535 } else {
1536 len = ed_pio_write_mbufs(sc, m, buffer);
1537 }
1538
1539 sc->txb_len[sc->txb_new] = MAX(len, ETHER_MIN_LEN);
1540
1541 sc->txb_inuse++;
1542
1543 /*
1544 * Point to next buffer slot and wrap if necessary.
1545 */
1546 sc->txb_new++;
1547 if (sc->txb_new == sc->txb_cnt)
1548 sc->txb_new = 0;
1549
1550 if (sc->xmit_busy == 0)
1551 ed_xmit(ifp);
1552 /*
1553 * If there is BPF support in the configuration, tap off here.
1554 * The following has support for converting trailer packets
1555 * back to normal.
1556 * XXX - support for trailer packets in BPF should be moved into
1557 * the bpf code proper to avoid code duplication in all of
1558 * the drivers.
1559 */
1560#if NBPFILTER > 0
1561 if (sc->bpf) {
1562 u_short etype;
1563 int off, datasize, resid;
1564 struct ether_header *eh;
1565 struct trailer_header trailer_header;
1566 char ether_packet[ETHER_MAX_LEN];
1567 char *ep;
1568
1569 ep = ether_packet;
1570
1571 /*
1572 * We handle trailers below:
1573 * Copy ether header first, then residual data,
1574 * then data. Put all this in a temporary buffer
1575 * 'ether_packet' and send off to bpf. Since the
1576 * system has generated this packet, we assume
1577 * that all of the offsets in the packet are
1578 * correct; if they're not, the system will almost
1579 * certainly crash in m_copydata.
1580 * We make no assumptions about how the data is
1581 * arranged in the mbuf chain (i.e. how much
1582 * data is in each mbuf, if mbuf clusters are
1583 * used, etc.), which is why we use m_copydata
1584 * to get the ether header rather than assume
1585 * that this is located in the first mbuf.
1586 */
1587 /* copy ether header */
1588 m_copydata(m0, 0, sizeof(struct ether_header), ep);
1589 eh = (struct ether_header *) ep;
1590 ep += sizeof(struct ether_header);
1591 etype = ntohs(eh->ether_type);
1592 if (etype >= ETHERTYPE_TRAIL &&
1593 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
1594 datasize = ((etype - ETHERTYPE_TRAIL) << 9);
1595 off = datasize + sizeof(struct ether_header);
1596
1597 /* copy trailer_header into a data structure */
1598 m_copydata(m0, off, sizeof(struct trailer_header),
1599 &trailer_header.ether_type);
1600
1601 /* copy residual data */
1602 m_copydata(m0, off+sizeof(struct trailer_header),
1603 resid = ntohs(trailer_header.ether_residual) -
1604 sizeof(struct trailer_header), ep);
1605 ep += resid;
1606
1607 /* copy data */
1608 m_copydata(m0, sizeof(struct ether_header),
1609 datasize, ep);
1610 ep += datasize;
1611
1612 /* restore original ether packet type */
1613 eh->ether_type = trailer_header.ether_type;
1614
1615 bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
1616 } else
1617 bpf_mtap(sc->bpf, m0);
1618 }
1619#endif
1620
1621 m_freem(m0);
1622
1623 /*
1624 * Loop back to the top to possibly buffer more packets
1625 */
1626 goto outloop;
1627}
1628
1629/*
1630 * Ethernet interface receiver interrupt.
1631 */
1632static inline void
1633ed_rint(unit)
1634 int unit;
1635{
1636 register struct ed_softc *sc = &ed_softc[unit];
1637 u_char boundry, current;
1638 u_short len;
1639 struct ed_ring packet_hdr;
1640 char *packet_ptr;
1641
1642 /*
1643 * Set NIC to page 1 registers to get 'current' pointer
1644 */
1645 if (sc->is790) {
1646 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1647 } else {
1648 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1649 }
1650 /*
1651 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
1652 * it points to where new data has been buffered. The 'CURR'
1653 * (current) register points to the logical end of the ring-buffer
1654 * - i.e. it points to where additional new data will be added.
1655 * We loop here until the logical beginning equals the logical
1656 * end (or in other words, until the ring-buffer is empty).
1657 */
1658 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
1659
1660 /* get pointer to this buffer's header structure */
1661 packet_ptr = sc->mem_ring +
1662 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
1663
1664 /*
1665 * The byte count includes the FCS - Frame Check Sequence (a
1666 * 32 bit CRC).
1667 */
1668 if (sc->mem_shared)
1669 packet_hdr = *(struct ed_ring *)packet_ptr;
1670 else
1671 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr,
1672 sizeof(packet_hdr));
1673 len = packet_hdr.count;
1674 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
1675 /*
1676 * Go get packet. len - 4 removes CRC from length.
1677 */
1678 ed_get_packet(sc, packet_ptr + 4, len - 4);
1679 ++sc->arpcom.ac_if.if_ipackets;
1680 } else {
1681 /*
1682 * Really BAD...probably indicates that the ring pointers
1683 * are corrupted. Also seen on early rev chips under
1684 * high load - the byte order of the length gets switched.
1685 */
1686 log(LOG_ERR,
1687 "ed%d: NIC memory corrupt - invalid packet length %d\n",
1688 unit, len);
1689 ++sc->arpcom.ac_if.if_ierrors;
1690 ed_reset(unit, 0);
1691 return;
1692 }
1693
1694 /*
1695 * Update next packet pointer
1696 */
1697 sc->next_packet = packet_hdr.next_packet;
1698
1699 /*
1700 * Update NIC boundry pointer - being careful to keep it
1701 * one buffer behind. (as recommended by NS databook)
1702 */
1703 boundry = sc->next_packet - 1;
1704 if (boundry < sc->rec_page_start)
1705 boundry = sc->rec_page_stop - 1;
1706
1707 /*
1708 * Set NIC to page 0 registers to update boundry register
1709 */
1710 if (sc->is790) {
1711 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1712 } else {
1713 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1714 }
1715 outb(sc->nic_addr + ED_P0_BNRY, boundry);
1716
1717 /*
1718 * Set NIC to page 1 registers before looping to top (prepare to
1719 * get 'CURR' current pointer)
1720 */
1721 if (sc->is790) {
1722 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA);
1723 } else {
1724 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA);
1725 }
1726 }
1727}
1728
1729/*
1730 * Ethernet interface interrupt processor
1731 */
1732void
1733edintr(unit)
1734 int unit;
1735{
1736 struct ed_softc *sc = &ed_softc[unit];
1737 u_char isr;
1738
1739 /*
1740 * Set NIC to page 0 registers
1741 */
1742 if (sc->is790) {
1743 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1744 } else {
1745 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1746 }
1747 /*
1748 * loop until there are no more new interrupts
1749 */
1750 while (isr = inb(sc->nic_addr + ED_P0_ISR)) {
1751
1752 /*
1753 * reset all the bits that we are 'acknowledging'
1754 * by writing a '1' to each bit position that was set
1755 * (writing a '1' *clears* the bit)
1756 */
1757 outb(sc->nic_addr + ED_P0_ISR, isr);
1758
1759 /*
1760 * Handle transmitter interrupts. Handle these first
1761 * because the receiver will reset the board under
1762 * some conditions.
1763 */
1764 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) {
1765 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
1766
1767 /*
1768 * Check for transmit error. If a TX completed with an
1769 * error, we end up throwing the packet away. Really
1770 * the only error that is possible is excessive
1771 * collisions, and in this case it is best to allow the
1772 * automatic mechanisms of TCP to backoff the flow. Of
1773 * course, with UDP we're screwed, but this is expected
1774 * when a network is heavily loaded.
1775 */
1776 (void) inb(sc->nic_addr + ED_P0_TSR);
1777 if (isr & ED_ISR_TXE) {
1778
1779 /*
1780 * Excessive collisions (16)
1781 */
1782 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT)
1783 && (collisions == 0)) {
1784 /*
1785 * When collisions total 16, the
1786 * P0_NCR will indicate 0, and the
1787 * TSR_ABT is set.
1788 */
1789 collisions = 16;
1790 }
1791
1792 /*
1793 * update output errors counter
1794 */
1795 ++sc->arpcom.ac_if.if_oerrors;
1796 } else {
1797 /*
1798 * Update total number of successfully
1799 * transmitted packets.
1800 */
1801 ++sc->arpcom.ac_if.if_opackets;
1802 }
1803
1804 /*
1805 * reset tx busy and output active flags
1806 */
1807 sc->xmit_busy = 0;
1808 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
1809
1810 /*
1811 * clear watchdog timer
1812 */
1813 sc->arpcom.ac_if.if_timer = 0;
1814
1815 /*
1816 * Add in total number of collisions on last
1817 * transmission.
1818 */
1819 sc->arpcom.ac_if.if_collisions += collisions;
1820
1821 /*
1822 * Decrement buffer in-use count if not zero (can only
1823 * be zero if a transmitter interrupt occured while
1824 * not actually transmitting).
1825 * If data is ready to transmit, start it transmitting,
1826 * otherwise defer until after handling receiver
1827 */
1828 if (sc->txb_inuse && --sc->txb_inuse)
1829 ed_xmit(&sc->arpcom.ac_if);
1830 }
1831
1832 /*
1833 * Handle receiver interrupts
1834 */
1835 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) {
1836 /*
1837 * Overwrite warning. In order to make sure that a lockup
1838 * of the local DMA hasn't occurred, we reset and
1839 * re-init the NIC. The NSC manual suggests only a
1840 * partial reset/re-init is necessary - but some
1841 * chips seem to want more. The DMA lockup has been
1842 * seen only with early rev chips - Methinks this
1843 * bug was fixed in later revs. -DG
1844 */
1845 if (isr & ED_ISR_OVW) {
1846 ++sc->arpcom.ac_if.if_ierrors;
1847#ifdef DIAGNOSTIC
1848 log(LOG_WARNING,
1849 "ed%d: warning - receiver ring buffer overrun\n",
1850 unit);
1851#endif
1852 /*
1853 * Stop/reset/re-init NIC
1854 */
1855 ed_reset(unit, 0);
1856 } else {
1857
1858 /*
1859 * Receiver Error. One or more of: CRC error, frame
1860 * alignment error FIFO overrun, or missed packet.
1861 */
1862 if (isr & ED_ISR_RXE) {
1863 ++sc->arpcom.ac_if.if_ierrors;
1864#ifdef ED_DEBUG
1865 printf("ed%d: receive error %x\n", unit,
1866 inb(sc->nic_addr + ED_P0_RSR));
1867#endif
1868 }
1869
1870 /*
1871 * Go get the packet(s)
1872 * XXX - Doing this on an error is dubious
1873 * because there shouldn't be any data to
1874 * get (we've configured the interface to
1875 * not accept packets with errors).
1876 */
1877
1878 /*
1879 * Enable 16bit access to shared memory first
1880 * on WD/SMC boards.
1881 */
1882 if (sc->isa16bit &&
1883 (sc->vendor == ED_VENDOR_WD_SMC)) {
1884
1885 outb(sc->asic_addr + ED_WD_LAAR,
1886 (sc->wd_laar_proto |=
1887 ED_WD_LAAR_M16EN));
1888 }
1889
1890 ed_rint (unit);
1891
1892 /* disable 16bit access */
1893 if (sc->isa16bit &&
1894 (sc->vendor == ED_VENDOR_WD_SMC)) {
1895
1896 outb(sc->asic_addr + ED_WD_LAAR,
1897 (sc->wd_laar_proto &=
1898 ~ED_WD_LAAR_M16EN));
1899 }
1900 }
1901 }
1902
1903 /*
1904 * If it looks like the transmitter can take more data,
1905 * attempt to start output on the interface.
1906 * This is done after handling the receiver to
1907 * give the receiver priority.
1908 */
1909 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0)
1910 ed_start(&sc->arpcom.ac_if);
1911
1912 /*
1913 * return NIC CR to standard state: page 0, remote DMA complete,
1914 * start (toggling the TXP bit off, even if was just set
1915 * in the transmit routine, is *okay* - it is 'edge'
1916 * triggered from low to high)
1917 */
1918 if (sc->is790) {
1919 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA);
1920 } else {
1921 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
1922 }
1923 /*
1924 * If the Network Talley Counters overflow, read them to
1925 * reset them. It appears that old 8390's won't
1926 * clear the ISR flag otherwise - resulting in an
1927 * infinite loop.
1928 */
1929 if (isr & ED_ISR_CNT) {
1930 (void) inb(sc->nic_addr + ED_P0_CNTR0);
1931 (void) inb(sc->nic_addr + ED_P0_CNTR1);
1932 (void) inb(sc->nic_addr + ED_P0_CNTR2);
1933 }
1934 }
1935}
1936
1937/*
1938 * Process an ioctl request. This code needs some work - it looks
1939 * pretty ugly.
1940 */
1941int
1942ed_ioctl(ifp, command, data)
1943 register struct ifnet *ifp;
1944 int command;
1945 caddr_t data;
1946{
1947 register struct ifaddr *ifa = (struct ifaddr *)data;
1948 struct ed_softc *sc = &ed_softc[ifp->if_unit];
1949 struct ifreq *ifr = (struct ifreq *)data;
1950 int s, error = 0;
1951
1952 s = splimp();
1953
1954 switch (command) {
1955
1956 case SIOCSIFADDR:
1957 ifp->if_flags |= IFF_UP;
1958
1959 switch (ifa->ifa_addr->sa_family) {
1960#ifdef INET
1961 case AF_INET:
1962 ed_init(ifp->if_unit); /* before arpwhohas */
1963 /*
1964 * See if another station has *our* IP address.
1965 * i.e.: There is an address conflict! If a
1966 * conflict exists, a message is sent to the
1967 * console.
1968 */
1969 ((struct arpcom *)ifp)->ac_ipaddr =
1970 IA_SIN(ifa)->sin_addr;
1971 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
1972 break;
1973#endif
1974#ifdef NS
1975 /*
1976 * XXX - This code is probably wrong
1977 */
1978 case AF_NS:
1979 {
1980 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
1981
1982 if (ns_nullhost(*ina))
1983 ina->x_host =
1984 *(union ns_host *)(sc->arpcom.ac_enaddr);
1985 else {
1986 /*
1987 *
1988 */
1989 bcopy((caddr_t)ina->x_host.c_host,
1990 (caddr_t)sc->arpcom.ac_enaddr,
1991 sizeof(sc->arpcom.ac_enaddr));
1992 }
1993 /*
1994 * Set new address
1995 */
1996 ed_init(ifp->if_unit);
1997 break;
1998 }
1999#endif
2000 default:
2001 ed_init(ifp->if_unit);
2002 break;
2003 }
2004 break;
2005
2006 case SIOCSIFFLAGS:
2007 /*
2008 * If interface is marked down and it is running, then stop it
2009 */
2010 if (((ifp->if_flags & IFF_UP) == 0) &&
2011 (ifp->if_flags & IFF_RUNNING)) {
2012 ed_stop(ifp->if_unit);
2013 ifp->if_flags &= ~IFF_RUNNING;
2014 } else {
2015 /*
2016 * If interface is marked up and it is stopped, then start it
2017 */
2018 if ((ifp->if_flags & IFF_UP) &&
2019 ((ifp->if_flags & IFF_RUNNING) == 0))
2020 ed_init(ifp->if_unit);
2021 }
2022#if NBPFILTER > 0
2023 if (ifp->if_flags & IFF_PROMISC) {
2024 /*
2025 * Set promiscuous mode on interface.
2026 * XXX - for multicasts to work, we would need to
2027 * write 1's in all bits of multicast
2028 * hashing array. For now we assume that
2029 * this was done in ed_init().
2030 */
2031 outb(sc->nic_addr + ED_P0_RCR,
2032 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB);
2033 } else {
2034 /*
2035 * XXX - for multicasts to work, we would need to
2036 * rewrite the multicast hashing array with the
2037 * proper hash (would have been destroyed above).
2038 */
2039 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
2040 }
2041#endif
2042 /*
2043 * An unfortunate hack to provide the (required) software control
2044 * of the tranceiver for 3Com boards. The ALTPHYS flag disables
2045 * the tranceiver if set.
2046 */
2047 if (sc->vendor == ED_VENDOR_3COM) {
2048 if (ifp->if_flags & IFF_ALTPHYS) {
2049 outb(sc->asic_addr + ED_3COM_CR, 0);
2050 } else {
2051 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2052 }
2053 }
2054
2055 break;
2056
2057 default:
2058 error = EINVAL;
2059 }
2060 (void) splx(s);
2061 return (error);
2062}
2063
2064/*
2065 * Macro to calculate a new address within shared memory when given an offset
2066 * from an address, taking into account ring-wrap.
2067 */
2068#define ringoffset(sc, start, off, type) \
2069 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \
2070 (((caddr_t)(start)+(off))) - (sc)->mem_end \
2071 + (sc)->mem_ring: \
2072 ((caddr_t)(start)+(off)) ))
2073
2074/*
2075 * Retreive packet from shared memory and send to the next level up via
2076 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2077 */
2078static void
2079ed_get_packet(sc, buf, len)
2080 struct ed_softc *sc;
2081 char *buf;
2082 u_short len;
2083{
2084 struct ether_header *eh;
2085 struct mbuf *m, *head = 0, *ed_ring_to_mbuf();
2086 u_short off;
2087 int resid;
2088 u_short etype;
2089 struct trailer_header trailer_header;
2090
2091 /* Allocate a header mbuf */
2092 MGETHDR(m, M_DONTWAIT, MT_DATA);
2093 if (m == 0)
2094 goto bad;
2095 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2096 m->m_pkthdr.len = len;
2097 m->m_len = 0;
2098 head = m;
2099
2100 /* The following sillines is to make NFS happy */
2101#define EROUND ((sizeof(struct ether_header) + 3) & ~3)
2102#define EOFF (EROUND - sizeof(struct ether_header))
2103
2104 /*
2105 * The following assumes there is room for
2106 * the ether header in the header mbuf
2107 */
2108 head->m_data += EOFF;
2109 eh = mtod(head, struct ether_header *);
2110
2111 if (sc->mem_shared)
2112 bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
2113 else
2114 ed_pio_readmem(sc, buf, mtod(head, caddr_t),
2115 sizeof(struct ether_header));
2116 buf += sizeof(struct ether_header);
2117 head->m_len += sizeof(struct ether_header);
2118 len -= sizeof(struct ether_header);
2119
2120 etype = ntohs((u_short)eh->ether_type);
2121
2122 /*
2123 * Deal with trailer protocol:
2124 * If trailer protocol, calculate the datasize as 'off',
2125 * which is also the offset to the trailer header.
2126 * Set resid to the amount of packet data following the
2127 * trailer header.
2128 * Finally, copy residual data into mbuf chain.
2129 */
2130 if (etype >= ETHERTYPE_TRAIL &&
2131 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
2132
2133 off = (etype - ETHERTYPE_TRAIL) << 9;
2134 if ((off + sizeof(struct trailer_header)) > len)
2135 goto bad; /* insanity */
2136
2137 /*
2138 * If we have shared memory, we can get info directly from the
2139 * stored packet, otherwise we must get a local copy
2140 * of the trailer header using PIO.
2141 */
2142 if (sc->mem_shared) {
2143 eh->ether_type = *ringoffset(sc, buf, off, u_short *);
2144 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
2145 } else {
2146 struct trailer_header trailer_header;
2147 ed_pio_readmem(sc,
2148 ringoffset(sc, buf, off, caddr_t),
2149 (char *) &trailer_header,
2150 sizeof(trailer_header));
2151 eh->ether_type = trailer_header.ether_type;
2152 resid = trailer_header.ether_residual;
2153 }
2154
2155 if ((off + resid) > len) goto bad; /* insanity */
2156
2157 resid -= sizeof(struct trailer_header);
2158 if (resid < 0) goto bad; /* insanity */
2159
2160 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid);
2161 if (m == 0) goto bad;
2162
2163 len = off;
2164 head->m_pkthdr.len -= 4; /* subtract trailer header */
2165 }
2166
2167 /*
2168 * Pull packet off interface. Or if this was a trailer packet,
2169 * the data portion is appended.
2170 */
2171 m = ed_ring_to_mbuf(sc, buf, m, len);
2172 if (m == 0) goto bad;
2173
2174#if NBPFILTER > 0
2175 /*
2176 * Check if there's a BPF listener on this interface.
2177 * If so, hand off the raw packet to bpf.
2178 */
2179 if (sc->bpf) {
2180 bpf_mtap(sc->bpf, head);
2181
2182 /*
2183 * Note that the interface cannot be in promiscuous mode if
2184 * there are no BPF listeners. And if we are in promiscuous
2185 * mode, we have to check if this packet is really ours.
2186 *
2187 * XXX This test does not support multicasts.
2188 */
2189 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2190 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2191 sizeof(eh->ether_dhost)) != 0 &&
2192 bcmp(eh->ether_dhost, etherbroadcastaddr,
2193 sizeof(eh->ether_dhost)) != 0) {
2194
2195 m_freem(head);
2196 return;
2197 }
2198 }
2199#endif
2200
2201 /*
2202 * Fix up data start offset in mbuf to point past ether header
2203 */
2204 m_adj(head, sizeof(struct ether_header));
2205
2206 /*
2207 * silly ether_input routine needs 'type' in host byte order
2208 */
2209 eh->ether_type = ntohs(eh->ether_type);
2210
2211 ether_input(&sc->arpcom.ac_if, eh, head);
2212 return;
2213
2214bad: if (head)
2215 m_freem(head);
2216 return;
2217}
2218
2219/*
2220 * Supporting routines
2221 */
2222
2223/*
2224 * Given a NIC memory source address and a host memory destination
2225 * address, copy 'amount' from NIC to host using Programmed I/O.
2226 * The 'amount' is rounded up to a word - okay as long as mbufs
2227 * are word sized.
2228 * This routine is currently Novell-specific.
2229 */
2230void
2231ed_pio_readmem(sc,src,dst,amount)
2232 struct ed_softc *sc;
2233 unsigned short src;
2234 unsigned char *dst;
2235 unsigned short amount;
2236{
2237 unsigned short tmp_amount;
2238
2239 /* select page 0 registers */
2240 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2241
2242 /* round up to a word */
2243 tmp_amount = amount;
2244 if (amount & 1) ++amount;
2245
2246 /* set up DMA byte count */
2247 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2248 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8);
2249
2250 /* set up source address in NIC mem */
2251 outb(sc->nic_addr + ED_P0_RSAR0, src);
2252 outb(sc->nic_addr + ED_P0_RSAR1, src>>8);
2253
2254 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2255
2256 if (sc->isa16bit) {
2257 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2);
2258 } else
2259 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2260
2261}
2262
2263/*
2264 * Stripped down routine for writing a linear buffer to NIC memory.
2265 * Only used in the probe routine to test the memory. 'len' must
2266 * be even.
2267 */
2268void
2269ed_pio_writemem(sc,src,dst,len)
2270 struct ed_softc *sc;
2271 char *src;
2272 unsigned short dst;
2273 unsigned short len;
2274{
2275 int maxwait=100; /* about 120us */
2276
2277 /* select page 0 registers */
2278 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2279
2280 /* reset remote DMA complete flag */
2281 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2282
2283 /* set up DMA byte count */
2284 outb(sc->nic_addr + ED_P0_RBCR0, len);
2285 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2286
2287 /* set up destination address in NIC mem */
2288 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2289 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2290
2291 /* set remote DMA write */
2292 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2293
2294 if (sc->isa16bit)
2295 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2);
2296 else
2297 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2298 /*
2299 * Wait for remote DMA complete. This is necessary because on the
2300 * transmit side, data is handled internally by the NIC in bursts
2301 * and we can't start another remote DMA until this one completes.
2302 * Not waiting causes really bad things to happen - like the NIC
2303 * irrecoverably jamming the ISA bus.
2304 */
2305 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2306}
2307
2308/*
2309 * Write an mbuf chain to the destination NIC memory address using
2310 * programmed I/O.
2311 */
2312u_short
2313ed_pio_write_mbufs(sc,m,dst)
2314 struct ed_softc *sc;
2315 struct mbuf *m;
2316 unsigned short dst;
2317{
2318 unsigned short len, mb_offset;
2319 struct mbuf *mp;
2320 unsigned char residual[2];
2321 int maxwait=100; /* about 120us */
2322
2323 /* First, count up the total number of bytes to copy */
2324 for (len = 0, mp = m; mp; mp = mp->m_next)
2325 len += mp->m_len;
2326
2327 /* select page 0 registers */
2328 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA);
2329
2330 /* reset remote DMA complete flag */
2331 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2332
2333 /* set up DMA byte count */
2334 outb(sc->nic_addr + ED_P0_RBCR0, len);
2335 outb(sc->nic_addr + ED_P0_RBCR1, len>>8);
2336
2337 /* set up destination address in NIC mem */
2338 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2339 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8);
2340
2341 /* set remote DMA write */
2342 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2343
2344 mb_offset = 0;
2345 /*
2346 * Transfer the mbuf chain to the NIC memory.
2347 * The following code isn't too pretty. The problem is that we can only
2348 * transfer words to the board, and if an mbuf has an odd number
2349 * of bytes in it, this is a problem. It's not a simple matter of
2350 * just removing a byte from the next mbuf (adjusting data++ and
2351 * len--) because this will hose-over the mbuf chain which might
2352 * be needed later for BPF. Instead, we maintain an offset
2353 * (mb_offset) which let's us skip over the first byte in the
2354 * following mbuf.
2355 */
2356 while (m) {
2357 if (m->m_len - mb_offset) {
2358 if (sc->isa16bit) {
2359 if ((m->m_len - mb_offset) > 1)
2360 outsw(sc->asic_addr + ED_NOVELL_DATA,
2361 mtod(m, caddr_t) + mb_offset,
2362 (m->m_len - mb_offset) / 2);
2363
2364 /*
2365 * if odd number of bytes, get the odd byte from
2366 * the next mbuf with data
2367 */
2368 if ((m->m_len - mb_offset) & 1) {
2369 /* first the last byte in current mbuf */
2370 residual[0] = *(mtod(m, caddr_t)
2371 + m->m_len - 1);
2372
2373 /* advance past any empty mbufs */
2374 while (m->m_next && (m->m_next->m_len == 0))
2375 m = m->m_next;
2376
2377 if (m->m_next) {
2378 /* remove first byte in next mbuf */
2379 residual[1] = *(mtod(m->m_next, caddr_t));
2380 mb_offset = 1;
2381 }
2382
2383 outw(sc->asic_addr + ED_NOVELL_DATA,
2384 *((unsigned short *) residual));
2385 } else
2386 mb_offset = 0;
2387 } else
2388 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len);
2389
2390 }
2391 m = m->m_next;
2392 }
2393
2394 /*
2395 * Wait for remote DMA complete. This is necessary because on the
2396 * transmit side, data is handled internally by the NIC in bursts
2397 * and we can't start another remote DMA until this one completes.
2398 * Not waiting causes really bad things to happen - like the NIC
2399 * irrecoverably jamming the ISA bus.
2400 */
2401 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2402
2403 if (!maxwait) {
2404 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2405 sc->arpcom.ac_if.if_unit);
2406 ed_reset(sc->arpcom.ac_if.if_unit, 0);
2407 }
2408
2409 return(len);
2410}
2411
2412/*
2413 * Given a source and destination address, copy 'amount' of a packet from
2414 * the ring buffer into a linear destination buffer. Takes into account
2415 * ring-wrap.
2416 */
2417static inline char *
2418ed_ring_copy(sc,src,dst,amount)
2419 struct ed_softc *sc;
2420 char *src;
2421 char *dst;
2422 u_short amount;
2423{
2424 u_short tmp_amount;
2425
2426 /* does copy wrap to lower addr in ring buffer? */
2427 if (src + amount > sc->mem_end) {
2428 tmp_amount = sc->mem_end - src;
2429
2430 /* copy amount up to end of NIC memory */
2431 if (sc->mem_shared)
2432 bcopy(src,dst,tmp_amount);
2433 else
2434 ed_pio_readmem(sc,src,dst,tmp_amount);
2435
2436 amount -= tmp_amount;
2437 src = sc->mem_ring;
2438 dst += tmp_amount;
2439 }
2440
2441 if (sc->mem_shared)
2442 bcopy(src, dst, amount);
2443 else
2444 ed_pio_readmem(sc, src, dst, amount);
2445
2446 return(src + amount);
2447}
2448
2449/*
2450 * Copy data from receive buffer to end of mbuf chain
2451 * allocate additional mbufs as needed. return pointer
2452 * to last mbuf in chain.
2453 * sc = ed info (softc)
2454 * src = pointer in ed ring buffer
2455 * dst = pointer to last mbuf in mbuf chain to copy to
2456 * amount = amount of data to copy
2457 */
2458struct mbuf *
2459ed_ring_to_mbuf(sc,src,dst,total_len)
2460 struct ed_softc *sc;
2461 char *src;
2462 struct mbuf *dst;
2463 u_short total_len;
2464{
2465 register struct mbuf *m = dst;
2466
2467 while (total_len) {
2468 register u_short amount = min(total_len, M_TRAILINGSPACE(m));
2469
2470 if (amount == 0) { /* no more data in this mbuf, alloc another */
2471 /*
2472 * If there is enough data for an mbuf cluster, attempt
2473 * to allocate one of those, otherwise, a regular
2474 * mbuf will do.
2475 * Note that a regular mbuf is always required, even if
2476 * we get a cluster - getting a cluster does not
2477 * allocate any mbufs, and one is needed to assign
2478 * the cluster to. The mbuf that has a cluster
2479 * extension can not be used to contain data - only
2480 * the cluster can contain data.
2481 */
2482 dst = m;
2483 MGET(m, M_DONTWAIT, MT_DATA);
2484 if (m == 0)
2485 return (0);
2486
2487 if (total_len >= MINCLSIZE)
2488 MCLGET(m, M_DONTWAIT);
2489
2490 m->m_len = 0;
2491 dst->m_next = m;
2492 amount = min(total_len, M_TRAILINGSPACE(m));
2493 }
2494
2495 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
2496
2497 m->m_len += amount;
2498 total_len -= amount;
2499
2500 }
2501 return (m);
2502}
2503#endif
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