1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 *
| 1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 *
|
27 * $FreeBSD: head/sys/dev/ed/if_ed.c 50808 1999-09-02 15:06:23Z kato $
| 27 * $FreeBSD: head/sys/dev/ed/if_ed.c 50852 1999-09-03 19:10:56Z peter $
|
28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39
| 28 */ 29 30/* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39
|
40#include "ed.h"
| |
41#include "bpf.h"
| 40#include "bpf.h"
|
42#include "pnp.h"
| |
43
| 41
|
44#ifndef EXTRA_ED 45# if NPNP > 0 46# define EXTRA_ED 8 47# else 48# define EXTRA_ED 0 49# endif 50#endif 51 52#define NEDTOT (NED + EXTRA_ED) 53
| |
54#include <sys/param.h> 55#include <sys/systm.h>
| 42#include <sys/param.h> 43#include <sys/systm.h>
|
| 44#include <sys/kernel.h>
|
56#include <sys/sockio.h> 57#include <sys/malloc.h> 58#include <sys/mbuf.h> 59#include <sys/socket.h> 60#include <sys/syslog.h> 61
| 45#include <sys/sockio.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/socket.h> 49#include <sys/syslog.h> 50
|
| 51#include <sys/module.h> 52#include <sys/bus.h> 53 54#include <machine/bus.h> 55#include <sys/rman.h> 56#include <machine/resource.h> 57
|
62#include <net/ethernet.h> 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/if_dl.h> 66#include <net/if_mib.h> 67 68#if NBPF > 0 69#include <net/bpf.h> 70#endif 71#include "opt_bdg.h" 72#ifdef BRIDGE 73#include <net/bridge.h> 74#endif 75 76#include <machine/clock.h> 77#include <machine/md_var.h> 78
| 58#include <net/ethernet.h> 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_mib.h> 63 64#if NBPF > 0 65#include <net/bpf.h> 66#endif 67#include "opt_bdg.h" 68#ifdef BRIDGE 69#include <net/bridge.h> 70#endif 71 72#include <machine/clock.h> 73#include <machine/md_var.h> 74
|
79#include <i386/isa/isa_device.h> 80#include <i386/isa/icu.h>
| |
81#include <i386/isa/if_edreg.h>
| 75#include <i386/isa/if_edreg.h>
|
| 76#include <i386/isa/if_edvar.h>
|
82
| 77
|
83#if NPNP > 0 84#include <i386/isa/pnp.h> 85#endif
| 78#include <isa/isavar.h> 79#include <isa/pnpvar.h>
|
86
| 80
|
87/* 88 * ed_softc: per line info and status 89 */ 90struct ed_softc { 91 struct arpcom arpcom; /* ethernet common */
| 81static int ed_alloc_port __P((device_t, int, int)); 82static int ed_alloc_memory __P((device_t, int, int)); 83static int ed_alloc_irq __P((device_t, int, int)); 84static void ed_release_resources __P((device_t));
|
92
| 85
|
93 char *type_str; /* pointer to type string */ 94 u_char vendor; /* interface vendor */ 95 u_char type; /* interface type code */ 96 u_char gone; /* HW missing, presumed having a good time */ 97 98 u_short asic_addr; /* ASIC I/O bus address */ 99 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 100 101/* 102 * The following 'proto' variable is part of a work-around for 8013EBT asics 103 * being write-only. It's sort of a prototype/shadow of the real thing. 104 */ 105 u_char wd_laar_proto; 106 u_char cr_proto; 107 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 108 int is790; /* set by the probe code if the card is 790 109 * based */ 110 111/* 112 * HP PC LAN PLUS card support. 113 */ 114 115 u_short hpp_options; /* flags controlling behaviour of the HP card */ 116 u_short hpp_id; /* software revision and other fields */ 117 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 118 119 caddr_t mem_start; /* NIC memory start address */ 120 caddr_t mem_end; /* NIC memory end address */ 121 u_long mem_size; /* total NIC memory size */ 122 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 123 124 u_char mem_shared; /* NIC memory is shared with host */ 125 u_char xmit_busy; /* transmitter is busy */ 126 u_char txb_cnt; /* number of transmit buffers */ 127 u_char txb_inuse; /* number of TX buffers currently in-use */ 128 129 u_char txb_new; /* pointer to where new buffer will be added */ 130 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 131 u_short txb_len[8]; /* buffered xmit buffer lengths */ 132 u_char tx_page_start; /* first page of TX buffer area */ 133 u_char rec_page_start; /* first page of RX ring-buffer */ 134 u_char rec_page_stop; /* last page of RX ring-buffer */ 135 u_char next_packet; /* pointer to next unread RX packet */ 136 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 137}; 138 139static struct ed_softc ed_softc[NEDTOT]; 140
| |
141static int ed_attach __P((struct ed_softc *, int, int));
| 86static int ed_attach __P((struct ed_softc *, int, int));
|
142static int ed_attach_isa __P((struct isa_device *));
| 87static int ed_isa_attach __P((device_t));
|
143 144static void ed_init __P((void *));
| 88 89static void ed_init __P((void *));
|
145static ointhand2_t edintr;
| 90static driver_intr_t edintr;
|
146static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
| 91static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
|
147static int ed_probe __P((struct isa_device *));
| 92static int ed_isa_probe __P((device_t));
|
148static void ed_start __P((struct ifnet *)); 149static void ed_reset __P((struct ifnet *)); 150static void ed_watchdog __P((struct ifnet *)); 151 152static void ed_stop __P((struct ed_softc *)); 153static int ed_probe_generic8390 __P((struct ed_softc *));
| 93static void ed_start __P((struct ifnet *)); 94static void ed_reset __P((struct ifnet *)); 95static void ed_watchdog __P((struct ifnet *)); 96 97static void ed_stop __P((struct ed_softc *)); 98static int ed_probe_generic8390 __P((struct ed_softc *));
|
154static int ed_probe_WD80x3 __P((struct isa_device *)); 155static int ed_probe_3Com __P((struct isa_device *)); 156static int ed_probe_Novell __P((struct isa_device *)); 157static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 158static int ed_probe_HP_pclanp __P((struct isa_device *));
| 99static int ed_probe_WD80x3 __P((device_t)); 100static int ed_probe_3Com __P((device_t)); 101static int ed_probe_Novell __P((device_t)); 102static int ed_probe_Novell_generic __P((device_t, int, int)); 103static int ed_probe_HP_pclanp __P((device_t));
|
159 160#include "pci.h" 161#if NPCI > 0
| 104 105#include "pci.h" 106#if NPCI > 0
|
162void *ed_attach_NE2000_pci __P((int, int));
| 107int ed_attach_NE2000_pci __P((device_t, int));
|
163#endif 164 165#include "card.h"
| 108#endif 109 110#include "card.h"
|
166#if NCARD > 0
| 111#if NCARDxx > 0
|
167static int ed_probe_pccard __P((struct isa_device *, u_char *)); 168#endif 169 170static void ds_getmcaf __P((struct ed_softc *, u_long *)); 171 172static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 173 174static __inline void ed_rint __P((struct ed_softc *)); 175static __inline void ed_xmit __P((struct ed_softc *)); 176static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 177 /* u_short */ int)); 178static void ed_hpp_set_physical_link __P((struct ed_softc *)); 179static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 180 /* u_short */ int)); 181static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 182 int)); 183 184static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 185 /* u_short */ int)); 186static void ed_pio_writemem __P((struct ed_softc *, char *, 187 /* u_short */ int, /* u_short */ int)); 188static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 189 int));
| 112static int ed_probe_pccard __P((struct isa_device *, u_char *)); 113#endif 114 115static void ds_getmcaf __P((struct ed_softc *, u_long *)); 116 117static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 118 119static __inline void ed_rint __P((struct ed_softc *)); 120static __inline void ed_xmit __P((struct ed_softc *)); 121static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 122 /* u_short */ int)); 123static void ed_hpp_set_physical_link __P((struct ed_softc *)); 124static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 125 /* u_short */ int)); 126static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 127 int)); 128 129static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 130 /* u_short */ int)); 131static void ed_pio_writemem __P((struct ed_softc *, char *, 132 /* u_short */ int, /* u_short */ int)); 133static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 134 int));
|
190void edintr_sc __P((struct ed_softc *));
| |
191 192static void ed_setrcr __P((struct ed_softc *)); 193 194static u_long ds_crc __P((u_char *ep)); 195
| 135 136static void ed_setrcr __P((struct ed_softc *)); 137 138static u_long ds_crc __P((u_char *ep)); 139
|
196#if (NCARD > 0) || (NPNP > 0) 197#include <sys/kernel.h> 198#endif 199#if NCARD > 0
| 140#if NCARDxx > 0
|
200#include <sys/select.h> 201#include <sys/module.h> 202#include <pccard/cardinfo.h> 203#include <pccard/slot.h> 204 205/* 206 * PC-Card (PCMCIA) specific code. 207 */ 208static int edinit __P((struct pccard_devinfo *)); 209static void edunload __P((struct pccard_devinfo *)); 210static int card_intr __P((struct pccard_devinfo *)); 211 212PCCARD_MODULE(ed, edinit, edunload, card_intr, 0, net_imask); 213 214/* 215 * Initialize the device - called from Slot manager. 216 */ 217static int 218edinit(struct pccard_devinfo *devi) 219{ 220 int i; 221 u_char e; 222 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 223 224 /* validate unit number. */ 225 if (devi->isahd.id_unit >= NEDTOT) 226 return(ENODEV); 227 /* 228 * Probe the device. If a value is returned, the 229 * device was found at the location. 230 */ 231 sc->gone = 0; 232 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0) 233 return(ENXIO); 234 e = 0; 235 for (i = 0; i < ETHER_ADDR_LEN; ++i) 236 e |= devi->misc[i]; 237 if (e) 238 for (i = 0; i < ETHER_ADDR_LEN; ++i) 239 sc->arpcom.ac_enaddr[i] = devi->misc[i];
| 141#include <sys/select.h> 142#include <sys/module.h> 143#include <pccard/cardinfo.h> 144#include <pccard/slot.h> 145 146/* 147 * PC-Card (PCMCIA) specific code. 148 */ 149static int edinit __P((struct pccard_devinfo *)); 150static void edunload __P((struct pccard_devinfo *)); 151static int card_intr __P((struct pccard_devinfo *)); 152 153PCCARD_MODULE(ed, edinit, edunload, card_intr, 0, net_imask); 154 155/* 156 * Initialize the device - called from Slot manager. 157 */ 158static int 159edinit(struct pccard_devinfo *devi) 160{ 161 int i; 162 u_char e; 163 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 164 165 /* validate unit number. */ 166 if (devi->isahd.id_unit >= NEDTOT) 167 return(ENODEV); 168 /* 169 * Probe the device. If a value is returned, the 170 * device was found at the location. 171 */ 172 sc->gone = 0; 173 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0) 174 return(ENXIO); 175 e = 0; 176 for (i = 0; i < ETHER_ADDR_LEN; ++i) 177 e |= devi->misc[i]; 178 if (e) 179 for (i = 0; i < ETHER_ADDR_LEN; ++i) 180 sc->arpcom.ac_enaddr[i] = devi->misc[i];
|
240 if (ed_attach_isa(&devi->isahd) == 0)
| 181 if (ed_isa_attach(&devi->isahd) == 0)
|
241 return(ENXIO); 242 243 return(0); 244} 245 246/* 247 * edunload - unload the driver and clear the table. 248 * XXX TODO: 249 * This is usually called when the card is ejected, but 250 * can be caused by a modunload of a controller driver. 251 * The idea is to reset the driver's view of the device 252 * and ensure that any driver entry points such as 253 * read and write do not hang. 254 */ 255static void 256edunload(struct pccard_devinfo *devi) 257{ 258 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 259 struct ifnet *ifp = &sc->arpcom.ac_if; 260 261 if (sc->gone) { 262 printf("ed%d: already unloaded\n", devi->isahd.id_unit); 263 return; 264 } 265 ifp->if_flags &= ~IFF_RUNNING; 266 if_down(ifp); 267 sc->gone = 1; 268 printf("ed%d: unload\n", devi->isahd.id_unit); 269} 270 271/* 272 * card_intr - Shared interrupt called from 273 * front end of PC-Card handler. 274 */ 275static int 276card_intr(struct pccard_devinfo *devi) 277{
| 182 return(ENXIO); 183 184 return(0); 185} 186 187/* 188 * edunload - unload the driver and clear the table. 189 * XXX TODO: 190 * This is usually called when the card is ejected, but 191 * can be caused by a modunload of a controller driver. 192 * The idea is to reset the driver's view of the device 193 * and ensure that any driver entry points such as 194 * read and write do not hang. 195 */ 196static void 197edunload(struct pccard_devinfo *devi) 198{ 199 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 200 struct ifnet *ifp = &sc->arpcom.ac_if; 201 202 if (sc->gone) { 203 printf("ed%d: already unloaded\n", devi->isahd.id_unit); 204 return; 205 } 206 ifp->if_flags &= ~IFF_RUNNING; 207 if_down(ifp); 208 sc->gone = 1; 209 printf("ed%d: unload\n", devi->isahd.id_unit); 210} 211 212/* 213 * card_intr - Shared interrupt called from 214 * front end of PC-Card handler. 215 */ 216static int 217card_intr(struct pccard_devinfo *devi) 218{
|
278 edintr_sc(&ed_softc[devi->isahd.id_unit]);
| 219 edintr(&ed_softc[devi->isahd.id_unit]);
|
279 return(1); 280} 281#endif /* NCARD > 0 */ 282
| 220 return(1); 221} 222#endif /* NCARD > 0 */ 223
|
283struct isa_driver eddriver = { 284 ed_probe, 285 ed_attach_isa, 286 "ed", 287 1 /* We are ultra sensitive */ 288}; 289
| |
290/* 291 * Interrupt conversion table for WD/SMC ASIC/83C584
| 224/* 225 * Interrupt conversion table for WD/SMC ASIC/83C584
|
292 * (IRQ* are defined in icu.h)
| |
293 */
| 226 */
|
294static unsigned short ed_intr_mask[] = { 295 IRQ9, 296 IRQ3, 297 IRQ5, 298 IRQ7, 299 IRQ10, 300 IRQ11, 301 IRQ15, 302 IRQ4
| 227static unsigned short ed_intr_val[] = { 228 9, 229 3, 230 5, 231 7, 232 10, 233 11, 234 15, 235 4
|
303}; 304 305/* 306 * Interrupt conversion table for 83C790 307 */
| 236}; 237 238/* 239 * Interrupt conversion table for 83C790 240 */
|
308static unsigned short ed_790_intr_mask[] = {
| 241static unsigned short ed_790_intr_val[] = {
|
309 0,
| 242 0,
|
310 IRQ9, 311 IRQ3, 312 IRQ5, 313 IRQ7, 314 IRQ10, 315 IRQ11, 316 IRQ15
| 243 9, 244 3, 245 5, 246 7, 247 10, 248 11, 249 15
|
317}; 318 319/* 320 * Interrupt conversion table for the HP PC LAN+ 321 */ 322
| 250}; 251 252/* 253 * Interrupt conversion table for the HP PC LAN+ 254 */ 255
|
323static unsigned short ed_hpp_intr_mask[] = {
| 256static unsigned short ed_hpp_intr_val[] = {
|
324 0, /* 0 */ 325 0, /* 1 */ 326 0, /* 2 */
| 257 0, /* 0 */ 258 0, /* 1 */ 259 0, /* 2 */
|
327 IRQ3, /* 3 */ 328 IRQ4, /* 4 */ 329 IRQ5, /* 5 */ 330 IRQ6, /* 6 */ 331 IRQ7, /* 7 */
| 260 3, /* 3 */ 261 4, /* 4 */ 262 5, /* 5 */ 263 6, /* 6 */ 264 7, /* 7 */
|
332 0, /* 8 */
| 265 0, /* 8 */
|
333 IRQ9, /* 9 */ 334 IRQ10, /* 10 */ 335 IRQ11, /* 11 */ 336 IRQ12, /* 12 */
| 266 9, /* 9 */ 267 10, /* 10 */ 268 11, /* 11 */ 269 12, /* 12 */
|
337 0, /* 13 */ 338 0, /* 14 */
| 270 0, /* 13 */ 271 0, /* 14 */
|
339 IRQ15 /* 15 */
| 272 15 /* 15 */
|
340}; 341
| 273}; 274
|
342/* 343 * Determine if the device is present 344 * 345 * on entry: 346 * a pointer to an isa_device struct 347 * on exit: 348 * NULL if device not found 349 * or # of i/o addresses used (if found) 350 */
| 275static struct isa_pnp_id ed_ids[] = { 276 { 0xd680d041, "NE2000 Compatible" }, /* PNP80d6 */ 277 { 0x1980635e, "WSC8019" }, /* WSC8019 */ 278 { 0x0131d805, "Acer ALN-101T" }, /* ANX3101 */ 279 { 0x01200507, "PLANET ENW-2401" }, /* AXE2001 */ 280 { 0x19808c4a, "Realtek Plug & Play Ethernet Card" }, /* RTL8019 */ 281 { 0x0090252a, "CNet NE2000 Compatible" }, /* JQE9000 */ 282 { 0x0020832e, "Kingston EtheRX KNE20 Plug & Play ISA" }, /* KTC2000 */ 283 { 0, NULL} 284}; 285
|
351static int
| 286static int
|
352ed_probe(isa_dev) 353 struct isa_device *isa_dev;
| 287ed_isa_probe(dev) 288 device_t dev;
|
354{
| 289{
|
355 int nports;
| 290 struct ed_softc *sc = device_get_softc(dev); 291 int error = 0;
|
356
| 292
|
357 nports = ed_probe_WD80x3(isa_dev); 358 if (nports) 359 return (nports);
| 293 bzero(sc, sizeof(struct ed_softc));
|
360
| 294
|
361 nports = ed_probe_3Com(isa_dev); 362 if (nports) 363 return (nports);
| 295 /* Check isapnp ids */ 296 error = ISA_PNP_PROBE(device_get_parent(dev), dev, ed_ids);
|
364
| 297
|
365 nports = ed_probe_Novell(isa_dev); 366 if (nports) 367 return (nports);
| 298 /* If the card had a PnP ID that didn't match any we know about */ 299 if (error == ENXIO) 300 goto end;
|
368
| 301
|
369 nports = ed_probe_HP_pclanp(isa_dev); 370 if (nports) 371 return (nports);
| 302 /* If we found a PnP card. */ 303 if (error == 0) { 304 error = ed_probe_Novell(dev); 305 goto end; 306 } 307 308 /* Heuristic probes */
|
372
| 309
|
373 return (0);
| 310 error = ed_probe_WD80x3(dev); 311 if (error == 0) 312 goto end; 313 ed_release_resources(dev); 314 315 error = ed_probe_3Com(dev); 316 if (error == 0) 317 goto end; 318 ed_release_resources(dev); 319 320 error = ed_probe_Novell(dev); 321 if (error == 0) 322 goto end; 323 ed_release_resources(dev); 324 325 error = ed_probe_HP_pclanp(dev); 326 if (error == 0) 327 goto end; 328 ed_release_resources(dev); 329 330end: 331 if (error == 0) 332 error = ed_alloc_irq(dev, 0, 0); 333 334 ed_release_resources(dev); 335 return (error);
|
374} 375 376/* 377 * Generic probe routine for testing for the existance of a DS8390. 378 * Must be called after the NIC has just been reset. This routine 379 * works by looking at certain register values that are guaranteed 380 * to be initialized a certain way after power-up or reset. Seems 381 * not to currently work on the 83C690. 382 * 383 * Specifically: 384 * 385 * Register reset bits set bits 386 * Command Register (CR) TXP, STA RD2, STP 387 * Interrupt Status (ISR) RST 388 * Interrupt Mask (IMR) All bits 389 * Data Control (DCR) LAS 390 * Transmit Config. (TCR) LB1, LB0 391 * 392 * We only look at the CR and ISR registers, however, because looking at 393 * the others would require changing register pages (which would be 394 * intrusive if this isn't an 8390). 395 * 396 * Return 1 if 8390 was found, 0 if not. 397 */ 398 399static int 400ed_probe_generic8390(sc) 401 struct ed_softc *sc; 402{ 403 if ((inb(sc->nic_addr + ED_P0_CR) & 404 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 405 (ED_CR_RD2 | ED_CR_STP)) 406 return (0); 407 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 408 return (0); 409 410 return (1); 411} 412 413/* 414 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 415 */ 416static int
| 336} 337 338/* 339 * Generic probe routine for testing for the existance of a DS8390. 340 * Must be called after the NIC has just been reset. This routine 341 * works by looking at certain register values that are guaranteed 342 * to be initialized a certain way after power-up or reset. Seems 343 * not to currently work on the 83C690. 344 * 345 * Specifically: 346 * 347 * Register reset bits set bits 348 * Command Register (CR) TXP, STA RD2, STP 349 * Interrupt Status (ISR) RST 350 * Interrupt Mask (IMR) All bits 351 * Data Control (DCR) LAS 352 * Transmit Config. (TCR) LB1, LB0 353 * 354 * We only look at the CR and ISR registers, however, because looking at 355 * the others would require changing register pages (which would be 356 * intrusive if this isn't an 8390). 357 * 358 * Return 1 if 8390 was found, 0 if not. 359 */ 360 361static int 362ed_probe_generic8390(sc) 363 struct ed_softc *sc; 364{ 365 if ((inb(sc->nic_addr + ED_P0_CR) & 366 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 367 (ED_CR_RD2 | ED_CR_STP)) 368 return (0); 369 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 370 return (0); 371 372 return (1); 373} 374 375/* 376 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 377 */ 378static int
|
417ed_probe_WD80x3(isa_dev) 418 struct isa_device *isa_dev;
| 379ed_probe_WD80x3(dev) 380 device_t dev;
|
419{
| 381{
|
420 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
| 382 struct ed_softc *sc = device_get_softc(dev); 383 int error;
|
421 int i;
| 384 int i;
|
| 385 int flags = isa_get_flags(dev);
|
422 u_int memsize, maddr; 423 u_char iptr, isa16bit, sum;
| 386 u_int memsize, maddr; 387 u_char iptr, isa16bit, sum;
|
| 388 u_long conf_maddr, conf_msize, irq, junk;
|
424
| 389
|
425 sc->asic_addr = isa_dev->id_iobase;
| 390 error = ed_alloc_port(dev, 0, ED_WD_IO_PORTS); 391 if (error) 392 return (error); 393 394 sc->asic_addr = rman_get_start(sc->port_res);
|
426 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 427 sc->is790 = 0; 428 429#ifdef TOSH_ETHER 430 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 431 DELAY(10000); 432#endif 433 434 /* 435 * Attempt to do a checksum over the station address PROM. If it 436 * fails, it's probably not a SMC/WD board. There is a problem with 437 * this, though: some clone WD boards don't pass the checksum test. 438 * Danpex boards for one. 439 */ 440 for (sum = 0, i = 0; i < 8; ++i) 441 sum += inb(sc->asic_addr + ED_WD_PROM + i); 442 443 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 444 445 /* 446 * Checksum is invalid. This often happens with cheap WD8003E 447 * clones. In this case, the checksum byte (the eighth byte) 448 * seems to always be zero. 449 */ 450 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 451 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
| 395 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 396 sc->is790 = 0; 397 398#ifdef TOSH_ETHER 399 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 400 DELAY(10000); 401#endif 402 403 /* 404 * Attempt to do a checksum over the station address PROM. If it 405 * fails, it's probably not a SMC/WD board. There is a problem with 406 * this, though: some clone WD boards don't pass the checksum test. 407 * Danpex boards for one. 408 */ 409 for (sum = 0, i = 0; i < 8; ++i) 410 sum += inb(sc->asic_addr + ED_WD_PROM + i); 411 412 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 413 414 /* 415 * Checksum is invalid. This often happens with cheap WD8003E 416 * clones. In this case, the checksum byte (the eighth byte) 417 * seems to always be zero. 418 */ 419 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 420 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
|
452 return (0);
| 421 return (ENXIO);
|
453 } 454 /* reset card to force it into a known state. */ 455#ifdef TOSH_ETHER 456 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 457#else 458 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 459#endif 460 DELAY(100); 461 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 462 /* wait in the case this card is reading its EEROM */ 463 DELAY(5000); 464 465 sc->vendor = ED_VENDOR_WD_SMC; 466 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 467 468 /* 469 * Set initial values for width/size. 470 */ 471 memsize = 8192; 472 isa16bit = 0; 473 switch (sc->type) { 474 case ED_TYPE_WD8003S: 475 sc->type_str = "WD8003S"; 476 break; 477 case ED_TYPE_WD8003E: 478 sc->type_str = "WD8003E"; 479 break; 480 case ED_TYPE_WD8003EB: 481 sc->type_str = "WD8003EB"; 482 break; 483 case ED_TYPE_WD8003W: 484 sc->type_str = "WD8003W"; 485 break; 486 case ED_TYPE_WD8013EBT: 487 sc->type_str = "WD8013EBT"; 488 memsize = 16384; 489 isa16bit = 1; 490 break; 491 case ED_TYPE_WD8013W: 492 sc->type_str = "WD8013W"; 493 memsize = 16384; 494 isa16bit = 1; 495 break; 496 case ED_TYPE_WD8013EP: /* also WD8003EP */ 497 if (inb(sc->asic_addr + ED_WD_ICR) 498 & ED_WD_ICR_16BIT) { 499 isa16bit = 1; 500 memsize = 16384; 501 sc->type_str = "WD8013EP"; 502 } else { 503 sc->type_str = "WD8003EP"; 504 } 505 break; 506 case ED_TYPE_WD8013WC: 507 sc->type_str = "WD8013WC"; 508 memsize = 16384; 509 isa16bit = 1; 510 break; 511 case ED_TYPE_WD8013EBP: 512 sc->type_str = "WD8013EBP"; 513 memsize = 16384; 514 isa16bit = 1; 515 break; 516 case ED_TYPE_WD8013EPC: 517 sc->type_str = "WD8013EPC"; 518 memsize = 16384; 519 isa16bit = 1; 520 break; 521 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 522 case ED_TYPE_SMC8216T: 523 if (sc->type == ED_TYPE_SMC8216C) { 524 sc->type_str = "SMC8216/SMC8216C"; 525 } else { 526 sc->type_str = "SMC8216T"; 527 } 528 529 outb(sc->asic_addr + ED_WD790_HWR, 530 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 531 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 532 case ED_WD790_RAR_SZ64: 533 memsize = 65536; 534 break; 535 case ED_WD790_RAR_SZ32: 536 memsize = 32768; 537 break; 538 case ED_WD790_RAR_SZ16: 539 memsize = 16384; 540 break; 541 case ED_WD790_RAR_SZ8: 542 /* 8216 has 16K shared mem -- 8416 has 8K */ 543 if (sc->type == ED_TYPE_SMC8216C) { 544 sc->type_str = "SMC8416C/SMC8416BT"; 545 } else { 546 sc->type_str = "SMC8416T"; 547 } 548 memsize = 8192; 549 break; 550 } 551 outb(sc->asic_addr + ED_WD790_HWR, 552 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 553 554 isa16bit = 1; 555 sc->is790 = 1; 556 break; 557#ifdef TOSH_ETHER 558 case ED_TYPE_TOSHIBA1: 559 sc->type_str = "Toshiba1"; 560 memsize = 32768; 561 isa16bit = 1; 562 break; 563 case ED_TYPE_TOSHIBA4: 564 sc->type_str = "Toshiba4"; 565 memsize = 32768; 566 isa16bit = 1; 567 break; 568#endif 569 default: 570 sc->type_str = ""; 571 break; 572 } 573 574 /* 575 * Make some adjustments to initial values depending on what is found 576 * in the ICR. 577 */ 578 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 579#ifdef TOSH_ETHER 580 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 581#endif 582 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 583 isa16bit = 0; 584 memsize = 8192; 585 } 586
| 422 } 423 /* reset card to force it into a known state. */ 424#ifdef TOSH_ETHER 425 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 426#else 427 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 428#endif 429 DELAY(100); 430 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 431 /* wait in the case this card is reading its EEROM */ 432 DELAY(5000); 433 434 sc->vendor = ED_VENDOR_WD_SMC; 435 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 436 437 /* 438 * Set initial values for width/size. 439 */ 440 memsize = 8192; 441 isa16bit = 0; 442 switch (sc->type) { 443 case ED_TYPE_WD8003S: 444 sc->type_str = "WD8003S"; 445 break; 446 case ED_TYPE_WD8003E: 447 sc->type_str = "WD8003E"; 448 break; 449 case ED_TYPE_WD8003EB: 450 sc->type_str = "WD8003EB"; 451 break; 452 case ED_TYPE_WD8003W: 453 sc->type_str = "WD8003W"; 454 break; 455 case ED_TYPE_WD8013EBT: 456 sc->type_str = "WD8013EBT"; 457 memsize = 16384; 458 isa16bit = 1; 459 break; 460 case ED_TYPE_WD8013W: 461 sc->type_str = "WD8013W"; 462 memsize = 16384; 463 isa16bit = 1; 464 break; 465 case ED_TYPE_WD8013EP: /* also WD8003EP */ 466 if (inb(sc->asic_addr + ED_WD_ICR) 467 & ED_WD_ICR_16BIT) { 468 isa16bit = 1; 469 memsize = 16384; 470 sc->type_str = "WD8013EP"; 471 } else { 472 sc->type_str = "WD8003EP"; 473 } 474 break; 475 case ED_TYPE_WD8013WC: 476 sc->type_str = "WD8013WC"; 477 memsize = 16384; 478 isa16bit = 1; 479 break; 480 case ED_TYPE_WD8013EBP: 481 sc->type_str = "WD8013EBP"; 482 memsize = 16384; 483 isa16bit = 1; 484 break; 485 case ED_TYPE_WD8013EPC: 486 sc->type_str = "WD8013EPC"; 487 memsize = 16384; 488 isa16bit = 1; 489 break; 490 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 491 case ED_TYPE_SMC8216T: 492 if (sc->type == ED_TYPE_SMC8216C) { 493 sc->type_str = "SMC8216/SMC8216C"; 494 } else { 495 sc->type_str = "SMC8216T"; 496 } 497 498 outb(sc->asic_addr + ED_WD790_HWR, 499 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 500 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 501 case ED_WD790_RAR_SZ64: 502 memsize = 65536; 503 break; 504 case ED_WD790_RAR_SZ32: 505 memsize = 32768; 506 break; 507 case ED_WD790_RAR_SZ16: 508 memsize = 16384; 509 break; 510 case ED_WD790_RAR_SZ8: 511 /* 8216 has 16K shared mem -- 8416 has 8K */ 512 if (sc->type == ED_TYPE_SMC8216C) { 513 sc->type_str = "SMC8416C/SMC8416BT"; 514 } else { 515 sc->type_str = "SMC8416T"; 516 } 517 memsize = 8192; 518 break; 519 } 520 outb(sc->asic_addr + ED_WD790_HWR, 521 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 522 523 isa16bit = 1; 524 sc->is790 = 1; 525 break; 526#ifdef TOSH_ETHER 527 case ED_TYPE_TOSHIBA1: 528 sc->type_str = "Toshiba1"; 529 memsize = 32768; 530 isa16bit = 1; 531 break; 532 case ED_TYPE_TOSHIBA4: 533 sc->type_str = "Toshiba4"; 534 memsize = 32768; 535 isa16bit = 1; 536 break; 537#endif 538 default: 539 sc->type_str = ""; 540 break; 541 } 542 543 /* 544 * Make some adjustments to initial values depending on what is found 545 * in the ICR. 546 */ 547 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 548#ifdef TOSH_ETHER 549 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 550#endif 551 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 552 isa16bit = 0; 553 memsize = 8192; 554 } 555
|
| 556 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 557 SYS_RES_MEMORY, 0, 558 &conf_maddr, &conf_msize); 559 if (error) 560 return (error); 561
|
587#if ED_DEBUG 588 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
| 562#if ED_DEBUG 563 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
|
589 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
| 564 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
|
590 for (i = 0; i < 8; i++) 591 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 592#endif 593 594 /* 595 * Allow the user to override the autoconfiguration 596 */
| 565 for (i = 0; i < 8; i++) 566 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 567#endif 568 569 /* 570 * Allow the user to override the autoconfiguration 571 */
|
597 if (isa_dev->id_msize) 598 memsize = isa_dev->id_msize;
| 572 if (conf_msize > 1) 573 memsize = conf_msize;
|
599
| 574
|
600 maddr = (u_int) isa_dev->id_maddr & 0xffffff;
| 575 maddr = conf_maddr;
|
601 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
| 576 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
|
602 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n", 603 isa_dev->id_unit, maddr, maddr + memsize); 604 return 0;
| 577 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 578 maddr, maddr + memsize); 579 return (ENXIO);
|
605 } 606 607 /* 608 * (note that if the user specifies both of the following flags that 609 * '8bit' mode intentionally has precedence) 610 */
| 580 } 581 582 /* 583 * (note that if the user specifies both of the following flags that 584 * '8bit' mode intentionally has precedence) 585 */
|
611 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
| 586 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
|
612 isa16bit = 1;
| 587 isa16bit = 1;
|
613 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
| 588 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
|
614 isa16bit = 0; 615 616 /* 617 * If possible, get the assigned interrupt number from the card and 618 * use it. 619 */ 620 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 621 622 /* 623 * Assemble together the encoded interrupt number. 624 */
| 589 isa16bit = 0; 590 591 /* 592 * If possible, get the assigned interrupt number from the card and 593 * use it. 594 */ 595 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 596 597 /* 598 * Assemble together the encoded interrupt number. 599 */
|
625 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 626 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
| 600 iptr = (inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_IR2) | 601 ((inb(sc->asic_addr + ED_WD_IRR) &
|
627 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 628 629 /* 630 * If no interrupt specified (or "?"), use what the board tells us. 631 */
| 602 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 603 604 /* 605 * If no interrupt specified (or "?"), use what the board tells us. 606 */
|
632 if (isa_dev->id_irq <= 0) 633 isa_dev->id_irq = ed_intr_mask[iptr];
| 607 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 608 SYS_RES_IRQ, 0, 609 &irq, &junk); 610 if (error) { 611 ISA_SET_RESOURCE(device_get_parent(dev), dev, 612 SYS_RES_IRQ, 0, 613 ed_intr_val[iptr], 1); 614 }
|
634 635 /* 636 * Enable the interrupt. 637 */
| 615 616 /* 617 * Enable the interrupt. 618 */
|
638 outb(isa_dev->id_iobase + ED_WD_IRR, 639 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
| 619 outb(sc->asic_addr + ED_WD_IRR, 620 inb(sc->asic_addr + ED_WD_IRR) | ED_WD_IRR_IEN);
|
640 } 641 if (sc->is790) {
| 621 } 622 if (sc->is790) {
|
642 outb(isa_dev->id_iobase + ED_WD790_HWR, 643 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 644 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 645 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
| 623 outb(sc->asic_addr + ED_WD790_HWR, 624 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 625 iptr = (((inb(sc->asic_addr + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 626 (inb(sc->asic_addr + ED_WD790_GCR) &
|
646 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
| 627 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
|
647 outb(isa_dev->id_iobase + ED_WD790_HWR, 648 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
| 628 outb(sc->asic_addr + ED_WD790_HWR, 629 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
|
649 650 /* 651 * If no interrupt specified (or "?"), use what the board tells us. 652 */
| 630 631 /* 632 * If no interrupt specified (or "?"), use what the board tells us. 633 */
|
653 if (isa_dev->id_irq <= 0) 654 isa_dev->id_irq = ed_790_intr_mask[iptr];
| 634 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 635 SYS_RES_IRQ, 0, 636 &irq, &junk); 637 if (error) { 638 ISA_SET_RESOURCE(device_get_parent(dev), dev, 639 SYS_RES_IRQ, 0, 640 ed_790_intr_val[iptr], 1); 641 }
|
655 656 /* 657 * Enable interrupts. 658 */
| 642 643 /* 644 * Enable interrupts. 645 */
|
659 outb(isa_dev->id_iobase + ED_WD790_ICR, 660 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
| 646 outb(sc->asic_addr + ED_WD790_ICR, 647 inb(sc->asic_addr + ED_WD790_ICR) | ED_WD790_ICR_EIL);
|
661 }
| 648 }
|
662 if (isa_dev->id_irq <= 0) { 663 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 664 isa_dev->id_unit, sc->type_str); 665 return (0);
| 649 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 650 SYS_RES_IRQ, 0, 651 &irq, &junk); 652 if (error) { 653 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 654 sc->type_str); 655 return (ENXIO);
|
666 } 667 sc->isa16bit = isa16bit; 668 sc->mem_shared = 1;
| 656 } 657 sc->isa16bit = isa16bit; 658 sc->mem_shared = 1;
|
669 isa_dev->id_msize = memsize; 670 sc->mem_start = (caddr_t) isa_dev->id_maddr;
| |
671
| 659
|
| 660 error = ed_alloc_memory(dev, 0, memsize); 661 if (error) 662 return (error); 663 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 664
|
672 /* 673 * allocate one xmit buffer if < 16k, two buffers otherwise 674 */ 675 if ((memsize < 16384) ||
| 665 /* 666 * allocate one xmit buffer if < 16k, two buffers otherwise 667 */ 668 if ((memsize < 16384) ||
|
676 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
| 669 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
|
677 sc->txb_cnt = 1; 678 } else { 679 sc->txb_cnt = 2; 680 } 681 sc->tx_page_start = ED_WD_PAGE_OFFSET; 682 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 683 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 684 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 685 sc->mem_size = memsize; 686 sc->mem_end = sc->mem_start + memsize; 687 688 /* 689 * Get station address from on-board ROM 690 */ 691 for (i = 0; i < ETHER_ADDR_LEN; ++i) 692 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 693 694 /* 695 * Set upper address bits and 8/16 bit access to shared memory. 696 */ 697 if (isa16bit) { 698 if (sc->is790) { 699 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 700 } else { 701 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 702 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 703 } 704 /* 705 * Enable 16bit access 706 */ 707 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 708 ED_WD_LAAR_M16EN); 709 } else { 710 if (((sc->type & ED_WD_SOFTCONFIG) || 711#ifdef TOSH_ETHER 712 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 713#endif 714 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 715 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 716 ED_WD_LAAR_ADDRHI; 717 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 718 } 719 } 720 721 /* 722 * Set address and enable interface shared memory. 723 */ 724 if (!sc->is790) { 725#ifdef TOSH_ETHER 726 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 727 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 728 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 729 730#else 731 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 732 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 733#endif 734 sc->cr_proto = ED_CR_RD2; 735 } else { 736 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 737 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 738 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 739 ((kvtop(sc->mem_start) >> 11) & 0x40) | 740 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 741 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 742 sc->cr_proto = 0; 743 } 744 745#if 0 746 printf("starting memory performance test at 0x%x, size %d...\n", 747 sc->mem_start, memsize*16384); 748 for (i = 0; i < 16384; i++) 749 bzero(sc->mem_start, memsize); 750 printf("***DONE***\n"); 751#endif 752 753 /* 754 * Now zero memory and verify that it is clear 755 */ 756 bzero(sc->mem_start, memsize); 757 758 for (i = 0; i < memsize; ++i) { 759 if (sc->mem_start[i]) {
| 670 sc->txb_cnt = 1; 671 } else { 672 sc->txb_cnt = 2; 673 } 674 sc->tx_page_start = ED_WD_PAGE_OFFSET; 675 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 676 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 677 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 678 sc->mem_size = memsize; 679 sc->mem_end = sc->mem_start + memsize; 680 681 /* 682 * Get station address from on-board ROM 683 */ 684 for (i = 0; i < ETHER_ADDR_LEN; ++i) 685 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 686 687 /* 688 * Set upper address bits and 8/16 bit access to shared memory. 689 */ 690 if (isa16bit) { 691 if (sc->is790) { 692 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 693 } else { 694 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 695 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 696 } 697 /* 698 * Enable 16bit access 699 */ 700 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 701 ED_WD_LAAR_M16EN); 702 } else { 703 if (((sc->type & ED_WD_SOFTCONFIG) || 704#ifdef TOSH_ETHER 705 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 706#endif 707 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 708 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 709 ED_WD_LAAR_ADDRHI; 710 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 711 } 712 } 713 714 /* 715 * Set address and enable interface shared memory. 716 */ 717 if (!sc->is790) { 718#ifdef TOSH_ETHER 719 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 720 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 721 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 722 723#else 724 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 725 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 726#endif 727 sc->cr_proto = ED_CR_RD2; 728 } else { 729 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 730 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 731 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 732 ((kvtop(sc->mem_start) >> 11) & 0x40) | 733 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 734 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 735 sc->cr_proto = 0; 736 } 737 738#if 0 739 printf("starting memory performance test at 0x%x, size %d...\n", 740 sc->mem_start, memsize*16384); 741 for (i = 0; i < 16384; i++) 742 bzero(sc->mem_start, memsize); 743 printf("***DONE***\n"); 744#endif 745 746 /* 747 * Now zero memory and verify that it is clear 748 */ 749 bzero(sc->mem_start, memsize); 750 751 for (i = 0; i < memsize; ++i) { 752 if (sc->mem_start[i]) {
|
760 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 761 isa_dev->id_unit, kvtop(sc->mem_start + i));
| 753 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 754 kvtop(sc->mem_start + i));
|
762 763 /* 764 * Disable 16 bit access to shared memory 765 */ 766 if (isa16bit) { 767 if (sc->is790) { 768 outb(sc->asic_addr + ED_WD_MSR, 0x00); 769 } 770 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 771 ~ED_WD_LAAR_M16EN); 772 }
| 755 756 /* 757 * Disable 16 bit access to shared memory 758 */ 759 if (isa16bit) { 760 if (sc->is790) { 761 outb(sc->asic_addr + ED_WD_MSR, 0x00); 762 } 763 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 764 ~ED_WD_LAAR_M16EN); 765 }
|
773 return (0);
| 766 return (ENXIO);
|
774 } 775 } 776 777 /* 778 * Disable 16bit access to shared memory - we leave it 779 * disabled so that 1) machines reboot properly when the board 780 * is set 16 bit mode and there are conflicting 8bit 781 * devices/ROMS in the same 128k address space as this boards 782 * shared memory. and 2) so that other 8 bit devices with 783 * shared memory can be used in this 128k region, too. 784 */ 785 if (isa16bit) { 786 if (sc->is790) { 787 outb(sc->asic_addr + ED_WD_MSR, 0x00); 788 } 789 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 790 ~ED_WD_LAAR_M16EN); 791 }
| 767 } 768 } 769 770 /* 771 * Disable 16bit access to shared memory - we leave it 772 * disabled so that 1) machines reboot properly when the board 773 * is set 16 bit mode and there are conflicting 8bit 774 * devices/ROMS in the same 128k address space as this boards 775 * shared memory. and 2) so that other 8 bit devices with 776 * shared memory can be used in this 128k region, too. 777 */ 778 if (isa16bit) { 779 if (sc->is790) { 780 outb(sc->asic_addr + ED_WD_MSR, 0x00); 781 } 782 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 783 ~ED_WD_LAAR_M16EN); 784 }
|
792 return (ED_WD_IO_PORTS);
| 785 return (0);
|
793} 794 795/* 796 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 797 */ 798static int
| 786} 787 788/* 789 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 790 */ 791static int
|
799ed_probe_3Com(isa_dev) 800 struct isa_device *isa_dev;
| 792ed_probe_3Com(dev) 793 device_t dev;
|
801{
| 794{
|
802 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
| 795 struct ed_softc *sc = device_get_softc(dev); 796 int error;
|
803 int i;
| 797 int i;
|
| 798 int flags = isa_get_flags(dev);
|
804 u_int memsize; 805 u_char isa16bit;
| 799 u_int memsize; 800 u_char isa16bit;
|
| 801 u_long conf_maddr, conf_msize, irq, junk;
|
806
| 802
|
807 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 808 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
| 803 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 804 if (error) 805 return (error);
|
809
| 806
|
| 807 sc->asic_addr = rman_get_start(sc->port_res) + ED_3COM_ASIC_OFFSET; 808 sc->nic_addr = rman_get_start(sc->port_res) + ED_3COM_NIC_OFFSET; 809
|
810 /* 811 * Verify that the kernel configured I/O address matches the board 812 * configured address 813 */ 814 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 815 case ED_3COM_BCFR_300:
| 810 /* 811 * Verify that the kernel configured I/O address matches the board 812 * configured address 813 */ 814 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 815 case ED_3COM_BCFR_300:
|
816 if (isa_dev->id_iobase != 0x300) 817 return (0);
| 816 if (rman_get_start(sc->port_res) != 0x300) 817 return (ENXIO);
|
818 break; 819 case ED_3COM_BCFR_310:
| 818 break; 819 case ED_3COM_BCFR_310:
|
820 if (isa_dev->id_iobase != 0x310) 821 return (0);
| 820 if (rman_get_start(sc->port_res) != 0x310) 821 return (ENXIO);
|
822 break; 823 case ED_3COM_BCFR_330:
| 822 break; 823 case ED_3COM_BCFR_330:
|
824 if (isa_dev->id_iobase != 0x330) 825 return (0);
| 824 if (rman_get_start(sc->port_res) != 0x330) 825 return (ENXIO);
|
826 break; 827 case ED_3COM_BCFR_350:
| 826 break; 827 case ED_3COM_BCFR_350:
|
828 if (isa_dev->id_iobase != 0x350) 829 return (0);
| 828 if (rman_get_start(sc->port_res) != 0x350) 829 return (ENXIO);
|
830 break; 831 case ED_3COM_BCFR_250:
| 830 break; 831 case ED_3COM_BCFR_250:
|
832 if (isa_dev->id_iobase != 0x250) 833 return (0);
| 832 if (rman_get_start(sc->port_res) != 0x250) 833 return (ENXIO);
|
834 break; 835 case ED_3COM_BCFR_280:
| 834 break; 835 case ED_3COM_BCFR_280:
|
836 if (isa_dev->id_iobase != 0x280) 837 return (0);
| 836 if (rman_get_start(sc->port_res) != 0x280) 837 return (ENXIO);
|
838 break; 839 case ED_3COM_BCFR_2A0:
| 838 break; 839 case ED_3COM_BCFR_2A0:
|
840 if (isa_dev->id_iobase != 0x2a0) 841 return (0);
| 840 if (rman_get_start(sc->port_res) != 0x2a0) 841 return (ENXIO);
|
842 break; 843 case ED_3COM_BCFR_2E0:
| 842 break; 843 case ED_3COM_BCFR_2E0:
|
844 if (isa_dev->id_iobase != 0x2e0) 845 return (0);
| 844 if (rman_get_start(sc->port_res) != 0x2e0) 845 return (ENXIO);
|
846 break; 847 default:
| 846 break; 847 default:
|
848 return (0);
| 848 return (ENXIO);
|
849 } 850
| 849 } 850
|
| 851 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 852 SYS_RES_MEMORY, 0, 853 &conf_maddr, &conf_msize); 854 if (error) 855 return (error); 856
|
851 /* 852 * Verify that the kernel shared memory address matches the board 853 * configured address. 854 */ 855 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 856 case ED_3COM_PCFR_DC000:
| 857 /* 858 * Verify that the kernel shared memory address matches the board 859 * configured address. 860 */ 861 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 862 case ED_3COM_PCFR_DC000:
|
857 if (kvtop(isa_dev->id_maddr) != 0xdc000) 858 return (0);
| 863 if (conf_maddr != 0xdc000) 864 return (ENXIO);
|
859 break; 860 case ED_3COM_PCFR_D8000:
| 865 break; 866 case ED_3COM_PCFR_D8000:
|
861 if (kvtop(isa_dev->id_maddr) != 0xd8000) 862 return (0);
| 867 if (conf_maddr != 0xd8000) 868 return (ENXIO);
|
863 break; 864 case ED_3COM_PCFR_CC000:
| 869 break; 870 case ED_3COM_PCFR_CC000:
|
865 if (kvtop(isa_dev->id_maddr) != 0xcc000) 866 return (0);
| 871 if (conf_maddr != 0xcc000) 872 return (ENXIO);
|
867 break; 868 case ED_3COM_PCFR_C8000:
| 873 break; 874 case ED_3COM_PCFR_C8000:
|
869 if (kvtop(isa_dev->id_maddr) != 0xc8000) 870 return (0);
| 875 if (conf_maddr != 0xc8000) 876 return (ENXIO);
|
871 break; 872 default:
| 877 break; 878 default:
|
873 return (0);
| 879 return (ENXIO);
|
874 } 875 876 877 /* 878 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 879 * sequence because it'll lock up if the cable isn't connected if we 880 * don't. 881 */ 882 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 883 884 /* 885 * Wait for a while, then un-reset it 886 */ 887 DELAY(50); 888 889 /* 890 * The 3Com ASIC defaults to rather strange settings for the CR after 891 * a reset - it's important to set it again after the following outb 892 * (this is done when we map the PROM below). 893 */ 894 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 895 896 /* 897 * Wait a bit for the NIC to recover from the reset 898 */ 899 DELAY(5000); 900 901 sc->vendor = ED_VENDOR_3COM; 902 sc->type_str = "3c503"; 903 sc->mem_shared = 1; 904 sc->cr_proto = ED_CR_RD2; 905 906 /* 907 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 908 * to it. 909 */ 910 memsize = 8192; 911 912 /* 913 * Get station address from on-board ROM 914 */ 915 916 /* 917 * First, map ethernet address PROM over the top of where the NIC 918 * registers normally appear. 919 */ 920 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 921 922 for (i = 0; i < ETHER_ADDR_LEN; ++i) 923 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 924 925 /* 926 * Unmap PROM - select NIC registers. The proper setting of the 927 * tranceiver is set in ed_init so that the attach code is given a 928 * chance to set the default based on a compile-time config option 929 */ 930 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 931 932 /* 933 * Determine if this is an 8bit or 16bit board 934 */ 935 936 /* 937 * select page 0 registers 938 */ 939 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 940 941 /* 942 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 943 * board. 944 */ 945 outb(sc->nic_addr + ED_P0_DCR, 0); 946 947 /* 948 * select page 2 registers 949 */ 950 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 951 952 /* 953 * The 3c503 forces the WTS bit to a one if this is a 16bit board 954 */ 955 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 956 isa16bit = 1; 957 else 958 isa16bit = 0; 959 960 /* 961 * select page 0 registers 962 */ 963 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 964
| 880 } 881 882 883 /* 884 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 885 * sequence because it'll lock up if the cable isn't connected if we 886 * don't. 887 */ 888 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 889 890 /* 891 * Wait for a while, then un-reset it 892 */ 893 DELAY(50); 894 895 /* 896 * The 3Com ASIC defaults to rather strange settings for the CR after 897 * a reset - it's important to set it again after the following outb 898 * (this is done when we map the PROM below). 899 */ 900 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 901 902 /* 903 * Wait a bit for the NIC to recover from the reset 904 */ 905 DELAY(5000); 906 907 sc->vendor = ED_VENDOR_3COM; 908 sc->type_str = "3c503"; 909 sc->mem_shared = 1; 910 sc->cr_proto = ED_CR_RD2; 911 912 /* 913 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 914 * to it. 915 */ 916 memsize = 8192; 917 918 /* 919 * Get station address from on-board ROM 920 */ 921 922 /* 923 * First, map ethernet address PROM over the top of where the NIC 924 * registers normally appear. 925 */ 926 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 927 928 for (i = 0; i < ETHER_ADDR_LEN; ++i) 929 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 930 931 /* 932 * Unmap PROM - select NIC registers. The proper setting of the 933 * tranceiver is set in ed_init so that the attach code is given a 934 * chance to set the default based on a compile-time config option 935 */ 936 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 937 938 /* 939 * Determine if this is an 8bit or 16bit board 940 */ 941 942 /* 943 * select page 0 registers 944 */ 945 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 946 947 /* 948 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 949 * board. 950 */ 951 outb(sc->nic_addr + ED_P0_DCR, 0); 952 953 /* 954 * select page 2 registers 955 */ 956 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 957 958 /* 959 * The 3c503 forces the WTS bit to a one if this is a 16bit board 960 */ 961 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 962 isa16bit = 1; 963 else 964 isa16bit = 0; 965 966 /* 967 * select page 0 registers 968 */ 969 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 970
|
965 sc->mem_start = (caddr_t) isa_dev->id_maddr;
| 971 error = ed_alloc_memory(dev, 0, memsize); 972 if (error) 973 return (error); 974 975 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
|
966 sc->mem_size = memsize; 967 sc->mem_end = sc->mem_start + memsize; 968 969 /* 970 * We have an entire 8k window to put the transmit buffers on the 971 * 16bit boards. But since the 16bit 3c503's shared memory is only 972 * fast enough to overlap the loading of one full-size packet, trying 973 * to load more than 2 buffers can actually leave the transmitter idle 974 * during the load. So 2 seems the best value. (Although a mix of 975 * variable-sized packets might change this assumption. Nonetheless, 976 * we optimize for linear transfers of same-size packets.) 977 */ 978 if (isa16bit) {
| 976 sc->mem_size = memsize; 977 sc->mem_end = sc->mem_start + memsize; 978 979 /* 980 * We have an entire 8k window to put the transmit buffers on the 981 * 16bit boards. But since the 16bit 3c503's shared memory is only 982 * fast enough to overlap the loading of one full-size packet, trying 983 * to load more than 2 buffers can actually leave the transmitter idle 984 * during the load. So 2 seems the best value. (Although a mix of 985 * variable-sized packets might change this assumption. Nonetheless, 986 * we optimize for linear transfers of same-size packets.) 987 */ 988 if (isa16bit) {
|
979 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
| 989 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
|
980 sc->txb_cnt = 1; 981 else 982 sc->txb_cnt = 2; 983 984 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 985 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 986 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 987 ED_3COM_RX_PAGE_OFFSET_16BIT; 988 sc->mem_ring = sc->mem_start; 989 } else { 990 sc->txb_cnt = 1; 991 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 992 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 993 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 994 ED_3COM_TX_PAGE_OFFSET_8BIT; 995 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 996 } 997 998 sc->isa16bit = isa16bit; 999 1000 /* 1001 * Initialize GA page start/stop registers. Probably only needed if 1002 * doing DMA, but what the hell. 1003 */ 1004 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1005 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1006 1007 /* 1008 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1009 */
| 990 sc->txb_cnt = 1; 991 else 992 sc->txb_cnt = 2; 993 994 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 995 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 996 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 997 ED_3COM_RX_PAGE_OFFSET_16BIT; 998 sc->mem_ring = sc->mem_start; 999 } else { 1000 sc->txb_cnt = 1; 1001 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 1002 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 1003 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 1004 ED_3COM_TX_PAGE_OFFSET_8BIT; 1005 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 1006 } 1007 1008 sc->isa16bit = isa16bit; 1009 1010 /* 1011 * Initialize GA page start/stop registers. Probably only needed if 1012 * doing DMA, but what the hell. 1013 */ 1014 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1015 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1016 1017 /* 1018 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1019 */
|
1010 switch (isa_dev->id_irq) { 1011 case IRQ2:
| 1020 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 1021 SYS_RES_IRQ, 0, 1022 &irq, &junk); 1023 if (error) 1024 return (error); 1025 1026 switch (irq) { 1027 case 2:
|
1012 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1013 break;
| 1028 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1029 break;
|
1014 case IRQ3:
| 1030 case 3:
|
1015 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1016 break;
| 1031 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1032 break;
|
1017 case IRQ4:
| 1033 case 4:
|
1018 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1019 break;
| 1034 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1035 break;
|
1020 case IRQ5:
| 1036 case 5:
|
1021 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1022 break; 1023 default:
| 1037 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1038 break; 1039 default:
|
1024 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1025 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1026 return (0);
| 1040 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 1041 irq); 1042 return (ENXIO);
|
1027 } 1028 1029 /* 1030 * Initialize GA configuration register. Set bank and enable shared 1031 * mem. 1032 */ 1033 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1034 ED_3COM_GACFR_MBS0); 1035 1036 /* 1037 * Initialize "Vector Pointer" registers. These gawd-awful things are 1038 * compared to 20 bits of the address on ISA, and if they match, the 1039 * shared memory is disabled. We set them to 0xffff0...allegedly the 1040 * reset vector. 1041 */ 1042 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1043 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1044 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1045 1046 /* 1047 * Zero memory and verify that it is clear 1048 */ 1049 bzero(sc->mem_start, memsize); 1050 1051 for (i = 0; i < memsize; ++i) 1052 if (sc->mem_start[i]) {
| 1043 } 1044 1045 /* 1046 * Initialize GA configuration register. Set bank and enable shared 1047 * mem. 1048 */ 1049 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1050 ED_3COM_GACFR_MBS0); 1051 1052 /* 1053 * Initialize "Vector Pointer" registers. These gawd-awful things are 1054 * compared to 20 bits of the address on ISA, and if they match, the 1055 * shared memory is disabled. We set them to 0xffff0...allegedly the 1056 * reset vector. 1057 */ 1058 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1059 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1060 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1061 1062 /* 1063 * Zero memory and verify that it is clear 1064 */ 1065 bzero(sc->mem_start, memsize); 1066 1067 for (i = 0; i < memsize; ++i) 1068 if (sc->mem_start[i]) {
|
1053 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1054 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1055 return (0);
| 1069 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n", 1070 kvtop(sc->mem_start + i)); 1071 return (ENXIO);
|
1056 }
| 1072 }
|
1057 isa_dev->id_msize = memsize; 1058 return (ED_3COM_IO_PORTS);
| 1073 return (0);
|
1059} 1060 1061/* 1062 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1063 */ 1064static int
| 1074} 1075 1076/* 1077 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1078 */ 1079static int
|
1065ed_probe_Novell_generic(sc, port, unit, flags) 1066 struct ed_softc *sc; 1067 int port; 1068 int unit;
| 1080ed_probe_Novell_generic(dev, port_rid, flags) 1081 device_t dev; 1082 int port_rid;
|
1069 int flags; 1070{
| 1083 int flags; 1084{
|
| 1085 struct ed_softc *sc = device_get_softc(dev);
|
1071 u_int memsize, n; 1072 u_char romdata[16], tmp; 1073 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1074 char test_buffer[32];
| 1086 u_int memsize, n; 1087 u_char romdata[16], tmp; 1088 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1089 char test_buffer[32];
|
| 1090 int error;
|
1075
| 1091
|
1076 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1077 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
| 1092 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 1093 if (error) 1094 return (error);
|
1078
| 1095
|
| 1096 sc->asic_addr = rman_get_start(sc->port_res) + ED_NOVELL_ASIC_OFFSET; 1097 sc->nic_addr = rman_get_start(sc->port_res) + ED_NOVELL_NIC_OFFSET; 1098
|
1079 /* XXX - do Novell-specific probe here */ 1080 1081 /* Reset the board */ 1082#ifdef GWETHER 1083 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1084 DELAY(200); 1085#endif /* GWETHER */ 1086 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1087 1088 /* 1089 * I don't know if this is necessary; probably cruft leftover from 1090 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1091 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1092 * non-invasive...but some boards don't seem to reset and I don't have 1093 * complete documentation on what the 'right' thing to do is...so we 1094 * do the invasive thing for now. Yuck.] 1095 */ 1096 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1097 DELAY(5000); 1098 1099 /* 1100 * This is needed because some NE clones apparently don't reset the 1101 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1102 * - this makes the probe invasive! ...Done against my better 1103 * judgement. -DLG 1104 */ 1105 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1106 1107 DELAY(5000); 1108 1109 /* Make sure that we really have an 8390 based board */ 1110 if (!ed_probe_generic8390(sc))
| 1099 /* XXX - do Novell-specific probe here */ 1100 1101 /* Reset the board */ 1102#ifdef GWETHER 1103 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1104 DELAY(200); 1105#endif /* GWETHER */ 1106 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1107 1108 /* 1109 * I don't know if this is necessary; probably cruft leftover from 1110 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1111 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1112 * non-invasive...but some boards don't seem to reset and I don't have 1113 * complete documentation on what the 'right' thing to do is...so we 1114 * do the invasive thing for now. Yuck.] 1115 */ 1116 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1117 DELAY(5000); 1118 1119 /* 1120 * This is needed because some NE clones apparently don't reset the 1121 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1122 * - this makes the probe invasive! ...Done against my better 1123 * judgement. -DLG 1124 */ 1125 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1126 1127 DELAY(5000); 1128 1129 /* Make sure that we really have an 8390 based board */ 1130 if (!ed_probe_generic8390(sc))
|
1111 return (0);
| 1131 return (ENXIO);
|
1112 1113 sc->vendor = ED_VENDOR_NOVELL; 1114 sc->mem_shared = 0; 1115 sc->cr_proto = ED_CR_RD2; 1116 1117 /* 1118 * Test the ability to read and write to the NIC memory. This has the 1119 * side affect of determining if this is an NE1000 or an NE2000. 1120 */ 1121 1122 /* 1123 * This prevents packets from being stored in the NIC memory when the 1124 * readmem routine turns on the start bit in the CR. 1125 */ 1126 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1127 1128 /* Temporarily initialize DCR for byte operations */ 1129 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1130 1131 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1132 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1133 1134 sc->isa16bit = 0; 1135 1136 /* 1137 * Write a test pattern in byte mode. If this fails, then there 1138 * probably isn't any memory at 8k - which likely means that the board 1139 * is an NE2000. 1140 */ 1141 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1142 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1143 1144 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1145 /* not an NE1000 - try NE2000 */ 1146 1147 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1148 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1149 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1150 1151 sc->isa16bit = 1; 1152 1153 /* 1154 * Write a test pattern in word mode. If this also fails, then 1155 * we don't know what this board is. 1156 */ 1157 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1158 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1159 1160 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
| 1132 1133 sc->vendor = ED_VENDOR_NOVELL; 1134 sc->mem_shared = 0; 1135 sc->cr_proto = ED_CR_RD2; 1136 1137 /* 1138 * Test the ability to read and write to the NIC memory. This has the 1139 * side affect of determining if this is an NE1000 or an NE2000. 1140 */ 1141 1142 /* 1143 * This prevents packets from being stored in the NIC memory when the 1144 * readmem routine turns on the start bit in the CR. 1145 */ 1146 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1147 1148 /* Temporarily initialize DCR for byte operations */ 1149 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1150 1151 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1152 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1153 1154 sc->isa16bit = 0; 1155 1156 /* 1157 * Write a test pattern in byte mode. If this fails, then there 1158 * probably isn't any memory at 8k - which likely means that the board 1159 * is an NE2000. 1160 */ 1161 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1162 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1163 1164 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1165 /* not an NE1000 - try NE2000 */ 1166 1167 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1168 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1169 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1170 1171 sc->isa16bit = 1; 1172 1173 /* 1174 * Write a test pattern in word mode. If this also fails, then 1175 * we don't know what this board is. 1176 */ 1177 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1178 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1179 1180 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
|
1161 return (0); /* not an NE2000 either */
| 1181 return (ENXIO); /* not an NE2000 either */
|
1162 1163 sc->type = ED_TYPE_NE2000; 1164 sc->type_str = "NE2000"; 1165 } else { 1166 sc->type = ED_TYPE_NE1000; 1167 sc->type_str = "NE1000"; 1168 } 1169 1170 /* 8k of memory plus an additional 8k if 16bit */ 1171 memsize = 8192 + sc->isa16bit * 8192; 1172 1173#if 0 /* probably not useful - NE boards only come two ways */ 1174 /* allow kernel config file overrides */ 1175 if (isa_dev->id_msize) 1176 memsize = isa_dev->id_msize; 1177#endif 1178 1179 sc->mem_size = memsize; 1180 1181 /* NIC memory doesn't start at zero on an NE board */ 1182 /* The start address is tied to the bus width */ 1183 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1184 sc->mem_end = sc->mem_start + memsize; 1185 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1186 1187#ifdef GWETHER 1188 { 1189 int x, i, mstart = 0, msize = 0; 1190 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1191 1192 for (i = 0; i < ED_PAGE_SIZE; i++) 1193 pbuf0[i] = 0; 1194 1195 /* Clear all the memory. */ 1196 for (x = 1; x < 256; x++) 1197 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1198 1199 /* Search for the start of RAM. */ 1200 for (x = 1; x < 256; x++) { 1201 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1202 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1203 for (i = 0; i < ED_PAGE_SIZE; i++) 1204 pbuf[i] = 255 - x; 1205 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1206 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1207 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1208 mstart = x * ED_PAGE_SIZE; 1209 msize = ED_PAGE_SIZE; 1210 break; 1211 } 1212 } 1213 } 1214 1215 if (mstart == 0) {
| 1182 1183 sc->type = ED_TYPE_NE2000; 1184 sc->type_str = "NE2000"; 1185 } else { 1186 sc->type = ED_TYPE_NE1000; 1187 sc->type_str = "NE1000"; 1188 } 1189 1190 /* 8k of memory plus an additional 8k if 16bit */ 1191 memsize = 8192 + sc->isa16bit * 8192; 1192 1193#if 0 /* probably not useful - NE boards only come two ways */ 1194 /* allow kernel config file overrides */ 1195 if (isa_dev->id_msize) 1196 memsize = isa_dev->id_msize; 1197#endif 1198 1199 sc->mem_size = memsize; 1200 1201 /* NIC memory doesn't start at zero on an NE board */ 1202 /* The start address is tied to the bus width */ 1203 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1204 sc->mem_end = sc->mem_start + memsize; 1205 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1206 1207#ifdef GWETHER 1208 { 1209 int x, i, mstart = 0, msize = 0; 1210 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1211 1212 for (i = 0; i < ED_PAGE_SIZE; i++) 1213 pbuf0[i] = 0; 1214 1215 /* Clear all the memory. */ 1216 for (x = 1; x < 256; x++) 1217 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1218 1219 /* Search for the start of RAM. */ 1220 for (x = 1; x < 256; x++) { 1221 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1222 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1223 for (i = 0; i < ED_PAGE_SIZE; i++) 1224 pbuf[i] = 255 - x; 1225 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1227 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1228 mstart = x * ED_PAGE_SIZE; 1229 msize = ED_PAGE_SIZE; 1230 break; 1231 } 1232 } 1233 } 1234 1235 if (mstart == 0) {
|
1216 printf("ed%d: Cannot find start of RAM.\n", unit); 1217 return 0;
| 1236 device_printf(dev, "Cannot find start of RAM.\n"); 1237 return (ENXIO);
|
1218 } 1219 /* Search for the start of RAM. */ 1220 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1221 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1222 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1223 for (i = 0; i < ED_PAGE_SIZE; i++) 1224 pbuf[i] = 255 - x; 1225 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1227 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1228 msize += ED_PAGE_SIZE; 1229 else { 1230 break; 1231 } 1232 } else { 1233 break; 1234 } 1235 } 1236 1237 if (msize == 0) {
| 1238 } 1239 /* Search for the start of RAM. */ 1240 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1241 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1242 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1243 for (i = 0; i < ED_PAGE_SIZE; i++) 1244 pbuf[i] = 255 - x; 1245 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1246 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1247 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1248 msize += ED_PAGE_SIZE; 1249 else { 1250 break; 1251 } 1252 } else { 1253 break; 1254 } 1255 } 1256 1257 if (msize == 0) {
|
1238 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1239 return 0;
| 1258 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1259 return (ENXIO);
|
1240 }
| 1260 }
|
1241 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
| 1261 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
|
1242 1243 sc->mem_size = msize; 1244 sc->mem_start = (char *) mstart; 1245 sc->mem_end = (char *) (msize + mstart); 1246 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1247 } 1248#endif /* GWETHER */ 1249 1250 /* 1251 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1252 * otherwise). 1253 */ 1254 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1255 sc->txb_cnt = 1; 1256 else 1257 sc->txb_cnt = 2; 1258 1259 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1260 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1261 1262 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1263 1264 ed_pio_readmem(sc, 0, romdata, 16); 1265 for (n = 0; n < ETHER_ADDR_LEN; n++) 1266 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1267 1268#ifdef GWETHER 1269 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1270 sc->type_str = "Gateway AT"; 1271 } 1272#endif /* GWETHER */ 1273 1274 /* clear any pending interrupts that might have occurred above */ 1275 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1276
| 1262 1263 sc->mem_size = msize; 1264 sc->mem_start = (char *) mstart; 1265 sc->mem_end = (char *) (msize + mstart); 1266 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1267 } 1268#endif /* GWETHER */ 1269 1270 /* 1271 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1272 * otherwise). 1273 */ 1274 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1275 sc->txb_cnt = 1; 1276 else 1277 sc->txb_cnt = 2; 1278 1279 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1280 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1281 1282 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1283 1284 ed_pio_readmem(sc, 0, romdata, 16); 1285 for (n = 0; n < ETHER_ADDR_LEN; n++) 1286 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1287 1288#ifdef GWETHER 1289 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1290 sc->type_str = "Gateway AT"; 1291 } 1292#endif /* GWETHER */ 1293 1294 /* clear any pending interrupts that might have occurred above */ 1295 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1296
|
1277 return (ED_NOVELL_IO_PORTS);
| 1297 return (0);
|
1278} 1279 1280static int
| 1298} 1299 1300static int
|
1281ed_probe_Novell(isa_dev) 1282 struct isa_device *isa_dev;
| 1301ed_probe_Novell(dev) 1302 device_t dev;
|
1283{
| 1303{
|
1284 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1285 int nports; 1286 1287 nports = ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1288 isa_dev->id_unit, isa_dev->id_flags); 1289 if (nports) 1290 isa_dev->id_maddr = 0; 1291 1292 return (nports);
| 1304 return ed_probe_Novell_generic(dev, 0, isa_get_flags(dev));
|
1293} 1294
| 1305} 1306
|
1295#if NCARD > 0
| 1307#if NCARDxx > 0
|
1296/* 1297 * Probe framework for pccards. Replicates the standard framework, 1298 * minus the pccard driver registration and ignores the ether address 1299 * supplied (from the CIS), relying on the probe to find it instead. 1300 */ 1301static int 1302ed_probe_pccard(isa_dev, ether) 1303 struct isa_device *isa_dev; 1304 u_char *ether; 1305{ 1306 int nports; 1307 1308 nports = ed_probe_WD80x3(isa_dev); 1309 if (nports) 1310 return (nports); 1311 1312 nports = ed_probe_Novell(isa_dev); 1313 if (nports) 1314 return (nports); 1315 1316 return (0); 1317} 1318 1319#endif /* NCARD > 0 */ 1320 1321#define ED_HPP_TEST_SIZE 16 1322 1323/* 1324 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1325 * (HP Part nos: 27247B and 27252A). 1326 * 1327 * The card has an asic wrapper around a DS8390 core. The asic handles 1328 * host accesses and offers both standard register IO and memory mapped 1329 * IO. Memory mapped I/O allows better performance at the expense of greater 1330 * chance of an incompatibility with existing ISA cards. 1331 * 1332 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1333 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1334 * don't allow 32 bit accesses; these are indicated by a bit in the software 1335 * ID register (see if_edreg.h). 1336 * 1337 * Other caveats are: we should read the MAC address only when the card 1338 * is inactive. 1339 * 1340 * For more information; please consult the CRYNWR packet driver. 1341 * 1342 * The AUI port is turned on using the "link2" option on the ifconfig 1343 * command line. 1344 */ 1345static int
| 1308/* 1309 * Probe framework for pccards. Replicates the standard framework, 1310 * minus the pccard driver registration and ignores the ether address 1311 * supplied (from the CIS), relying on the probe to find it instead. 1312 */ 1313static int 1314ed_probe_pccard(isa_dev, ether) 1315 struct isa_device *isa_dev; 1316 u_char *ether; 1317{ 1318 int nports; 1319 1320 nports = ed_probe_WD80x3(isa_dev); 1321 if (nports) 1322 return (nports); 1323 1324 nports = ed_probe_Novell(isa_dev); 1325 if (nports) 1326 return (nports); 1327 1328 return (0); 1329} 1330 1331#endif /* NCARD > 0 */ 1332 1333#define ED_HPP_TEST_SIZE 16 1334 1335/* 1336 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1337 * (HP Part nos: 27247B and 27252A). 1338 * 1339 * The card has an asic wrapper around a DS8390 core. The asic handles 1340 * host accesses and offers both standard register IO and memory mapped 1341 * IO. Memory mapped I/O allows better performance at the expense of greater 1342 * chance of an incompatibility with existing ISA cards. 1343 * 1344 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1345 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1346 * don't allow 32 bit accesses; these are indicated by a bit in the software 1347 * ID register (see if_edreg.h). 1348 * 1349 * Other caveats are: we should read the MAC address only when the card 1350 * is inactive. 1351 * 1352 * For more information; please consult the CRYNWR packet driver. 1353 * 1354 * The AUI port is turned on using the "link2" option on the ifconfig 1355 * command line. 1356 */ 1357static int
|
1346ed_probe_HP_pclanp(isa_dev) 1347 struct isa_device *isa_dev;
| 1358ed_probe_HP_pclanp(dev) 1359 device_t dev;
|
1348{
| 1360{
|
1349 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
| 1361 struct ed_softc *sc = device_get_softc(dev); 1362 int error;
|
1350 int n; /* temp var */ 1351 int memsize; /* mem on board */ 1352 u_char checksum; /* checksum of board address */ 1353 u_char irq; /* board configured IRQ */ 1354 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1355 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
| 1363 int n; /* temp var */ 1364 int memsize; /* mem on board */ 1365 u_char checksum; /* checksum of board address */ 1366 u_char irq; /* board configured IRQ */ 1367 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1368 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
|
| 1369 u_long conf_maddr, conf_msize, conf_irq, junk;
|
1356
| 1370
|
| 1371 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1372 if (error) 1373 return (error);
|
1357 1358 /* Fill in basic information */
| 1374 1375 /* Fill in basic information */
|
1359 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1360 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
| 1376 sc->asic_addr = rman_get_start(sc->port_res) + ED_HPP_ASIC_OFFSET; 1377 sc->nic_addr = rman_get_start(sc->port_res) + ED_HPP_NIC_OFFSET;
|
1361 sc->is790 = 0; 1362 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1363 1364 /* 1365 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1366 */ 1367 1368 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1369 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1370 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1371 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1372 return 0; 1373 1374 /* 1375 * Read the MAC address and verify checksum on the address. 1376 */ 1377 1378 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1379 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1380 checksum += (sc->arpcom.ac_enaddr[n] = 1381 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1382 1383 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1384 1385 if (checksum != 0xFF) 1386 return 0; 1387 1388 /* 1389 * Verify that the software model number is 0. 1390 */ 1391 1392 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1393 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1394 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1395 return 0; 1396 1397 /* 1398 * Read in and save the current options configured on card. 1399 */ 1400 1401 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1402 1403 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1404 ED_HPP_OPTION_CHIP_RESET | 1405 ED_HPP_OPTION_ENABLE_IRQ); 1406 1407 /* 1408 * Reset the chip. This requires writing to the option register 1409 * so take care to preserve the other bits. 1410 */ 1411 1412 outw(sc->asic_addr + ED_HPP_OPTION, 1413 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1414 ED_HPP_OPTION_CHIP_RESET))); 1415 1416 DELAY(5000); /* wait for chip reset to complete */ 1417 1418 outw(sc->asic_addr + ED_HPP_OPTION, 1419 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1420 ED_HPP_OPTION_CHIP_RESET | 1421 ED_HPP_OPTION_ENABLE_IRQ))); 1422 1423 DELAY(5000); 1424 1425 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1426 return 0; /* reset did not complete */ 1427 1428 /* 1429 * Read out configuration information. 1430 */ 1431 1432 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1433 1434 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1435 1436 /* 1437 * Check for impossible IRQ. 1438 */ 1439
| 1378 sc->is790 = 0; 1379 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1380 1381 /* 1382 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1383 */ 1384 1385 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1386 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1387 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1388 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1389 return 0; 1390 1391 /* 1392 * Read the MAC address and verify checksum on the address. 1393 */ 1394 1395 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1396 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1397 checksum += (sc->arpcom.ac_enaddr[n] = 1398 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1399 1400 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1401 1402 if (checksum != 0xFF) 1403 return 0; 1404 1405 /* 1406 * Verify that the software model number is 0. 1407 */ 1408 1409 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1410 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1411 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1412 return 0; 1413 1414 /* 1415 * Read in and save the current options configured on card. 1416 */ 1417 1418 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1419 1420 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1421 ED_HPP_OPTION_CHIP_RESET | 1422 ED_HPP_OPTION_ENABLE_IRQ); 1423 1424 /* 1425 * Reset the chip. This requires writing to the option register 1426 * so take care to preserve the other bits. 1427 */ 1428 1429 outw(sc->asic_addr + ED_HPP_OPTION, 1430 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1431 ED_HPP_OPTION_CHIP_RESET))); 1432 1433 DELAY(5000); /* wait for chip reset to complete */ 1434 1435 outw(sc->asic_addr + ED_HPP_OPTION, 1436 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1437 ED_HPP_OPTION_CHIP_RESET | 1438 ED_HPP_OPTION_ENABLE_IRQ))); 1439 1440 DELAY(5000); 1441 1442 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1443 return 0; /* reset did not complete */ 1444 1445 /* 1446 * Read out configuration information. 1447 */ 1448 1449 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1450 1451 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1452 1453 /* 1454 * Check for impossible IRQ. 1455 */ 1456
|
1440 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
| 1457 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
|
1441 return 0; 1442 1443 /* 1444 * If the kernel IRQ was specified with a '?' use the cards idea 1445 * of the IRQ. If the kernel IRQ was explicitly specified, it 1446 * should match that of the hardware. 1447 */
| 1458 return 0; 1459 1460 /* 1461 * If the kernel IRQ was specified with a '?' use the cards idea 1462 * of the IRQ. If the kernel IRQ was explicitly specified, it 1463 * should match that of the hardware. 1464 */
|
| 1465 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 1466 SYS_RES_IRQ, 0, 1467 &conf_irq, &junk); 1468 if (error) { 1469 ISA_SET_RESOURCE(device_get_parent(dev), dev, 1470 SYS_RES_IRQ, 0, 1471 ed_hpp_intr_val[irq], 1); 1472 } else { 1473 if (conf_irq != ed_hpp_intr_val[irq]) 1474 return (ENXIO); 1475 }
|
1448
| 1476
|
1449 if (isa_dev->id_irq <= 0) 1450 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1451 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1452 return 0; 1453
| |
1454 /* 1455 * Fill in softconfig info. 1456 */ 1457 1458 sc->vendor = ED_VENDOR_HP; 1459 sc->type = ED_TYPE_HP_PCLANPLUS; 1460 sc->type_str = "HP-PCLAN+"; 1461 1462 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1463 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1464 1465 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1466 1467 /*
| 1477 /* 1478 * Fill in softconfig info. 1479 */ 1480 1481 sc->vendor = ED_VENDOR_HP; 1482 sc->type = ED_TYPE_HP_PCLANPLUS; 1483 sc->type_str = "HP-PCLAN+"; 1484 1485 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1486 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1487 1488 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1489 1490 /*
|
| 1491 * The board has 32KB of memory. Is there a way to determine 1492 * this programmatically? 1493 */ 1494 1495 memsize = 32768; 1496 1497 /*
|
1468 * Check if memory mapping of the I/O registers possible. 1469 */ 1470 1471 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1472 { 1473 u_long mem_addr; 1474 1475 /* 1476 * determine the memory address from the board. 1477 */ 1478 1479 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1480 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1481 1482 /* 1483 * Check that the kernel specified start of memory and 1484 * hardware's idea of it match. 1485 */
| 1498 * Check if memory mapping of the I/O registers possible. 1499 */ 1500 1501 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1502 { 1503 u_long mem_addr; 1504 1505 /* 1506 * determine the memory address from the board. 1507 */ 1508 1509 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1510 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1511 1512 /* 1513 * Check that the kernel specified start of memory and 1514 * hardware's idea of it match. 1515 */
|
| 1516 error = ISA_GET_RESOURCE(device_get_parent(dev), dev, 1517 SYS_RES_MEMORY, 0, 1518 &conf_maddr, &conf_msize); 1519 if (error) 1520 return (error);
|
1486
| 1521
|
1487 if (mem_addr != kvtop(isa_dev->id_maddr))
| 1522 if (mem_addr != conf_maddr)
|
1488 return 0; 1489
| 1523 return 0; 1524
|
1490 sc->hpp_mem_start = isa_dev->id_maddr;
| 1525 error = ed_alloc_memory(dev, 0, memsize); 1526 if (error) 1527 return (error); 1528 1529 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
|
1491 } 1492 1493 /*
| 1530 } 1531 1532 /*
|
1494 * The board has 32KB of memory. Is there a way to determine 1495 * this programmatically? 1496 */ 1497 1498 memsize = 32768; 1499 1500 /*
| |
1501 * Fill in the rest of the soft config structure. 1502 */ 1503 1504 /* 1505 * The transmit page index. 1506 */ 1507 1508 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1509
| 1533 * Fill in the rest of the soft config structure. 1534 */ 1535 1536 /* 1537 * The transmit page index. 1538 */ 1539 1540 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1541
|
1510 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
| 1542 if (isa_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
|
1511 sc->txb_cnt = 1; 1512 else 1513 sc->txb_cnt = 2; 1514 1515 /* 1516 * Memory description 1517 */ 1518 1519 sc->mem_size = memsize; 1520 sc->mem_ring = sc->mem_start + 1521 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1522 sc->mem_end = sc->mem_start + sc->mem_size; 1523 1524 /* 1525 * Receive area starts after the transmit area and 1526 * continues till the end of memory. 1527 */ 1528 1529 sc->rec_page_start = sc->tx_page_start + 1530 (sc->txb_cnt * ED_TXBUF_SIZE); 1531 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1532 1533 1534 sc->cr_proto = 0; /* value works */ 1535 1536 /* 1537 * Set the wrap registers for string I/O reads. 1538 */ 1539 1540 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1541 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1542 ((sc->rec_page_start / ED_PAGE_SIZE) | 1543 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1544 1545 /* 1546 * Reset the register page to normal operation. 1547 */ 1548 1549 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1550 1551 /* 1552 * Verify that we can read/write from adapter memory. 1553 * Create test pattern. 1554 */ 1555 1556 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1557 { 1558 test_pattern[n] = (n*n) ^ ~n; 1559 } 1560 1561#undef ED_HPP_TEST_SIZE 1562 1563 /* 1564 * Check that the memory is accessible thru the I/O ports. 1565 * Write out the contents of "test_pattern", read back 1566 * into "test_buffer" and compare the two for any 1567 * mismatch. 1568 */ 1569 1570 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1571 1572 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1573 sizeof(test_pattern)); 1574 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1575 test_buffer, sizeof(test_pattern)); 1576 1577 if (bcmp(test_pattern, test_buffer, 1578 sizeof(test_pattern))) 1579 return 0; 1580 } 1581 1582 return (ED_HPP_IO_PORTS); 1583 1584} 1585 1586/* 1587 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1588 */ 1589 1590void 1591ed_hpp_set_physical_link(struct ed_softc *sc) 1592{ 1593 struct ifnet *ifp = &sc->arpcom.ac_if; 1594 int lan_page; 1595 1596 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1597 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1598 1599 if (ifp->if_flags & IFF_ALTPHYS) { 1600 1601 /* 1602 * Use the AUI port. 1603 */ 1604 1605 lan_page |= ED_HPP_LAN_AUI; 1606 1607 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1608 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1609 1610 1611 } else { 1612 1613 /* 1614 * Use the ThinLan interface 1615 */ 1616 1617 lan_page &= ~ED_HPP_LAN_AUI; 1618 1619 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1620 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1621 1622 } 1623 1624 /* 1625 * Wait for the lan card to re-initialize itself 1626 */ 1627 1628 DELAY(150000); /* wait 150 ms */ 1629 1630 /* 1631 * Restore normal pages. 1632 */ 1633 1634 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1635 1636} 1637
| 1543 sc->txb_cnt = 1; 1544 else 1545 sc->txb_cnt = 2; 1546 1547 /* 1548 * Memory description 1549 */ 1550 1551 sc->mem_size = memsize; 1552 sc->mem_ring = sc->mem_start + 1553 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1554 sc->mem_end = sc->mem_start + sc->mem_size; 1555 1556 /* 1557 * Receive area starts after the transmit area and 1558 * continues till the end of memory. 1559 */ 1560 1561 sc->rec_page_start = sc->tx_page_start + 1562 (sc->txb_cnt * ED_TXBUF_SIZE); 1563 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1564 1565 1566 sc->cr_proto = 0; /* value works */ 1567 1568 /* 1569 * Set the wrap registers for string I/O reads. 1570 */ 1571 1572 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1573 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1574 ((sc->rec_page_start / ED_PAGE_SIZE) | 1575 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1576 1577 /* 1578 * Reset the register page to normal operation. 1579 */ 1580 1581 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1582 1583 /* 1584 * Verify that we can read/write from adapter memory. 1585 * Create test pattern. 1586 */ 1587 1588 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1589 { 1590 test_pattern[n] = (n*n) ^ ~n; 1591 } 1592 1593#undef ED_HPP_TEST_SIZE 1594 1595 /* 1596 * Check that the memory is accessible thru the I/O ports. 1597 * Write out the contents of "test_pattern", read back 1598 * into "test_buffer" and compare the two for any 1599 * mismatch. 1600 */ 1601 1602 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1603 1604 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1605 sizeof(test_pattern)); 1606 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1607 test_buffer, sizeof(test_pattern)); 1608 1609 if (bcmp(test_pattern, test_buffer, 1610 sizeof(test_pattern))) 1611 return 0; 1612 } 1613 1614 return (ED_HPP_IO_PORTS); 1615 1616} 1617 1618/* 1619 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1620 */ 1621 1622void 1623ed_hpp_set_physical_link(struct ed_softc *sc) 1624{ 1625 struct ifnet *ifp = &sc->arpcom.ac_if; 1626 int lan_page; 1627 1628 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1629 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1630 1631 if (ifp->if_flags & IFF_ALTPHYS) { 1632 1633 /* 1634 * Use the AUI port. 1635 */ 1636 1637 lan_page |= ED_HPP_LAN_AUI; 1638 1639 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1640 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1641 1642 1643 } else { 1644 1645 /* 1646 * Use the ThinLan interface 1647 */ 1648 1649 lan_page &= ~ED_HPP_LAN_AUI; 1650 1651 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1652 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1653 1654 } 1655 1656 /* 1657 * Wait for the lan card to re-initialize itself 1658 */ 1659 1660 DELAY(150000); /* wait 150 ms */ 1661 1662 /* 1663 * Restore normal pages. 1664 */ 1665 1666 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1667 1668} 1669
|
| 1670/* 1671 * Allocate a port resource with the given resource id. 1672 */ 1673static int 1674ed_alloc_port(dev, rid, size) 1675 device_t dev; 1676 int rid; 1677 int size; 1678{ 1679 struct ed_softc *sc = device_get_softc(dev); 1680 struct resource *res;
|
1638
| 1681
|
| 1682 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1683 0ul, ~0ul, size, RF_ACTIVE); 1684 if (res) { 1685 sc->port_rid = rid; 1686 sc->port_res = res; 1687 sc->port_used = 1; 1688 return (0); 1689 } else { 1690 return (ENOENT); 1691 } 1692} 1693
|
1639/*
| 1694/*
|
| 1695 * Allocate a memory resource with the given resource id. 1696 */ 1697static int 1698ed_alloc_memory(dev, rid, size) 1699 device_t dev; 1700 int rid; 1701 int size; 1702{ 1703 struct ed_softc *sc = device_get_softc(dev); 1704 struct resource *res; 1705 1706 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1707 0ul, ~0ul, size, RF_ACTIVE); 1708 if (res) { 1709 sc->mem_rid = rid; 1710 sc->mem_res = res; 1711 sc->mem_used = 1; 1712 return (0); 1713 } else { 1714 return (ENOENT); 1715 } 1716} 1717 1718/* 1719 * Allocate an irq resource with the given resource id. 1720 */ 1721static int 1722ed_alloc_irq(dev, rid, flags) 1723 device_t dev; 1724 int rid; 1725 int flags; 1726{ 1727 struct ed_softc *sc = device_get_softc(dev); 1728 struct resource *res; 1729 1730 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1731 0ul, ~0ul, 1, (RF_ACTIVE | flags)); 1732 if (res) { 1733 sc->irq_rid = rid; 1734 sc->irq_res = res; 1735 return (0); 1736 } else { 1737 return (ENOENT); 1738 } 1739} 1740 1741/* 1742 * Release all resources 1743 */ 1744static void 1745ed_release_resources(dev) 1746 device_t dev; 1747{ 1748 struct ed_softc *sc = device_get_softc(dev); 1749 1750 if (sc->port_res) { 1751 bus_release_resource(dev, SYS_RES_IOPORT, 1752 sc->port_rid, sc->port_res); 1753 sc->port_res = 0; 1754 } 1755 if (sc->mem_res) { 1756 bus_release_resource(dev, SYS_RES_MEMORY, 1757 sc->mem_rid, sc->mem_res); 1758 sc->mem_res = 0; 1759 } 1760 if (sc->irq_res) { 1761 bus_release_resource(dev, SYS_RES_IRQ, 1762 sc->irq_rid, sc->irq_res); 1763 sc->irq_res = 0; 1764 } 1765} 1766 1767/*
|
1640 * Install interface into kernel networking data structures 1641 */ 1642static int 1643ed_attach(sc, unit, flags) 1644 struct ed_softc *sc; 1645 int unit; 1646 int flags; 1647{ 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 1650 /* 1651 * Set interface to stopped condition (reset) 1652 */ 1653 ed_stop(sc); 1654 1655 if (!ifp->if_name) { 1656 /* 1657 * Initialize ifnet structure 1658 */ 1659 ifp->if_softc = sc; 1660 ifp->if_unit = unit; 1661 ifp->if_name = "ed"; 1662 ifp->if_output = ether_output; 1663 ifp->if_start = ed_start; 1664 ifp->if_ioctl = ed_ioctl; 1665 ifp->if_watchdog = ed_watchdog; 1666 ifp->if_init = ed_init; 1667 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1668 ifp->if_linkmib = &sc->mibdata; 1669 ifp->if_linkmiblen = sizeof sc->mibdata; 1670 /* 1671 * XXX - should do a better job. 1672 */ 1673 if (sc->is790) 1674 sc->mibdata.dot3StatsEtherChipSet = 1675 DOT3CHIPSET(dot3VendorWesternDigital, 1676 dot3ChipSetWesternDigital83C790); 1677 else 1678 sc->mibdata.dot3StatsEtherChipSet = 1679 DOT3CHIPSET(dot3VendorNational, 1680 dot3ChipSetNational8390); 1681 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1682 1683 /* 1684 * Set default state for ALTPHYS flag (used to disable the 1685 * tranceiver for AUI operation), based on compile-time 1686 * config option. 1687 */ 1688 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1689 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1690 IFF_MULTICAST | IFF_ALTPHYS); 1691 else 1692 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1693 IFF_MULTICAST); 1694 1695 /* 1696 * Attach the interface 1697 */ 1698 if_attach(ifp); 1699 ether_ifattach(ifp); 1700 } 1701 /* device attach does transition from UNCONFIGURED to IDLE state */ 1702 1703 /* 1704 * Print additional info when attached 1705 */ 1706 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1707 sc->arpcom.ac_enaddr, ":"); 1708 1709 if (sc->type_str && (*sc->type_str != 0)) 1710 printf("type %s ", sc->type_str); 1711 else 1712 printf("type unknown (0x%x) ", sc->type); 1713 1714 if (sc->vendor == ED_VENDOR_HP) 1715 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1716 "16-bit" : "32-bit", 1717 sc->hpp_mem_start ? "memory mapped" : "regular"); 1718 else 1719 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1720 1721 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1722 (sc->vendor == ED_VENDOR_HP)) && 1723 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1724 1725 /* 1726 * If BPF is in the kernel, call the attach for it 1727 */ 1728#if NBPF > 0 1729 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1730#endif
| 1768 * Install interface into kernel networking data structures 1769 */ 1770static int 1771ed_attach(sc, unit, flags) 1772 struct ed_softc *sc; 1773 int unit; 1774 int flags; 1775{ 1776 struct ifnet *ifp = &sc->arpcom.ac_if; 1777 1778 /* 1779 * Set interface to stopped condition (reset) 1780 */ 1781 ed_stop(sc); 1782 1783 if (!ifp->if_name) { 1784 /* 1785 * Initialize ifnet structure 1786 */ 1787 ifp->if_softc = sc; 1788 ifp->if_unit = unit; 1789 ifp->if_name = "ed"; 1790 ifp->if_output = ether_output; 1791 ifp->if_start = ed_start; 1792 ifp->if_ioctl = ed_ioctl; 1793 ifp->if_watchdog = ed_watchdog; 1794 ifp->if_init = ed_init; 1795 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1796 ifp->if_linkmib = &sc->mibdata; 1797 ifp->if_linkmiblen = sizeof sc->mibdata; 1798 /* 1799 * XXX - should do a better job. 1800 */ 1801 if (sc->is790) 1802 sc->mibdata.dot3StatsEtherChipSet = 1803 DOT3CHIPSET(dot3VendorWesternDigital, 1804 dot3ChipSetWesternDigital83C790); 1805 else 1806 sc->mibdata.dot3StatsEtherChipSet = 1807 DOT3CHIPSET(dot3VendorNational, 1808 dot3ChipSetNational8390); 1809 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1810 1811 /* 1812 * Set default state for ALTPHYS flag (used to disable the 1813 * tranceiver for AUI operation), based on compile-time 1814 * config option. 1815 */ 1816 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1817 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1818 IFF_MULTICAST | IFF_ALTPHYS); 1819 else 1820 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1821 IFF_MULTICAST); 1822 1823 /* 1824 * Attach the interface 1825 */ 1826 if_attach(ifp); 1827 ether_ifattach(ifp); 1828 } 1829 /* device attach does transition from UNCONFIGURED to IDLE state */ 1830 1831 /* 1832 * Print additional info when attached 1833 */ 1834 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1835 sc->arpcom.ac_enaddr, ":"); 1836 1837 if (sc->type_str && (*sc->type_str != 0)) 1838 printf("type %s ", sc->type_str); 1839 else 1840 printf("type unknown (0x%x) ", sc->type); 1841 1842 if (sc->vendor == ED_VENDOR_HP) 1843 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1844 "16-bit" : "32-bit", 1845 sc->hpp_mem_start ? "memory mapped" : "regular"); 1846 else 1847 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1848 1849 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1850 (sc->vendor == ED_VENDOR_HP)) && 1851 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1852 1853 /* 1854 * If BPF is in the kernel, call the attach for it 1855 */ 1856#if NBPF > 0 1857 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1858#endif
|
1731 return 1;
| 1859 return (0);
|
1732} 1733 1734static int
| 1860} 1861 1862static int
|
1735ed_attach_isa(isa_dev) 1736 struct isa_device *isa_dev;
| 1863ed_isa_attach(dev) 1864 device_t dev;
|
1737{
| 1865{
|
1738 int unit = isa_dev->id_unit; 1739 struct ed_softc *sc = &ed_softc[unit]; 1740 int flags = isa_dev->id_flags;
| 1866 struct ed_softc *sc = device_get_softc(dev); 1867 int flags = isa_get_flags(dev); 1868 int error;
|
1741
| 1869
|
1742 isa_dev->id_ointr = edintr; 1743 return ed_attach(sc, unit, flags);
| 1870 if (sc->port_used > 0) 1871 ed_alloc_port(dev, sc->port_rid, 1); 1872 if (sc->mem_used) 1873 ed_alloc_memory(dev, sc->mem_rid, 1); 1874 ed_alloc_irq(dev, sc->irq_rid, 0); 1875 1876 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET, 1877 edintr, sc, &sc->irq_handle); 1878 if (error) { 1879 ed_release_resources(dev); 1880 return (error); 1881 } 1882 1883 return ed_attach(sc, device_get_unit(dev), flags);
|
1744} 1745 1746#if NPCI > 0
| 1884} 1885 1886#if NPCI > 0
|
1747void * 1748ed_attach_NE2000_pci(unit, port) 1749 int unit; 1750 int port;
| 1887int 1888ed_attach_NE2000_pci(dev, port_rid) 1889 device_t dev; 1890 int port_rid;
|
1751{
| 1891{
|
1752 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1753 int isa_flags = 0;
| 1892 struct ed_softc *sc = device_get_softc(dev); 1893 int flags = 0; 1894 int error;
|
1754
| 1895
|
1755 if (!sc) 1756 return sc;
| 1896 error = ed_probe_Novell_generic(dev, port_rid, flags); 1897 if (error) 1898 return (error);
|
1757
| 1899
|
1758 bzero(sc, sizeof *sc); 1759 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1760 || ed_attach(sc, unit, isa_flags) == 0) { 1761 free(sc, M_DEVBUF); 1762 return NULL;
| 1900 error = ed_alloc_irq(dev, 0, RF_SHAREABLE); 1901 if (error) { 1902 ed_release_resources(dev); 1903 return (error);
|
1763 }
| 1904 }
|
1764 return sc;
| 1905 1906 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET, 1907 edintr, sc, &sc->irq_handle); 1908 if (error) { 1909 ed_release_resources(dev); 1910 return (error); 1911 } 1912 1913 return ed_attach(sc, device_get_unit(dev), flags);
|
1765} 1766#endif 1767 1768/* 1769 * Reset interface. 1770 */ 1771static void 1772ed_reset(ifp) 1773 struct ifnet *ifp; 1774{ 1775 struct ed_softc *sc = ifp->if_softc; 1776 int s; 1777 1778 if (sc->gone) 1779 return; 1780 s = splimp(); 1781 1782 /* 1783 * Stop interface and re-initialize. 1784 */ 1785 ed_stop(sc); 1786 ed_init(sc); 1787 1788 (void) splx(s); 1789} 1790 1791/* 1792 * Take interface offline. 1793 */ 1794static void 1795ed_stop(sc) 1796 struct ed_softc *sc; 1797{ 1798 int n = 5000; 1799 1800 if (sc->gone) 1801 return; 1802 /* 1803 * Stop everything on the interface, and select page 0 registers. 1804 */ 1805 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1806 1807 /* 1808 * Wait for interface to enter stopped state, but limit # of checks to 1809 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1810 * just in case it's an old one. 1811 */ 1812 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1813} 1814 1815/* 1816 * Device timeout/watchdog routine. Entered if the device neglects to 1817 * generate an interrupt after a transmit has been started on it. 1818 */ 1819static void 1820ed_watchdog(ifp) 1821 struct ifnet *ifp; 1822{ 1823 struct ed_softc *sc = ifp->if_softc; 1824 1825 if (sc->gone) 1826 return; 1827 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1828 ifp->if_oerrors++; 1829 1830 ed_reset(ifp); 1831} 1832 1833/* 1834 * Initialize device. 1835 */ 1836static void 1837ed_init(xsc) 1838 void *xsc; 1839{ 1840 struct ed_softc *sc = xsc; 1841 struct ifnet *ifp = &sc->arpcom.ac_if; 1842 int i, s; 1843 1844 if (sc->gone) 1845 return; 1846 1847 /* address not known */ 1848 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1849 return; 1850 1851 /* 1852 * Initialize the NIC in the exact order outlined in the NS manual. 1853 * This init procedure is "mandatory"...don't change what or when 1854 * things happen. 1855 */ 1856 s = splimp(); 1857 1858 /* reset transmitter flags */ 1859 sc->xmit_busy = 0; 1860 ifp->if_timer = 0; 1861 1862 sc->txb_inuse = 0; 1863 sc->txb_new = 0; 1864 sc->txb_next_tx = 0; 1865 1866 /* This variable is used below - don't move this assignment */ 1867 sc->next_packet = sc->rec_page_start + 1; 1868 1869 /* 1870 * Set interface for page 0, Remote DMA complete, Stopped 1871 */ 1872 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1873 1874 if (sc->isa16bit) { 1875 1876 /* 1877 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1878 * order=80x86, word-wide DMA xfers, 1879 */ 1880 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1881 } else { 1882 1883 /* 1884 * Same as above, but byte-wide DMA xfers 1885 */ 1886 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1887 } 1888 1889 /* 1890 * Clear Remote Byte Count Registers 1891 */ 1892 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1893 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1894 1895 /* 1896 * For the moment, don't store incoming packets in memory. 1897 */ 1898 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1899 1900 /* 1901 * Place NIC in internal loopback mode 1902 */ 1903 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1904 1905 /* 1906 * Initialize transmit/receive (ring-buffer) Page Start 1907 */ 1908 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1909 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1910 /* Set lower bits of byte addressable framing to 0 */ 1911 if (sc->is790) 1912 outb(sc->nic_addr + 0x09, 0); 1913 1914 /* 1915 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1916 */ 1917 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1918 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1919 1920 /* 1921 * Clear all interrupts. A '1' in each bit position clears the 1922 * corresponding flag. 1923 */ 1924 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1925 1926 /* 1927 * Enable the following interrupts: receive/transmit complete, 1928 * receive/transmit error, and Receiver OverWrite. 1929 * 1930 * Counter overflow and Remote DMA complete are *not* enabled. 1931 */ 1932 outb(sc->nic_addr + ED_P0_IMR, 1933 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1934 1935 /* 1936 * Program Command Register for page 1 1937 */ 1938 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1939 1940 /* 1941 * Copy out our station address 1942 */ 1943 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1944 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1945 1946 /* 1947 * Set Current Page pointer to next_packet (initialized above) 1948 */ 1949 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1950 1951 /* 1952 * Program Receiver Configuration Register and multicast filter. CR is 1953 * set to page 0 on return. 1954 */ 1955 ed_setrcr(sc); 1956 1957 /* 1958 * Take interface out of loopback 1959 */ 1960 outb(sc->nic_addr + ED_P0_TCR, 0); 1961 1962 /* 1963 * If this is a 3Com board, the tranceiver must be software enabled 1964 * (there is no settable hardware default). 1965 */ 1966 if (sc->vendor == ED_VENDOR_3COM) { 1967 if (ifp->if_flags & IFF_ALTPHYS) { 1968 outb(sc->asic_addr + ED_3COM_CR, 0); 1969 } else { 1970 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1971 } 1972 } 1973 1974 /* 1975 * Set 'running' flag, and clear output active flag. 1976 */ 1977 ifp->if_flags |= IFF_RUNNING; 1978 ifp->if_flags &= ~IFF_OACTIVE; 1979 1980 /* 1981 * ...and attempt to start output 1982 */ 1983 ed_start(ifp); 1984 1985 (void) splx(s); 1986} 1987 1988/* 1989 * This routine actually starts the transmission on the interface 1990 */ 1991static __inline void 1992ed_xmit(sc) 1993 struct ed_softc *sc; 1994{ 1995 struct ifnet *ifp = (struct ifnet *)sc; 1996 unsigned short len; 1997 1998 if (sc->gone) 1999 return; 2000 len = sc->txb_len[sc->txb_next_tx]; 2001 2002 /* 2003 * Set NIC for page 0 register access 2004 */ 2005 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2006 2007 /* 2008 * Set TX buffer start page 2009 */ 2010 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2011 sc->txb_next_tx * ED_TXBUF_SIZE); 2012 2013 /* 2014 * Set TX length 2015 */ 2016 outb(sc->nic_addr + ED_P0_TBCR0, len); 2017 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2018 2019 /* 2020 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2021 */ 2022 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2023 sc->xmit_busy = 1; 2024 2025 /* 2026 * Point to next transmit buffer slot and wrap if necessary. 2027 */ 2028 sc->txb_next_tx++; 2029 if (sc->txb_next_tx == sc->txb_cnt) 2030 sc->txb_next_tx = 0; 2031 2032 /* 2033 * Set a timer just in case we never hear from the board again 2034 */ 2035 ifp->if_timer = 2; 2036} 2037 2038/* 2039 * Start output on interface. 2040 * We make two assumptions here: 2041 * 1) that the current priority is set to splimp _before_ this code 2042 * is called *and* is returned to the appropriate priority after 2043 * return 2044 * 2) that the IFF_OACTIVE flag is checked before this code is called 2045 * (i.e. that the output part of the interface is idle) 2046 */ 2047static void 2048ed_start(ifp) 2049 struct ifnet *ifp; 2050{ 2051 struct ed_softc *sc = ifp->if_softc; 2052 struct mbuf *m0, *m; 2053 caddr_t buffer; 2054 int len; 2055 2056 if (sc->gone) { 2057 printf("ed_start(%p) GONE\n",ifp); 2058 return; 2059 } 2060outloop: 2061 2062 /* 2063 * First, see if there are buffered packets and an idle transmitter - 2064 * should never happen at this point. 2065 */ 2066 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2067 printf("ed: packets buffered, but transmitter idle\n"); 2068 ed_xmit(sc); 2069 } 2070 2071 /* 2072 * See if there is room to put another packet in the buffer. 2073 */ 2074 if (sc->txb_inuse == sc->txb_cnt) { 2075 2076 /* 2077 * No room. Indicate this to the outside world and exit. 2078 */ 2079 ifp->if_flags |= IFF_OACTIVE; 2080 return; 2081 } 2082 IF_DEQUEUE(&ifp->if_snd, m); 2083 if (m == 0) { 2084 2085 /* 2086 * We are using the !OACTIVE flag to indicate to the outside 2087 * world that we can accept an additional packet rather than 2088 * that the transmitter is _actually_ active. Indeed, the 2089 * transmitter may be active, but if we haven't filled all the 2090 * buffers with data then we still want to accept more. 2091 */ 2092 ifp->if_flags &= ~IFF_OACTIVE; 2093 return; 2094 } 2095 2096 /* 2097 * Copy the mbuf chain into the transmit buffer 2098 */ 2099 2100 m0 = m; 2101 2102 /* txb_new points to next open buffer slot */ 2103 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2104 2105 if (sc->mem_shared) { 2106 2107 /* 2108 * Special case setup for 16 bit boards... 2109 */ 2110 if (sc->isa16bit) { 2111 switch (sc->vendor) { 2112 2113 /* 2114 * For 16bit 3Com boards (which have 16k of 2115 * memory), we have the xmit buffers in a 2116 * different page of memory ('page 0') - so 2117 * change pages. 2118 */ 2119 case ED_VENDOR_3COM: 2120 outb(sc->asic_addr + ED_3COM_GACFR, 2121 ED_3COM_GACFR_RSEL); 2122 break; 2123 2124 /* 2125 * Enable 16bit access to shared memory on 2126 * WD/SMC boards. 2127 */ 2128 case ED_VENDOR_WD_SMC:{ 2129 outb(sc->asic_addr + ED_WD_LAAR, 2130 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2131 if (sc->is790) { 2132 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2133 } 2134 break; 2135 } 2136 } 2137 } 2138 for (len = 0; m != 0; m = m->m_next) { 2139 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2140 buffer += m->m_len; 2141 len += m->m_len; 2142 } 2143 2144 /* 2145 * Restore previous shared memory access 2146 */ 2147 if (sc->isa16bit) { 2148 switch (sc->vendor) { 2149 case ED_VENDOR_3COM: 2150 outb(sc->asic_addr + ED_3COM_GACFR, 2151 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2152 break; 2153 case ED_VENDOR_WD_SMC:{ 2154 if (sc->is790) { 2155 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2156 } 2157 outb(sc->asic_addr + ED_WD_LAAR, 2158 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2159 break; 2160 } 2161 } 2162 } 2163 } else { 2164 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2165 if (len == 0) 2166 goto outloop; 2167 } 2168 2169 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2170 2171 sc->txb_inuse++; 2172 2173 /* 2174 * Point to next buffer slot and wrap if necessary. 2175 */ 2176 sc->txb_new++; 2177 if (sc->txb_new == sc->txb_cnt) 2178 sc->txb_new = 0; 2179 2180 if (sc->xmit_busy == 0) 2181 ed_xmit(sc); 2182 2183 /* 2184 * Tap off here if there is a bpf listener. 2185 */ 2186#if NBPF > 0 2187 if (ifp->if_bpf) { 2188 bpf_mtap(ifp, m0); 2189 } 2190#endif 2191 2192 m_freem(m0); 2193 2194 /* 2195 * Loop back to the top to possibly buffer more packets 2196 */ 2197 goto outloop; 2198} 2199 2200/* 2201 * Ethernet interface receiver interrupt. 2202 */ 2203static __inline void 2204ed_rint(sc) 2205 struct ed_softc *sc; 2206{ 2207 struct ifnet *ifp = &sc->arpcom.ac_if; 2208 u_char boundry; 2209 u_short len; 2210 struct ed_ring packet_hdr; 2211 char *packet_ptr; 2212 2213 if (sc->gone) 2214 return; 2215 2216 /* 2217 * Set NIC to page 1 registers to get 'current' pointer 2218 */ 2219 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2220 2221 /* 2222 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2223 * i.e. it points to where new data has been buffered. The 'CURR' 2224 * (current) register points to the logical end of the ring-buffer - 2225 * i.e. it points to where additional new data will be added. We loop 2226 * here until the logical beginning equals the logical end (or in 2227 * other words, until the ring-buffer is empty). 2228 */ 2229 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2230 2231 /* get pointer to this buffer's header structure */ 2232 packet_ptr = sc->mem_ring + 2233 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2234 2235 /* 2236 * The byte count includes a 4 byte header that was added by 2237 * the NIC. 2238 */ 2239 if (sc->mem_shared) 2240 packet_hdr = *(struct ed_ring *) packet_ptr; 2241 else 2242 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2243 sizeof(packet_hdr)); 2244 len = packet_hdr.count; 2245 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2246 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2247 /* 2248 * Length is a wild value. There's a good chance that 2249 * this was caused by the NIC being old and buggy. 2250 * The bug is that the length low byte is duplicated in 2251 * the high byte. Try to recalculate the length based on 2252 * the pointer to the next packet. 2253 */ 2254 /* 2255 * NOTE: sc->next_packet is pointing at the current packet. 2256 */ 2257 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2258 if (packet_hdr.next_packet >= sc->next_packet) { 2259 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2260 } else { 2261 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2262 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2263 } 2264 /* 2265 * because buffers are aligned on 256-byte boundary, 2266 * the length computed above is off by 256 in almost 2267 * all cases. Fix it... 2268 */ 2269 if (len & 0xff) 2270 len -= 256 ; 2271 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2272 + sizeof(struct ed_ring))) 2273 sc->mibdata.dot3StatsFrameTooLongs++; 2274 } 2275 /* 2276 * Be fairly liberal about what we allow as a "reasonable" length 2277 * so that a [crufty] packet will make it to BPF (and can thus 2278 * be analyzed). Note that all that is really important is that 2279 * we have a length that will fit into one mbuf cluster or less; 2280 * the upper layer protocols can then figure out the length from 2281 * their own length field(s). 2282 */ 2283 if ((len > sizeof(struct ed_ring)) && 2284 (len <= MCLBYTES) && 2285 (packet_hdr.next_packet >= sc->rec_page_start) && 2286 (packet_hdr.next_packet < sc->rec_page_stop)) { 2287 /* 2288 * Go get packet. 2289 */ 2290 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2291 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2292 ifp->if_ipackets++; 2293 } else { 2294 /* 2295 * Really BAD. The ring pointers are corrupted. 2296 */ 2297 log(LOG_ERR, 2298 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2299 ifp->if_unit, len); 2300 ifp->if_ierrors++; 2301 ed_reset(ifp); 2302 return; 2303 } 2304 2305 /* 2306 * Update next packet pointer 2307 */ 2308 sc->next_packet = packet_hdr.next_packet; 2309 2310 /* 2311 * Update NIC boundry pointer - being careful to keep it one 2312 * buffer behind. (as recommended by NS databook) 2313 */ 2314 boundry = sc->next_packet - 1; 2315 if (boundry < sc->rec_page_start) 2316 boundry = sc->rec_page_stop - 1; 2317 2318 /* 2319 * Set NIC to page 0 registers to update boundry register 2320 */ 2321 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2322 2323 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2324 2325 /* 2326 * Set NIC to page 1 registers before looping to top (prepare 2327 * to get 'CURR' current pointer) 2328 */ 2329 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2330 } 2331} 2332 2333/* 2334 * Ethernet interface interrupt processor 2335 */
| 1914} 1915#endif 1916 1917/* 1918 * Reset interface. 1919 */ 1920static void 1921ed_reset(ifp) 1922 struct ifnet *ifp; 1923{ 1924 struct ed_softc *sc = ifp->if_softc; 1925 int s; 1926 1927 if (sc->gone) 1928 return; 1929 s = splimp(); 1930 1931 /* 1932 * Stop interface and re-initialize. 1933 */ 1934 ed_stop(sc); 1935 ed_init(sc); 1936 1937 (void) splx(s); 1938} 1939 1940/* 1941 * Take interface offline. 1942 */ 1943static void 1944ed_stop(sc) 1945 struct ed_softc *sc; 1946{ 1947 int n = 5000; 1948 1949 if (sc->gone) 1950 return; 1951 /* 1952 * Stop everything on the interface, and select page 0 registers. 1953 */ 1954 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1955 1956 /* 1957 * Wait for interface to enter stopped state, but limit # of checks to 1958 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1959 * just in case it's an old one. 1960 */ 1961 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1962} 1963 1964/* 1965 * Device timeout/watchdog routine. Entered if the device neglects to 1966 * generate an interrupt after a transmit has been started on it. 1967 */ 1968static void 1969ed_watchdog(ifp) 1970 struct ifnet *ifp; 1971{ 1972 struct ed_softc *sc = ifp->if_softc; 1973 1974 if (sc->gone) 1975 return; 1976 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1977 ifp->if_oerrors++; 1978 1979 ed_reset(ifp); 1980} 1981 1982/* 1983 * Initialize device. 1984 */ 1985static void 1986ed_init(xsc) 1987 void *xsc; 1988{ 1989 struct ed_softc *sc = xsc; 1990 struct ifnet *ifp = &sc->arpcom.ac_if; 1991 int i, s; 1992 1993 if (sc->gone) 1994 return; 1995 1996 /* address not known */ 1997 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1998 return; 1999 2000 /* 2001 * Initialize the NIC in the exact order outlined in the NS manual. 2002 * This init procedure is "mandatory"...don't change what or when 2003 * things happen. 2004 */ 2005 s = splimp(); 2006 2007 /* reset transmitter flags */ 2008 sc->xmit_busy = 0; 2009 ifp->if_timer = 0; 2010 2011 sc->txb_inuse = 0; 2012 sc->txb_new = 0; 2013 sc->txb_next_tx = 0; 2014 2015 /* This variable is used below - don't move this assignment */ 2016 sc->next_packet = sc->rec_page_start + 1; 2017 2018 /* 2019 * Set interface for page 0, Remote DMA complete, Stopped 2020 */ 2021 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 2022 2023 if (sc->isa16bit) { 2024 2025 /* 2026 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 2027 * order=80x86, word-wide DMA xfers, 2028 */ 2029 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 2030 } else { 2031 2032 /* 2033 * Same as above, but byte-wide DMA xfers 2034 */ 2035 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 2036 } 2037 2038 /* 2039 * Clear Remote Byte Count Registers 2040 */ 2041 outb(sc->nic_addr + ED_P0_RBCR0, 0); 2042 outb(sc->nic_addr + ED_P0_RBCR1, 0); 2043 2044 /* 2045 * For the moment, don't store incoming packets in memory. 2046 */ 2047 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 2048 2049 /* 2050 * Place NIC in internal loopback mode 2051 */ 2052 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 2053 2054 /* 2055 * Initialize transmit/receive (ring-buffer) Page Start 2056 */ 2057 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 2058 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 2059 /* Set lower bits of byte addressable framing to 0 */ 2060 if (sc->is790) 2061 outb(sc->nic_addr + 0x09, 0); 2062 2063 /* 2064 * Initialize Receiver (ring-buffer) Page Stop and Boundry 2065 */ 2066 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 2067 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 2068 2069 /* 2070 * Clear all interrupts. A '1' in each bit position clears the 2071 * corresponding flag. 2072 */ 2073 outb(sc->nic_addr + ED_P0_ISR, 0xff); 2074 2075 /* 2076 * Enable the following interrupts: receive/transmit complete, 2077 * receive/transmit error, and Receiver OverWrite. 2078 * 2079 * Counter overflow and Remote DMA complete are *not* enabled. 2080 */ 2081 outb(sc->nic_addr + ED_P0_IMR, 2082 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 2083 2084 /* 2085 * Program Command Register for page 1 2086 */ 2087 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 2088 2089 /* 2090 * Copy out our station address 2091 */ 2092 for (i = 0; i < ETHER_ADDR_LEN; ++i) 2093 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 2094 2095 /* 2096 * Set Current Page pointer to next_packet (initialized above) 2097 */ 2098 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 2099 2100 /* 2101 * Program Receiver Configuration Register and multicast filter. CR is 2102 * set to page 0 on return. 2103 */ 2104 ed_setrcr(sc); 2105 2106 /* 2107 * Take interface out of loopback 2108 */ 2109 outb(sc->nic_addr + ED_P0_TCR, 0); 2110 2111 /* 2112 * If this is a 3Com board, the tranceiver must be software enabled 2113 * (there is no settable hardware default). 2114 */ 2115 if (sc->vendor == ED_VENDOR_3COM) { 2116 if (ifp->if_flags & IFF_ALTPHYS) { 2117 outb(sc->asic_addr + ED_3COM_CR, 0); 2118 } else { 2119 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2120 } 2121 } 2122 2123 /* 2124 * Set 'running' flag, and clear output active flag. 2125 */ 2126 ifp->if_flags |= IFF_RUNNING; 2127 ifp->if_flags &= ~IFF_OACTIVE; 2128 2129 /* 2130 * ...and attempt to start output 2131 */ 2132 ed_start(ifp); 2133 2134 (void) splx(s); 2135} 2136 2137/* 2138 * This routine actually starts the transmission on the interface 2139 */ 2140static __inline void 2141ed_xmit(sc) 2142 struct ed_softc *sc; 2143{ 2144 struct ifnet *ifp = (struct ifnet *)sc; 2145 unsigned short len; 2146 2147 if (sc->gone) 2148 return; 2149 len = sc->txb_len[sc->txb_next_tx]; 2150 2151 /* 2152 * Set NIC for page 0 register access 2153 */ 2154 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2155 2156 /* 2157 * Set TX buffer start page 2158 */ 2159 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2160 sc->txb_next_tx * ED_TXBUF_SIZE); 2161 2162 /* 2163 * Set TX length 2164 */ 2165 outb(sc->nic_addr + ED_P0_TBCR0, len); 2166 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2167 2168 /* 2169 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2170 */ 2171 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2172 sc->xmit_busy = 1; 2173 2174 /* 2175 * Point to next transmit buffer slot and wrap if necessary. 2176 */ 2177 sc->txb_next_tx++; 2178 if (sc->txb_next_tx == sc->txb_cnt) 2179 sc->txb_next_tx = 0; 2180 2181 /* 2182 * Set a timer just in case we never hear from the board again 2183 */ 2184 ifp->if_timer = 2; 2185} 2186 2187/* 2188 * Start output on interface. 2189 * We make two assumptions here: 2190 * 1) that the current priority is set to splimp _before_ this code 2191 * is called *and* is returned to the appropriate priority after 2192 * return 2193 * 2) that the IFF_OACTIVE flag is checked before this code is called 2194 * (i.e. that the output part of the interface is idle) 2195 */ 2196static void 2197ed_start(ifp) 2198 struct ifnet *ifp; 2199{ 2200 struct ed_softc *sc = ifp->if_softc; 2201 struct mbuf *m0, *m; 2202 caddr_t buffer; 2203 int len; 2204 2205 if (sc->gone) { 2206 printf("ed_start(%p) GONE\n",ifp); 2207 return; 2208 } 2209outloop: 2210 2211 /* 2212 * First, see if there are buffered packets and an idle transmitter - 2213 * should never happen at this point. 2214 */ 2215 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2216 printf("ed: packets buffered, but transmitter idle\n"); 2217 ed_xmit(sc); 2218 } 2219 2220 /* 2221 * See if there is room to put another packet in the buffer. 2222 */ 2223 if (sc->txb_inuse == sc->txb_cnt) { 2224 2225 /* 2226 * No room. Indicate this to the outside world and exit. 2227 */ 2228 ifp->if_flags |= IFF_OACTIVE; 2229 return; 2230 } 2231 IF_DEQUEUE(&ifp->if_snd, m); 2232 if (m == 0) { 2233 2234 /* 2235 * We are using the !OACTIVE flag to indicate to the outside 2236 * world that we can accept an additional packet rather than 2237 * that the transmitter is _actually_ active. Indeed, the 2238 * transmitter may be active, but if we haven't filled all the 2239 * buffers with data then we still want to accept more. 2240 */ 2241 ifp->if_flags &= ~IFF_OACTIVE; 2242 return; 2243 } 2244 2245 /* 2246 * Copy the mbuf chain into the transmit buffer 2247 */ 2248 2249 m0 = m; 2250 2251 /* txb_new points to next open buffer slot */ 2252 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2253 2254 if (sc->mem_shared) { 2255 2256 /* 2257 * Special case setup for 16 bit boards... 2258 */ 2259 if (sc->isa16bit) { 2260 switch (sc->vendor) { 2261 2262 /* 2263 * For 16bit 3Com boards (which have 16k of 2264 * memory), we have the xmit buffers in a 2265 * different page of memory ('page 0') - so 2266 * change pages. 2267 */ 2268 case ED_VENDOR_3COM: 2269 outb(sc->asic_addr + ED_3COM_GACFR, 2270 ED_3COM_GACFR_RSEL); 2271 break; 2272 2273 /* 2274 * Enable 16bit access to shared memory on 2275 * WD/SMC boards. 2276 */ 2277 case ED_VENDOR_WD_SMC:{ 2278 outb(sc->asic_addr + ED_WD_LAAR, 2279 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2280 if (sc->is790) { 2281 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2282 } 2283 break; 2284 } 2285 } 2286 } 2287 for (len = 0; m != 0; m = m->m_next) { 2288 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2289 buffer += m->m_len; 2290 len += m->m_len; 2291 } 2292 2293 /* 2294 * Restore previous shared memory access 2295 */ 2296 if (sc->isa16bit) { 2297 switch (sc->vendor) { 2298 case ED_VENDOR_3COM: 2299 outb(sc->asic_addr + ED_3COM_GACFR, 2300 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2301 break; 2302 case ED_VENDOR_WD_SMC:{ 2303 if (sc->is790) { 2304 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2305 } 2306 outb(sc->asic_addr + ED_WD_LAAR, 2307 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2308 break; 2309 } 2310 } 2311 } 2312 } else { 2313 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2314 if (len == 0) 2315 goto outloop; 2316 } 2317 2318 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2319 2320 sc->txb_inuse++; 2321 2322 /* 2323 * Point to next buffer slot and wrap if necessary. 2324 */ 2325 sc->txb_new++; 2326 if (sc->txb_new == sc->txb_cnt) 2327 sc->txb_new = 0; 2328 2329 if (sc->xmit_busy == 0) 2330 ed_xmit(sc); 2331 2332 /* 2333 * Tap off here if there is a bpf listener. 2334 */ 2335#if NBPF > 0 2336 if (ifp->if_bpf) { 2337 bpf_mtap(ifp, m0); 2338 } 2339#endif 2340 2341 m_freem(m0); 2342 2343 /* 2344 * Loop back to the top to possibly buffer more packets 2345 */ 2346 goto outloop; 2347} 2348 2349/* 2350 * Ethernet interface receiver interrupt. 2351 */ 2352static __inline void 2353ed_rint(sc) 2354 struct ed_softc *sc; 2355{ 2356 struct ifnet *ifp = &sc->arpcom.ac_if; 2357 u_char boundry; 2358 u_short len; 2359 struct ed_ring packet_hdr; 2360 char *packet_ptr; 2361 2362 if (sc->gone) 2363 return; 2364 2365 /* 2366 * Set NIC to page 1 registers to get 'current' pointer 2367 */ 2368 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2369 2370 /* 2371 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2372 * i.e. it points to where new data has been buffered. The 'CURR' 2373 * (current) register points to the logical end of the ring-buffer - 2374 * i.e. it points to where additional new data will be added. We loop 2375 * here until the logical beginning equals the logical end (or in 2376 * other words, until the ring-buffer is empty). 2377 */ 2378 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2379 2380 /* get pointer to this buffer's header structure */ 2381 packet_ptr = sc->mem_ring + 2382 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2383 2384 /* 2385 * The byte count includes a 4 byte header that was added by 2386 * the NIC. 2387 */ 2388 if (sc->mem_shared) 2389 packet_hdr = *(struct ed_ring *) packet_ptr; 2390 else 2391 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2392 sizeof(packet_hdr)); 2393 len = packet_hdr.count; 2394 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2395 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2396 /* 2397 * Length is a wild value. There's a good chance that 2398 * this was caused by the NIC being old and buggy. 2399 * The bug is that the length low byte is duplicated in 2400 * the high byte. Try to recalculate the length based on 2401 * the pointer to the next packet. 2402 */ 2403 /* 2404 * NOTE: sc->next_packet is pointing at the current packet. 2405 */ 2406 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2407 if (packet_hdr.next_packet >= sc->next_packet) { 2408 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2409 } else { 2410 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2411 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2412 } 2413 /* 2414 * because buffers are aligned on 256-byte boundary, 2415 * the length computed above is off by 256 in almost 2416 * all cases. Fix it... 2417 */ 2418 if (len & 0xff) 2419 len -= 256 ; 2420 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2421 + sizeof(struct ed_ring))) 2422 sc->mibdata.dot3StatsFrameTooLongs++; 2423 } 2424 /* 2425 * Be fairly liberal about what we allow as a "reasonable" length 2426 * so that a [crufty] packet will make it to BPF (and can thus 2427 * be analyzed). Note that all that is really important is that 2428 * we have a length that will fit into one mbuf cluster or less; 2429 * the upper layer protocols can then figure out the length from 2430 * their own length field(s). 2431 */ 2432 if ((len > sizeof(struct ed_ring)) && 2433 (len <= MCLBYTES) && 2434 (packet_hdr.next_packet >= sc->rec_page_start) && 2435 (packet_hdr.next_packet < sc->rec_page_stop)) { 2436 /* 2437 * Go get packet. 2438 */ 2439 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2440 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2441 ifp->if_ipackets++; 2442 } else { 2443 /* 2444 * Really BAD. The ring pointers are corrupted. 2445 */ 2446 log(LOG_ERR, 2447 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2448 ifp->if_unit, len); 2449 ifp->if_ierrors++; 2450 ed_reset(ifp); 2451 return; 2452 } 2453 2454 /* 2455 * Update next packet pointer 2456 */ 2457 sc->next_packet = packet_hdr.next_packet; 2458 2459 /* 2460 * Update NIC boundry pointer - being careful to keep it one 2461 * buffer behind. (as recommended by NS databook) 2462 */ 2463 boundry = sc->next_packet - 1; 2464 if (boundry < sc->rec_page_start) 2465 boundry = sc->rec_page_stop - 1; 2466 2467 /* 2468 * Set NIC to page 0 registers to update boundry register 2469 */ 2470 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2471 2472 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2473 2474 /* 2475 * Set NIC to page 1 registers before looping to top (prepare 2476 * to get 'CURR' current pointer) 2477 */ 2478 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2479 } 2480} 2481 2482/* 2483 * Ethernet interface interrupt processor 2484 */
|
2336void 2337edintr_sc(sc) 2338 struct ed_softc *sc;
| 2485static void 2486edintr(arg) 2487 void *arg;
|
2339{
| 2488{
|
| 2489 struct ed_softc *sc = (struct ed_softc*) arg;
|
2340 struct ifnet *ifp = (struct ifnet *)sc; 2341 u_char isr; 2342 2343 if (sc->gone) 2344 return; 2345 /* 2346 * Set NIC to page 0 registers 2347 */ 2348 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2349 2350 /* 2351 * loop until there are no more new interrupts 2352 */ 2353 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2354 2355 /* 2356 * reset all the bits that we are 'acknowledging' by writing a 2357 * '1' to each bit position that was set (writing a '1' 2358 * *clears* the bit) 2359 */ 2360 outb(sc->nic_addr + ED_P0_ISR, isr); 2361 2362 /* 2363 * Handle transmitter interrupts. Handle these first because 2364 * the receiver will reset the board under some conditions. 2365 */ 2366 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2367 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2368 2369 /* 2370 * Check for transmit error. If a TX completed with an 2371 * error, we end up throwing the packet away. Really 2372 * the only error that is possible is excessive 2373 * collisions, and in this case it is best to allow 2374 * the automatic mechanisms of TCP to backoff the 2375 * flow. Of course, with UDP we're screwed, but this 2376 * is expected when a network is heavily loaded. 2377 */ 2378 (void) inb(sc->nic_addr + ED_P0_TSR); 2379 if (isr & ED_ISR_TXE) { 2380 u_char tsr; 2381 2382 /* 2383 * Excessive collisions (16) 2384 */ 2385 tsr = inb(sc->nic_addr + ED_P0_TSR); 2386 if ((tsr & ED_TSR_ABT) 2387 && (collisions == 0)) { 2388 2389 /* 2390 * When collisions total 16, the 2391 * P0_NCR will indicate 0, and the 2392 * TSR_ABT is set. 2393 */ 2394 collisions = 16; 2395 sc->mibdata.dot3StatsExcessiveCollisions++; 2396 sc->mibdata.dot3StatsCollFrequencies[15]++; 2397 } 2398 if (tsr & ED_TSR_OWC) 2399 sc->mibdata.dot3StatsLateCollisions++; 2400 if (tsr & ED_TSR_CDH) 2401 sc->mibdata.dot3StatsSQETestErrors++; 2402 if (tsr & ED_TSR_CRS) 2403 sc->mibdata.dot3StatsCarrierSenseErrors++; 2404 if (tsr & ED_TSR_FU) 2405 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2406 2407 /* 2408 * update output errors counter 2409 */ 2410 ifp->if_oerrors++; 2411 } else { 2412 2413 /* 2414 * Update total number of successfully 2415 * transmitted packets. 2416 */ 2417 ifp->if_opackets++; 2418 } 2419 2420 /* 2421 * reset tx busy and output active flags 2422 */ 2423 sc->xmit_busy = 0; 2424 ifp->if_flags &= ~IFF_OACTIVE; 2425 2426 /* 2427 * clear watchdog timer 2428 */ 2429 ifp->if_timer = 0; 2430 2431 /* 2432 * Add in total number of collisions on last 2433 * transmission. 2434 */ 2435 ifp->if_collisions += collisions; 2436 switch(collisions) { 2437 case 0: 2438 case 16: 2439 break; 2440 case 1: 2441 sc->mibdata.dot3StatsSingleCollisionFrames++; 2442 sc->mibdata.dot3StatsCollFrequencies[0]++; 2443 break; 2444 default: 2445 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2446 sc->mibdata. 2447 dot3StatsCollFrequencies[collisions-1] 2448 ++; 2449 break; 2450 } 2451 2452 /* 2453 * Decrement buffer in-use count if not zero (can only 2454 * be zero if a transmitter interrupt occured while 2455 * not actually transmitting). If data is ready to 2456 * transmit, start it transmitting, otherwise defer 2457 * until after handling receiver 2458 */ 2459 if (sc->txb_inuse && --sc->txb_inuse) 2460 ed_xmit(sc); 2461 } 2462 2463 /* 2464 * Handle receiver interrupts 2465 */ 2466 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2467 2468 /* 2469 * Overwrite warning. In order to make sure that a 2470 * lockup of the local DMA hasn't occurred, we reset 2471 * and re-init the NIC. The NSC manual suggests only a 2472 * partial reset/re-init is necessary - but some chips 2473 * seem to want more. The DMA lockup has been seen 2474 * only with early rev chips - Methinks this bug was 2475 * fixed in later revs. -DG 2476 */ 2477 if (isr & ED_ISR_OVW) { 2478 ifp->if_ierrors++; 2479#ifdef DIAGNOSTIC 2480 log(LOG_WARNING, 2481 "ed%d: warning - receiver ring buffer overrun\n", 2482 ifp->if_unit); 2483#endif 2484 2485 /* 2486 * Stop/reset/re-init NIC 2487 */ 2488 ed_reset(ifp); 2489 } else { 2490 2491 /* 2492 * Receiver Error. One or more of: CRC error, 2493 * frame alignment error FIFO overrun, or 2494 * missed packet. 2495 */ 2496 if (isr & ED_ISR_RXE) { 2497 u_char rsr; 2498 rsr = inb(sc->nic_addr + ED_P0_RSR); 2499 if (rsr & ED_RSR_CRC) 2500 sc->mibdata.dot3StatsFCSErrors++; 2501 if (rsr & ED_RSR_FAE) 2502 sc->mibdata.dot3StatsAlignmentErrors++; 2503 if (rsr & ED_RSR_FO) 2504 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2505 ifp->if_ierrors++; 2506#ifdef ED_DEBUG 2507 printf("ed%d: receive error %x\n", ifp->if_unit, 2508 inb(sc->nic_addr + ED_P0_RSR)); 2509#endif 2510 } 2511 2512 /* 2513 * Go get the packet(s) XXX - Doing this on an 2514 * error is dubious because there shouldn't be 2515 * any data to get (we've configured the 2516 * interface to not accept packets with 2517 * errors). 2518 */ 2519 2520 /* 2521 * Enable 16bit access to shared memory first 2522 * on WD/SMC boards. 2523 */ 2524 if (sc->isa16bit && 2525 (sc->vendor == ED_VENDOR_WD_SMC)) { 2526 2527 outb(sc->asic_addr + ED_WD_LAAR, 2528 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2529 if (sc->is790) { 2530 outb(sc->asic_addr + ED_WD_MSR, 2531 ED_WD_MSR_MENB); 2532 } 2533 } 2534 ed_rint(sc); 2535 2536 /* disable 16bit access */ 2537 if (sc->isa16bit && 2538 (sc->vendor == ED_VENDOR_WD_SMC)) { 2539 2540 if (sc->is790) { 2541 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2542 } 2543 outb(sc->asic_addr + ED_WD_LAAR, 2544 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2545 } 2546 } 2547 } 2548 2549 /* 2550 * If it looks like the transmitter can take more data, 2551 * attempt to start output on the interface. This is done 2552 * after handling the receiver to give the receiver priority. 2553 */ 2554 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2555 ed_start(ifp); 2556 2557 /* 2558 * return NIC CR to standard state: page 0, remote DMA 2559 * complete, start (toggling the TXP bit off, even if was just 2560 * set in the transmit routine, is *okay* - it is 'edge' 2561 * triggered from low to high) 2562 */ 2563 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2564 2565 /* 2566 * If the Network Talley Counters overflow, read them to reset 2567 * them. It appears that old 8390's won't clear the ISR flag 2568 * otherwise - resulting in an infinite loop. 2569 */ 2570 if (isr & ED_ISR_CNT) { 2571 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2572 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2573 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2574 } 2575 } 2576} 2577
| 2490 struct ifnet *ifp = (struct ifnet *)sc; 2491 u_char isr; 2492 2493 if (sc->gone) 2494 return; 2495 /* 2496 * Set NIC to page 0 registers 2497 */ 2498 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2499 2500 /* 2501 * loop until there are no more new interrupts 2502 */ 2503 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2504 2505 /* 2506 * reset all the bits that we are 'acknowledging' by writing a 2507 * '1' to each bit position that was set (writing a '1' 2508 * *clears* the bit) 2509 */ 2510 outb(sc->nic_addr + ED_P0_ISR, isr); 2511 2512 /* 2513 * Handle transmitter interrupts. Handle these first because 2514 * the receiver will reset the board under some conditions. 2515 */ 2516 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2517 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2518 2519 /* 2520 * Check for transmit error. If a TX completed with an 2521 * error, we end up throwing the packet away. Really 2522 * the only error that is possible is excessive 2523 * collisions, and in this case it is best to allow 2524 * the automatic mechanisms of TCP to backoff the 2525 * flow. Of course, with UDP we're screwed, but this 2526 * is expected when a network is heavily loaded. 2527 */ 2528 (void) inb(sc->nic_addr + ED_P0_TSR); 2529 if (isr & ED_ISR_TXE) { 2530 u_char tsr; 2531 2532 /* 2533 * Excessive collisions (16) 2534 */ 2535 tsr = inb(sc->nic_addr + ED_P0_TSR); 2536 if ((tsr & ED_TSR_ABT) 2537 && (collisions == 0)) { 2538 2539 /* 2540 * When collisions total 16, the 2541 * P0_NCR will indicate 0, and the 2542 * TSR_ABT is set. 2543 */ 2544 collisions = 16; 2545 sc->mibdata.dot3StatsExcessiveCollisions++; 2546 sc->mibdata.dot3StatsCollFrequencies[15]++; 2547 } 2548 if (tsr & ED_TSR_OWC) 2549 sc->mibdata.dot3StatsLateCollisions++; 2550 if (tsr & ED_TSR_CDH) 2551 sc->mibdata.dot3StatsSQETestErrors++; 2552 if (tsr & ED_TSR_CRS) 2553 sc->mibdata.dot3StatsCarrierSenseErrors++; 2554 if (tsr & ED_TSR_FU) 2555 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2556 2557 /* 2558 * update output errors counter 2559 */ 2560 ifp->if_oerrors++; 2561 } else { 2562 2563 /* 2564 * Update total number of successfully 2565 * transmitted packets. 2566 */ 2567 ifp->if_opackets++; 2568 } 2569 2570 /* 2571 * reset tx busy and output active flags 2572 */ 2573 sc->xmit_busy = 0; 2574 ifp->if_flags &= ~IFF_OACTIVE; 2575 2576 /* 2577 * clear watchdog timer 2578 */ 2579 ifp->if_timer = 0; 2580 2581 /* 2582 * Add in total number of collisions on last 2583 * transmission. 2584 */ 2585 ifp->if_collisions += collisions; 2586 switch(collisions) { 2587 case 0: 2588 case 16: 2589 break; 2590 case 1: 2591 sc->mibdata.dot3StatsSingleCollisionFrames++; 2592 sc->mibdata.dot3StatsCollFrequencies[0]++; 2593 break; 2594 default: 2595 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2596 sc->mibdata. 2597 dot3StatsCollFrequencies[collisions-1] 2598 ++; 2599 break; 2600 } 2601 2602 /* 2603 * Decrement buffer in-use count if not zero (can only 2604 * be zero if a transmitter interrupt occured while 2605 * not actually transmitting). If data is ready to 2606 * transmit, start it transmitting, otherwise defer 2607 * until after handling receiver 2608 */ 2609 if (sc->txb_inuse && --sc->txb_inuse) 2610 ed_xmit(sc); 2611 } 2612 2613 /* 2614 * Handle receiver interrupts 2615 */ 2616 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2617 2618 /* 2619 * Overwrite warning. In order to make sure that a 2620 * lockup of the local DMA hasn't occurred, we reset 2621 * and re-init the NIC. The NSC manual suggests only a 2622 * partial reset/re-init is necessary - but some chips 2623 * seem to want more. The DMA lockup has been seen 2624 * only with early rev chips - Methinks this bug was 2625 * fixed in later revs. -DG 2626 */ 2627 if (isr & ED_ISR_OVW) { 2628 ifp->if_ierrors++; 2629#ifdef DIAGNOSTIC 2630 log(LOG_WARNING, 2631 "ed%d: warning - receiver ring buffer overrun\n", 2632 ifp->if_unit); 2633#endif 2634 2635 /* 2636 * Stop/reset/re-init NIC 2637 */ 2638 ed_reset(ifp); 2639 } else { 2640 2641 /* 2642 * Receiver Error. One or more of: CRC error, 2643 * frame alignment error FIFO overrun, or 2644 * missed packet. 2645 */ 2646 if (isr & ED_ISR_RXE) { 2647 u_char rsr; 2648 rsr = inb(sc->nic_addr + ED_P0_RSR); 2649 if (rsr & ED_RSR_CRC) 2650 sc->mibdata.dot3StatsFCSErrors++; 2651 if (rsr & ED_RSR_FAE) 2652 sc->mibdata.dot3StatsAlignmentErrors++; 2653 if (rsr & ED_RSR_FO) 2654 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2655 ifp->if_ierrors++; 2656#ifdef ED_DEBUG 2657 printf("ed%d: receive error %x\n", ifp->if_unit, 2658 inb(sc->nic_addr + ED_P0_RSR)); 2659#endif 2660 } 2661 2662 /* 2663 * Go get the packet(s) XXX - Doing this on an 2664 * error is dubious because there shouldn't be 2665 * any data to get (we've configured the 2666 * interface to not accept packets with 2667 * errors). 2668 */ 2669 2670 /* 2671 * Enable 16bit access to shared memory first 2672 * on WD/SMC boards. 2673 */ 2674 if (sc->isa16bit && 2675 (sc->vendor == ED_VENDOR_WD_SMC)) { 2676 2677 outb(sc->asic_addr + ED_WD_LAAR, 2678 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2679 if (sc->is790) { 2680 outb(sc->asic_addr + ED_WD_MSR, 2681 ED_WD_MSR_MENB); 2682 } 2683 } 2684 ed_rint(sc); 2685 2686 /* disable 16bit access */ 2687 if (sc->isa16bit && 2688 (sc->vendor == ED_VENDOR_WD_SMC)) { 2689 2690 if (sc->is790) { 2691 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2692 } 2693 outb(sc->asic_addr + ED_WD_LAAR, 2694 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2695 } 2696 } 2697 } 2698 2699 /* 2700 * If it looks like the transmitter can take more data, 2701 * attempt to start output on the interface. This is done 2702 * after handling the receiver to give the receiver priority. 2703 */ 2704 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2705 ed_start(ifp); 2706 2707 /* 2708 * return NIC CR to standard state: page 0, remote DMA 2709 * complete, start (toggling the TXP bit off, even if was just 2710 * set in the transmit routine, is *okay* - it is 'edge' 2711 * triggered from low to high) 2712 */ 2713 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2714 2715 /* 2716 * If the Network Talley Counters overflow, read them to reset 2717 * them. It appears that old 8390's won't clear the ISR flag 2718 * otherwise - resulting in an infinite loop. 2719 */ 2720 if (isr & ED_ISR_CNT) { 2721 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2722 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2723 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2724 } 2725 } 2726} 2727
|
2578static void 2579edintr(unit) 2580 int unit; 2581{ 2582 edintr_sc (&ed_softc[unit]); 2583} 2584
| |
2585/* 2586 * Process an ioctl request. This code needs some work - it looks 2587 * pretty ugly. 2588 */ 2589static int 2590ed_ioctl(ifp, command, data) 2591 register struct ifnet *ifp; 2592 u_long command; 2593 caddr_t data; 2594{ 2595 struct ed_softc *sc = ifp->if_softc; 2596 int s, error = 0; 2597 2598 if (sc->gone) { 2599 ifp->if_flags &= ~IFF_RUNNING; 2600 return ENXIO; 2601 } 2602 s = splimp(); 2603 2604 switch (command) { 2605 2606 case SIOCSIFADDR: 2607 case SIOCGIFADDR: 2608 case SIOCSIFMTU: 2609 error = ether_ioctl(ifp, command, data); 2610 break; 2611 2612 case SIOCSIFFLAGS: 2613 2614 /* 2615 * If the interface is marked up and stopped, then start it. 2616 * If it is marked down and running, then stop it. 2617 */ 2618 if (ifp->if_flags & IFF_UP) { 2619 if ((ifp->if_flags & IFF_RUNNING) == 0) 2620 ed_init(sc); 2621 } else { 2622 if (ifp->if_flags & IFF_RUNNING) { 2623 ed_stop(sc); 2624 ifp->if_flags &= ~IFF_RUNNING; 2625 } 2626 } 2627 2628#if NBPF > 0 2629 2630 /* 2631 * Promiscuous flag may have changed, so reprogram the RCR. 2632 */ 2633 ed_setrcr(sc); 2634#endif 2635 2636 /* 2637 * An unfortunate hack to provide the (required) software 2638 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2639 * disables the tranceiver if set. 2640 */ 2641 if (sc->vendor == ED_VENDOR_3COM) { 2642 if (ifp->if_flags & IFF_ALTPHYS) { 2643 outb(sc->asic_addr + ED_3COM_CR, 0); 2644 } else { 2645 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2646 } 2647 } else if (sc->vendor == ED_VENDOR_HP) 2648 ed_hpp_set_physical_link(sc); 2649 break; 2650 2651 case SIOCADDMULTI: 2652 case SIOCDELMULTI: 2653 /* 2654 * Multicast list has changed; set the hardware filter 2655 * accordingly. 2656 */ 2657 ed_setrcr(sc); 2658 error = 0; 2659 break; 2660 2661 default: 2662 error = EINVAL; 2663 } 2664 (void) splx(s); 2665 return (error); 2666} 2667 2668/* 2669 * Given a source and destination address, copy 'amount' of a packet from 2670 * the ring buffer into a linear destination buffer. Takes into account 2671 * ring-wrap. 2672 */ 2673static __inline char * 2674ed_ring_copy(sc, src, dst, amount) 2675 struct ed_softc *sc; 2676 char *src; 2677 char *dst; 2678 u_short amount; 2679{ 2680 u_short tmp_amount; 2681 2682 /* does copy wrap to lower addr in ring buffer? */ 2683 if (src + amount > sc->mem_end) { 2684 tmp_amount = sc->mem_end - src; 2685 2686 /* copy amount up to end of NIC memory */ 2687 if (sc->mem_shared) 2688 bcopy(src, dst, tmp_amount); 2689 else 2690 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2691 2692 amount -= tmp_amount; 2693 src = sc->mem_ring; 2694 dst += tmp_amount; 2695 } 2696 if (sc->mem_shared) 2697 bcopy(src, dst, amount); 2698 else 2699 ed_pio_readmem(sc, (int)src, dst, amount); 2700 2701 return (src + amount); 2702} 2703 2704/* 2705 * Retreive packet from shared memory and send to the next level up via 2706 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2707 */ 2708static void 2709ed_get_packet(sc, buf, len, multicast) 2710 struct ed_softc *sc; 2711 char *buf; 2712 u_short len; 2713 int multicast; 2714{ 2715 struct ether_header *eh; 2716 struct mbuf *m; 2717 2718 /* Allocate a header mbuf */ 2719 MGETHDR(m, M_DONTWAIT, MT_DATA); 2720 if (m == NULL) 2721 return; 2722 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2723 m->m_pkthdr.len = m->m_len = len; 2724 2725 /* 2726 * We always put the received packet in a single buffer - 2727 * either with just an mbuf header or in a cluster attached 2728 * to the header. The +2 is to compensate for the alignment 2729 * fixup below. 2730 */ 2731 if ((len + 2) > MHLEN) { 2732 /* Attach an mbuf cluster */ 2733 MCLGET(m, M_DONTWAIT); 2734 2735 /* Insist on getting a cluster */ 2736 if ((m->m_flags & M_EXT) == 0) { 2737 m_freem(m); 2738 return; 2739 } 2740 } 2741 2742 /* 2743 * The +2 is to longword align the start of the real packet. 2744 * This is important for NFS. 2745 */ 2746 m->m_data += 2; 2747 eh = mtod(m, struct ether_header *); 2748 2749#ifdef BRIDGE 2750 /* 2751 * Get link layer header, invoke brige_in, then 2752 * depending on the outcome of the test fetch the rest of the 2753 * packet and either pass up or call bdg_forward. 2754 */ 2755 if (do_bridge) { 2756 struct ifnet *ifp ; 2757 int need_more = 1 ; /* in case not bpf */ 2758 2759#if NBPF > 0 2760 if (sc->arpcom.ac_if.if_bpf) { 2761 need_more = 0 ; 2762 ed_ring_copy(sc, buf, (char *)eh, len); 2763 bpf_mtap(&sc->arpcom.ac_if, m); 2764 } else 2765#endif 2766 ed_ring_copy(sc, buf, (char *)eh, 14); 2767 ifp = bridge_in(m); 2768 if (ifp == BDG_DROP) { 2769 m_freem(m); 2770 return ; 2771 } 2772 /* else fetch rest of pkt and continue */ 2773 if (need_more && len > 14) 2774 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2775 if (ifp != BDG_LOCAL ) 2776 bdg_forward(&m, ifp); /* not local, need forwarding */ 2777 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2778 goto getit ; 2779 /* not local and not multicast, just drop it */ 2780 if (m) 2781 m_freem(m); 2782 return ; 2783 } 2784#endif 2785 /* 2786 * Get packet, including link layer address, from interface. 2787 */ 2788 ed_ring_copy(sc, buf, (char *)eh, len); 2789 2790#if NBPF > 0 2791 2792 /* 2793 * Check if there's a BPF listener on this interface. If so, hand off 2794 * the raw packet to bpf. 2795 */ 2796 if (sc->arpcom.ac_if.if_bpf) 2797 bpf_mtap(&sc->arpcom.ac_if, m); 2798#endif 2799 /* 2800 * If we are in promiscuous mode, we have to check whether 2801 * this packet is really for us. 2802 */ 2803 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2804 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2805 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2806 m_freem(m); 2807 return; 2808 } 2809 2810#ifdef BRIDGE 2811getit: 2812#endif 2813 /* 2814 * Remove link layer address. 2815 */ 2816 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2817 m->m_data += sizeof(struct ether_header); 2818 2819 ether_input(&sc->arpcom.ac_if, eh, m); 2820 return; 2821} 2822 2823/* 2824 * Supporting routines 2825 */ 2826 2827/* 2828 * Given a NIC memory source address and a host memory destination 2829 * address, copy 'amount' from NIC to host using Programmed I/O. 2830 * The 'amount' is rounded up to a word - okay as long as mbufs 2831 * are word sized. 2832 * This routine is currently Novell-specific. 2833 */ 2834static void 2835ed_pio_readmem(sc, src, dst, amount) 2836 struct ed_softc *sc; 2837 int src; 2838 unsigned char *dst; 2839 unsigned short amount; 2840{ 2841 /* HP cards need special handling */ 2842 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2843 ed_hpp_readmem(sc, src, dst, amount); 2844 return; 2845 } 2846 2847 /* Regular Novell cards */ 2848 /* select page 0 registers */ 2849 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2850 2851 /* round up to a word */ 2852 if (amount & 1) 2853 ++amount; 2854 2855 /* set up DMA byte count */ 2856 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2857 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2858 2859 /* set up source address in NIC mem */ 2860 outb(sc->nic_addr + ED_P0_RSAR0, src); 2861 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2862 2863 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2864 2865 if (sc->isa16bit) { 2866 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2867 } else 2868 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2869 2870} 2871 2872/* 2873 * Stripped down routine for writing a linear buffer to NIC memory. 2874 * Only used in the probe routine to test the memory. 'len' must 2875 * be even. 2876 */ 2877static void 2878ed_pio_writemem(sc, src, dst, len) 2879 struct ed_softc *sc; 2880 char *src; 2881 unsigned short dst; 2882 unsigned short len; 2883{ 2884 int maxwait = 200; /* about 240us */ 2885 2886 if (sc->vendor == ED_VENDOR_NOVELL) { 2887 2888 /* select page 0 registers */ 2889 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2890 2891 /* reset remote DMA complete flag */ 2892 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2893 2894 /* set up DMA byte count */ 2895 outb(sc->nic_addr + ED_P0_RBCR0, len); 2896 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2897 2898 /* set up destination address in NIC mem */ 2899 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2900 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2901 2902 /* set remote DMA write */ 2903 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2904 2905 if (sc->isa16bit) 2906 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2907 else 2908 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2909 2910 /* 2911 * Wait for remote DMA complete. This is necessary because on the 2912 * transmit side, data is handled internally by the NIC in bursts and 2913 * we can't start another remote DMA until this one completes. Not 2914 * waiting causes really bad things to happen - like the NIC 2915 * irrecoverably jamming the ISA bus. 2916 */ 2917 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2918 2919 } else if ((sc->vendor == ED_VENDOR_HP) && 2920 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2921 2922 /* HP PCLAN+ */ 2923 2924 /* reset remote DMA complete flag */ 2925 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2926 2927 /* program the write address in RAM */ 2928 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2929 2930 if (sc->hpp_mem_start) { 2931 u_short *s = (u_short *) src; 2932 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2933 u_short *const fence = s + (len >> 1); 2934 2935 /* 2936 * Enable memory mapped access. 2937 */ 2938 2939 outw(sc->asic_addr + ED_HPP_OPTION, 2940 sc->hpp_options & 2941 ~(ED_HPP_OPTION_MEM_DISABLE | 2942 ED_HPP_OPTION_BOOT_ROM_ENB)); 2943 2944 /* 2945 * Copy to NIC memory. 2946 */ 2947 2948 while (s < fence) 2949 *d = *s++; 2950 2951 /* 2952 * Restore Boot ROM access. 2953 */ 2954 2955 outw(sc->asic_addr + ED_HPP_OPTION, 2956 sc->hpp_options); 2957 2958 } else { 2959 /* write data using I/O writes */ 2960 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2961 } 2962 2963 } 2964} 2965 2966/* 2967 * Write an mbuf chain to the destination NIC memory address using 2968 * programmed I/O. 2969 */ 2970static u_short 2971ed_pio_write_mbufs(sc, m, dst) 2972 struct ed_softc *sc; 2973 struct mbuf *m; 2974 int dst; 2975{ 2976 struct ifnet *ifp = (struct ifnet *)sc; 2977 unsigned short total_len, dma_len; 2978 struct mbuf *mp; 2979 int maxwait = 200; /* about 240us */ 2980 2981 /* HP PC Lan+ cards need special handling */ 2982 if ((sc->vendor == ED_VENDOR_HP) && 2983 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2984 return ed_hpp_write_mbufs(sc, m, dst); 2985 } 2986 2987 /* First, count up the total number of bytes to copy */ 2988 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2989 total_len += mp->m_len; 2990 2991 dma_len = total_len; 2992 if (sc->isa16bit && (dma_len & 1)) 2993 dma_len++; 2994 2995 /* select page 0 registers */ 2996 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2997 2998 /* reset remote DMA complete flag */ 2999 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3000 3001 /* set up DMA byte count */ 3002 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 3003 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 3004 3005 /* set up destination address in NIC mem */ 3006 outb(sc->nic_addr + ED_P0_RSAR0, dst); 3007 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3008 3009 /* set remote DMA write */ 3010 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3011 3012 /* 3013 * Transfer the mbuf chain to the NIC memory. 3014 * 16-bit cards require that data be transferred as words, and only words. 3015 * So that case requires some extra code to patch over odd-length mbufs. 3016 */ 3017 3018 if (!sc->isa16bit) { 3019 /* NE1000s are easy */ 3020 while (m) { 3021 if (m->m_len) { 3022 outsb(sc->asic_addr + ED_NOVELL_DATA, 3023 m->m_data, m->m_len); 3024 } 3025 m = m->m_next; 3026 } 3027 } else { 3028 /* NE2000s are a pain */ 3029 unsigned char *data; 3030 int len, wantbyte; 3031 unsigned char savebyte[2]; 3032 3033 wantbyte = 0; 3034 3035 while (m) { 3036 len = m->m_len; 3037 if (len) { 3038 data = mtod(m, caddr_t); 3039 /* finish the last word */ 3040 if (wantbyte) { 3041 savebyte[1] = *data; 3042 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3043 data++; 3044 len--; 3045 wantbyte = 0; 3046 } 3047 /* output contiguous words */ 3048 if (len > 1) { 3049 outsw(sc->asic_addr + ED_NOVELL_DATA, 3050 data, len >> 1); 3051 data += len & ~1; 3052 len &= 1; 3053 } 3054 /* save last byte, if necessary */ 3055 if (len == 1) { 3056 savebyte[0] = *data; 3057 wantbyte = 1; 3058 } 3059 } 3060 m = m->m_next; 3061 } 3062 /* spit last byte */ 3063 if (wantbyte) { 3064 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3065 } 3066 } 3067 3068 /* 3069 * Wait for remote DMA complete. This is necessary because on the 3070 * transmit side, data is handled internally by the NIC in bursts and 3071 * we can't start another remote DMA until this one completes. Not 3072 * waiting causes really bad things to happen - like the NIC 3073 * irrecoverably jamming the ISA bus. 3074 */ 3075 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3076 3077 if (!maxwait) { 3078 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3079 ifp->if_unit); 3080 ed_reset(ifp); 3081 return(0); 3082 } 3083 return (total_len); 3084} 3085 3086/* 3087 * Support routines to handle the HP PC Lan+ card. 3088 */ 3089 3090/* 3091 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3092 * IO. 3093 */ 3094 3095static void 3096ed_hpp_readmem(sc, src, dst, amount) 3097 struct ed_softc *sc; 3098 unsigned short src; 3099 unsigned char *dst; 3100 unsigned short amount; 3101{ 3102 3103 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3104 3105 3106 /* Program the source address in RAM */ 3107 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3108 3109 /* 3110 * The HP PC Lan+ card supports word reads as well as 3111 * a memory mapped i/o port that is aliased to every 3112 * even address on the board. 3113 */ 3114 3115 if (sc->hpp_mem_start) { 3116 3117 /* Enable memory mapped access. */ 3118 outw(sc->asic_addr + ED_HPP_OPTION, 3119 sc->hpp_options & 3120 ~(ED_HPP_OPTION_MEM_DISABLE | 3121 ED_HPP_OPTION_BOOT_ROM_ENB)); 3122 3123 if (use_32bit_access && (amount > 3)) { 3124 u_long *dl = (u_long *) dst; 3125 volatile u_long *const sl = 3126 (u_long *) sc->hpp_mem_start; 3127 u_long *const fence = dl + (amount >> 2); 3128 3129 /* Copy out NIC data. We could probably write this 3130 as a `movsl'. The currently generated code is lousy. 3131 */ 3132 3133 while (dl < fence) 3134 *dl++ = *sl; 3135 3136 dst += (amount & ~3); 3137 amount &= 3; 3138 3139 } 3140 3141 /* Finish off any words left, as a series of short reads */ 3142 if (amount > 1) { 3143 u_short *d = (u_short *) dst; 3144 volatile u_short *const s = 3145 (u_short *) sc->hpp_mem_start; 3146 u_short *const fence = d + (amount >> 1); 3147 3148 /* Copy out NIC data. */ 3149 3150 while (d < fence) 3151 *d++ = *s; 3152 3153 dst += (amount & ~1); 3154 amount &= 1; 3155 } 3156 3157 /* 3158 * read in a byte; however we need to always read 16 bits 3159 * at a time or the hardware gets into a funny state 3160 */ 3161 3162 if (amount == 1) { 3163 /* need to read in a short and copy LSB */ 3164 volatile u_short *const s = 3165 (volatile u_short *) sc->hpp_mem_start; 3166 3167 *dst = (*s) & 0xFF; 3168 } 3169 3170 /* Restore Boot ROM access. */ 3171 3172 outw(sc->asic_addr + ED_HPP_OPTION, 3173 sc->hpp_options); 3174 3175 3176 } else { 3177 /* Read in data using the I/O port */ 3178 if (use_32bit_access && (amount > 3)) { 3179 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3180 dst += (amount & ~3); 3181 amount &= 3; 3182 } 3183 if (amount > 1) { 3184 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3185 dst += (amount & ~1); 3186 amount &= 1; 3187 } 3188 if (amount == 1) { /* read in a short and keep the LSB */ 3189 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3190 } 3191 } 3192} 3193 3194/* 3195 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3196 * outsw() or via the memory mapped interface to the same register. 3197 * Writes have to be in word units; byte accesses won't work and may cause 3198 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3199 * allows it. 3200 */ 3201 3202static u_short 3203ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3204{ 3205 int len, wantbyte; 3206 unsigned short total_len; 3207 unsigned char savebyte[2]; 3208 volatile u_short * const d = 3209 (volatile u_short *) sc->hpp_mem_start; 3210 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3211 3212 /* select page 0 registers */ 3213 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3214 3215 /* reset remote DMA complete flag */ 3216 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3217 3218 /* program the write address in RAM */ 3219 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3220 3221 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3222 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3223 ~(ED_HPP_OPTION_MEM_DISABLE | 3224 ED_HPP_OPTION_BOOT_ROM_ENB)); 3225 3226 wantbyte = 0; 3227 total_len = 0; 3228 3229 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3230 while (m) { 3231 total_len += (len = m->m_len); 3232 if (len) { 3233 caddr_t data = mtod(m, caddr_t); 3234 /* finish the last word of the previous mbuf */ 3235 if (wantbyte) { 3236 savebyte[1] = *data; 3237 *d = *((ushort *) savebyte); 3238 data++; len--; wantbyte = 0; 3239 } 3240 /* output contiguous words */ 3241 if ((len > 3) && (use_32bit_accesses)) { 3242 volatile u_long *const dl = 3243 (volatile u_long *) d; 3244 u_long *sl = (u_long *) data; 3245 u_long *fence = sl + (len >> 2); 3246 3247 while (sl < fence) 3248 *dl = *sl++; 3249 3250 data += (len & ~3); 3251 len &= 3; 3252 } 3253 /* finish off remain 16 bit writes */ 3254 if (len > 1) { 3255 u_short *s = (u_short *) data; 3256 u_short *fence = s + (len >> 1); 3257 3258 while (s < fence) 3259 *d = *s++; 3260 3261 data += (len & ~1); 3262 len &= 1; 3263 } 3264 /* save last byte if needed */ 3265 if ((wantbyte = (len == 1)) != 0) 3266 savebyte[0] = *data; 3267 } 3268 m = m->m_next; /* to next mbuf */ 3269 } 3270 if (wantbyte) /* write last byte */ 3271 *d = *((u_short *) savebyte); 3272 } else { 3273 /* use programmed I/O */ 3274 while (m) { 3275 total_len += (len = m->m_len); 3276 if (len) { 3277 caddr_t data = mtod(m, caddr_t); 3278 /* finish the last word of the previous mbuf */ 3279 if (wantbyte) { 3280 savebyte[1] = *data; 3281 outw(sc->asic_addr + ED_HPP_PAGE_4, 3282 *((u_short *)savebyte)); 3283 data++; 3284 len--; 3285 wantbyte = 0; 3286 } 3287 /* output contiguous words */ 3288 if ((len > 3) && use_32bit_accesses) { 3289 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3290 data, len >> 2); 3291 data += (len & ~3); 3292 len &= 3; 3293 } 3294 /* finish off remaining 16 bit accesses */ 3295 if (len > 1) { 3296 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3297 data, len >> 1); 3298 data += (len & ~1); 3299 len &= 1; 3300 } 3301 if ((wantbyte = (len == 1)) != 0) 3302 savebyte[0] = *data; 3303 3304 } /* if len != 0 */ 3305 m = m->m_next; 3306 } 3307 if (wantbyte) /* spit last byte */ 3308 outw(sc->asic_addr + ED_HPP_PAGE_4, 3309 *(u_short *)savebyte); 3310 3311 } 3312 3313 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3314 outw(sc->asic_addr + ED_HPP_OPTION, 3315 sc->hpp_options); 3316 3317 return (total_len); 3318} 3319 3320static void 3321ed_setrcr(sc) 3322 struct ed_softc *sc; 3323{ 3324 struct ifnet *ifp = (struct ifnet *)sc; 3325 int i; 3326 3327 /* set page 1 registers */ 3328 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3329 3330 if (ifp->if_flags & IFF_PROMISC) { 3331 3332 /* 3333 * Reconfigure the multicast filter. 3334 */ 3335 for (i = 0; i < 8; i++) 3336 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3337 3338 /* 3339 * And turn on promiscuous mode. Also enable reception of 3340 * runts and packets with CRC & alignment errors. 3341 */ 3342 /* Set page 0 registers */ 3343 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3344 3345 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3346 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3347 } else { 3348 /* set up multicast addresses and filter modes */ 3349 if (ifp->if_flags & IFF_MULTICAST) { 3350 u_long mcaf[2]; 3351 3352 if (ifp->if_flags & IFF_ALLMULTI) { 3353 mcaf[0] = 0xffffffff; 3354 mcaf[1] = 0xffffffff; 3355 } else 3356 ds_getmcaf(sc, mcaf); 3357 3358 /* 3359 * Set multicast filter on chip. 3360 */ 3361 for (i = 0; i < 8; i++) 3362 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3363 3364 /* Set page 0 registers */ 3365 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3366 3367 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3368 } else { 3369 3370 /* 3371 * Initialize multicast address hashing registers to 3372 * not accept multicasts. 3373 */ 3374 for (i = 0; i < 8; ++i) 3375 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3376 3377 /* Set page 0 registers */ 3378 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3379 3380 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3381 } 3382 } 3383 3384 /* 3385 * Start interface. 3386 */ 3387 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3388} 3389 3390/* 3391 * Compute crc for ethernet address 3392 */ 3393static u_long 3394ds_crc(ep) 3395 u_char *ep; 3396{ 3397#define POLYNOMIAL 0x04c11db6 3398 register u_long crc = 0xffffffffL; 3399 register int carry, i, j; 3400 register u_char b; 3401 3402 for (i = 6; --i >= 0;) { 3403 b = *ep++; 3404 for (j = 8; --j >= 0;) { 3405 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3406 crc <<= 1; 3407 b >>= 1; 3408 if (carry) 3409 crc = ((crc ^ POLYNOMIAL) | carry); 3410 } 3411 } 3412 return crc; 3413#undef POLYNOMIAL 3414} 3415 3416/* 3417 * Compute the multicast address filter from the 3418 * list of multicast addresses we need to listen to. 3419 */ 3420static void 3421ds_getmcaf(sc, mcaf) 3422 struct ed_softc *sc; 3423 u_long *mcaf; 3424{ 3425 register u_int index; 3426 register u_char *af = (u_char *) mcaf; 3427 struct ifmultiaddr *ifma; 3428 3429 mcaf[0] = 0; 3430 mcaf[1] = 0; 3431 3432 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3433 ifma = ifma->ifma_link.le_next) { 3434 if (ifma->ifma_addr->sa_family != AF_LINK) 3435 continue; 3436 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3437 >> 26; 3438 af[index >> 3] |= 1 << (index & 7); 3439 } 3440} 3441
| 2728/* 2729 * Process an ioctl request. This code needs some work - it looks 2730 * pretty ugly. 2731 */ 2732static int 2733ed_ioctl(ifp, command, data) 2734 register struct ifnet *ifp; 2735 u_long command; 2736 caddr_t data; 2737{ 2738 struct ed_softc *sc = ifp->if_softc; 2739 int s, error = 0; 2740 2741 if (sc->gone) { 2742 ifp->if_flags &= ~IFF_RUNNING; 2743 return ENXIO; 2744 } 2745 s = splimp(); 2746 2747 switch (command) { 2748 2749 case SIOCSIFADDR: 2750 case SIOCGIFADDR: 2751 case SIOCSIFMTU: 2752 error = ether_ioctl(ifp, command, data); 2753 break; 2754 2755 case SIOCSIFFLAGS: 2756 2757 /* 2758 * If the interface is marked up and stopped, then start it. 2759 * If it is marked down and running, then stop it. 2760 */ 2761 if (ifp->if_flags & IFF_UP) { 2762 if ((ifp->if_flags & IFF_RUNNING) == 0) 2763 ed_init(sc); 2764 } else { 2765 if (ifp->if_flags & IFF_RUNNING) { 2766 ed_stop(sc); 2767 ifp->if_flags &= ~IFF_RUNNING; 2768 } 2769 } 2770 2771#if NBPF > 0 2772 2773 /* 2774 * Promiscuous flag may have changed, so reprogram the RCR. 2775 */ 2776 ed_setrcr(sc); 2777#endif 2778 2779 /* 2780 * An unfortunate hack to provide the (required) software 2781 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2782 * disables the tranceiver if set. 2783 */ 2784 if (sc->vendor == ED_VENDOR_3COM) { 2785 if (ifp->if_flags & IFF_ALTPHYS) { 2786 outb(sc->asic_addr + ED_3COM_CR, 0); 2787 } else { 2788 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2789 } 2790 } else if (sc->vendor == ED_VENDOR_HP) 2791 ed_hpp_set_physical_link(sc); 2792 break; 2793 2794 case SIOCADDMULTI: 2795 case SIOCDELMULTI: 2796 /* 2797 * Multicast list has changed; set the hardware filter 2798 * accordingly. 2799 */ 2800 ed_setrcr(sc); 2801 error = 0; 2802 break; 2803 2804 default: 2805 error = EINVAL; 2806 } 2807 (void) splx(s); 2808 return (error); 2809} 2810 2811/* 2812 * Given a source and destination address, copy 'amount' of a packet from 2813 * the ring buffer into a linear destination buffer. Takes into account 2814 * ring-wrap. 2815 */ 2816static __inline char * 2817ed_ring_copy(sc, src, dst, amount) 2818 struct ed_softc *sc; 2819 char *src; 2820 char *dst; 2821 u_short amount; 2822{ 2823 u_short tmp_amount; 2824 2825 /* does copy wrap to lower addr in ring buffer? */ 2826 if (src + amount > sc->mem_end) { 2827 tmp_amount = sc->mem_end - src; 2828 2829 /* copy amount up to end of NIC memory */ 2830 if (sc->mem_shared) 2831 bcopy(src, dst, tmp_amount); 2832 else 2833 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2834 2835 amount -= tmp_amount; 2836 src = sc->mem_ring; 2837 dst += tmp_amount; 2838 } 2839 if (sc->mem_shared) 2840 bcopy(src, dst, amount); 2841 else 2842 ed_pio_readmem(sc, (int)src, dst, amount); 2843 2844 return (src + amount); 2845} 2846 2847/* 2848 * Retreive packet from shared memory and send to the next level up via 2849 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2850 */ 2851static void 2852ed_get_packet(sc, buf, len, multicast) 2853 struct ed_softc *sc; 2854 char *buf; 2855 u_short len; 2856 int multicast; 2857{ 2858 struct ether_header *eh; 2859 struct mbuf *m; 2860 2861 /* Allocate a header mbuf */ 2862 MGETHDR(m, M_DONTWAIT, MT_DATA); 2863 if (m == NULL) 2864 return; 2865 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2866 m->m_pkthdr.len = m->m_len = len; 2867 2868 /* 2869 * We always put the received packet in a single buffer - 2870 * either with just an mbuf header or in a cluster attached 2871 * to the header. The +2 is to compensate for the alignment 2872 * fixup below. 2873 */ 2874 if ((len + 2) > MHLEN) { 2875 /* Attach an mbuf cluster */ 2876 MCLGET(m, M_DONTWAIT); 2877 2878 /* Insist on getting a cluster */ 2879 if ((m->m_flags & M_EXT) == 0) { 2880 m_freem(m); 2881 return; 2882 } 2883 } 2884 2885 /* 2886 * The +2 is to longword align the start of the real packet. 2887 * This is important for NFS. 2888 */ 2889 m->m_data += 2; 2890 eh = mtod(m, struct ether_header *); 2891 2892#ifdef BRIDGE 2893 /* 2894 * Get link layer header, invoke brige_in, then 2895 * depending on the outcome of the test fetch the rest of the 2896 * packet and either pass up or call bdg_forward. 2897 */ 2898 if (do_bridge) { 2899 struct ifnet *ifp ; 2900 int need_more = 1 ; /* in case not bpf */ 2901 2902#if NBPF > 0 2903 if (sc->arpcom.ac_if.if_bpf) { 2904 need_more = 0 ; 2905 ed_ring_copy(sc, buf, (char *)eh, len); 2906 bpf_mtap(&sc->arpcom.ac_if, m); 2907 } else 2908#endif 2909 ed_ring_copy(sc, buf, (char *)eh, 14); 2910 ifp = bridge_in(m); 2911 if (ifp == BDG_DROP) { 2912 m_freem(m); 2913 return ; 2914 } 2915 /* else fetch rest of pkt and continue */ 2916 if (need_more && len > 14) 2917 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2918 if (ifp != BDG_LOCAL ) 2919 bdg_forward(&m, ifp); /* not local, need forwarding */ 2920 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2921 goto getit ; 2922 /* not local and not multicast, just drop it */ 2923 if (m) 2924 m_freem(m); 2925 return ; 2926 } 2927#endif 2928 /* 2929 * Get packet, including link layer address, from interface. 2930 */ 2931 ed_ring_copy(sc, buf, (char *)eh, len); 2932 2933#if NBPF > 0 2934 2935 /* 2936 * Check if there's a BPF listener on this interface. If so, hand off 2937 * the raw packet to bpf. 2938 */ 2939 if (sc->arpcom.ac_if.if_bpf) 2940 bpf_mtap(&sc->arpcom.ac_if, m); 2941#endif 2942 /* 2943 * If we are in promiscuous mode, we have to check whether 2944 * this packet is really for us. 2945 */ 2946 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2947 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2948 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2949 m_freem(m); 2950 return; 2951 } 2952 2953#ifdef BRIDGE 2954getit: 2955#endif 2956 /* 2957 * Remove link layer address. 2958 */ 2959 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2960 m->m_data += sizeof(struct ether_header); 2961 2962 ether_input(&sc->arpcom.ac_if, eh, m); 2963 return; 2964} 2965 2966/* 2967 * Supporting routines 2968 */ 2969 2970/* 2971 * Given a NIC memory source address and a host memory destination 2972 * address, copy 'amount' from NIC to host using Programmed I/O. 2973 * The 'amount' is rounded up to a word - okay as long as mbufs 2974 * are word sized. 2975 * This routine is currently Novell-specific. 2976 */ 2977static void 2978ed_pio_readmem(sc, src, dst, amount) 2979 struct ed_softc *sc; 2980 int src; 2981 unsigned char *dst; 2982 unsigned short amount; 2983{ 2984 /* HP cards need special handling */ 2985 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2986 ed_hpp_readmem(sc, src, dst, amount); 2987 return; 2988 } 2989 2990 /* Regular Novell cards */ 2991 /* select page 0 registers */ 2992 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2993 2994 /* round up to a word */ 2995 if (amount & 1) 2996 ++amount; 2997 2998 /* set up DMA byte count */ 2999 outb(sc->nic_addr + ED_P0_RBCR0, amount); 3000 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 3001 3002 /* set up source address in NIC mem */ 3003 outb(sc->nic_addr + ED_P0_RSAR0, src); 3004 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 3005 3006 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 3007 3008 if (sc->isa16bit) { 3009 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 3010 } else 3011 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 3012 3013} 3014 3015/* 3016 * Stripped down routine for writing a linear buffer to NIC memory. 3017 * Only used in the probe routine to test the memory. 'len' must 3018 * be even. 3019 */ 3020static void 3021ed_pio_writemem(sc, src, dst, len) 3022 struct ed_softc *sc; 3023 char *src; 3024 unsigned short dst; 3025 unsigned short len; 3026{ 3027 int maxwait = 200; /* about 240us */ 3028 3029 if (sc->vendor == ED_VENDOR_NOVELL) { 3030 3031 /* select page 0 registers */ 3032 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 3033 3034 /* reset remote DMA complete flag */ 3035 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3036 3037 /* set up DMA byte count */ 3038 outb(sc->nic_addr + ED_P0_RBCR0, len); 3039 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 3040 3041 /* set up destination address in NIC mem */ 3042 outb(sc->nic_addr + ED_P0_RSAR0, dst); 3043 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3044 3045 /* set remote DMA write */ 3046 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3047 3048 if (sc->isa16bit) 3049 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 3050 else 3051 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 3052 3053 /* 3054 * Wait for remote DMA complete. This is necessary because on the 3055 * transmit side, data is handled internally by the NIC in bursts and 3056 * we can't start another remote DMA until this one completes. Not 3057 * waiting causes really bad things to happen - like the NIC 3058 * irrecoverably jamming the ISA bus. 3059 */ 3060 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3061 3062 } else if ((sc->vendor == ED_VENDOR_HP) && 3063 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 3064 3065 /* HP PCLAN+ */ 3066 3067 /* reset remote DMA complete flag */ 3068 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3069 3070 /* program the write address in RAM */ 3071 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3072 3073 if (sc->hpp_mem_start) { 3074 u_short *s = (u_short *) src; 3075 volatile u_short *d = (u_short *) sc->hpp_mem_start; 3076 u_short *const fence = s + (len >> 1); 3077 3078 /* 3079 * Enable memory mapped access. 3080 */ 3081 3082 outw(sc->asic_addr + ED_HPP_OPTION, 3083 sc->hpp_options & 3084 ~(ED_HPP_OPTION_MEM_DISABLE | 3085 ED_HPP_OPTION_BOOT_ROM_ENB)); 3086 3087 /* 3088 * Copy to NIC memory. 3089 */ 3090 3091 while (s < fence) 3092 *d = *s++; 3093 3094 /* 3095 * Restore Boot ROM access. 3096 */ 3097 3098 outw(sc->asic_addr + ED_HPP_OPTION, 3099 sc->hpp_options); 3100 3101 } else { 3102 /* write data using I/O writes */ 3103 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 3104 } 3105 3106 } 3107} 3108 3109/* 3110 * Write an mbuf chain to the destination NIC memory address using 3111 * programmed I/O. 3112 */ 3113static u_short 3114ed_pio_write_mbufs(sc, m, dst) 3115 struct ed_softc *sc; 3116 struct mbuf *m; 3117 int dst; 3118{ 3119 struct ifnet *ifp = (struct ifnet *)sc; 3120 unsigned short total_len, dma_len; 3121 struct mbuf *mp; 3122 int maxwait = 200; /* about 240us */ 3123 3124 /* HP PC Lan+ cards need special handling */ 3125 if ((sc->vendor == ED_VENDOR_HP) && 3126 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 3127 return ed_hpp_write_mbufs(sc, m, dst); 3128 } 3129 3130 /* First, count up the total number of bytes to copy */ 3131 for (total_len = 0, mp = m; mp; mp = mp->m_next) 3132 total_len += mp->m_len; 3133 3134 dma_len = total_len; 3135 if (sc->isa16bit && (dma_len & 1)) 3136 dma_len++; 3137 3138 /* select page 0 registers */ 3139 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 3140 3141 /* reset remote DMA complete flag */ 3142 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3143 3144 /* set up DMA byte count */ 3145 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 3146 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 3147 3148 /* set up destination address in NIC mem */ 3149 outb(sc->nic_addr + ED_P0_RSAR0, dst); 3150 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3151 3152 /* set remote DMA write */ 3153 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3154 3155 /* 3156 * Transfer the mbuf chain to the NIC memory. 3157 * 16-bit cards require that data be transferred as words, and only words. 3158 * So that case requires some extra code to patch over odd-length mbufs. 3159 */ 3160 3161 if (!sc->isa16bit) { 3162 /* NE1000s are easy */ 3163 while (m) { 3164 if (m->m_len) { 3165 outsb(sc->asic_addr + ED_NOVELL_DATA, 3166 m->m_data, m->m_len); 3167 } 3168 m = m->m_next; 3169 } 3170 } else { 3171 /* NE2000s are a pain */ 3172 unsigned char *data; 3173 int len, wantbyte; 3174 unsigned char savebyte[2]; 3175 3176 wantbyte = 0; 3177 3178 while (m) { 3179 len = m->m_len; 3180 if (len) { 3181 data = mtod(m, caddr_t); 3182 /* finish the last word */ 3183 if (wantbyte) { 3184 savebyte[1] = *data; 3185 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3186 data++; 3187 len--; 3188 wantbyte = 0; 3189 } 3190 /* output contiguous words */ 3191 if (len > 1) { 3192 outsw(sc->asic_addr + ED_NOVELL_DATA, 3193 data, len >> 1); 3194 data += len & ~1; 3195 len &= 1; 3196 } 3197 /* save last byte, if necessary */ 3198 if (len == 1) { 3199 savebyte[0] = *data; 3200 wantbyte = 1; 3201 } 3202 } 3203 m = m->m_next; 3204 } 3205 /* spit last byte */ 3206 if (wantbyte) { 3207 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3208 } 3209 } 3210 3211 /* 3212 * Wait for remote DMA complete. This is necessary because on the 3213 * transmit side, data is handled internally by the NIC in bursts and 3214 * we can't start another remote DMA until this one completes. Not 3215 * waiting causes really bad things to happen - like the NIC 3216 * irrecoverably jamming the ISA bus. 3217 */ 3218 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3219 3220 if (!maxwait) { 3221 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3222 ifp->if_unit); 3223 ed_reset(ifp); 3224 return(0); 3225 } 3226 return (total_len); 3227} 3228 3229/* 3230 * Support routines to handle the HP PC Lan+ card. 3231 */ 3232 3233/* 3234 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3235 * IO. 3236 */ 3237 3238static void 3239ed_hpp_readmem(sc, src, dst, amount) 3240 struct ed_softc *sc; 3241 unsigned short src; 3242 unsigned char *dst; 3243 unsigned short amount; 3244{ 3245 3246 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3247 3248 3249 /* Program the source address in RAM */ 3250 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3251 3252 /* 3253 * The HP PC Lan+ card supports word reads as well as 3254 * a memory mapped i/o port that is aliased to every 3255 * even address on the board. 3256 */ 3257 3258 if (sc->hpp_mem_start) { 3259 3260 /* Enable memory mapped access. */ 3261 outw(sc->asic_addr + ED_HPP_OPTION, 3262 sc->hpp_options & 3263 ~(ED_HPP_OPTION_MEM_DISABLE | 3264 ED_HPP_OPTION_BOOT_ROM_ENB)); 3265 3266 if (use_32bit_access && (amount > 3)) { 3267 u_long *dl = (u_long *) dst; 3268 volatile u_long *const sl = 3269 (u_long *) sc->hpp_mem_start; 3270 u_long *const fence = dl + (amount >> 2); 3271 3272 /* Copy out NIC data. We could probably write this 3273 as a `movsl'. The currently generated code is lousy. 3274 */ 3275 3276 while (dl < fence) 3277 *dl++ = *sl; 3278 3279 dst += (amount & ~3); 3280 amount &= 3; 3281 3282 } 3283 3284 /* Finish off any words left, as a series of short reads */ 3285 if (amount > 1) { 3286 u_short *d = (u_short *) dst; 3287 volatile u_short *const s = 3288 (u_short *) sc->hpp_mem_start; 3289 u_short *const fence = d + (amount >> 1); 3290 3291 /* Copy out NIC data. */ 3292 3293 while (d < fence) 3294 *d++ = *s; 3295 3296 dst += (amount & ~1); 3297 amount &= 1; 3298 } 3299 3300 /* 3301 * read in a byte; however we need to always read 16 bits 3302 * at a time or the hardware gets into a funny state 3303 */ 3304 3305 if (amount == 1) { 3306 /* need to read in a short and copy LSB */ 3307 volatile u_short *const s = 3308 (volatile u_short *) sc->hpp_mem_start; 3309 3310 *dst = (*s) & 0xFF; 3311 } 3312 3313 /* Restore Boot ROM access. */ 3314 3315 outw(sc->asic_addr + ED_HPP_OPTION, 3316 sc->hpp_options); 3317 3318 3319 } else { 3320 /* Read in data using the I/O port */ 3321 if (use_32bit_access && (amount > 3)) { 3322 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3323 dst += (amount & ~3); 3324 amount &= 3; 3325 } 3326 if (amount > 1) { 3327 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3328 dst += (amount & ~1); 3329 amount &= 1; 3330 } 3331 if (amount == 1) { /* read in a short and keep the LSB */ 3332 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3333 } 3334 } 3335} 3336 3337/* 3338 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3339 * outsw() or via the memory mapped interface to the same register. 3340 * Writes have to be in word units; byte accesses won't work and may cause 3341 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3342 * allows it. 3343 */ 3344 3345static u_short 3346ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3347{ 3348 int len, wantbyte; 3349 unsigned short total_len; 3350 unsigned char savebyte[2]; 3351 volatile u_short * const d = 3352 (volatile u_short *) sc->hpp_mem_start; 3353 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3354 3355 /* select page 0 registers */ 3356 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3357 3358 /* reset remote DMA complete flag */ 3359 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3360 3361 /* program the write address in RAM */ 3362 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3363 3364 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3365 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3366 ~(ED_HPP_OPTION_MEM_DISABLE | 3367 ED_HPP_OPTION_BOOT_ROM_ENB)); 3368 3369 wantbyte = 0; 3370 total_len = 0; 3371 3372 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3373 while (m) { 3374 total_len += (len = m->m_len); 3375 if (len) { 3376 caddr_t data = mtod(m, caddr_t); 3377 /* finish the last word of the previous mbuf */ 3378 if (wantbyte) { 3379 savebyte[1] = *data; 3380 *d = *((ushort *) savebyte); 3381 data++; len--; wantbyte = 0; 3382 } 3383 /* output contiguous words */ 3384 if ((len > 3) && (use_32bit_accesses)) { 3385 volatile u_long *const dl = 3386 (volatile u_long *) d; 3387 u_long *sl = (u_long *) data; 3388 u_long *fence = sl + (len >> 2); 3389 3390 while (sl < fence) 3391 *dl = *sl++; 3392 3393 data += (len & ~3); 3394 len &= 3; 3395 } 3396 /* finish off remain 16 bit writes */ 3397 if (len > 1) { 3398 u_short *s = (u_short *) data; 3399 u_short *fence = s + (len >> 1); 3400 3401 while (s < fence) 3402 *d = *s++; 3403 3404 data += (len & ~1); 3405 len &= 1; 3406 } 3407 /* save last byte if needed */ 3408 if ((wantbyte = (len == 1)) != 0) 3409 savebyte[0] = *data; 3410 } 3411 m = m->m_next; /* to next mbuf */ 3412 } 3413 if (wantbyte) /* write last byte */ 3414 *d = *((u_short *) savebyte); 3415 } else { 3416 /* use programmed I/O */ 3417 while (m) { 3418 total_len += (len = m->m_len); 3419 if (len) { 3420 caddr_t data = mtod(m, caddr_t); 3421 /* finish the last word of the previous mbuf */ 3422 if (wantbyte) { 3423 savebyte[1] = *data; 3424 outw(sc->asic_addr + ED_HPP_PAGE_4, 3425 *((u_short *)savebyte)); 3426 data++; 3427 len--; 3428 wantbyte = 0; 3429 } 3430 /* output contiguous words */ 3431 if ((len > 3) && use_32bit_accesses) { 3432 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3433 data, len >> 2); 3434 data += (len & ~3); 3435 len &= 3; 3436 } 3437 /* finish off remaining 16 bit accesses */ 3438 if (len > 1) { 3439 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3440 data, len >> 1); 3441 data += (len & ~1); 3442 len &= 1; 3443 } 3444 if ((wantbyte = (len == 1)) != 0) 3445 savebyte[0] = *data; 3446 3447 } /* if len != 0 */ 3448 m = m->m_next; 3449 } 3450 if (wantbyte) /* spit last byte */ 3451 outw(sc->asic_addr + ED_HPP_PAGE_4, 3452 *(u_short *)savebyte); 3453 3454 } 3455 3456 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3457 outw(sc->asic_addr + ED_HPP_OPTION, 3458 sc->hpp_options); 3459 3460 return (total_len); 3461} 3462 3463static void 3464ed_setrcr(sc) 3465 struct ed_softc *sc; 3466{ 3467 struct ifnet *ifp = (struct ifnet *)sc; 3468 int i; 3469 3470 /* set page 1 registers */ 3471 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3472 3473 if (ifp->if_flags & IFF_PROMISC) { 3474 3475 /* 3476 * Reconfigure the multicast filter. 3477 */ 3478 for (i = 0; i < 8; i++) 3479 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3480 3481 /* 3482 * And turn on promiscuous mode. Also enable reception of 3483 * runts and packets with CRC & alignment errors. 3484 */ 3485 /* Set page 0 registers */ 3486 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3487 3488 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3489 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3490 } else { 3491 /* set up multicast addresses and filter modes */ 3492 if (ifp->if_flags & IFF_MULTICAST) { 3493 u_long mcaf[2]; 3494 3495 if (ifp->if_flags & IFF_ALLMULTI) { 3496 mcaf[0] = 0xffffffff; 3497 mcaf[1] = 0xffffffff; 3498 } else 3499 ds_getmcaf(sc, mcaf); 3500 3501 /* 3502 * Set multicast filter on chip. 3503 */ 3504 for (i = 0; i < 8; i++) 3505 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3506 3507 /* Set page 0 registers */ 3508 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3509 3510 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3511 } else { 3512 3513 /* 3514 * Initialize multicast address hashing registers to 3515 * not accept multicasts. 3516 */ 3517 for (i = 0; i < 8; ++i) 3518 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3519 3520 /* Set page 0 registers */ 3521 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3522 3523 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3524 } 3525 } 3526 3527 /* 3528 * Start interface. 3529 */ 3530 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3531} 3532 3533/* 3534 * Compute crc for ethernet address 3535 */ 3536static u_long 3537ds_crc(ep) 3538 u_char *ep; 3539{ 3540#define POLYNOMIAL 0x04c11db6 3541 register u_long crc = 0xffffffffL; 3542 register int carry, i, j; 3543 register u_char b; 3544 3545 for (i = 6; --i >= 0;) { 3546 b = *ep++; 3547 for (j = 8; --j >= 0;) { 3548 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3549 crc <<= 1; 3550 b >>= 1; 3551 if (carry) 3552 crc = ((crc ^ POLYNOMIAL) | carry); 3553 } 3554 } 3555 return crc; 3556#undef POLYNOMIAL 3557} 3558 3559/* 3560 * Compute the multicast address filter from the 3561 * list of multicast addresses we need to listen to. 3562 */ 3563static void 3564ds_getmcaf(sc, mcaf) 3565 struct ed_softc *sc; 3566 u_long *mcaf; 3567{ 3568 register u_int index; 3569 register u_char *af = (u_char *) mcaf; 3570 struct ifmultiaddr *ifma; 3571 3572 mcaf[0] = 0; 3573 mcaf[1] = 0; 3574 3575 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3576 ifma = ifma->ifma_link.le_next) { 3577 if (ifma->ifma_addr->sa_family != AF_LINK) 3578 continue; 3579 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3580 >> 26; 3581 af[index >> 3] |= 1 << (index & 7); 3582 } 3583} 3584
|
3442/* 3443 * support PnP cards if we are using 'em 3444 */
| 3585static device_method_t ed_isa_methods[] = { 3586 /* Device interface */ 3587 DEVMETHOD(device_probe, ed_isa_probe), 3588 DEVMETHOD(device_attach, ed_isa_attach),
|
3445
| 3589
|
3446#if NPNP > 0 3447 3448static pnpid_t edpnp_ids[] = { 3449 { 0xd680d041, "NE2000"}, 3450 { 0 }
| 3590 { 0, 0 }
|
3451}; 3452
| 3591}; 3592
|
3453static char *edpnp_probe(u_long csn, u_long vend_id); 3454static void edpnp_attach(u_long csn, u_long vend_id, char *name, 3455 struct isa_device *dev); 3456static u_long nedpnp = NED; 3457 3458static struct pnp_device edpnp = { 3459 "edpnp", 3460 edpnp_probe, 3461 edpnp_attach, 3462 &nedpnp, 3463 &net_imask
| 3593static driver_t ed_isa_driver = { 3594 "ed", 3595 ed_isa_methods, 3596 sizeof(struct ed_softc)
|
3464};
| 3597};
|
3465DATA_SET (pnpdevice_set, edpnp);
| |
3466
| 3598
|
3467static char * 3468edpnp_probe(u_long csn, u_long vend_id) 3469{ 3470 pnpid_t *id; 3471 char *s = NULL;
| 3599static devclass_t ed_isa_devclass;
|
3472
| 3600
|
3473 for(id = edpnp_ids; id->vend_id != 0; id++) { 3474 if (vend_id == id->vend_id) { 3475 s = id->id_str; 3476 break; 3477 } 3478 } 3479 3480 if (s) { 3481 struct pnp_cinfo d; 3482 read_pnp_parms(&d, 0); 3483 if (d.enable == 0 || d.flags & 1) { 3484 printf("CSN %lu is disabled.\n", csn); 3485 return (NULL); 3486 } 3487 3488 } 3489 3490 return (s); 3491} 3492 3493static void 3494edpnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev) 3495{ 3496 struct pnp_cinfo d; 3497 3498 if (dev->id_unit >= NEDTOT) 3499 return; 3500 3501 if (read_pnp_parms(&d, 0) == 0) { 3502 printf("failed to read pnp parms\n"); 3503 return; 3504 } 3505 3506 write_pnp_parms(&d, 0); 3507 3508 enable_pnp_card(); 3509 3510 dev->id_iobase = d.port[0]; 3511 dev->id_irq = (1 << d.irq[0]); 3512 dev->id_ointr = edintr; 3513 dev->id_drq = -1; 3514 3515 if (dev->id_driver == NULL) { 3516 dev->id_driver = &eddriver; 3517 dev->id_id = isa_compat_nextid(); 3518 } 3519 3520 if ((dev->id_alive = ed_probe(dev)) != 0) 3521 ed_attach_isa(dev); 3522 else 3523 printf("ed%d: probe failed\n", dev->id_unit); 3524} 3525#endif
| 3601DRIVER_MODULE(ed, isa, ed_isa_driver, ed_isa_devclass, 0, 0);
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