1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
|
29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 141548 2005-02-08 23:57:43Z imp $");
| 29__FBSDID("$FreeBSD: head/sys/dev/ed/if_ed.c 141586 2005-02-09 20:03:40Z imp $");
|
30
31/*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41#include "opt_ed.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/syslog.h>
50
51#include <sys/bus.h>
52
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_mib.h>
62#include <net/if_media.h>
63
64#ifndef ED_NO_MIIBUS
65#include <dev/mii/mii.h>
66#include <dev/mii/miivar.h>
67#endif
68
69#include <net/bpf.h>
70
| 30
31/*
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
34 *
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
38 *
39 */
40
41#include "opt_ed.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/sockio.h>
46#include <sys/mbuf.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/syslog.h>
50
51#include <sys/bus.h>
52
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_arp.h>
60#include <net/if_dl.h>
61#include <net/if_mib.h>
62#include <net/if_media.h>
63
64#ifndef ED_NO_MIIBUS
65#include <dev/mii/mii.h>
66#include <dev/mii/miivar.h>
67#endif
68
69#include <net/bpf.h>
70
|
71#include <machine/md_var.h>
72
| |
73#include <dev/ed/if_edreg.h>
74#include <dev/ed/if_edvar.h>
75
76devclass_t ed_devclass;
77
78static void ed_init(void *);
79static int ed_ioctl(struct ifnet *, u_long, caddr_t);
80static void ed_start(struct ifnet *);
81static void ed_reset(struct ifnet *);
82static void ed_watchdog(struct ifnet *);
83#ifndef ED_NO_MIIBUS
84static void ed_tick(void *);
85#endif
86
87static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
88
89static void ed_get_packet(struct ed_softc *, char *, u_short);
90
91static __inline void ed_rint(struct ed_softc *);
92static __inline void ed_xmit(struct ed_softc *);
93static __inline char *ed_ring_copy(struct ed_softc *, char *, char *, u_short);
| 71#include <dev/ed/if_edreg.h>
72#include <dev/ed/if_edvar.h>
73
74devclass_t ed_devclass;
75
76static void ed_init(void *);
77static int ed_ioctl(struct ifnet *, u_long, caddr_t);
78static void ed_start(struct ifnet *);
79static void ed_reset(struct ifnet *);
80static void ed_watchdog(struct ifnet *);
81#ifndef ED_NO_MIIBUS
82static void ed_tick(void *);
83#endif
84
85static void ed_ds_getmcaf(struct ed_softc *, uint32_t *);
86
87static void ed_get_packet(struct ed_softc *, char *, u_short);
88
89static __inline void ed_rint(struct ed_softc *);
90static __inline void ed_xmit(struct ed_softc *);
91static __inline char *ed_ring_copy(struct ed_softc *, char *, char *, u_short);
|
94static void ed_hpp_set_physical_link(struct ed_softc *);
95static void ed_hpp_readmem(struct ed_softc *, long, uint8_t *, uint16_t);
96static void ed_hpp_writemem(struct ed_softc *, uint8_t *, uint16_t,
97 uint16_t);
98static u_short ed_hpp_write_mbufs(struct ed_softc *, struct mbuf *, int);
99
| |
100static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, long);
101
102static void ed_setrcr(struct ed_softc *);
103
104/*
| 92static u_short ed_pio_write_mbufs(struct ed_softc *, struct mbuf *, long);
93
94static void ed_setrcr(struct ed_softc *);
95
96/*
|
105 * Interrupt conversion table for WD/SMC ASIC/83C584
106 */
107static uint16_t ed_intr_val[] = {
108 9,
109 3,
110 5,
111 7,
112 10,
113 11,
114 15,
115 4
116};
117
118/*
119 * Interrupt conversion table for 83C790
120 */
121static uint16_t ed_790_intr_val[] = {
122 0,
123 9,
124 3,
125 5,
126 7,
127 10,
128 11,
129 15
130};
131
132/*
133 * Interrupt conversion table for the HP PC LAN+
134 */
135
136static uint16_t ed_hpp_intr_val[] = {
137 0, /* 0 */
138 0, /* 1 */
139 0, /* 2 */
140 3, /* 3 */
141 4, /* 4 */
142 5, /* 5 */
143 6, /* 6 */
144 7, /* 7 */
145 0, /* 8 */
146 9, /* 9 */
147 10, /* 10 */
148 11, /* 11 */
149 12, /* 12 */
150 0, /* 13 */
151 0, /* 14 */
152 15 /* 15 */
153};
154
155/*
| |
156 * Generic probe routine for testing for the existance of a DS8390.
157 * Must be called after the NIC has just been reset. This routine
158 * works by looking at certain register values that are guaranteed
159 * to be initialized a certain way after power-up or reset. Seems
160 * not to currently work on the 83C690.
161 *
162 * Specifically:
163 *
164 * Register reset bits set bits
165 * Command Register (CR) TXP, STA RD2, STP
166 * Interrupt Status (ISR) RST
167 * Interrupt Mask (IMR) All bits
168 * Data Control (DCR) LAS
169 * Transmit Config. (TCR) LB1, LB0
170 *
171 * We only look at the CR and ISR registers, however, because looking at
172 * the others would require changing register pages (which would be
173 * intrusive if this isn't an 8390).
174 *
175 * Return 1 if 8390 was found, 0 if not.
176 */
177
178int
179ed_probe_generic8390(struct ed_softc *sc)
180{
181 if ((ed_nic_inb(sc, ED_P0_CR) &
182 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
183 (ED_CR_RD2 | ED_CR_STP))
184 return (0);
185 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
186 return (0);
187
188 return (1);
189}
190
191/*
| 97 * Generic probe routine for testing for the existance of a DS8390.
98 * Must be called after the NIC has just been reset. This routine
99 * works by looking at certain register values that are guaranteed
100 * to be initialized a certain way after power-up or reset. Seems
101 * not to currently work on the 83C690.
102 *
103 * Specifically:
104 *
105 * Register reset bits set bits
106 * Command Register (CR) TXP, STA RD2, STP
107 * Interrupt Status (ISR) RST
108 * Interrupt Mask (IMR) All bits
109 * Data Control (DCR) LAS
110 * Transmit Config. (TCR) LB1, LB0
111 *
112 * We only look at the CR and ISR registers, however, because looking at
113 * the others would require changing register pages (which would be
114 * intrusive if this isn't an 8390).
115 *
116 * Return 1 if 8390 was found, 0 if not.
117 */
118
119int
120ed_probe_generic8390(struct ed_softc *sc)
121{
122 if ((ed_nic_inb(sc, ED_P0_CR) &
123 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
124 (ED_CR_RD2 | ED_CR_STP))
125 return (0);
126 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
127 return (0);
128
129 return (1);
130}
131
132/*
|
192 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
193 */
194int
195ed_probe_WD80x3_generic(device_t dev, int flags, uint16_t *intr_vals[])
196{
197 struct ed_softc *sc = device_get_softc(dev);
198 int error;
199 int i;
200 u_int memsize, maddr;
201 u_char iptr, isa16bit, sum, totalsum;
202 u_long conf_maddr, conf_msize, irq, junk;
203
204 sc->chip_type = ED_CHIP_TYPE_DP8390;
205
206 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
207 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
208 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
209 DELAY(10000);
210 }
211 else
212 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
213
214 /*
215 * Attempt to do a checksum over the station address PROM. If it
216 * fails, it's probably not a SMC/WD board. There is a problem with
217 * this, though: some clone WD boards don't pass the checksum test.
218 * Danpex boards for one.
219 */
220 for (sum = 0, i = 0; i < 8; ++i)
221 sum += ed_asic_inb(sc, ED_WD_PROM + i);
222
223 if (sum != totalsum) {
224
225 /*
226 * Checksum is invalid. This often happens with cheap WD8003E
227 * clones. In this case, the checksum byte (the eighth byte)
228 * seems to always be zero.
229 */
230 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
231 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
232 return (ENXIO);
233 }
234 /* reset card to force it into a known state. */
235 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
236 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
237 else
238 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
239
240 DELAY(100);
241 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
242 /* wait in the case this card is reading its EEROM */
243 DELAY(5000);
244
245 sc->vendor = ED_VENDOR_WD_SMC;
246 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
247
248 /*
249 * Set initial values for width/size.
250 */
251 memsize = 8192;
252 isa16bit = 0;
253 switch (sc->type) {
254 case ED_TYPE_WD8003S:
255 sc->type_str = "WD8003S";
256 break;
257 case ED_TYPE_WD8003E:
258 sc->type_str = "WD8003E";
259 break;
260 case ED_TYPE_WD8003EB:
261 sc->type_str = "WD8003EB";
262 break;
263 case ED_TYPE_WD8003W:
264 sc->type_str = "WD8003W";
265 break;
266 case ED_TYPE_WD8013EBT:
267 sc->type_str = "WD8013EBT";
268 memsize = 16384;
269 isa16bit = 1;
270 break;
271 case ED_TYPE_WD8013W:
272 sc->type_str = "WD8013W";
273 memsize = 16384;
274 isa16bit = 1;
275 break;
276 case ED_TYPE_WD8013EP: /* also WD8003EP */
277 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
278 isa16bit = 1;
279 memsize = 16384;
280 sc->type_str = "WD8013EP";
281 } else {
282 sc->type_str = "WD8003EP";
283 }
284 break;
285 case ED_TYPE_WD8013WC:
286 sc->type_str = "WD8013WC";
287 memsize = 16384;
288 isa16bit = 1;
289 break;
290 case ED_TYPE_WD8013EBP:
291 sc->type_str = "WD8013EBP";
292 memsize = 16384;
293 isa16bit = 1;
294 break;
295 case ED_TYPE_WD8013EPC:
296 sc->type_str = "WD8013EPC";
297 memsize = 16384;
298 isa16bit = 1;
299 break;
300 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
301 case ED_TYPE_SMC8216T:
302 if (sc->type == ED_TYPE_SMC8216C) {
303 sc->type_str = "SMC8216/SMC8216C";
304 } else {
305 sc->type_str = "SMC8216T";
306 }
307
308 ed_asic_outb(sc, ED_WD790_HWR,
309 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
310 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
311 case ED_WD790_RAR_SZ64:
312 memsize = 65536;
313 break;
314 case ED_WD790_RAR_SZ32:
315 memsize = 32768;
316 break;
317 case ED_WD790_RAR_SZ16:
318 memsize = 16384;
319 break;
320 case ED_WD790_RAR_SZ8:
321 /* 8216 has 16K shared mem -- 8416 has 8K */
322 if (sc->type == ED_TYPE_SMC8216C) {
323 sc->type_str = "SMC8416C/SMC8416BT";
324 } else {
325 sc->type_str = "SMC8416T";
326 }
327 memsize = 8192;
328 break;
329 }
330 ed_asic_outb(sc, ED_WD790_HWR,
331 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
332
333 isa16bit = 1;
334 sc->chip_type = ED_CHIP_TYPE_WD790;
335 break;
336 case ED_TYPE_TOSHIBA1:
337 sc->type_str = "Toshiba1";
338 memsize = 32768;
339 isa16bit = 1;
340 break;
341 case ED_TYPE_TOSHIBA4:
342 sc->type_str = "Toshiba4";
343 memsize = 32768;
344 isa16bit = 1;
345 break;
346 default:
347 sc->type_str = "";
348 break;
349 }
350
351 /*
352 * Make some adjustments to initial values depending on what is found
353 * in the ICR.
354 */
355 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
356 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
357 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
358 isa16bit = 0;
359 memsize = 8192;
360 }
361
362 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
363 &conf_maddr, &conf_msize);
364 if (error)
365 return (error);
366
367#ifdef ED_DEBUG
368 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%lu\n",
369 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
370 for (i = 0; i < 8; i++)
371 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
372#endif
373
374 /*
375 * Allow the user to override the autoconfiguration
376 */
377 if (conf_msize > 1)
378 memsize = conf_msize;
379
380 maddr = conf_maddr;
381 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
382 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
383 maddr, maddr + memsize);
384 return (ENXIO);
385 }
386
387 /*
388 * (note that if the user specifies both of the following flags that
389 * '8bit' mode intentionally has precedence)
390 */
391 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
392 isa16bit = 1;
393 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
394 isa16bit = 0;
395
396 /*
397 * If possible, get the assigned interrupt number from the card and
398 * use it.
399 */
400 if ((sc->type & ED_WD_SOFTCONFIG) &&
401 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
402
403 /*
404 * Assemble together the encoded interrupt number.
405 */
406 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
407 ((ed_asic_inb(sc, ED_WD_IRR) &
408 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
409
410 /*
411 * If no interrupt specified (or "?"), use what the board tells us.
412 */
413 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
414 &irq, &junk);
415 if (error && intr_vals[0] != NULL) {
416 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
417 intr_vals[0][iptr], 1);
418 }
419 if (error)
420 return (error);
421
422 /*
423 * Enable the interrupt.
424 */
425 ed_asic_outb(sc, ED_WD_IRR,
426 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
427 }
428 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
429 ed_asic_outb(sc, ED_WD790_HWR,
430 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
431 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
432 (ed_asic_inb(sc, ED_WD790_GCR) &
433 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
434 ed_asic_outb(sc, ED_WD790_HWR,
435 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
436
437 /*
438 * If no interrupt specified (or "?"), use what the board tells us.
439 */
440 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
441 &irq, &junk);
442 if (error && intr_vals[1] != NULL) {
443 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
444 intr_vals[1][iptr], 1);
445 }
446 if (error)
447 return (error);
448
449 /*
450 * Enable interrupts.
451 */
452 ed_asic_outb(sc, ED_WD790_ICR,
453 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
454 }
455 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
456 &irq, &junk);
457 if (error) {
458 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
459 sc->type_str);
460 return (ENXIO);
461 }
462 sc->isa16bit = isa16bit;
463 sc->mem_shared = 1;
464
465 error = ed_alloc_memory(dev, 0, memsize);
466 if (error) {
467 printf("*** ed_alloc_memory() failed! (%d)\n", error);
468 return (error);
469 }
470 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
471
472 /*
473 * allocate one xmit buffer if < 16k, two buffers otherwise
474 */
475 if ((memsize < 16384) ||
476 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
477 sc->txb_cnt = 1;
478 } else {
479 sc->txb_cnt = 2;
480 }
481 sc->tx_page_start = ED_WD_PAGE_OFFSET;
482 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
483 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
484 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
485 sc->mem_size = memsize;
486 sc->mem_end = sc->mem_start + memsize;
487
488 /*
489 * Get station address from on-board ROM
490 */
491 for (i = 0; i < ETHER_ADDR_LEN; ++i)
492 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
493
494 /*
495 * Set upper address bits and 8/16 bit access to shared memory.
496 */
497 if (isa16bit) {
498 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
499 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
500 } else {
501 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
502 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
503 }
504 /*
505 * Enable 16bit access
506 */
507 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
508 ED_WD_LAAR_M16EN);
509 } else {
510 if (((sc->type & ED_WD_SOFTCONFIG) ||
511 (sc->type == ED_TYPE_TOSHIBA1) ||
512 (sc->type == ED_TYPE_TOSHIBA4) ||
513 (sc->type == ED_TYPE_WD8013EBT)) &&
514 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
515 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
516 ED_WD_LAAR_ADDRHI;
517 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
518 }
519 }
520
521 /*
522 * Set address and enable interface shared memory.
523 */
524 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
525 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
526 ed_asic_outb(sc, ED_WD_MSR + 1,
527 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
528 ed_asic_outb(sc, ED_WD_MSR + 2,
529 ((kvtop(sc->mem_start) >> 16) & 0x0f));
530 ed_asic_outb(sc, ED_WD_MSR,
531 ED_WD_MSR_MENB | ED_WD_MSR_POW);
532 } else {
533 ed_asic_outb(sc, ED_WD_MSR,
534 ((kvtop(sc->mem_start) >> 13) &
535 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
536 }
537 sc->cr_proto = ED_CR_RD2;
538 } else {
539 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
540 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
541 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
542 ((kvtop(sc->mem_start) >> 11) & 0x40) |
543 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
544 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
545 sc->cr_proto = 0;
546 }
547
548#if 0
549 printf("starting memory performance test at 0x%x, size %d...\n",
550 sc->mem_start, memsize*16384);
551 for (i = 0; i < 16384; i++)
552 bzero(sc->mem_start, memsize);
553 printf("***DONE***\n");
554#endif
555
556 /*
557 * Now zero memory and verify that it is clear
558 */
559 bzero(sc->mem_start, memsize);
560
561 for (i = 0; i < memsize; ++i) {
562 if (sc->mem_start[i]) {
563 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
564 (uintmax_t)kvtop(sc->mem_start + i));
565
566 /*
567 * Disable 16 bit access to shared memory
568 */
569 if (isa16bit) {
570 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
571 ed_asic_outb(sc, ED_WD_MSR, 0x00);
572 }
573 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
574 ~ED_WD_LAAR_M16EN);
575 }
576 return (ENXIO);
577 }
578 }
579
580 /*
581 * Disable 16bit access to shared memory - we leave it
582 * disabled so that 1) machines reboot properly when the board
583 * is set 16 bit mode and there are conflicting 8bit
584 * devices/ROMS in the same 128k address space as this boards
585 * shared memory. and 2) so that other 8 bit devices with
586 * shared memory can be used in this 128k region, too.
587 */
588 if (isa16bit) {
589 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
590 ed_asic_outb(sc, ED_WD_MSR, 0x00);
591 }
592 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
593 ~ED_WD_LAAR_M16EN);
594 }
595 return (0);
596}
597
598int
599ed_probe_WD80x3(device_t dev, int port_rid, int flags)
600{
601 struct ed_softc *sc = device_get_softc(dev);
602 int error;
603 static uint16_t *intr_vals[] = {ed_intr_val, ed_790_intr_val};
604
605 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
606 if (error)
607 return (error);
608
609 sc->asic_offset = ED_WD_ASIC_OFFSET;
610 sc->nic_offset = ED_WD_NIC_OFFSET;
611
612 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
613}
614
615/*
616 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
617 */
618int
619ed_probe_3Com(device_t dev, int port_rid, int flags)
620{
621 struct ed_softc *sc = device_get_softc(dev);
622 int error;
623 int i;
624 u_int memsize;
625 u_char isa16bit;
626 u_long conf_maddr, conf_msize, irq, junk;
627
628 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
629 if (error)
630 return (error);
631
632 sc->asic_offset = ED_3COM_ASIC_OFFSET;
633 sc->nic_offset = ED_3COM_NIC_OFFSET;
634
635 /*
636 * Verify that the kernel configured I/O address matches the board
637 * configured address
638 */
639 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
640 case ED_3COM_BCFR_300:
641 if (rman_get_start(sc->port_res) != 0x300)
642 return (ENXIO);
643 break;
644 case ED_3COM_BCFR_310:
645 if (rman_get_start(sc->port_res) != 0x310)
646 return (ENXIO);
647 break;
648 case ED_3COM_BCFR_330:
649 if (rman_get_start(sc->port_res) != 0x330)
650 return (ENXIO);
651 break;
652 case ED_3COM_BCFR_350:
653 if (rman_get_start(sc->port_res) != 0x350)
654 return (ENXIO);
655 break;
656 case ED_3COM_BCFR_250:
657 if (rman_get_start(sc->port_res) != 0x250)
658 return (ENXIO);
659 break;
660 case ED_3COM_BCFR_280:
661 if (rman_get_start(sc->port_res) != 0x280)
662 return (ENXIO);
663 break;
664 case ED_3COM_BCFR_2A0:
665 if (rman_get_start(sc->port_res) != 0x2a0)
666 return (ENXIO);
667 break;
668 case ED_3COM_BCFR_2E0:
669 if (rman_get_start(sc->port_res) != 0x2e0)
670 return (ENXIO);
671 break;
672 default:
673 return (ENXIO);
674 }
675
676 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
677 &conf_maddr, &conf_msize);
678 if (error)
679 return (error);
680
681 /*
682 * Verify that the kernel shared memory address matches the board
683 * configured address.
684 */
685 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
686 case ED_3COM_PCFR_DC000:
687 if (conf_maddr != 0xdc000)
688 return (ENXIO);
689 break;
690 case ED_3COM_PCFR_D8000:
691 if (conf_maddr != 0xd8000)
692 return (ENXIO);
693 break;
694 case ED_3COM_PCFR_CC000:
695 if (conf_maddr != 0xcc000)
696 return (ENXIO);
697 break;
698 case ED_3COM_PCFR_C8000:
699 if (conf_maddr != 0xc8000)
700 return (ENXIO);
701 break;
702 default:
703 return (ENXIO);
704 }
705
706
707 /*
708 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
709 * sequence because it'll lock up if the cable isn't connected if we
710 * don't.
711 */
712 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
713
714 /*
715 * Wait for a while, then un-reset it
716 */
717 DELAY(50);
718
719 /*
720 * The 3Com ASIC defaults to rather strange settings for the CR after
721 * a reset - it's important to set it again after the following outb
722 * (this is done when we map the PROM below).
723 */
724 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
725
726 /*
727 * Wait a bit for the NIC to recover from the reset
728 */
729 DELAY(5000);
730
731 sc->vendor = ED_VENDOR_3COM;
732 sc->type_str = "3c503";
733 sc->mem_shared = 1;
734 sc->cr_proto = ED_CR_RD2;
735
736 /*
737 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
738 * to it.
739 */
740 memsize = 8192;
741
742 /*
743 * Get station address from on-board ROM
744 */
745
746 /*
747 * First, map ethernet address PROM over the top of where the NIC
748 * registers normally appear.
749 */
750 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
751
752 for (i = 0; i < ETHER_ADDR_LEN; ++i)
753 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
754
755 /*
756 * Unmap PROM - select NIC registers. The proper setting of the
757 * tranceiver is set in ed_init so that the attach code is given a
758 * chance to set the default based on a compile-time config option
759 */
760 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
761
762 /*
763 * Determine if this is an 8bit or 16bit board
764 */
765
766 /*
767 * select page 0 registers
768 */
769 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
770
771 /*
772 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
773 * board.
774 */
775 ed_nic_outb(sc, ED_P0_DCR, 0);
776
777 /*
778 * select page 2 registers
779 */
780 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
781
782 /*
783 * The 3c503 forces the WTS bit to a one if this is a 16bit board
784 */
785 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
786 isa16bit = 1;
787 else
788 isa16bit = 0;
789
790 /*
791 * select page 0 registers
792 */
793 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
794
795 error = ed_alloc_memory(dev, 0, memsize);
796 if (error)
797 return (error);
798
799 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
800 sc->mem_size = memsize;
801 sc->mem_end = sc->mem_start + memsize;
802
803 /*
804 * We have an entire 8k window to put the transmit buffers on the
805 * 16bit boards. But since the 16bit 3c503's shared memory is only
806 * fast enough to overlap the loading of one full-size packet, trying
807 * to load more than 2 buffers can actually leave the transmitter idle
808 * during the load. So 2 seems the best value. (Although a mix of
809 * variable-sized packets might change this assumption. Nonetheless,
810 * we optimize for linear transfers of same-size packets.)
811 */
812 if (isa16bit) {
813 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
814 sc->txb_cnt = 1;
815 else
816 sc->txb_cnt = 2;
817
818 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
819 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
820 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
821 ED_3COM_RX_PAGE_OFFSET_16BIT;
822 sc->mem_ring = sc->mem_start;
823 } else {
824 sc->txb_cnt = 1;
825 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
826 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
827 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
828 ED_3COM_TX_PAGE_OFFSET_8BIT;
829 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
830 }
831
832 sc->isa16bit = isa16bit;
833
834 /*
835 * Initialize GA page start/stop registers. Probably only needed if
836 * doing DMA, but what the hell.
837 */
838 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
839 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
840
841 /*
842 * Set IRQ. 3c503 only allows a choice of irq 2-5.
843 */
844 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
845 if (error)
846 return (error);
847
848 switch (irq) {
849 case 2:
850 case 9:
851 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
852 break;
853 case 3:
854 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
855 break;
856 case 4:
857 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
858 break;
859 case 5:
860 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
861 break;
862 default:
863 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
864 irq);
865 return (ENXIO);
866 }
867
868 /*
869 * Initialize GA configuration register. Set bank and enable shared
870 * mem.
871 */
872 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
873 ED_3COM_GACFR_MBS0);
874
875 /*
876 * Initialize "Vector Pointer" registers. These gawd-awful things are
877 * compared to 20 bits of the address on ISA, and if they match, the
878 * shared memory is disabled. We set them to 0xffff0...allegedly the
879 * reset vector.
880 */
881 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
882 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
883 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
884
885 /*
886 * Zero memory and verify that it is clear
887 */
888 bzero(sc->mem_start, memsize);
889
890 for (i = 0; i < memsize; ++i)
891 if (sc->mem_start[i]) {
892 device_printf(dev, "failed to clear shared memory at %jx - check configuration\n",
893 (uintmax_t)kvtop(sc->mem_start + i));
894 return (ENXIO);
895 }
896 return (0);
897}
898
899/*
900 * Probe and vendor-specific initialization routine for SIC boards
901 */
902int
903ed_probe_SIC(device_t dev, int port_rid, int flags)
904{
905 struct ed_softc *sc = device_get_softc(dev);
906 int error;
907 int i;
908 u_int memsize;
909 u_long conf_maddr, conf_msize;
910 u_char sum;
911
912 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
913 if (error)
914 return (error);
915
916 sc->asic_offset = ED_SIC_ASIC_OFFSET;
917 sc->nic_offset = ED_SIC_NIC_OFFSET;
918
919 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
920 &conf_maddr, &conf_msize);
921 if (error)
922 return (error);
923
924 memsize = 16384;
925 if (conf_msize > 1)
926 memsize = conf_msize;
927
928 error = ed_alloc_memory(dev, 0, memsize);
929 if (error)
930 return (error);
931
932 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
933 sc->mem_size = memsize;
934
935 /* Reset card to force it into a known state. */
936 ed_asic_outb(sc, 0, 0x00);
937 DELAY(100);
938
939 /*
940 * Here we check the card ROM, if the checksum passes, and the
941 * type code and ethernet address check out, then we know we have
942 * an SIC card.
943 */
944 ed_asic_outb(sc, 0, 0x81);
945 DELAY(100);
946
947 sum = sc->mem_start[6];
948 for (i = 0; i < ETHER_ADDR_LEN; i++) {
949 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
950 }
951#ifdef ED_DEBUG
952 device_printf(dev, "ed_probe_sic: got address %6D\n",
953 sc->arpcom.ac_enaddr, ":");
954#endif
955 if (sum != 0) {
956 return (ENXIO);
957 }
958 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
959 sc->arpcom.ac_enaddr[2]) == 0) {
960 return (ENXIO);
961 }
962
963 sc->vendor = ED_VENDOR_SIC;
964 sc->type_str = "SIC";
965 sc->isa16bit = 0;
966 sc->cr_proto = 0;
967
968 /*
969 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
970 */
971 ed_asic_outb(sc, 0, 0x80);
972 DELAY(100);
973
974 /*
975 * Now zero memory and verify that it is clear
976 */
977 bzero(sc->mem_start, sc->mem_size);
978
979 for (i = 0; i < sc->mem_size; i++) {
980 if (sc->mem_start[i]) {
981 device_printf(dev, "failed to clear shared memory "
982 "at %jx - check configuration\n",
983 (uintmax_t)kvtop(sc->mem_start + i));
984
985 return (ENXIO);
986 }
987 }
988
989 sc->mem_shared = 1;
990 sc->mem_end = sc->mem_start + sc->mem_size;
991
992 /*
993 * allocate one xmit buffer if < 16k, two buffers otherwise
994 */
995 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
996 sc->txb_cnt = 1;
997 } else {
998 sc->txb_cnt = 2;
999 }
1000 sc->tx_page_start = 0;
1001
1002 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1003 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1004
1005 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1006
1007 return (0);
1008}
1009
1010/*
1011 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1012 */
1013int
1014ed_probe_Novell_generic(device_t dev, int flags)
1015{
1016 struct ed_softc *sc = device_get_softc(dev);
1017 u_int memsize, n;
1018 u_char romdata[16], tmp;
1019 static char test_pattern[32] = "THIS is A memory TEST pattern";
1020 char test_buffer[32];
1021
1022 /* XXX - do Novell-specific probe here */
1023
1024 /* Reset the board */
1025 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1026 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1027 DELAY(200);
1028 }
1029 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1030
1031 /*
1032 * I don't know if this is necessary; probably cruft leftover from
1033 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1034 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1035 * non-invasive...but some boards don't seem to reset and I don't have
1036 * complete documentation on what the 'right' thing to do is...so we
1037 * do the invasive thing for now. Yuck.]
1038 */
1039 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1040 DELAY(5000);
1041
1042 /*
1043 * This is needed because some NE clones apparently don't reset the
1044 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1045 * - this makes the probe invasive! ...Done against my better
1046 * judgement. -DLG
1047 */
1048 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1049
1050 DELAY(5000);
1051
1052 /* Make sure that we really have an 8390 based board */
1053 if (!ed_probe_generic8390(sc))
1054 return (ENXIO);
1055
1056 sc->vendor = ED_VENDOR_NOVELL;
1057 sc->mem_shared = 0;
1058 sc->cr_proto = ED_CR_RD2;
1059
1060 /*
1061 * Test the ability to read and write to the NIC memory. This has the
1062 * side affect of determining if this is an NE1000 or an NE2000.
1063 */
1064
1065 /*
1066 * This prevents packets from being stored in the NIC memory when the
1067 * readmem routine turns on the start bit in the CR.
1068 */
1069 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1070
1071 /* Temporarily initialize DCR for byte operations */
1072 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1073
1074 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1075 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1076
1077 sc->isa16bit = 0;
1078
1079 /*
1080 * Write a test pattern in byte mode. If this fails, then there
1081 * probably isn't any memory at 8k - which likely means that the board
1082 * is an NE2000.
1083 */
1084 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1085 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1086
1087 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1088 sc->type = ED_TYPE_NE1000;
1089 sc->type_str = "NE1000";
1090 } else {
1091
1092 /* neither an NE1000 nor a Linksys - try NE2000 */
1093 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1094 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1095 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1096
1097 sc->isa16bit = 1;
1098
1099 /*
1100 * Write a test pattern in word mode. If this also fails, then
1101 * we don't know what this board is.
1102 */
1103 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1104 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1105 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1106 sc->type = ED_TYPE_NE2000;
1107 sc->type_str = "NE2000";
1108 } else {
1109 return (ENXIO);
1110 }
1111 }
1112
1113
1114 /* 8k of memory plus an additional 8k if 16bit */
1115 memsize = 8192 + sc->isa16bit * 8192;
1116
1117#if 0 /* probably not useful - NE boards only come two ways */
1118 /* allow kernel config file overrides */
1119 if (isa_dev->id_msize)
1120 memsize = isa_dev->id_msize;
1121#endif
1122
1123 sc->mem_size = memsize;
1124
1125 /* NIC memory doesn't start at zero on an NE board */
1126 /* The start address is tied to the bus width */
1127 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1128 sc->mem_end = sc->mem_start + memsize;
1129 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1130
1131 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1132 int x, i, msize = 0;
1133 long mstart = 0;
1134 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1135
1136 for (i = 0; i < ED_PAGE_SIZE; i++)
1137 pbuf0[i] = 0;
1138
1139 /* Clear all the memory. */
1140 for (x = 1; x < 256; x++)
1141 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1142
1143 /* Search for the start of RAM. */
1144 for (x = 1; x < 256; x++) {
1145 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1146 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1147 for (i = 0; i < ED_PAGE_SIZE; i++)
1148 pbuf[i] = 255 - x;
1149 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1150 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1151 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1152 mstart = x * ED_PAGE_SIZE;
1153 msize = ED_PAGE_SIZE;
1154 break;
1155 }
1156 }
1157 }
1158
1159 if (mstart == 0) {
1160 device_printf(dev, "Cannot find start of RAM.\n");
1161 return (ENXIO);
1162 }
1163 /* Search for the start of RAM. */
1164 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1165 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1166 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1167 for (i = 0; i < ED_PAGE_SIZE; i++)
1168 pbuf[i] = 255 - x;
1169 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1170 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1171 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1172 msize += ED_PAGE_SIZE;
1173 else {
1174 break;
1175 }
1176 } else {
1177 break;
1178 }
1179 }
1180
1181 if (msize == 0) {
1182 device_printf(dev, "Cannot find any RAM, start : %ld, x = %d.\n", mstart, x);
1183 return (ENXIO);
1184 }
1185 device_printf(dev, "RAM start at %ld, size : %d.\n", mstart, msize);
1186
1187 sc->mem_size = msize;
1188 sc->mem_start = (caddr_t)(uintptr_t) mstart;
1189 sc->mem_end = (caddr_t)(uintptr_t) (msize + mstart);
1190 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1191 }
1192
1193 /*
1194 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1195 * otherwise).
1196 */
1197 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1198 sc->txb_cnt = 1;
1199 else
1200 sc->txb_cnt = 2;
1201
1202 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1203 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1204
1205 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1206
1207 ed_pio_readmem(sc, 0, romdata, 16);
1208 for (n = 0; n < ETHER_ADDR_LEN; n++)
1209 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1210
1211 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1212 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1213 sc->type_str = "Gateway AT";
1214 }
1215
1216 /* clear any pending interrupts that might have occurred above */
1217 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1218
1219 return (0);
1220}
1221
1222int
1223ed_probe_Novell(device_t dev, int port_rid, int flags)
1224{
1225 struct ed_softc *sc = device_get_softc(dev);
1226 int error;
1227
1228 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1229 if (error)
1230 return (error);
1231
1232 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1233 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1234
1235 return ed_probe_Novell_generic(dev, flags);
1236}
1237
1238#define ED_HPP_TEST_SIZE 16
1239
1240/*
1241 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1242 * (HP Part nos: 27247B and 27252A).
1243 *
1244 * The card has an asic wrapper around a DS8390 core. The asic handles
1245 * host accesses and offers both standard register IO and memory mapped
1246 * IO. Memory mapped I/O allows better performance at the expense of greater
1247 * chance of an incompatibility with existing ISA cards.
1248 *
1249 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1250 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1251 * don't allow 32 bit accesses; these are indicated by a bit in the software
1252 * ID register (see if_edreg.h).
1253 *
1254 * Other caveats are: we should read the MAC address only when the card
1255 * is inactive.
1256 *
1257 * For more information; please consult the CRYNWR packet driver.
1258 *
1259 * The AUI port is turned on using the "link2" option on the ifconfig
1260 * command line.
1261 */
1262int
1263ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
1264{
1265 struct ed_softc *sc = device_get_softc(dev);
1266 int error;
1267 int n; /* temp var */
1268 int memsize; /* mem on board */
1269 u_char checksum; /* checksum of board address */
1270 u_char irq; /* board configured IRQ */
1271 uint8_t test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1272 uint8_t test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1273 u_long conf_maddr, conf_msize, conf_irq, junk;
1274
1275 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1276 if (error)
1277 return (error);
1278
1279 /* Fill in basic information */
1280 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1281 sc->nic_offset = ED_HPP_NIC_OFFSET;
1282
1283 sc->chip_type = ED_CHIP_TYPE_DP8390;
1284 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1285
1286 /*
1287 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1288 */
1289
1290 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1291 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1292 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1293 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1294 return ENXIO;
1295
1296 /*
1297 * Read the MAC address and verify checksum on the address.
1298 */
1299
1300 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1301 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1302 checksum += (sc->arpcom.ac_enaddr[n] =
1303 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1304
1305 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1306
1307 if (checksum != 0xFF)
1308 return ENXIO;
1309
1310 /*
1311 * Verify that the software model number is 0.
1312 */
1313
1314 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1315 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1316 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1317 return ENXIO;
1318
1319 /*
1320 * Read in and save the current options configured on card.
1321 */
1322
1323 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1324
1325 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1326 ED_HPP_OPTION_CHIP_RESET |
1327 ED_HPP_OPTION_ENABLE_IRQ);
1328
1329 /*
1330 * Reset the chip. This requires writing to the option register
1331 * so take care to preserve the other bits.
1332 */
1333
1334 ed_asic_outw(sc, ED_HPP_OPTION,
1335 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1336 ED_HPP_OPTION_CHIP_RESET)));
1337
1338 DELAY(5000); /* wait for chip reset to complete */
1339
1340 ed_asic_outw(sc, ED_HPP_OPTION,
1341 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1342 ED_HPP_OPTION_CHIP_RESET |
1343 ED_HPP_OPTION_ENABLE_IRQ)));
1344
1345 DELAY(5000);
1346
1347 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1348 return ENXIO; /* reset did not complete */
1349
1350 /*
1351 * Read out configuration information.
1352 */
1353
1354 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1355
1356 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1357
1358 /*
1359 * Check for impossible IRQ.
1360 */
1361
1362 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1363 return ENXIO;
1364
1365 /*
1366 * If the kernel IRQ was specified with a '?' use the cards idea
1367 * of the IRQ. If the kernel IRQ was explicitly specified, it
1368 * should match that of the hardware.
1369 */
1370 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1371 &conf_irq, &junk);
1372 if (error) {
1373 bus_set_resource(dev, SYS_RES_IRQ, 0,
1374 ed_hpp_intr_val[irq], 1);
1375 } else {
1376 if (conf_irq != ed_hpp_intr_val[irq])
1377 return (ENXIO);
1378 }
1379
1380 /*
1381 * Fill in softconfig info.
1382 */
1383
1384 sc->vendor = ED_VENDOR_HP;
1385 sc->type = ED_TYPE_HP_PCLANPLUS;
1386 sc->type_str = "HP-PCLAN+";
1387
1388 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1389 sc->mem_start = 0; /* we use offsets inside the card RAM */
1390
1391 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1392
1393 /*
1394 * The board has 32KB of memory. Is there a way to determine
1395 * this programmatically?
1396 */
1397
1398 memsize = 32768;
1399
1400 /*
1401 * Check if memory mapping of the I/O registers possible.
1402 */
1403
1404 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1405 {
1406 u_long mem_addr;
1407
1408 /*
1409 * determine the memory address from the board.
1410 */
1411
1412 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1413 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1414
1415 /*
1416 * Check that the kernel specified start of memory and
1417 * hardware's idea of it match.
1418 */
1419 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1420 &conf_maddr, &conf_msize);
1421 if (error)
1422 return (error);
1423
1424 if (mem_addr != conf_maddr)
1425 return ENXIO;
1426
1427 error = ed_alloc_memory(dev, 0, memsize);
1428 if (error)
1429 return (error);
1430
1431 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1432 }
1433
1434 /*
1435 * Fill in the rest of the soft config structure.
1436 */
1437
1438 /*
1439 * The transmit page index.
1440 */
1441
1442 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1443
1444 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1445 sc->txb_cnt = 1;
1446 else
1447 sc->txb_cnt = 2;
1448
1449 /*
1450 * Memory description
1451 */
1452
1453 sc->mem_size = memsize;
1454 sc->mem_ring = sc->mem_start +
1455 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1456 sc->mem_end = sc->mem_start + sc->mem_size;
1457
1458 /*
1459 * Receive area starts after the transmit area and
1460 * continues till the end of memory.
1461 */
1462
1463 sc->rec_page_start = sc->tx_page_start +
1464 (sc->txb_cnt * ED_TXBUF_SIZE);
1465 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1466
1467
1468 sc->cr_proto = 0; /* value works */
1469
1470 /*
1471 * Set the wrap registers for string I/O reads.
1472 */
1473
1474 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1475 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1476 ((sc->rec_page_start / ED_PAGE_SIZE) |
1477 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1478
1479 /*
1480 * Reset the register page to normal operation.
1481 */
1482
1483 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1484
1485 /*
1486 * Verify that we can read/write from adapter memory.
1487 * Create test pattern.
1488 */
1489
1490 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1491 {
1492 test_pattern[n] = (n*n) ^ ~n;
1493 }
1494
1495#undef ED_HPP_TEST_SIZE
1496
1497 /*
1498 * Check that the memory is accessible thru the I/O ports.
1499 * Write out the contents of "test_pattern", read back
1500 * into "test_buffer" and compare the two for any
1501 * mismatch.
1502 */
1503
1504 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1505
1506 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1507 sizeof(test_pattern));
1508 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1509 test_buffer, sizeof(test_pattern));
1510
1511 if (bcmp(test_pattern, test_buffer,
1512 sizeof(test_pattern)))
1513 return ENXIO;
1514 }
1515
1516 return (0);
1517
1518}
1519
1520/*
1521 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1522 */
1523
1524static void
1525ed_hpp_set_physical_link(struct ed_softc *sc)
1526{
1527 struct ifnet *ifp = &sc->arpcom.ac_if;
1528 int lan_page;
1529
1530 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1531 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1532
1533 if (ifp->if_flags & IFF_ALTPHYS) {
1534
1535 /*
1536 * Use the AUI port.
1537 */
1538
1539 lan_page |= ED_HPP_LAN_AUI;
1540
1541 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1542 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1543
1544
1545 } else {
1546
1547 /*
1548 * Use the ThinLan interface
1549 */
1550
1551 lan_page &= ~ED_HPP_LAN_AUI;
1552
1553 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1554 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1555
1556 }
1557
1558 /*
1559 * Wait for the lan card to re-initialize itself
1560 */
1561
1562 DELAY(150000); /* wait 150 ms */
1563
1564 /*
1565 * Restore normal pages.
1566 */
1567
1568 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1569
1570}
1571
1572/*
| |
1573 * Allocate a port resource with the given resource id.
1574 */
1575int
1576ed_alloc_port(device_t dev, int rid, int size)
1577{
1578 struct ed_softc *sc = device_get_softc(dev);
1579 struct resource *res;
1580
1581 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
| 133 * Allocate a port resource with the given resource id.
134 */
135int
136ed_alloc_port(device_t dev, int rid, int size)
137{
138 struct ed_softc *sc = device_get_softc(dev);
139 struct resource *res;
140
141 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
|
1582 0ul, ~0ul, size, RF_ACTIVE);
| 142 0ul, ~0ul, size, RF_ACTIVE);
|
1583 if (res) {
1584 sc->port_rid = rid;
1585 sc->port_res = res;
1586 sc->port_used = size;
1587 return (0);
1588 } else {
1589 return (ENOENT);
1590 }
1591}
1592
1593/*
1594 * Allocate a memory resource with the given resource id.
1595 */
1596int
1597ed_alloc_memory(device_t dev, int rid, int size)
1598{
1599 struct ed_softc *sc = device_get_softc(dev);
1600 struct resource *res;
1601
1602 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
| 143 if (res) {
144 sc->port_rid = rid;
145 sc->port_res = res;
146 sc->port_used = size;
147 return (0);
148 } else {
149 return (ENOENT);
150 }
151}
152
153/*
154 * Allocate a memory resource with the given resource id.
155 */
156int
157ed_alloc_memory(device_t dev, int rid, int size)
158{
159 struct ed_softc *sc = device_get_softc(dev);
160 struct resource *res;
161
162 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
1603 0ul, ~0ul, size, RF_ACTIVE);
| 163 0ul, ~0ul, size, RF_ACTIVE);
|
1604 if (res) {
1605 sc->mem_rid = rid;
1606 sc->mem_res = res;
1607 sc->mem_used = size;
1608 return (0);
1609 } else {
1610 return (ENOENT);
1611 }
1612}
1613
1614/*
1615 * Allocate an irq resource with the given resource id.
1616 */
1617int
1618ed_alloc_irq(device_t dev, int rid, int flags)
1619{
1620 struct ed_softc *sc = device_get_softc(dev);
1621 struct resource *res;
1622
| 164 if (res) {
165 sc->mem_rid = rid;
166 sc->mem_res = res;
167 sc->mem_used = size;
168 return (0);
169 } else {
170 return (ENOENT);
171 }
172}
173
174/*
175 * Allocate an irq resource with the given resource id.
176 */
177int
178ed_alloc_irq(device_t dev, int rid, int flags)
179{
180 struct ed_softc *sc = device_get_softc(dev);
181 struct resource *res;
182
|
1623 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1624 (RF_ACTIVE | flags));
| 183 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | flags);
|
1625 if (res) {
1626 sc->irq_rid = rid;
1627 sc->irq_res = res;
1628 return (0);
1629 } else {
1630 return (ENOENT);
1631 }
1632}
1633
1634/*
1635 * Release all resources
1636 */
1637void
1638ed_release_resources(device_t dev)
1639{
1640 struct ed_softc *sc = device_get_softc(dev);
1641
1642 if (sc->port_res) {
1643 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1644 sc->port_rid, sc->port_res);
1645 bus_release_resource(dev, SYS_RES_IOPORT,
1646 sc->port_rid, sc->port_res);
1647 sc->port_res = 0;
1648 }
1649 if (sc->mem_res) {
1650 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1651 sc->mem_rid, sc->mem_res);
1652 bus_release_resource(dev, SYS_RES_MEMORY,
1653 sc->mem_rid, sc->mem_res);
1654 sc->mem_res = 0;
1655 }
1656 if (sc->irq_res) {
1657 bus_deactivate_resource(dev, SYS_RES_IRQ,
1658 sc->irq_rid, sc->irq_res);
1659 bus_release_resource(dev, SYS_RES_IRQ,
1660 sc->irq_rid, sc->irq_res);
1661 sc->irq_res = 0;
1662 }
1663}
1664
1665/*
1666 * Install interface into kernel networking data structures
1667 */
1668int
1669ed_attach(device_t dev)
1670{
1671 struct ed_softc *sc = device_get_softc(dev);
1672 struct ifnet *ifp = &sc->arpcom.ac_if;
1673
1674 callout_handle_init(&sc->tick_ch);
1675 /*
1676 * Set interface to stopped condition (reset)
1677 */
1678 ed_stop(sc);
1679
1680 /*
1681 * Initialize ifnet structure
1682 */
1683 ifp->if_softc = sc;
1684 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1685 ifp->if_start = ed_start;
1686 ifp->if_ioctl = ed_ioctl;
1687 ifp->if_watchdog = ed_watchdog;
1688 ifp->if_init = ed_init;
1689 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
1690 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
1691 IFQ_SET_READY(&ifp->if_snd);
1692 ifp->if_linkmib = &sc->mibdata;
1693 ifp->if_linkmiblen = sizeof sc->mibdata;
1694 /*
1695 * XXX - should do a better job.
1696 */
1697 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1698 sc->mibdata.dot3StatsEtherChipSet =
1699 DOT3CHIPSET(dot3VendorWesternDigital,
1700 dot3ChipSetWesternDigital83C790);
1701 else
1702 sc->mibdata.dot3StatsEtherChipSet =
1703 DOT3CHIPSET(dot3VendorNational,
1704 dot3ChipSetNational8390);
1705 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1706
1707 /*
1708 * Set default state for ALTPHYS flag (used to disable the
1709 * tranceiver for AUI operation), based on compile-time
1710 * config option.
1711 */
1712 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1713 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1714 IFF_MULTICAST | IFF_ALTPHYS | IFF_NEEDSGIANT);
1715 else
1716 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1717 IFF_MULTICAST | IFF_NEEDSGIANT);
1718
1719 /*
1720 * Attach the interface
1721 */
1722 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1723 /* device attach does transition from UNCONFIGURED to IDLE state */
1724
1725 if (bootverbose || 1) {
1726 if (sc->type_str && (*sc->type_str != 0))
1727 device_printf(dev, "type %s ", sc->type_str);
1728 else
1729 device_printf(dev, "type unknown (0x%x) ", sc->type);
1730
| 184 if (res) {
185 sc->irq_rid = rid;
186 sc->irq_res = res;
187 return (0);
188 } else {
189 return (ENOENT);
190 }
191}
192
193/*
194 * Release all resources
195 */
196void
197ed_release_resources(device_t dev)
198{
199 struct ed_softc *sc = device_get_softc(dev);
200
201 if (sc->port_res) {
202 bus_deactivate_resource(dev, SYS_RES_IOPORT,
203 sc->port_rid, sc->port_res);
204 bus_release_resource(dev, SYS_RES_IOPORT,
205 sc->port_rid, sc->port_res);
206 sc->port_res = 0;
207 }
208 if (sc->mem_res) {
209 bus_deactivate_resource(dev, SYS_RES_MEMORY,
210 sc->mem_rid, sc->mem_res);
211 bus_release_resource(dev, SYS_RES_MEMORY,
212 sc->mem_rid, sc->mem_res);
213 sc->mem_res = 0;
214 }
215 if (sc->irq_res) {
216 bus_deactivate_resource(dev, SYS_RES_IRQ,
217 sc->irq_rid, sc->irq_res);
218 bus_release_resource(dev, SYS_RES_IRQ,
219 sc->irq_rid, sc->irq_res);
220 sc->irq_res = 0;
221 }
222}
223
224/*
225 * Install interface into kernel networking data structures
226 */
227int
228ed_attach(device_t dev)
229{
230 struct ed_softc *sc = device_get_softc(dev);
231 struct ifnet *ifp = &sc->arpcom.ac_if;
232
233 callout_handle_init(&sc->tick_ch);
234 /*
235 * Set interface to stopped condition (reset)
236 */
237 ed_stop(sc);
238
239 /*
240 * Initialize ifnet structure
241 */
242 ifp->if_softc = sc;
243 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
244 ifp->if_start = ed_start;
245 ifp->if_ioctl = ed_ioctl;
246 ifp->if_watchdog = ed_watchdog;
247 ifp->if_init = ed_init;
248 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
249 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
250 IFQ_SET_READY(&ifp->if_snd);
251 ifp->if_linkmib = &sc->mibdata;
252 ifp->if_linkmiblen = sizeof sc->mibdata;
253 /*
254 * XXX - should do a better job.
255 */
256 if (sc->chip_type == ED_CHIP_TYPE_WD790)
257 sc->mibdata.dot3StatsEtherChipSet =
258 DOT3CHIPSET(dot3VendorWesternDigital,
259 dot3ChipSetWesternDigital83C790);
260 else
261 sc->mibdata.dot3StatsEtherChipSet =
262 DOT3CHIPSET(dot3VendorNational,
263 dot3ChipSetNational8390);
264 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
265
266 /*
267 * Set default state for ALTPHYS flag (used to disable the
268 * tranceiver for AUI operation), based on compile-time
269 * config option.
270 */
271 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
272 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
273 IFF_MULTICAST | IFF_ALTPHYS | IFF_NEEDSGIANT);
274 else
275 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
276 IFF_MULTICAST | IFF_NEEDSGIANT);
277
278 /*
279 * Attach the interface
280 */
281 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
282 /* device attach does transition from UNCONFIGURED to IDLE state */
283
284 if (bootverbose || 1) {
285 if (sc->type_str && (*sc->type_str != 0))
286 device_printf(dev, "type %s ", sc->type_str);
287 else
288 device_printf(dev, "type unknown (0x%x) ", sc->type);
289
|
| 290#ifdef ED_HPP
|
1731 if (sc->vendor == ED_VENDOR_HP)
1732 printf("(%s %s IO)",
1733 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1734 "16-bit" : "32-bit",
1735 sc->hpp_mem_start ? "memory mapped" : "regular");
1736 else
| 291 if (sc->vendor == ED_VENDOR_HP)
292 printf("(%s %s IO)",
293 (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
294 "16-bit" : "32-bit",
295 sc->hpp_mem_start ? "memory mapped" : "regular");
296 else
|
| 297#endif
|
1737 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1738
1739 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1740 (sc->vendor == ED_VENDOR_HP)) &&
1741 (ifp->if_flags & IFF_ALTPHYS)) ?
1742 " tranceiver disabled" : "");
1743 }
1744 return (0);
1745}
1746
1747/*
1748 * Detach the driver from the hardware and other systems in the kernel.
1749 */
1750int
1751ed_detach(device_t dev)
1752{
1753 struct ed_softc *sc = device_get_softc(dev);
1754 struct ifnet *ifp = &sc->arpcom.ac_if;
1755
1756 if (sc->gone)
1757 return (0);
1758 ed_stop(sc);
1759 ifp->if_flags &= ~IFF_RUNNING;
1760 ether_ifdetach(ifp);
1761 sc->gone = 1;
1762 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
1763 ed_release_resources(dev);
1764 return (0);
1765}
1766
1767/*
1768 * Reset interface.
1769 */
1770static void
1771ed_reset(struct ifnet *ifp)
1772{
1773 struct ed_softc *sc = ifp->if_softc;
1774 int s;
1775
1776 if (sc->gone)
1777 return;
1778 s = splimp();
1779
1780 /*
1781 * Stop interface and re-initialize.
1782 */
1783 ed_stop(sc);
1784 ed_init(sc);
1785
1786 (void) splx(s);
1787}
1788
1789/*
1790 * Take interface offline.
1791 */
1792void
1793ed_stop(struct ed_softc *sc)
1794{
1795 int n = 5000;
1796
1797#ifndef ED_NO_MIIBUS
1798 untimeout(ed_tick, sc, sc->tick_ch);
1799 callout_handle_init(&sc->tick_ch);
1800#endif
1801 if (sc->gone)
1802 return;
1803 /*
1804 * Stop everything on the interface, and select page 0 registers.
1805 */
1806 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1807
1808 /*
1809 * Wait for interface to enter stopped state, but limit # of checks to
1810 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1811 * just in case it's an old one.
1812 */
1813 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1814 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1815}
1816
1817/*
1818 * Device timeout/watchdog routine. Entered if the device neglects to
1819 * generate an interrupt after a transmit has been started on it.
1820 */
1821static void
1822ed_watchdog(struct ifnet *ifp)
1823{
1824 struct ed_softc *sc = ifp->if_softc;
1825
1826 if (sc->gone)
1827 return;
1828 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1829 ifp->if_oerrors++;
1830
1831 ed_reset(ifp);
1832}
1833
1834#ifndef ED_NO_MIIBUS
1835static void
1836ed_tick(void *arg)
1837{
1838 struct ed_softc *sc = arg;
1839 struct mii_data *mii;
1840 int s;
1841
1842 if (sc->gone) {
1843 callout_handle_init(&sc->tick_ch);
1844 return;
1845 }
1846 s = splimp();
1847 if (sc->miibus != NULL) {
1848 mii = device_get_softc(sc->miibus);
1849 mii_tick(mii);
1850 }
1851 sc->tick_ch = timeout(ed_tick, sc, hz);
1852 splx(s);
1853}
1854#endif
1855
1856/*
1857 * Initialize device.
1858 */
1859static void
1860ed_init(void *xsc)
1861{
1862 struct ed_softc *sc = xsc;
1863 struct ifnet *ifp = &sc->arpcom.ac_if;
1864 int i, s;
1865
1866 if (sc->gone)
1867 return;
1868
1869 /*
1870 * Initialize the NIC in the exact order outlined in the NS manual.
1871 * This init procedure is "mandatory"...don't change what or when
1872 * things happen.
1873 */
1874 s = splimp();
1875
1876 /* reset transmitter flags */
1877 sc->xmit_busy = 0;
1878 ifp->if_timer = 0;
1879
1880 sc->txb_inuse = 0;
1881 sc->txb_new = 0;
1882 sc->txb_next_tx = 0;
1883
1884 /* This variable is used below - don't move this assignment */
1885 sc->next_packet = sc->rec_page_start + 1;
1886
1887 /*
1888 * Set interface for page 0, Remote DMA complete, Stopped
1889 */
1890 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1891
1892 if (sc->isa16bit) {
1893
1894 /*
1895 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1896 * order=80x86, word-wide DMA xfers,
1897 */
1898 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1899 } else {
1900
1901 /*
1902 * Same as above, but byte-wide DMA xfers
1903 */
1904 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1905 }
1906
1907 /*
1908 * Clear Remote Byte Count Registers
1909 */
1910 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1911 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1912
1913 /*
1914 * For the moment, don't store incoming packets in memory.
1915 */
1916 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1917
1918 /*
1919 * Place NIC in internal loopback mode
1920 */
1921 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1922
1923 /*
1924 * Initialize transmit/receive (ring-buffer) Page Start
1925 */
1926 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1927 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1928 /* Set lower bits of byte addressable framing to 0 */
1929 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1930 ed_nic_outb(sc, 0x09, 0);
1931
1932 /*
1933 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1934 */
1935 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1936 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1937
1938 /*
1939 * Clear all interrupts. A '1' in each bit position clears the
1940 * corresponding flag.
1941 */
1942 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1943
1944 /*
1945 * Enable the following interrupts: receive/transmit complete,
1946 * receive/transmit error, and Receiver OverWrite.
1947 *
1948 * Counter overflow and Remote DMA complete are *not* enabled.
1949 */
1950 ed_nic_outb(sc, ED_P0_IMR,
1951 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1952
1953 /*
1954 * Program Command Register for page 1
1955 */
1956 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1957
1958 /*
1959 * Copy out our station address
1960 */
1961 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1962 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1963
1964 /*
1965 * Set Current Page pointer to next_packet (initialized above)
1966 */
1967 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1968
1969 /*
1970 * Program Receiver Configuration Register and multicast filter. CR is
1971 * set to page 0 on return.
1972 */
1973 ed_setrcr(sc);
1974
1975 /*
1976 * Take interface out of loopback
1977 */
1978 ed_nic_outb(sc, ED_P0_TCR, 0);
1979
1980 /*
1981 * If this is a 3Com board, the tranceiver must be software enabled
1982 * (there is no settable hardware default).
1983 */
1984 if (sc->vendor == ED_VENDOR_3COM) {
1985 if (ifp->if_flags & IFF_ALTPHYS) {
1986 ed_asic_outb(sc, ED_3COM_CR, 0);
1987 } else {
1988 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1989 }
1990 }
1991
1992#ifndef ED_NO_MIIBUS
1993 if (sc->miibus != NULL) {
1994 struct mii_data *mii;
1995 mii = device_get_softc(sc->miibus);
1996 mii_mediachg(mii);
1997 }
1998#endif
1999 /*
2000 * Set 'running' flag, and clear output active flag.
2001 */
2002 ifp->if_flags |= IFF_RUNNING;
2003 ifp->if_flags &= ~IFF_OACTIVE;
2004
2005 /*
2006 * ...and attempt to start output
2007 */
2008 ed_start(ifp);
2009
2010#ifndef ED_NO_MIIBUS
2011 untimeout(ed_tick, sc, sc->tick_ch);
2012 sc->tick_ch = timeout(ed_tick, sc, hz);
2013#endif
2014 (void) splx(s);
2015}
2016
2017/*
2018 * This routine actually starts the transmission on the interface
2019 */
2020static __inline void
2021ed_xmit(struct ed_softc *sc)
2022{
2023 struct ifnet *ifp = (struct ifnet *)sc;
2024 unsigned short len;
2025
2026 if (sc->gone)
2027 return;
2028 len = sc->txb_len[sc->txb_next_tx];
2029
2030 /*
2031 * Set NIC for page 0 register access
2032 */
2033 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2034
2035 /*
2036 * Set TX buffer start page
2037 */
2038 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2039 sc->txb_next_tx * ED_TXBUF_SIZE);
2040
2041 /*
2042 * Set TX length
2043 */
2044 ed_nic_outb(sc, ED_P0_TBCR0, len);
2045 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2046
2047 /*
2048 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2049 */
2050 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2051 sc->xmit_busy = 1;
2052
2053 /*
2054 * Point to next transmit buffer slot and wrap if necessary.
2055 */
2056 sc->txb_next_tx++;
2057 if (sc->txb_next_tx == sc->txb_cnt)
2058 sc->txb_next_tx = 0;
2059
2060 /*
2061 * Set a timer just in case we never hear from the board again
2062 */
2063 ifp->if_timer = 2;
2064}
2065
2066/*
2067 * Start output on interface.
2068 * We make two assumptions here:
2069 * 1) that the current priority is set to splimp _before_ this code
2070 * is called *and* is returned to the appropriate priority after
2071 * return
2072 * 2) that the IFF_OACTIVE flag is checked before this code is called
2073 * (i.e. that the output part of the interface is idle)
2074 */
2075static void
2076ed_start(struct ifnet *ifp)
2077{
2078 struct ed_softc *sc = ifp->if_softc;
2079 struct mbuf *m0, *m;
2080 caddr_t buffer;
2081 int len;
2082
2083 if (sc->gone) {
2084 printf("ed_start(%p) GONE\n",ifp);
2085 return;
2086 }
2087outloop:
2088
2089 /*
2090 * First, see if there are buffered packets and an idle transmitter -
2091 * should never happen at this point.
2092 */
2093 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2094 printf("ed: packets buffered, but transmitter idle\n");
2095 ed_xmit(sc);
2096 }
2097
2098 /*
2099 * See if there is room to put another packet in the buffer.
2100 */
2101 if (sc->txb_inuse == sc->txb_cnt) {
2102
2103 /*
2104 * No room. Indicate this to the outside world and exit.
2105 */
2106 ifp->if_flags |= IFF_OACTIVE;
2107 return;
2108 }
2109 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
2110 if (m == 0) {
2111
2112 /*
2113 * We are using the !OACTIVE flag to indicate to the outside
2114 * world that we can accept an additional packet rather than
2115 * that the transmitter is _actually_ active. Indeed, the
2116 * transmitter may be active, but if we haven't filled all the
2117 * buffers with data then we still want to accept more.
2118 */
2119 ifp->if_flags &= ~IFF_OACTIVE;
2120 return;
2121 }
2122
2123 /*
2124 * Copy the mbuf chain into the transmit buffer
2125 */
2126
2127 m0 = m;
2128
2129 /* txb_new points to next open buffer slot */
2130 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2131
2132 if (sc->mem_shared) {
2133
2134 /*
2135 * Special case setup for 16 bit boards...
2136 */
2137 if (sc->isa16bit) {
2138 switch (sc->vendor) {
2139
2140 /*
2141 * For 16bit 3Com boards (which have 16k of
2142 * memory), we have the xmit buffers in a
2143 * different page of memory ('page 0') - so
2144 * change pages.
2145 */
2146 case ED_VENDOR_3COM:
2147 ed_asic_outb(sc, ED_3COM_GACFR,
2148 ED_3COM_GACFR_RSEL);
2149 break;
2150
2151 /*
2152 * Enable 16bit access to shared memory on
2153 * WD/SMC boards.
2154 */
2155 case ED_VENDOR_WD_SMC:
2156 ed_asic_outb(sc, ED_WD_LAAR,
2157 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2158 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2159 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2160 }
2161 break;
2162 }
2163 }
2164 for (len = 0; m != 0; m = m->m_next) {
2165 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2166 buffer += m->m_len;
2167 len += m->m_len;
2168 }
2169
2170 /*
2171 * Restore previous shared memory access
2172 */
2173 if (sc->isa16bit) {
2174 switch (sc->vendor) {
2175 case ED_VENDOR_3COM:
2176 ed_asic_outb(sc, ED_3COM_GACFR,
2177 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2178 break;
2179 case ED_VENDOR_WD_SMC:
2180 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2181 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2182 }
2183 ed_asic_outb(sc, ED_WD_LAAR,
2184 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2185 break;
2186 }
2187 }
2188 } else {
2189 len = ed_pio_write_mbufs(sc, m, (uintptr_t)buffer);
2190 if (len == 0) {
2191 m_freem(m0);
2192 goto outloop;
2193 }
2194 }
2195
2196 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2197
2198 sc->txb_inuse++;
2199
2200 /*
2201 * Point to next buffer slot and wrap if necessary.
2202 */
2203 sc->txb_new++;
2204 if (sc->txb_new == sc->txb_cnt)
2205 sc->txb_new = 0;
2206
2207 if (sc->xmit_busy == 0)
2208 ed_xmit(sc);
2209
2210 /*
2211 * Tap off here if there is a bpf listener.
2212 */
2213 BPF_MTAP(ifp, m0);
2214
2215 m_freem(m0);
2216
2217 /*
2218 * Loop back to the top to possibly buffer more packets
2219 */
2220 goto outloop;
2221}
2222
2223/*
2224 * Ethernet interface receiver interrupt.
2225 */
2226static __inline void
2227ed_rint(struct ed_softc *sc)
2228{
2229 struct ifnet *ifp = &sc->arpcom.ac_if;
2230 u_char boundry;
2231 u_short len;
2232 struct ed_ring packet_hdr;
2233 char *packet_ptr;
2234
2235 if (sc->gone)
2236 return;
2237
2238 /*
2239 * Set NIC to page 1 registers to get 'current' pointer
2240 */
2241 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2242
2243 /*
2244 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2245 * i.e. it points to where new data has been buffered. The 'CURR'
2246 * (current) register points to the logical end of the ring-buffer -
2247 * i.e. it points to where additional new data will be added. We loop
2248 * here until the logical beginning equals the logical end (or in
2249 * other words, until the ring-buffer is empty).
2250 */
2251 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2252
2253 /* get pointer to this buffer's header structure */
2254 packet_ptr = sc->mem_ring +
2255 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2256
2257 /*
2258 * The byte count includes a 4 byte header that was added by
2259 * the NIC.
2260 */
2261 if (sc->mem_shared)
2262 packet_hdr = *(struct ed_ring *) packet_ptr;
2263 else
2264 ed_pio_readmem(sc, (uintptr_t)packet_ptr,
2265 (char *) &packet_hdr, sizeof(packet_hdr));
2266 len = packet_hdr.count;
2267 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2268 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2269 /*
2270 * Length is a wild value. There's a good chance that
2271 * this was caused by the NIC being old and buggy.
2272 * The bug is that the length low byte is duplicated in
2273 * the high byte. Try to recalculate the length based on
2274 * the pointer to the next packet.
2275 */
2276 /*
2277 * NOTE: sc->next_packet is pointing at the current packet.
2278 */
2279 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2280 if (packet_hdr.next_packet >= sc->next_packet) {
2281 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2282 } else {
2283 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2284 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2285 }
2286 /*
2287 * because buffers are aligned on 256-byte boundary,
2288 * the length computed above is off by 256 in almost
2289 * all cases. Fix it...
2290 */
2291 if (len & 0xff)
2292 len -= 256 ;
2293 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2294 + sizeof(struct ed_ring)))
2295 sc->mibdata.dot3StatsFrameTooLongs++;
2296 }
2297 /*
2298 * Be fairly liberal about what we allow as a "reasonable" length
2299 * so that a [crufty] packet will make it to BPF (and can thus
2300 * be analyzed). Note that all that is really important is that
2301 * we have a length that will fit into one mbuf cluster or less;
2302 * the upper layer protocols can then figure out the length from
2303 * their own length field(s).
2304 * But make sure that we have at least a full ethernet header
2305 * or we would be unable to call ether_input() later.
2306 */
2307 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2308 (len <= MCLBYTES) &&
2309 (packet_hdr.next_packet >= sc->rec_page_start) &&
2310 (packet_hdr.next_packet < sc->rec_page_stop)) {
2311 /*
2312 * Go get packet.
2313 */
2314 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2315 len - sizeof(struct ed_ring));
2316 ifp->if_ipackets++;
2317 } else {
2318 /*
2319 * Really BAD. The ring pointers are corrupted.
2320 */
2321 log(LOG_ERR,
2322 "%s: NIC memory corrupt - invalid packet length %d\n",
2323 ifp->if_xname, len);
2324 ifp->if_ierrors++;
2325 ed_reset(ifp);
2326 return;
2327 }
2328
2329 /*
2330 * Update next packet pointer
2331 */
2332 sc->next_packet = packet_hdr.next_packet;
2333
2334 /*
2335 * Update NIC boundry pointer - being careful to keep it one
2336 * buffer behind. (as recommended by NS databook)
2337 */
2338 boundry = sc->next_packet - 1;
2339 if (boundry < sc->rec_page_start)
2340 boundry = sc->rec_page_stop - 1;
2341
2342 /*
2343 * Set NIC to page 0 registers to update boundry register
2344 */
2345 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2346
2347 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2348
2349 /*
2350 * Set NIC to page 1 registers before looping to top (prepare
2351 * to get 'CURR' current pointer)
2352 */
2353 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2354 }
2355}
2356
2357/*
2358 * Ethernet interface interrupt processor
2359 */
2360void
2361edintr(void *arg)
2362{
2363 struct ed_softc *sc = (struct ed_softc*) arg;
2364 struct ifnet *ifp = (struct ifnet *)sc;
2365 u_char isr;
2366 int count;
2367
2368 if (sc->gone)
2369 return;
2370 /*
2371 * Set NIC to page 0 registers
2372 */
2373 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2374
2375 /*
2376 * loop until there are no more new interrupts. When the card
2377 * goes away, the hardware will read back 0xff. Looking at
2378 * the interrupts, it would appear that 0xff is impossible,
2379 * or at least extremely unlikely.
2380 */
2381 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2382
2383 /*
2384 * reset all the bits that we are 'acknowledging' by writing a
2385 * '1' to each bit position that was set (writing a '1'
2386 * *clears* the bit)
2387 */
2388 ed_nic_outb(sc, ED_P0_ISR, isr);
2389
2390 /*
2391 * XXX workaround for AX88190
2392 * We limit this to 5000 iterations. At 1us per inb/outb,
2393 * this translates to about 15ms, which should be plenty
2394 * of time, and also gives protection in the card eject
2395 * case.
2396 */
2397 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2398 count = 5000; /* 15ms */
2399 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2400 ed_nic_outb(sc, ED_P0_ISR,0);
2401 ed_nic_outb(sc, ED_P0_ISR,isr);
2402 }
2403 if (count == 0)
2404 break;
2405 }
2406
2407 /*
2408 * Handle transmitter interrupts. Handle these first because
2409 * the receiver will reset the board under some conditions.
2410 */
2411 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2412 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2413
2414 /*
2415 * Check for transmit error. If a TX completed with an
2416 * error, we end up throwing the packet away. Really
2417 * the only error that is possible is excessive
2418 * collisions, and in this case it is best to allow
2419 * the automatic mechanisms of TCP to backoff the
2420 * flow. Of course, with UDP we're screwed, but this
2421 * is expected when a network is heavily loaded.
2422 */
2423 (void) ed_nic_inb(sc, ED_P0_TSR);
2424 if (isr & ED_ISR_TXE) {
2425 u_char tsr;
2426
2427 /*
2428 * Excessive collisions (16)
2429 */
2430 tsr = ed_nic_inb(sc, ED_P0_TSR);
2431 if ((tsr & ED_TSR_ABT)
2432 && (collisions == 0)) {
2433
2434 /*
2435 * When collisions total 16, the
2436 * P0_NCR will indicate 0, and the
2437 * TSR_ABT is set.
2438 */
2439 collisions = 16;
2440 sc->mibdata.dot3StatsExcessiveCollisions++;
2441 sc->mibdata.dot3StatsCollFrequencies[15]++;
2442 }
2443 if (tsr & ED_TSR_OWC)
2444 sc->mibdata.dot3StatsLateCollisions++;
2445 if (tsr & ED_TSR_CDH)
2446 sc->mibdata.dot3StatsSQETestErrors++;
2447 if (tsr & ED_TSR_CRS)
2448 sc->mibdata.dot3StatsCarrierSenseErrors++;
2449 if (tsr & ED_TSR_FU)
2450 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2451
2452 /*
2453 * update output errors counter
2454 */
2455 ifp->if_oerrors++;
2456 } else {
2457
2458 /*
2459 * Update total number of successfully
2460 * transmitted packets.
2461 */
2462 ifp->if_opackets++;
2463 }
2464
2465 /*
2466 * reset tx busy and output active flags
2467 */
2468 sc->xmit_busy = 0;
2469 ifp->if_flags &= ~IFF_OACTIVE;
2470
2471 /*
2472 * clear watchdog timer
2473 */
2474 ifp->if_timer = 0;
2475
2476 /*
2477 * Add in total number of collisions on last
2478 * transmission.
2479 */
2480 ifp->if_collisions += collisions;
2481 switch(collisions) {
2482 case 0:
2483 case 16:
2484 break;
2485 case 1:
2486 sc->mibdata.dot3StatsSingleCollisionFrames++;
2487 sc->mibdata.dot3StatsCollFrequencies[0]++;
2488 break;
2489 default:
2490 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2491 sc->mibdata.
2492 dot3StatsCollFrequencies[collisions-1]
2493 ++;
2494 break;
2495 }
2496
2497 /*
2498 * Decrement buffer in-use count if not zero (can only
2499 * be zero if a transmitter interrupt occured while
2500 * not actually transmitting). If data is ready to
2501 * transmit, start it transmitting, otherwise defer
2502 * until after handling receiver
2503 */
2504 if (sc->txb_inuse && --sc->txb_inuse)
2505 ed_xmit(sc);
2506 }
2507
2508 /*
2509 * Handle receiver interrupts
2510 */
2511 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2512
2513 /*
2514 * Overwrite warning. In order to make sure that a
2515 * lockup of the local DMA hasn't occurred, we reset
2516 * and re-init the NIC. The NSC manual suggests only a
2517 * partial reset/re-init is necessary - but some chips
2518 * seem to want more. The DMA lockup has been seen
2519 * only with early rev chips - Methinks this bug was
2520 * fixed in later revs. -DG
2521 */
2522 if (isr & ED_ISR_OVW) {
2523 ifp->if_ierrors++;
2524#ifdef DIAGNOSTIC
2525 log(LOG_WARNING,
2526 "%s: warning - receiver ring buffer overrun\n",
2527 ifp->if_xname);
2528#endif
2529
2530 /*
2531 * Stop/reset/re-init NIC
2532 */
2533 ed_reset(ifp);
2534 } else {
2535
2536 /*
2537 * Receiver Error. One or more of: CRC error,
2538 * frame alignment error FIFO overrun, or
2539 * missed packet.
2540 */
2541 if (isr & ED_ISR_RXE) {
2542 u_char rsr;
2543 rsr = ed_nic_inb(sc, ED_P0_RSR);
2544 if (rsr & ED_RSR_CRC)
2545 sc->mibdata.dot3StatsFCSErrors++;
2546 if (rsr & ED_RSR_FAE)
2547 sc->mibdata.dot3StatsAlignmentErrors++;
2548 if (rsr & ED_RSR_FO)
2549 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2550 ifp->if_ierrors++;
2551#ifdef ED_DEBUG
2552 if_printf(ifp, "receive error %x\n",
2553 ed_nic_inb(sc, ED_P0_RSR));
2554#endif
2555 }
2556
2557 /*
2558 * Go get the packet(s) XXX - Doing this on an
2559 * error is dubious because there shouldn't be
2560 * any data to get (we've configured the
2561 * interface to not accept packets with
2562 * errors).
2563 */
2564
2565 /*
2566 * Enable 16bit access to shared memory first
2567 * on WD/SMC boards.
2568 */
2569 if (sc->isa16bit &&
2570 (sc->vendor == ED_VENDOR_WD_SMC)) {
2571
2572 ed_asic_outb(sc, ED_WD_LAAR,
2573 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2574 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2575 ed_asic_outb(sc, ED_WD_MSR,
2576 ED_WD_MSR_MENB);
2577 }
2578 }
2579 ed_rint(sc);
2580
2581 /* disable 16bit access */
2582 if (sc->isa16bit &&
2583 (sc->vendor == ED_VENDOR_WD_SMC)) {
2584
2585 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2586 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2587 }
2588 ed_asic_outb(sc, ED_WD_LAAR,
2589 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2590 }
2591 }
2592 }
2593
2594 /*
2595 * If it looks like the transmitter can take more data,
2596 * attempt to start output on the interface. This is done
2597 * after handling the receiver to give the receiver priority.
2598 */
2599 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2600 ed_start(ifp);
2601
2602 /*
2603 * return NIC CR to standard state: page 0, remote DMA
2604 * complete, start (toggling the TXP bit off, even if was just
2605 * set in the transmit routine, is *okay* - it is 'edge'
2606 * triggered from low to high)
2607 */
2608 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2609
2610 /*
2611 * If the Network Talley Counters overflow, read them to reset
2612 * them. It appears that old 8390's won't clear the ISR flag
2613 * otherwise - resulting in an infinite loop.
2614 */
2615 if (isr & ED_ISR_CNT) {
2616 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2617 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2618 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2619 }
2620 }
2621}
2622
2623/*
2624 * Process an ioctl request.
2625 */
2626static int
2627ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2628{
2629 struct ed_softc *sc = ifp->if_softc;
2630#ifndef ED_NO_MIIBUS
2631 struct ifreq *ifr = (struct ifreq *)data;
2632 struct mii_data *mii;
2633#endif
2634 int s, error = 0;
2635
2636 if (sc == NULL || sc->gone) {
2637 ifp->if_flags &= ~IFF_RUNNING;
2638 return ENXIO;
2639 }
2640 s = splimp();
2641
2642 switch (command) {
2643 case SIOCSIFFLAGS:
2644
2645 /*
2646 * If the interface is marked up and stopped, then start it.
2647 * If it is marked down and running, then stop it.
2648 */
2649 if (ifp->if_flags & IFF_UP) {
2650 if ((ifp->if_flags & IFF_RUNNING) == 0)
2651 ed_init(sc);
2652 } else {
2653 if (ifp->if_flags & IFF_RUNNING) {
2654 ed_stop(sc);
2655 ifp->if_flags &= ~IFF_RUNNING;
2656 }
2657 }
2658
2659 /*
2660 * Promiscuous flag may have changed, so reprogram the RCR.
2661 */
2662 ed_setrcr(sc);
2663
2664 /*
2665 * An unfortunate hack to provide the (required) software
2666 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2667 * disables the tranceiver if set.
2668 */
2669 if (sc->vendor == ED_VENDOR_3COM) {
2670 if (ifp->if_flags & IFF_ALTPHYS) {
2671 ed_asic_outb(sc, ED_3COM_CR, 0);
2672 } else {
2673 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2674 }
| 298 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
299
300 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
301 (sc->vendor == ED_VENDOR_HP)) &&
302 (ifp->if_flags & IFF_ALTPHYS)) ?
303 " tranceiver disabled" : "");
304 }
305 return (0);
306}
307
308/*
309 * Detach the driver from the hardware and other systems in the kernel.
310 */
311int
312ed_detach(device_t dev)
313{
314 struct ed_softc *sc = device_get_softc(dev);
315 struct ifnet *ifp = &sc->arpcom.ac_if;
316
317 if (sc->gone)
318 return (0);
319 ed_stop(sc);
320 ifp->if_flags &= ~IFF_RUNNING;
321 ether_ifdetach(ifp);
322 sc->gone = 1;
323 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
324 ed_release_resources(dev);
325 return (0);
326}
327
328/*
329 * Reset interface.
330 */
331static void
332ed_reset(struct ifnet *ifp)
333{
334 struct ed_softc *sc = ifp->if_softc;
335 int s;
336
337 if (sc->gone)
338 return;
339 s = splimp();
340
341 /*
342 * Stop interface and re-initialize.
343 */
344 ed_stop(sc);
345 ed_init(sc);
346
347 (void) splx(s);
348}
349
350/*
351 * Take interface offline.
352 */
353void
354ed_stop(struct ed_softc *sc)
355{
356 int n = 5000;
357
358#ifndef ED_NO_MIIBUS
359 untimeout(ed_tick, sc, sc->tick_ch);
360 callout_handle_init(&sc->tick_ch);
361#endif
362 if (sc->gone)
363 return;
364 /*
365 * Stop everything on the interface, and select page 0 registers.
366 */
367 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
368
369 /*
370 * Wait for interface to enter stopped state, but limit # of checks to
371 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
372 * just in case it's an old one.
373 */
374 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
375 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
376}
377
378/*
379 * Device timeout/watchdog routine. Entered if the device neglects to
380 * generate an interrupt after a transmit has been started on it.
381 */
382static void
383ed_watchdog(struct ifnet *ifp)
384{
385 struct ed_softc *sc = ifp->if_softc;
386
387 if (sc->gone)
388 return;
389 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
390 ifp->if_oerrors++;
391
392 ed_reset(ifp);
393}
394
395#ifndef ED_NO_MIIBUS
396static void
397ed_tick(void *arg)
398{
399 struct ed_softc *sc = arg;
400 struct mii_data *mii;
401 int s;
402
403 if (sc->gone) {
404 callout_handle_init(&sc->tick_ch);
405 return;
406 }
407 s = splimp();
408 if (sc->miibus != NULL) {
409 mii = device_get_softc(sc->miibus);
410 mii_tick(mii);
411 }
412 sc->tick_ch = timeout(ed_tick, sc, hz);
413 splx(s);
414}
415#endif
416
417/*
418 * Initialize device.
419 */
420static void
421ed_init(void *xsc)
422{
423 struct ed_softc *sc = xsc;
424 struct ifnet *ifp = &sc->arpcom.ac_if;
425 int i, s;
426
427 if (sc->gone)
428 return;
429
430 /*
431 * Initialize the NIC in the exact order outlined in the NS manual.
432 * This init procedure is "mandatory"...don't change what or when
433 * things happen.
434 */
435 s = splimp();
436
437 /* reset transmitter flags */
438 sc->xmit_busy = 0;
439 ifp->if_timer = 0;
440
441 sc->txb_inuse = 0;
442 sc->txb_new = 0;
443 sc->txb_next_tx = 0;
444
445 /* This variable is used below - don't move this assignment */
446 sc->next_packet = sc->rec_page_start + 1;
447
448 /*
449 * Set interface for page 0, Remote DMA complete, Stopped
450 */
451 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
452
453 if (sc->isa16bit) {
454
455 /*
456 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
457 * order=80x86, word-wide DMA xfers,
458 */
459 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
460 } else {
461
462 /*
463 * Same as above, but byte-wide DMA xfers
464 */
465 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
466 }
467
468 /*
469 * Clear Remote Byte Count Registers
470 */
471 ed_nic_outb(sc, ED_P0_RBCR0, 0);
472 ed_nic_outb(sc, ED_P0_RBCR1, 0);
473
474 /*
475 * For the moment, don't store incoming packets in memory.
476 */
477 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
478
479 /*
480 * Place NIC in internal loopback mode
481 */
482 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
483
484 /*
485 * Initialize transmit/receive (ring-buffer) Page Start
486 */
487 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
488 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
489 /* Set lower bits of byte addressable framing to 0 */
490 if (sc->chip_type == ED_CHIP_TYPE_WD790)
491 ed_nic_outb(sc, 0x09, 0);
492
493 /*
494 * Initialize Receiver (ring-buffer) Page Stop and Boundry
495 */
496 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
497 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
498
499 /*
500 * Clear all interrupts. A '1' in each bit position clears the
501 * corresponding flag.
502 */
503 ed_nic_outb(sc, ED_P0_ISR, 0xff);
504
505 /*
506 * Enable the following interrupts: receive/transmit complete,
507 * receive/transmit error, and Receiver OverWrite.
508 *
509 * Counter overflow and Remote DMA complete are *not* enabled.
510 */
511 ed_nic_outb(sc, ED_P0_IMR,
512 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
513
514 /*
515 * Program Command Register for page 1
516 */
517 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
518
519 /*
520 * Copy out our station address
521 */
522 for (i = 0; i < ETHER_ADDR_LEN; ++i)
523 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
524
525 /*
526 * Set Current Page pointer to next_packet (initialized above)
527 */
528 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
529
530 /*
531 * Program Receiver Configuration Register and multicast filter. CR is
532 * set to page 0 on return.
533 */
534 ed_setrcr(sc);
535
536 /*
537 * Take interface out of loopback
538 */
539 ed_nic_outb(sc, ED_P0_TCR, 0);
540
541 /*
542 * If this is a 3Com board, the tranceiver must be software enabled
543 * (there is no settable hardware default).
544 */
545 if (sc->vendor == ED_VENDOR_3COM) {
546 if (ifp->if_flags & IFF_ALTPHYS) {
547 ed_asic_outb(sc, ED_3COM_CR, 0);
548 } else {
549 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
550 }
551 }
552
553#ifndef ED_NO_MIIBUS
554 if (sc->miibus != NULL) {
555 struct mii_data *mii;
556 mii = device_get_softc(sc->miibus);
557 mii_mediachg(mii);
558 }
559#endif
560 /*
561 * Set 'running' flag, and clear output active flag.
562 */
563 ifp->if_flags |= IFF_RUNNING;
564 ifp->if_flags &= ~IFF_OACTIVE;
565
566 /*
567 * ...and attempt to start output
568 */
569 ed_start(ifp);
570
571#ifndef ED_NO_MIIBUS
572 untimeout(ed_tick, sc, sc->tick_ch);
573 sc->tick_ch = timeout(ed_tick, sc, hz);
574#endif
575 (void) splx(s);
576}
577
578/*
579 * This routine actually starts the transmission on the interface
580 */
581static __inline void
582ed_xmit(struct ed_softc *sc)
583{
584 struct ifnet *ifp = (struct ifnet *)sc;
585 unsigned short len;
586
587 if (sc->gone)
588 return;
589 len = sc->txb_len[sc->txb_next_tx];
590
591 /*
592 * Set NIC for page 0 register access
593 */
594 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
595
596 /*
597 * Set TX buffer start page
598 */
599 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
600 sc->txb_next_tx * ED_TXBUF_SIZE);
601
602 /*
603 * Set TX length
604 */
605 ed_nic_outb(sc, ED_P0_TBCR0, len);
606 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
607
608 /*
609 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
610 */
611 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
612 sc->xmit_busy = 1;
613
614 /*
615 * Point to next transmit buffer slot and wrap if necessary.
616 */
617 sc->txb_next_tx++;
618 if (sc->txb_next_tx == sc->txb_cnt)
619 sc->txb_next_tx = 0;
620
621 /*
622 * Set a timer just in case we never hear from the board again
623 */
624 ifp->if_timer = 2;
625}
626
627/*
628 * Start output on interface.
629 * We make two assumptions here:
630 * 1) that the current priority is set to splimp _before_ this code
631 * is called *and* is returned to the appropriate priority after
632 * return
633 * 2) that the IFF_OACTIVE flag is checked before this code is called
634 * (i.e. that the output part of the interface is idle)
635 */
636static void
637ed_start(struct ifnet *ifp)
638{
639 struct ed_softc *sc = ifp->if_softc;
640 struct mbuf *m0, *m;
641 caddr_t buffer;
642 int len;
643
644 if (sc->gone) {
645 printf("ed_start(%p) GONE\n",ifp);
646 return;
647 }
648outloop:
649
650 /*
651 * First, see if there are buffered packets and an idle transmitter -
652 * should never happen at this point.
653 */
654 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
655 printf("ed: packets buffered, but transmitter idle\n");
656 ed_xmit(sc);
657 }
658
659 /*
660 * See if there is room to put another packet in the buffer.
661 */
662 if (sc->txb_inuse == sc->txb_cnt) {
663
664 /*
665 * No room. Indicate this to the outside world and exit.
666 */
667 ifp->if_flags |= IFF_OACTIVE;
668 return;
669 }
670 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
671 if (m == 0) {
672
673 /*
674 * We are using the !OACTIVE flag to indicate to the outside
675 * world that we can accept an additional packet rather than
676 * that the transmitter is _actually_ active. Indeed, the
677 * transmitter may be active, but if we haven't filled all the
678 * buffers with data then we still want to accept more.
679 */
680 ifp->if_flags &= ~IFF_OACTIVE;
681 return;
682 }
683
684 /*
685 * Copy the mbuf chain into the transmit buffer
686 */
687
688 m0 = m;
689
690 /* txb_new points to next open buffer slot */
691 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
692
693 if (sc->mem_shared) {
694
695 /*
696 * Special case setup for 16 bit boards...
697 */
698 if (sc->isa16bit) {
699 switch (sc->vendor) {
700
701 /*
702 * For 16bit 3Com boards (which have 16k of
703 * memory), we have the xmit buffers in a
704 * different page of memory ('page 0') - so
705 * change pages.
706 */
707 case ED_VENDOR_3COM:
708 ed_asic_outb(sc, ED_3COM_GACFR,
709 ED_3COM_GACFR_RSEL);
710 break;
711
712 /*
713 * Enable 16bit access to shared memory on
714 * WD/SMC boards.
715 */
716 case ED_VENDOR_WD_SMC:
717 ed_asic_outb(sc, ED_WD_LAAR,
718 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
719 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
720 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
721 }
722 break;
723 }
724 }
725 for (len = 0; m != 0; m = m->m_next) {
726 bcopy(mtod(m, caddr_t), buffer, m->m_len);
727 buffer += m->m_len;
728 len += m->m_len;
729 }
730
731 /*
732 * Restore previous shared memory access
733 */
734 if (sc->isa16bit) {
735 switch (sc->vendor) {
736 case ED_VENDOR_3COM:
737 ed_asic_outb(sc, ED_3COM_GACFR,
738 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
739 break;
740 case ED_VENDOR_WD_SMC:
741 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
742 ed_asic_outb(sc, ED_WD_MSR, 0x00);
743 }
744 ed_asic_outb(sc, ED_WD_LAAR,
745 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
746 break;
747 }
748 }
749 } else {
750 len = ed_pio_write_mbufs(sc, m, (uintptr_t)buffer);
751 if (len == 0) {
752 m_freem(m0);
753 goto outloop;
754 }
755 }
756
757 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
758
759 sc->txb_inuse++;
760
761 /*
762 * Point to next buffer slot and wrap if necessary.
763 */
764 sc->txb_new++;
765 if (sc->txb_new == sc->txb_cnt)
766 sc->txb_new = 0;
767
768 if (sc->xmit_busy == 0)
769 ed_xmit(sc);
770
771 /*
772 * Tap off here if there is a bpf listener.
773 */
774 BPF_MTAP(ifp, m0);
775
776 m_freem(m0);
777
778 /*
779 * Loop back to the top to possibly buffer more packets
780 */
781 goto outloop;
782}
783
784/*
785 * Ethernet interface receiver interrupt.
786 */
787static __inline void
788ed_rint(struct ed_softc *sc)
789{
790 struct ifnet *ifp = &sc->arpcom.ac_if;
791 u_char boundry;
792 u_short len;
793 struct ed_ring packet_hdr;
794 char *packet_ptr;
795
796 if (sc->gone)
797 return;
798
799 /*
800 * Set NIC to page 1 registers to get 'current' pointer
801 */
802 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
803
804 /*
805 * 'sc->next_packet' is the logical beginning of the ring-buffer -
806 * i.e. it points to where new data has been buffered. The 'CURR'
807 * (current) register points to the logical end of the ring-buffer -
808 * i.e. it points to where additional new data will be added. We loop
809 * here until the logical beginning equals the logical end (or in
810 * other words, until the ring-buffer is empty).
811 */
812 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
813
814 /* get pointer to this buffer's header structure */
815 packet_ptr = sc->mem_ring +
816 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
817
818 /*
819 * The byte count includes a 4 byte header that was added by
820 * the NIC.
821 */
822 if (sc->mem_shared)
823 packet_hdr = *(struct ed_ring *) packet_ptr;
824 else
825 ed_pio_readmem(sc, (uintptr_t)packet_ptr,
826 (char *) &packet_hdr, sizeof(packet_hdr));
827 len = packet_hdr.count;
828 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
829 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
830 /*
831 * Length is a wild value. There's a good chance that
832 * this was caused by the NIC being old and buggy.
833 * The bug is that the length low byte is duplicated in
834 * the high byte. Try to recalculate the length based on
835 * the pointer to the next packet.
836 */
837 /*
838 * NOTE: sc->next_packet is pointing at the current packet.
839 */
840 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
841 if (packet_hdr.next_packet >= sc->next_packet) {
842 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
843 } else {
844 len += ((packet_hdr.next_packet - sc->rec_page_start) +
845 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
846 }
847 /*
848 * because buffers are aligned on 256-byte boundary,
849 * the length computed above is off by 256 in almost
850 * all cases. Fix it...
851 */
852 if (len & 0xff)
853 len -= 256 ;
854 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
855 + sizeof(struct ed_ring)))
856 sc->mibdata.dot3StatsFrameTooLongs++;
857 }
858 /*
859 * Be fairly liberal about what we allow as a "reasonable" length
860 * so that a [crufty] packet will make it to BPF (and can thus
861 * be analyzed). Note that all that is really important is that
862 * we have a length that will fit into one mbuf cluster or less;
863 * the upper layer protocols can then figure out the length from
864 * their own length field(s).
865 * But make sure that we have at least a full ethernet header
866 * or we would be unable to call ether_input() later.
867 */
868 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
869 (len <= MCLBYTES) &&
870 (packet_hdr.next_packet >= sc->rec_page_start) &&
871 (packet_hdr.next_packet < sc->rec_page_stop)) {
872 /*
873 * Go get packet.
874 */
875 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
876 len - sizeof(struct ed_ring));
877 ifp->if_ipackets++;
878 } else {
879 /*
880 * Really BAD. The ring pointers are corrupted.
881 */
882 log(LOG_ERR,
883 "%s: NIC memory corrupt - invalid packet length %d\n",
884 ifp->if_xname, len);
885 ifp->if_ierrors++;
886 ed_reset(ifp);
887 return;
888 }
889
890 /*
891 * Update next packet pointer
892 */
893 sc->next_packet = packet_hdr.next_packet;
894
895 /*
896 * Update NIC boundry pointer - being careful to keep it one
897 * buffer behind. (as recommended by NS databook)
898 */
899 boundry = sc->next_packet - 1;
900 if (boundry < sc->rec_page_start)
901 boundry = sc->rec_page_stop - 1;
902
903 /*
904 * Set NIC to page 0 registers to update boundry register
905 */
906 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
907
908 ed_nic_outb(sc, ED_P0_BNRY, boundry);
909
910 /*
911 * Set NIC to page 1 registers before looping to top (prepare
912 * to get 'CURR' current pointer)
913 */
914 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
915 }
916}
917
918/*
919 * Ethernet interface interrupt processor
920 */
921void
922edintr(void *arg)
923{
924 struct ed_softc *sc = (struct ed_softc*) arg;
925 struct ifnet *ifp = (struct ifnet *)sc;
926 u_char isr;
927 int count;
928
929 if (sc->gone)
930 return;
931 /*
932 * Set NIC to page 0 registers
933 */
934 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
935
936 /*
937 * loop until there are no more new interrupts. When the card
938 * goes away, the hardware will read back 0xff. Looking at
939 * the interrupts, it would appear that 0xff is impossible,
940 * or at least extremely unlikely.
941 */
942 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
943
944 /*
945 * reset all the bits that we are 'acknowledging' by writing a
946 * '1' to each bit position that was set (writing a '1'
947 * *clears* the bit)
948 */
949 ed_nic_outb(sc, ED_P0_ISR, isr);
950
951 /*
952 * XXX workaround for AX88190
953 * We limit this to 5000 iterations. At 1us per inb/outb,
954 * this translates to about 15ms, which should be plenty
955 * of time, and also gives protection in the card eject
956 * case.
957 */
958 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
959 count = 5000; /* 15ms */
960 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
961 ed_nic_outb(sc, ED_P0_ISR,0);
962 ed_nic_outb(sc, ED_P0_ISR,isr);
963 }
964 if (count == 0)
965 break;
966 }
967
968 /*
969 * Handle transmitter interrupts. Handle these first because
970 * the receiver will reset the board under some conditions.
971 */
972 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
973 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
974
975 /*
976 * Check for transmit error. If a TX completed with an
977 * error, we end up throwing the packet away. Really
978 * the only error that is possible is excessive
979 * collisions, and in this case it is best to allow
980 * the automatic mechanisms of TCP to backoff the
981 * flow. Of course, with UDP we're screwed, but this
982 * is expected when a network is heavily loaded.
983 */
984 (void) ed_nic_inb(sc, ED_P0_TSR);
985 if (isr & ED_ISR_TXE) {
986 u_char tsr;
987
988 /*
989 * Excessive collisions (16)
990 */
991 tsr = ed_nic_inb(sc, ED_P0_TSR);
992 if ((tsr & ED_TSR_ABT)
993 && (collisions == 0)) {
994
995 /*
996 * When collisions total 16, the
997 * P0_NCR will indicate 0, and the
998 * TSR_ABT is set.
999 */
1000 collisions = 16;
1001 sc->mibdata.dot3StatsExcessiveCollisions++;
1002 sc->mibdata.dot3StatsCollFrequencies[15]++;
1003 }
1004 if (tsr & ED_TSR_OWC)
1005 sc->mibdata.dot3StatsLateCollisions++;
1006 if (tsr & ED_TSR_CDH)
1007 sc->mibdata.dot3StatsSQETestErrors++;
1008 if (tsr & ED_TSR_CRS)
1009 sc->mibdata.dot3StatsCarrierSenseErrors++;
1010 if (tsr & ED_TSR_FU)
1011 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
1012
1013 /*
1014 * update output errors counter
1015 */
1016 ifp->if_oerrors++;
1017 } else {
1018
1019 /*
1020 * Update total number of successfully
1021 * transmitted packets.
1022 */
1023 ifp->if_opackets++;
1024 }
1025
1026 /*
1027 * reset tx busy and output active flags
1028 */
1029 sc->xmit_busy = 0;
1030 ifp->if_flags &= ~IFF_OACTIVE;
1031
1032 /*
1033 * clear watchdog timer
1034 */
1035 ifp->if_timer = 0;
1036
1037 /*
1038 * Add in total number of collisions on last
1039 * transmission.
1040 */
1041 ifp->if_collisions += collisions;
1042 switch(collisions) {
1043 case 0:
1044 case 16:
1045 break;
1046 case 1:
1047 sc->mibdata.dot3StatsSingleCollisionFrames++;
1048 sc->mibdata.dot3StatsCollFrequencies[0]++;
1049 break;
1050 default:
1051 sc->mibdata.dot3StatsMultipleCollisionFrames++;
1052 sc->mibdata.
1053 dot3StatsCollFrequencies[collisions-1]
1054 ++;
1055 break;
1056 }
1057
1058 /*
1059 * Decrement buffer in-use count if not zero (can only
1060 * be zero if a transmitter interrupt occured while
1061 * not actually transmitting). If data is ready to
1062 * transmit, start it transmitting, otherwise defer
1063 * until after handling receiver
1064 */
1065 if (sc->txb_inuse && --sc->txb_inuse)
1066 ed_xmit(sc);
1067 }
1068
1069 /*
1070 * Handle receiver interrupts
1071 */
1072 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
1073
1074 /*
1075 * Overwrite warning. In order to make sure that a
1076 * lockup of the local DMA hasn't occurred, we reset
1077 * and re-init the NIC. The NSC manual suggests only a
1078 * partial reset/re-init is necessary - but some chips
1079 * seem to want more. The DMA lockup has been seen
1080 * only with early rev chips - Methinks this bug was
1081 * fixed in later revs. -DG
1082 */
1083 if (isr & ED_ISR_OVW) {
1084 ifp->if_ierrors++;
1085#ifdef DIAGNOSTIC
1086 log(LOG_WARNING,
1087 "%s: warning - receiver ring buffer overrun\n",
1088 ifp->if_xname);
1089#endif
1090
1091 /*
1092 * Stop/reset/re-init NIC
1093 */
1094 ed_reset(ifp);
1095 } else {
1096
1097 /*
1098 * Receiver Error. One or more of: CRC error,
1099 * frame alignment error FIFO overrun, or
1100 * missed packet.
1101 */
1102 if (isr & ED_ISR_RXE) {
1103 u_char rsr;
1104 rsr = ed_nic_inb(sc, ED_P0_RSR);
1105 if (rsr & ED_RSR_CRC)
1106 sc->mibdata.dot3StatsFCSErrors++;
1107 if (rsr & ED_RSR_FAE)
1108 sc->mibdata.dot3StatsAlignmentErrors++;
1109 if (rsr & ED_RSR_FO)
1110 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
1111 ifp->if_ierrors++;
1112#ifdef ED_DEBUG
1113 if_printf(ifp, "receive error %x\n",
1114 ed_nic_inb(sc, ED_P0_RSR));
1115#endif
1116 }
1117
1118 /*
1119 * Go get the packet(s) XXX - Doing this on an
1120 * error is dubious because there shouldn't be
1121 * any data to get (we've configured the
1122 * interface to not accept packets with
1123 * errors).
1124 */
1125
1126 /*
1127 * Enable 16bit access to shared memory first
1128 * on WD/SMC boards.
1129 */
1130 if (sc->isa16bit &&
1131 (sc->vendor == ED_VENDOR_WD_SMC)) {
1132
1133 ed_asic_outb(sc, ED_WD_LAAR,
1134 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
1135 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
1136 ed_asic_outb(sc, ED_WD_MSR,
1137 ED_WD_MSR_MENB);
1138 }
1139 }
1140 ed_rint(sc);
1141
1142 /* disable 16bit access */
1143 if (sc->isa16bit &&
1144 (sc->vendor == ED_VENDOR_WD_SMC)) {
1145
1146 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
1147 ed_asic_outb(sc, ED_WD_MSR, 0x00);
1148 }
1149 ed_asic_outb(sc, ED_WD_LAAR,
1150 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
1151 }
1152 }
1153 }
1154
1155 /*
1156 * If it looks like the transmitter can take more data,
1157 * attempt to start output on the interface. This is done
1158 * after handling the receiver to give the receiver priority.
1159 */
1160 if ((ifp->if_flags & IFF_OACTIVE) == 0)
1161 ed_start(ifp);
1162
1163 /*
1164 * return NIC CR to standard state: page 0, remote DMA
1165 * complete, start (toggling the TXP bit off, even if was just
1166 * set in the transmit routine, is *okay* - it is 'edge'
1167 * triggered from low to high)
1168 */
1169 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1170
1171 /*
1172 * If the Network Talley Counters overflow, read them to reset
1173 * them. It appears that old 8390's won't clear the ISR flag
1174 * otherwise - resulting in an infinite loop.
1175 */
1176 if (isr & ED_ISR_CNT) {
1177 (void) ed_nic_inb(sc, ED_P0_CNTR0);
1178 (void) ed_nic_inb(sc, ED_P0_CNTR1);
1179 (void) ed_nic_inb(sc, ED_P0_CNTR2);
1180 }
1181 }
1182}
1183
1184/*
1185 * Process an ioctl request.
1186 */
1187static int
1188ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1189{
1190 struct ed_softc *sc = ifp->if_softc;
1191#ifndef ED_NO_MIIBUS
1192 struct ifreq *ifr = (struct ifreq *)data;
1193 struct mii_data *mii;
1194#endif
1195 int s, error = 0;
1196
1197 if (sc == NULL || sc->gone) {
1198 ifp->if_flags &= ~IFF_RUNNING;
1199 return ENXIO;
1200 }
1201 s = splimp();
1202
1203 switch (command) {
1204 case SIOCSIFFLAGS:
1205
1206 /*
1207 * If the interface is marked up and stopped, then start it.
1208 * If it is marked down and running, then stop it.
1209 */
1210 if (ifp->if_flags & IFF_UP) {
1211 if ((ifp->if_flags & IFF_RUNNING) == 0)
1212 ed_init(sc);
1213 } else {
1214 if (ifp->if_flags & IFF_RUNNING) {
1215 ed_stop(sc);
1216 ifp->if_flags &= ~IFF_RUNNING;
1217 }
1218 }
1219
1220 /*
1221 * Promiscuous flag may have changed, so reprogram the RCR.
1222 */
1223 ed_setrcr(sc);
1224
1225 /*
1226 * An unfortunate hack to provide the (required) software
1227 * control of the tranceiver for 3Com boards. The ALTPHYS flag
1228 * disables the tranceiver if set.
1229 */
1230 if (sc->vendor == ED_VENDOR_3COM) {
1231 if (ifp->if_flags & IFF_ALTPHYS) {
1232 ed_asic_outb(sc, ED_3COM_CR, 0);
1233 } else {
1234 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1235 }
|
2675 } else if (sc->vendor == ED_VENDOR_HP)
| 1236 }
1237#ifdef ED_HPP
1238 else if (sc->vendor == ED_VENDOR_HP)
|
2676 ed_hpp_set_physical_link(sc);
| 1239 ed_hpp_set_physical_link(sc);
|
| 1240#endif
|
2677 break;
2678
2679 case SIOCADDMULTI:
2680 case SIOCDELMULTI:
2681 /*
2682 * Multicast list has changed; set the hardware filter
2683 * accordingly.
2684 */
2685 ed_setrcr(sc);
2686 error = 0;
2687 break;
2688
2689#ifndef ED_NO_MIIBUS
2690 case SIOCGIFMEDIA:
2691 case SIOCSIFMEDIA:
2692 if (sc->miibus == NULL) {
2693 error = EINVAL;
2694 break;
2695 }
2696 mii = device_get_softc(sc->miibus);
2697 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2698 break;
2699#endif
2700
2701 default:
2702 error = ether_ioctl(ifp, command, data);
2703 }
2704 (void) splx(s);
2705 return (error);
2706}
2707
2708/*
2709 * Given a source and destination address, copy 'amount' of a packet from
2710 * the ring buffer into a linear destination buffer. Takes into account
2711 * ring-wrap.
2712 */
2713static __inline char *
2714ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
2715{
2716 u_short tmp_amount;
2717
2718 /* does copy wrap to lower addr in ring buffer? */
2719 if (src + amount > sc->mem_end) {
2720 tmp_amount = sc->mem_end - src;
2721
2722 /* copy amount up to end of NIC memory */
2723 if (sc->mem_shared)
2724 bcopy(src, dst, tmp_amount);
2725 else
2726 ed_pio_readmem(sc, (uintptr_t)src, dst, tmp_amount);
2727
2728 amount -= tmp_amount;
2729 src = sc->mem_ring;
2730 dst += tmp_amount;
2731 }
2732 if (sc->mem_shared)
2733 bcopy(src, dst, amount);
2734 else
2735 ed_pio_readmem(sc, (uintptr_t)src, dst, amount);
2736
2737 return (src + amount);
2738}
2739
2740/*
2741 * Retreive packet from shared memory and send to the next level up via
2742 * ether_input().
2743 */
2744static void
2745ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
2746{
2747 struct ifnet *ifp = &sc->arpcom.ac_if;
2748 struct ether_header *eh;
2749 struct mbuf *m;
2750
2751 /* Allocate a header mbuf */
2752 MGETHDR(m, M_DONTWAIT, MT_DATA);
2753 if (m == NULL)
2754 return;
2755 m->m_pkthdr.rcvif = ifp;
2756 m->m_pkthdr.len = m->m_len = len;
2757
2758 /*
2759 * We always put the received packet in a single buffer -
2760 * either with just an mbuf header or in a cluster attached
2761 * to the header. The +2 is to compensate for the alignment
2762 * fixup below.
2763 */
2764 if ((len + 2) > MHLEN) {
2765 /* Attach an mbuf cluster */
2766 MCLGET(m, M_DONTWAIT);
2767
2768 /* Insist on getting a cluster */
2769 if ((m->m_flags & M_EXT) == 0) {
2770 m_freem(m);
2771 return;
2772 }
2773 }
2774
2775 /*
2776 * The +2 is to longword align the start of the real packet.
2777 * This is important for NFS.
2778 */
2779 m->m_data += 2;
2780 eh = mtod(m, struct ether_header *);
2781
2782 /*
2783 * Get packet, including link layer address, from interface.
2784 */
2785 ed_ring_copy(sc, buf, (char *)eh, len);
2786
2787 m->m_pkthdr.len = m->m_len = len;
2788
2789 (*ifp->if_input)(ifp, m);
2790}
2791
2792/*
2793 * Supporting routines
2794 */
2795
2796/*
2797 * Given a NIC memory source address and a host memory destination
2798 * address, copy 'amount' from NIC to host using Programmed I/O.
2799 * The 'amount' is rounded up to a word - okay as long as mbufs
2800 * are word sized.
2801 * This routine is currently Novell-specific.
2802 */
2803void
2804ed_pio_readmem(struct ed_softc *sc, long src, uint8_t *dst, uint16_t amount)
2805{
| 1241 break;
1242
1243 case SIOCADDMULTI:
1244 case SIOCDELMULTI:
1245 /*
1246 * Multicast list has changed; set the hardware filter
1247 * accordingly.
1248 */
1249 ed_setrcr(sc);
1250 error = 0;
1251 break;
1252
1253#ifndef ED_NO_MIIBUS
1254 case SIOCGIFMEDIA:
1255 case SIOCSIFMEDIA:
1256 if (sc->miibus == NULL) {
1257 error = EINVAL;
1258 break;
1259 }
1260 mii = device_get_softc(sc->miibus);
1261 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1262 break;
1263#endif
1264
1265 default:
1266 error = ether_ioctl(ifp, command, data);
1267 }
1268 (void) splx(s);
1269 return (error);
1270}
1271
1272/*
1273 * Given a source and destination address, copy 'amount' of a packet from
1274 * the ring buffer into a linear destination buffer. Takes into account
1275 * ring-wrap.
1276 */
1277static __inline char *
1278ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
1279{
1280 u_short tmp_amount;
1281
1282 /* does copy wrap to lower addr in ring buffer? */
1283 if (src + amount > sc->mem_end) {
1284 tmp_amount = sc->mem_end - src;
1285
1286 /* copy amount up to end of NIC memory */
1287 if (sc->mem_shared)
1288 bcopy(src, dst, tmp_amount);
1289 else
1290 ed_pio_readmem(sc, (uintptr_t)src, dst, tmp_amount);
1291
1292 amount -= tmp_amount;
1293 src = sc->mem_ring;
1294 dst += tmp_amount;
1295 }
1296 if (sc->mem_shared)
1297 bcopy(src, dst, amount);
1298 else
1299 ed_pio_readmem(sc, (uintptr_t)src, dst, amount);
1300
1301 return (src + amount);
1302}
1303
1304/*
1305 * Retreive packet from shared memory and send to the next level up via
1306 * ether_input().
1307 */
1308static void
1309ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
1310{
1311 struct ifnet *ifp = &sc->arpcom.ac_if;
1312 struct ether_header *eh;
1313 struct mbuf *m;
1314
1315 /* Allocate a header mbuf */
1316 MGETHDR(m, M_DONTWAIT, MT_DATA);
1317 if (m == NULL)
1318 return;
1319 m->m_pkthdr.rcvif = ifp;
1320 m->m_pkthdr.len = m->m_len = len;
1321
1322 /*
1323 * We always put the received packet in a single buffer -
1324 * either with just an mbuf header or in a cluster attached
1325 * to the header. The +2 is to compensate for the alignment
1326 * fixup below.
1327 */
1328 if ((len + 2) > MHLEN) {
1329 /* Attach an mbuf cluster */
1330 MCLGET(m, M_DONTWAIT);
1331
1332 /* Insist on getting a cluster */
1333 if ((m->m_flags & M_EXT) == 0) {
1334 m_freem(m);
1335 return;
1336 }
1337 }
1338
1339 /*
1340 * The +2 is to longword align the start of the real packet.
1341 * This is important for NFS.
1342 */
1343 m->m_data += 2;
1344 eh = mtod(m, struct ether_header *);
1345
1346 /*
1347 * Get packet, including link layer address, from interface.
1348 */
1349 ed_ring_copy(sc, buf, (char *)eh, len);
1350
1351 m->m_pkthdr.len = m->m_len = len;
1352
1353 (*ifp->if_input)(ifp, m);
1354}
1355
1356/*
1357 * Supporting routines
1358 */
1359
1360/*
1361 * Given a NIC memory source address and a host memory destination
1362 * address, copy 'amount' from NIC to host using Programmed I/O.
1363 * The 'amount' is rounded up to a word - okay as long as mbufs
1364 * are word sized.
1365 * This routine is currently Novell-specific.
1366 */
1367void
1368ed_pio_readmem(struct ed_softc *sc, long src, uint8_t *dst, uint16_t amount)
1369{
|
| 1370#ifdef ED_HPP
|
2806 /* HP PC Lan+ cards need special handling */
2807 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2808 ed_hpp_readmem(sc, src, dst, amount);
2809 return;
2810 }
| 1371 /* HP PC Lan+ cards need special handling */
1372 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
1373 ed_hpp_readmem(sc, src, dst, amount);
1374 return;
1375 }
|
| 1376#endif
|
2811
2812 /* Regular Novell cards */
2813 /* select page 0 registers */
2814 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2815
2816 /* round up to a word */
2817 if (amount & 1)
2818 ++amount;
2819
2820 /* set up DMA byte count */
2821 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2822 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2823
2824 /* set up source address in NIC mem */
2825 ed_nic_outb(sc, ED_P0_RSAR0, src);
2826 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2827
2828 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2829
2830 if (sc->isa16bit) {
2831 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2832 } else {
2833 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2834 }
2835}
2836
2837/*
2838 * Stripped down routine for writing a linear buffer to NIC memory.
2839 * Only used in the probe routine to test the memory. 'len' must
2840 * be even.
2841 */
2842void
2843ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
2844{
2845 int maxwait = 200; /* about 240us */
2846
2847 /* select page 0 registers */
2848 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2849
2850 /* reset remote DMA complete flag */
2851 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2852
2853 /* set up DMA byte count */
2854 ed_nic_outb(sc, ED_P0_RBCR0, len);
2855 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2856
2857 /* set up destination address in NIC mem */
2858 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2859 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2860
2861 /* set remote DMA write */
2862 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2863
2864 if (sc->isa16bit) {
2865 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2866 } else {
2867 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2868 }
2869
2870 /*
2871 * Wait for remote DMA complete. This is necessary because on the
2872 * transmit side, data is handled internally by the NIC in bursts and
2873 * we can't start another remote DMA until this one completes. Not
2874 * waiting causes really bad things to happen - like the NIC
2875 * irrecoverably jamming the ISA bus.
2876 */
2877 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2878}
2879
2880/*
2881 * Write an mbuf chain to the destination NIC memory address using
2882 * programmed I/O.
2883 */
2884static u_short
2885ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, long dst)
2886{
2887 struct ifnet *ifp = (struct ifnet *)sc;
2888 unsigned short total_len, dma_len;
2889 struct mbuf *mp;
2890 int maxwait = 200; /* about 240us */
2891
| 1377
1378 /* Regular Novell cards */
1379 /* select page 0 registers */
1380 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1381
1382 /* round up to a word */
1383 if (amount & 1)
1384 ++amount;
1385
1386 /* set up DMA byte count */
1387 ed_nic_outb(sc, ED_P0_RBCR0, amount);
1388 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
1389
1390 /* set up source address in NIC mem */
1391 ed_nic_outb(sc, ED_P0_RSAR0, src);
1392 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
1393
1394 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
1395
1396 if (sc->isa16bit) {
1397 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
1398 } else {
1399 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
1400 }
1401}
1402
1403/*
1404 * Stripped down routine for writing a linear buffer to NIC memory.
1405 * Only used in the probe routine to test the memory. 'len' must
1406 * be even.
1407 */
1408void
1409ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
1410{
1411 int maxwait = 200; /* about 240us */
1412
1413 /* select page 0 registers */
1414 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1415
1416 /* reset remote DMA complete flag */
1417 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1418
1419 /* set up DMA byte count */
1420 ed_nic_outb(sc, ED_P0_RBCR0, len);
1421 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
1422
1423 /* set up destination address in NIC mem */
1424 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1425 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1426
1427 /* set remote DMA write */
1428 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1429
1430 if (sc->isa16bit) {
1431 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
1432 } else {
1433 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
1434 }
1435
1436 /*
1437 * Wait for remote DMA complete. This is necessary because on the
1438 * transmit side, data is handled internally by the NIC in bursts and
1439 * we can't start another remote DMA until this one completes. Not
1440 * waiting causes really bad things to happen - like the NIC
1441 * irrecoverably jamming the ISA bus.
1442 */
1443 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
1444}
1445
1446/*
1447 * Write an mbuf chain to the destination NIC memory address using
1448 * programmed I/O.
1449 */
1450static u_short
1451ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, long dst)
1452{
1453 struct ifnet *ifp = (struct ifnet *)sc;
1454 unsigned short total_len, dma_len;
1455 struct mbuf *mp;
1456 int maxwait = 200; /* about 240us */
1457
|
| 1458#ifdef ED_HPP
|
2892 /* HP PC Lan+ cards need special handling */
| 1459 /* HP PC Lan+ cards need special handling */
|
2893 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
| 1460 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS)
|
2894 return ed_hpp_write_mbufs(sc, m, dst);
| 1461 return ed_hpp_write_mbufs(sc, m, dst);
|
2895 }
| 1462#endif
|
2896
2897 /* Regular Novell cards */
2898 /* First, count up the total number of bytes to copy */
2899 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2900 total_len += mp->m_len;
2901
2902 dma_len = total_len;
2903 if (sc->isa16bit && (dma_len & 1))
2904 dma_len++;
2905
2906 /* select page 0 registers */
2907 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2908
2909 /* reset remote DMA complete flag */
2910 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2911
2912 /* set up DMA byte count */
2913 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2914 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2915
2916 /* set up destination address in NIC mem */
2917 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2918 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2919
2920 /* set remote DMA write */
2921 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2922
2923 /*
2924 * Transfer the mbuf chain to the NIC memory.
2925 * 16-bit cards require that data be transferred as words, and only words.
2926 * So that case requires some extra code to patch over odd-length mbufs.
2927 */
2928
2929 if (!sc->isa16bit) {
2930 /* NE1000s are easy */
2931 while (m) {
2932 if (m->m_len) {
2933 ed_asic_outsb(sc, ED_NOVELL_DATA,
2934 m->m_data, m->m_len);
2935 }
2936 m = m->m_next;
2937 }
2938 } else {
2939 /* NE2000s are a pain */
2940 unsigned char *data;
2941 int len, wantbyte;
2942 unsigned char savebyte[2];
2943
2944 wantbyte = 0;
2945
2946 while (m) {
2947 len = m->m_len;
2948 if (len) {
2949 data = mtod(m, caddr_t);
2950 /* finish the last word */
2951 if (wantbyte) {
2952 savebyte[1] = *data;
2953 ed_asic_outw(sc, ED_NOVELL_DATA,
2954 *(u_short *)savebyte);
2955 data++;
2956 len--;
2957 wantbyte = 0;
2958 }
2959 /* output contiguous words */
2960 if (len > 1) {
2961 ed_asic_outsw(sc, ED_NOVELL_DATA,
2962 data, len >> 1);
2963 data += len & ~1;
2964 len &= 1;
2965 }
2966 /* save last byte, if necessary */
2967 if (len == 1) {
2968 savebyte[0] = *data;
2969 wantbyte = 1;
2970 }
2971 }
2972 m = m->m_next;
2973 }
2974 /* spit last byte */
2975 if (wantbyte) {
2976 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2977 }
2978 }
2979
2980 /*
2981 * Wait for remote DMA complete. This is necessary because on the
2982 * transmit side, data is handled internally by the NIC in bursts and
2983 * we can't start another remote DMA until this one completes. Not
2984 * waiting causes really bad things to happen - like the NIC
2985 * irrecoverably jamming the ISA bus.
2986 */
2987 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2988
2989 if (!maxwait) {
2990 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
2991 ifp->if_xname);
2992 ed_reset(ifp);
2993 return(0);
2994 }
2995 return (total_len);
2996}
2997
| 1463
1464 /* Regular Novell cards */
1465 /* First, count up the total number of bytes to copy */
1466 for (total_len = 0, mp = m; mp; mp = mp->m_next)
1467 total_len += mp->m_len;
1468
1469 dma_len = total_len;
1470 if (sc->isa16bit && (dma_len & 1))
1471 dma_len++;
1472
1473 /* select page 0 registers */
1474 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
1475
1476 /* reset remote DMA complete flag */
1477 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
1478
1479 /* set up DMA byte count */
1480 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
1481 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
1482
1483 /* set up destination address in NIC mem */
1484 ed_nic_outb(sc, ED_P0_RSAR0, dst);
1485 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
1486
1487 /* set remote DMA write */
1488 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
1489
1490 /*
1491 * Transfer the mbuf chain to the NIC memory.
1492 * 16-bit cards require that data be transferred as words, and only words.
1493 * So that case requires some extra code to patch over odd-length mbufs.
1494 */
1495
1496 if (!sc->isa16bit) {
1497 /* NE1000s are easy */
1498 while (m) {
1499 if (m->m_len) {
1500 ed_asic_outsb(sc, ED_NOVELL_DATA,
1501 m->m_data, m->m_len);
1502 }
1503 m = m->m_next;
1504 }
1505 } else {
1506 /* NE2000s are a pain */
1507 unsigned char *data;
1508 int len, wantbyte;
1509 unsigned char savebyte[2];
1510
1511 wantbyte = 0;
1512
1513 while (m) {
1514 len = m->m_len;
1515 if (len) {
1516 data = mtod(m, caddr_t);
1517 /* finish the last word */
1518 if (wantbyte) {
1519 savebyte[1] = *data;
1520 ed_asic_outw(sc, ED_NOVELL_DATA,
1521 *(u_short *)savebyte);
1522 data++;
1523 len--;
1524 wantbyte = 0;
1525 }
1526 /* output contiguous words */
1527 if (len > 1) {
1528 ed_asic_outsw(sc, ED_NOVELL_DATA,
1529 data, len >> 1);
1530 data += len & ~1;
1531 len &= 1;
1532 }
1533 /* save last byte, if necessary */
1534 if (len == 1) {
1535 savebyte[0] = *data;
1536 wantbyte = 1;
1537 }
1538 }
1539 m = m->m_next;
1540 }
1541 /* spit last byte */
1542 if (wantbyte) {
1543 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
1544 }
1545 }
1546
1547 /*
1548 * Wait for remote DMA complete. This is necessary because on the
1549 * transmit side, data is handled internally by the NIC in bursts and
1550 * we can't start another remote DMA until this one completes. Not
1551 * waiting causes really bad things to happen - like the NIC
1552 * irrecoverably jamming the ISA bus.
1553 */
1554 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
1555
1556 if (!maxwait) {
1557 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
1558 ifp->if_xname);
1559 ed_reset(ifp);
1560 return(0);
1561 }
1562 return (total_len);
1563}
1564
|
2998/*
2999 * Support routines to handle the HP PC Lan+ card.
3000 */
3001
3002/*
3003 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3004 * IO.
3005 */
3006
3007static void
3008ed_hpp_readmem(struct ed_softc *sc, long src, uint8_t *dst, uint16_t amount)
3009{
3010
3011 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3012
3013
3014 /* Program the source address in RAM */
3015 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3016
3017 /*
3018 * The HP PC Lan+ card supports word reads as well as
3019 * a memory mapped i/o port that is aliased to every
3020 * even address on the board.
3021 */
3022
3023 if (sc->hpp_mem_start) {
3024
3025 /* Enable memory mapped access. */
3026 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3027 ~(ED_HPP_OPTION_MEM_DISABLE |
3028 ED_HPP_OPTION_BOOT_ROM_ENB));
3029
3030 if (use_32bit_access && (amount > 3)) {
3031 uint32_t *dl = (uint32_t *) dst;
3032 volatile uint32_t *const sl =
3033 (uint32_t *) sc->hpp_mem_start;
3034 uint32_t *const fence = dl + (amount >> 2);
3035
3036 /* Copy out NIC data. We could probably write this
3037 as a `movsl'. The currently generated code is lousy.
3038 */
3039
3040 while (dl < fence)
3041 *dl++ = *sl;
3042
3043 dst += (amount & ~3);
3044 amount &= 3;
3045
3046 }
3047
3048 /* Finish off any words left, as a series of short reads */
3049 if (amount > 1) {
3050 u_short *d = (u_short *) dst;
3051 volatile u_short *const s =
3052 (u_short *) sc->hpp_mem_start;
3053 u_short *const fence = d + (amount >> 1);
3054
3055 /* Copy out NIC data. */
3056
3057 while (d < fence)
3058 *d++ = *s;
3059
3060 dst += (amount & ~1);
3061 amount &= 1;
3062 }
3063
3064 /*
3065 * read in a byte; however we need to always read 16 bits
3066 * at a time or the hardware gets into a funny state
3067 */
3068
3069 if (amount == 1) {
3070 /* need to read in a short and copy LSB */
3071 volatile u_short *const s =
3072 (volatile u_short *) sc->hpp_mem_start;
3073
3074 *dst = (*s) & 0xFF;
3075 }
3076
3077 /* Restore Boot ROM access. */
3078
3079 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3080
3081
3082 } else {
3083 /* Read in data using the I/O port */
3084 if (use_32bit_access && (amount > 3)) {
3085 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3086 dst += (amount & ~3);
3087 amount &= 3;
3088 }
3089 if (amount > 1) {
3090 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3091 dst += (amount & ~1);
3092 amount &= 1;
3093 }
3094 if (amount == 1) { /* read in a short and keep the LSB */
3095 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3096 }
3097 }
3098}
3099
3100/*
3101 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3102 * IO.
3103 * Only used in the probe routine to test the memory. 'len' must
3104 * be even.
3105 */
3106static void
3107ed_hpp_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len)
3108{
3109 /* reset remote DMA complete flag */
3110 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3111
3112 /* program the write address in RAM */
3113 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3114
3115 if (sc->hpp_mem_start) {
3116 u_short *s = (u_short *) src;
3117 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3118 u_short *const fence = s + (len >> 1);
3119
3120 /*
3121 * Enable memory mapped access.
3122 */
3123
3124 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3125 ~(ED_HPP_OPTION_MEM_DISABLE |
3126 ED_HPP_OPTION_BOOT_ROM_ENB));
3127
3128 /*
3129 * Copy to NIC memory.
3130 */
3131
3132 while (s < fence)
3133 *d = *s++;
3134
3135 /*
3136 * Restore Boot ROM access.
3137 */
3138
3139 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3140
3141 } else {
3142 /* write data using I/O writes */
3143 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3144 }
3145}
3146
3147/*
3148 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3149 * outsw() or via the memory mapped interface to the same register.
3150 * Writes have to be in word units; byte accesses won't work and may cause
3151 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3152 * allows it.
3153 */
3154
3155static u_short
3156ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3157{
3158 int len, wantbyte;
3159 unsigned short total_len;
3160 unsigned char savebyte[2];
3161 volatile u_short * const d =
3162 (volatile u_short *) sc->hpp_mem_start;
3163 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3164
3165 /* select page 0 registers */
3166 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3167
3168 /* reset remote DMA complete flag */
3169 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3170
3171 /* program the write address in RAM */
3172 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3173
3174 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3175 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3176 ~(ED_HPP_OPTION_MEM_DISABLE |
3177 ED_HPP_OPTION_BOOT_ROM_ENB));
3178
3179 wantbyte = 0;
3180 total_len = 0;
3181
3182 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3183 while (m) {
3184 total_len += (len = m->m_len);
3185 if (len) {
3186 caddr_t data = mtod(m, caddr_t);
3187 /* finish the last word of the previous mbuf */
3188 if (wantbyte) {
3189 savebyte[1] = *data;
3190 *d = *((u_short *) savebyte);
3191 data++; len--; wantbyte = 0;
3192 }
3193 /* output contiguous words */
3194 if ((len > 3) && (use_32bit_accesses)) {
3195 volatile uint32_t *const dl =
3196 (volatile uint32_t *) d;
3197 uint32_t *sl = (uint32_t *) data;
3198 uint32_t *fence = sl + (len >> 2);
3199
3200 while (sl < fence)
3201 *dl = *sl++;
3202
3203 data += (len & ~3);
3204 len &= 3;
3205 }
3206 /* finish off remain 16 bit writes */
3207 if (len > 1) {
3208 u_short *s = (u_short *) data;
3209 u_short *fence = s + (len >> 1);
3210
3211 while (s < fence)
3212 *d = *s++;
3213
3214 data += (len & ~1);
3215 len &= 1;
3216 }
3217 /* save last byte if needed */
3218 if ((wantbyte = (len == 1)) != 0)
3219 savebyte[0] = *data;
3220 }
3221 m = m->m_next; /* to next mbuf */
3222 }
3223 if (wantbyte) /* write last byte */
3224 *d = *((u_short *) savebyte);
3225 } else {
3226 /* use programmed I/O */
3227 while (m) {
3228 total_len += (len = m->m_len);
3229 if (len) {
3230 caddr_t data = mtod(m, caddr_t);
3231 /* finish the last word of the previous mbuf */
3232 if (wantbyte) {
3233 savebyte[1] = *data;
3234 ed_asic_outw(sc, ED_HPP_PAGE_4,
3235 *((u_short *)savebyte));
3236 data++;
3237 len--;
3238 wantbyte = 0;
3239 }
3240 /* output contiguous words */
3241 if ((len > 3) && use_32bit_accesses) {
3242 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3243 data, len >> 2);
3244 data += (len & ~3);
3245 len &= 3;
3246 }
3247 /* finish off remaining 16 bit accesses */
3248 if (len > 1) {
3249 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3250 data, len >> 1);
3251 data += (len & ~1);
3252 len &= 1;
3253 }
3254 if ((wantbyte = (len == 1)) != 0)
3255 savebyte[0] = *data;
3256
3257 } /* if len != 0 */
3258 m = m->m_next;
3259 }
3260 if (wantbyte) /* spit last byte */
3261 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3262
3263 }
3264
3265 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3266 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3267
3268 return (total_len);
3269}
3270
| |
3271#ifndef ED_NO_MIIBUS
3272/*
3273 * MII bus support routines.
3274 */
3275int
3276ed_miibus_readreg(device_t dev, int phy, int reg)
3277{
3278 struct ed_softc *sc;
3279 int failed, s, val;
3280
3281 s = splimp();
3282 sc = device_get_softc(dev);
3283 if (sc->gone) {
3284 splx(s);
3285 return (0);
3286 }
3287
3288 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3289 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3290 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3291 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3292 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3293
3294 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3295 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3296 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3297
3298 splx(s);
3299 return (failed ? 0 : val);
3300}
3301
3302void
3303ed_miibus_writereg(device_t dev, int phy, int reg, int data)
3304{
3305 struct ed_softc *sc;
3306 int s;
3307
3308 s = splimp();
3309 sc = device_get_softc(dev);
3310 if (sc->gone) {
3311 splx(s);
3312 return;
3313 }
3314
3315 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3316 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3317 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3318 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3319 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3320 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3321 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3322 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3323
3324 splx(s);
3325}
3326
3327int
3328ed_ifmedia_upd(struct ifnet *ifp)
3329{
3330 struct ed_softc *sc;
3331 struct mii_data *mii;
3332
3333 sc = ifp->if_softc;
3334 if (sc->gone || sc->miibus == NULL)
3335 return (ENXIO);
3336
3337 mii = device_get_softc(sc->miibus);
3338 return mii_mediachg(mii);
3339}
3340
3341void
3342ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3343{
3344 struct ed_softc *sc;
3345 struct mii_data *mii;
3346
3347 sc = ifp->if_softc;
3348 if (sc->gone || sc->miibus == NULL)
3349 return;
3350
3351 mii = device_get_softc(sc->miibus);
3352 mii_pollstat(mii);
3353 ifmr->ifm_active = mii->mii_media_active;
3354 ifmr->ifm_status = mii->mii_media_status;
3355}
3356
3357void
3358ed_child_detached(device_t dev, device_t child)
3359{
3360 struct ed_softc *sc;
3361
3362 sc = device_get_softc(dev);
3363 if (child == sc->miibus)
3364 sc->miibus = NULL;
3365}
3366#endif
3367
3368static void
3369ed_setrcr(struct ed_softc *sc)
3370{
3371 struct ifnet *ifp = (struct ifnet *)sc;
3372 int i;
3373 u_char reg1;
3374
3375 /* Bit 6 in AX88190 RCR register must be set. */
3376 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3377 reg1 = ED_RCR_INTT;
3378 else
3379 reg1 = 0x00;
3380
3381 /* set page 1 registers */
3382 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3383
3384 if (ifp->if_flags & IFF_PROMISC) {
3385
3386 /*
3387 * Reconfigure the multicast filter.
3388 */
3389 for (i = 0; i < 8; i++)
3390 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3391
3392 /*
3393 * And turn on promiscuous mode. Also enable reception of
3394 * runts and packets with CRC & alignment errors.
3395 */
3396 /* Set page 0 registers */
3397 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3398
3399 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3400 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3401 } else {
3402 /* set up multicast addresses and filter modes */
3403 if (ifp->if_flags & IFF_MULTICAST) {
3404 uint32_t mcaf[2];
3405
3406 if (ifp->if_flags & IFF_ALLMULTI) {
3407 mcaf[0] = 0xffffffff;
3408 mcaf[1] = 0xffffffff;
3409 } else
3410 ed_ds_getmcaf(sc, mcaf);
3411
3412 /*
3413 * Set multicast filter on chip.
3414 */
3415 for (i = 0; i < 8; i++)
3416 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3417
3418 /* Set page 0 registers */
3419 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3420
3421 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3422 } else {
3423
3424 /*
3425 * Initialize multicast address hashing registers to
3426 * not accept multicasts.
3427 */
3428 for (i = 0; i < 8; ++i)
3429 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3430
3431 /* Set page 0 registers */
3432 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3433
3434 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3435 }
3436 }
3437
3438 /*
3439 * Start interface.
3440 */
3441 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3442}
3443
3444/*
3445 * Compute the multicast address filter from the
3446 * list of multicast addresses we need to listen to.
3447 */
3448static void
3449ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
3450{
3451 uint32_t index;
3452 u_char *af = (u_char *) mcaf;
3453 struct ifmultiaddr *ifma;
3454
3455 mcaf[0] = 0;
3456 mcaf[1] = 0;
3457
3458 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
3459 if (ifma->ifma_addr->sa_family != AF_LINK)
3460 continue;
3461 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3462 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
3463 af[index >> 3] |= 1 << (index & 7);
3464 }
3465}
3466
3467int
| 1565#ifndef ED_NO_MIIBUS
1566/*
1567 * MII bus support routines.
1568 */
1569int
1570ed_miibus_readreg(device_t dev, int phy, int reg)
1571{
1572 struct ed_softc *sc;
1573 int failed, s, val;
1574
1575 s = splimp();
1576 sc = device_get_softc(dev);
1577 if (sc->gone) {
1578 splx(s);
1579 return (0);
1580 }
1581
1582 (*sc->mii_writebits)(sc, 0xffffffff, 32);
1583 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
1584 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
1585 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
1586 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
1587
1588 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
1589 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
1590 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
1591
1592 splx(s);
1593 return (failed ? 0 : val);
1594}
1595
1596void
1597ed_miibus_writereg(device_t dev, int phy, int reg, int data)
1598{
1599 struct ed_softc *sc;
1600 int s;
1601
1602 s = splimp();
1603 sc = device_get_softc(dev);
1604 if (sc->gone) {
1605 splx(s);
1606 return;
1607 }
1608
1609 (*sc->mii_writebits)(sc, 0xffffffff, 32);
1610 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
1611 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
1612 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
1613 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
1614 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
1615 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
1616 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
1617
1618 splx(s);
1619}
1620
1621int
1622ed_ifmedia_upd(struct ifnet *ifp)
1623{
1624 struct ed_softc *sc;
1625 struct mii_data *mii;
1626
1627 sc = ifp->if_softc;
1628 if (sc->gone || sc->miibus == NULL)
1629 return (ENXIO);
1630
1631 mii = device_get_softc(sc->miibus);
1632 return mii_mediachg(mii);
1633}
1634
1635void
1636ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1637{
1638 struct ed_softc *sc;
1639 struct mii_data *mii;
1640
1641 sc = ifp->if_softc;
1642 if (sc->gone || sc->miibus == NULL)
1643 return;
1644
1645 mii = device_get_softc(sc->miibus);
1646 mii_pollstat(mii);
1647 ifmr->ifm_active = mii->mii_media_active;
1648 ifmr->ifm_status = mii->mii_media_status;
1649}
1650
1651void
1652ed_child_detached(device_t dev, device_t child)
1653{
1654 struct ed_softc *sc;
1655
1656 sc = device_get_softc(dev);
1657 if (child == sc->miibus)
1658 sc->miibus = NULL;
1659}
1660#endif
1661
1662static void
1663ed_setrcr(struct ed_softc *sc)
1664{
1665 struct ifnet *ifp = (struct ifnet *)sc;
1666 int i;
1667 u_char reg1;
1668
1669 /* Bit 6 in AX88190 RCR register must be set. */
1670 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
1671 reg1 = ED_RCR_INTT;
1672 else
1673 reg1 = 0x00;
1674
1675 /* set page 1 registers */
1676 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1677
1678 if (ifp->if_flags & IFF_PROMISC) {
1679
1680 /*
1681 * Reconfigure the multicast filter.
1682 */
1683 for (i = 0; i < 8; i++)
1684 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
1685
1686 /*
1687 * And turn on promiscuous mode. Also enable reception of
1688 * runts and packets with CRC & alignment errors.
1689 */
1690 /* Set page 0 registers */
1691 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1692
1693 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
1694 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
1695 } else {
1696 /* set up multicast addresses and filter modes */
1697 if (ifp->if_flags & IFF_MULTICAST) {
1698 uint32_t mcaf[2];
1699
1700 if (ifp->if_flags & IFF_ALLMULTI) {
1701 mcaf[0] = 0xffffffff;
1702 mcaf[1] = 0xffffffff;
1703 } else
1704 ed_ds_getmcaf(sc, mcaf);
1705
1706 /*
1707 * Set multicast filter on chip.
1708 */
1709 for (i = 0; i < 8; i++)
1710 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
1711
1712 /* Set page 0 registers */
1713 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1714
1715 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
1716 } else {
1717
1718 /*
1719 * Initialize multicast address hashing registers to
1720 * not accept multicasts.
1721 */
1722 for (i = 0; i < 8; ++i)
1723 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
1724
1725 /* Set page 0 registers */
1726 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1727
1728 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
1729 }
1730 }
1731
1732 /*
1733 * Start interface.
1734 */
1735 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1736}
1737
1738/*
1739 * Compute the multicast address filter from the
1740 * list of multicast addresses we need to listen to.
1741 */
1742static void
1743ed_ds_getmcaf(struct ed_softc *sc, uint32_t *mcaf)
1744{
1745 uint32_t index;
1746 u_char *af = (u_char *) mcaf;
1747 struct ifmultiaddr *ifma;
1748
1749 mcaf[0] = 0;
1750 mcaf[1] = 0;
1751
1752 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
1753 if (ifma->ifma_addr->sa_family != AF_LINK)
1754 continue;
1755 index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1756 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
1757 af[index >> 3] |= 1 << (index & 7);
1758 }
1759}
1760
1761int
|
| 1762ed_isa_mem_ok(device_t dev, u_long pmem, u_int memsize)
1763{
1764 if (pmem < 0xa0000 || pmem + memsize > 0x1000000) {
1765 device_printf(dev, "Invalid ISA memory address range "
1766 "configured: 0x%lx - 0x%lx\n", pmem, pmem + memsize);
1767 return (ENXIO);
1768 }
1769 return (0);
1770}
1771
1772int
|
3468ed_clear_memory(device_t dev)
3469{
3470 struct ed_softc *sc = device_get_softc(dev);
3471 int i;
3472
3473 /*
3474 * Now zero memory and verify that it is clear
3475 */
3476 bzero(sc->mem_start, sc->mem_size);
3477
3478 for (i = 0; i < sc->mem_size; ++i) {
3479 if (sc->mem_start[i]) {
3480 device_printf(dev, "failed to clear shared memory at "
3481 "0x%jx - check configuration\n",
3482 (uintmax_t)rman_get_start(sc->mem_res) + i);
3483 return (ENXIO);
3484 }
3485 }
3486 return (0);
3487}
| 1773ed_clear_memory(device_t dev)
1774{
1775 struct ed_softc *sc = device_get_softc(dev);
1776 int i;
1777
1778 /*
1779 * Now zero memory and verify that it is clear
1780 */
1781 bzero(sc->mem_start, sc->mem_size);
1782
1783 for (i = 0; i < sc->mem_size; ++i) {
1784 if (sc->mem_start[i]) {
1785 device_printf(dev, "failed to clear shared memory at "
1786 "0x%jx - check configuration\n",
1787 (uintmax_t)rman_get_start(sc->mem_res) + i);
1788 return (ENXIO);
1789 }
1790 }
1791 return (0);
1792}
|