1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/ed/if_ed.c 72193 2001-02-08 22:54:57Z luigi $
28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/sockio.h>
43#include <sys/mbuf.h>
44#include <sys/socket.h>
45#include <sys/syslog.h>
46
47#include <sys/bus.h>
48
49#include <machine/bus.h>
50#include <sys/rman.h>
51#include <machine/resource.h>
52
53#include <net/ethernet.h>
54#include <net/if.h>
55#include <net/if_arp.h>
56#include <net/if_dl.h>
57#include <net/if_mib.h>
58
59#include <net/bpf.h>
60#include "opt_bdg.h"
61#ifdef BRIDGE
62#include <net/bridge.h>
63#endif
64
65#include <machine/md_var.h>
66
67#include <dev/ed/if_edreg.h>
68#include <dev/ed/if_edvar.h>
69
70devclass_t ed_devclass;
71
72static void ed_init __P((void *));
73static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
74static void ed_start __P((struct ifnet *));
75static void ed_reset __P((struct ifnet *));
76static void ed_watchdog __P((struct ifnet *));
77
78static void ds_getmcaf __P((struct ed_softc *, u_int32_t *));
79
80static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
81
82static __inline void ed_rint __P((struct ed_softc *));
83static __inline void ed_xmit __P((struct ed_softc *));
84static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
85 /* u_short */ int));
86static void ed_hpp_set_physical_link __P((struct ed_softc *));
87static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
88 /* u_short */ int));
89static void ed_hpp_writemem __P((struct ed_softc *, unsigned char *,
90 /* u_short */ int, /* u_short */ int));
91static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
92 int));
93
94static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
95 int));
96
97static void ed_setrcr __P((struct ed_softc *));
98
99static u_int32_t ds_crc __P((u_char *ep));
100
101/*
102 * Interrupt conversion table for WD/SMC ASIC/83C584
103 */
104static unsigned short ed_intr_val[] = {
105 9,
106 3,
107 5,
108 7,
109 10,
110 11,
111 15,
112 4
113};
114
115/*
116 * Interrupt conversion table for 83C790
117 */
118static unsigned short ed_790_intr_val[] = {
119 0,
120 9,
121 3,
122 5,
123 7,
124 10,
125 11,
126 15
127};
128
129/*
130 * Interrupt conversion table for the HP PC LAN+
131 */
132
133static unsigned short ed_hpp_intr_val[] = {
134 0, /* 0 */
135 0, /* 1 */
136 0, /* 2 */
137 3, /* 3 */
138 4, /* 4 */
139 5, /* 5 */
140 6, /* 6 */
141 7, /* 7 */
142 0, /* 8 */
143 9, /* 9 */
144 10, /* 10 */
145 11, /* 11 */
146 12, /* 12 */
147 0, /* 13 */
148 0, /* 14 */
149 15 /* 15 */
150};
151
152/*
153 * Generic probe routine for testing for the existance of a DS8390.
154 * Must be called after the NIC has just been reset. This routine
155 * works by looking at certain register values that are guaranteed
156 * to be initialized a certain way after power-up or reset. Seems
157 * not to currently work on the 83C690.
158 *
159 * Specifically:
160 *
161 * Register reset bits set bits
162 * Command Register (CR) TXP, STA RD2, STP
163 * Interrupt Status (ISR) RST
164 * Interrupt Mask (IMR) All bits
165 * Data Control (DCR) LAS
166 * Transmit Config. (TCR) LB1, LB0
167 *
168 * We only look at the CR and ISR registers, however, because looking at
169 * the others would require changing register pages (which would be
170 * intrusive if this isn't an 8390).
171 *
172 * Return 1 if 8390 was found, 0 if not.
173 */
174
175int
176ed_probe_generic8390(sc)
177 struct ed_softc *sc;
178{
179 if ((ed_nic_inb(sc, ED_P0_CR) &
180 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
181 (ED_CR_RD2 | ED_CR_STP))
182 return (0);
183 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
184 return (0);
185
186 return (1);
187}
188
189/*
190 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
191 */
192int
193ed_probe_WD80x3_generic(dev, flags, intr_vals)
194 device_t dev;
195 int flags;
196 unsigned short *intr_vals[];
197{
198 struct ed_softc *sc = device_get_softc(dev);
199 int error;
200 int i;
201 u_int memsize, maddr;
202 u_char iptr, isa16bit, sum, totalsum;
203 u_long conf_maddr, conf_msize, irq, junk;
204
205 sc->chip_type = ED_CHIP_TYPE_DP8390;
206
207 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
208 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
209 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
210 DELAY(10000);
211 }
212 else
213 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
214
215 /*
216 * Attempt to do a checksum over the station address PROM. If it
217 * fails, it's probably not a SMC/WD board. There is a problem with
218 * this, though: some clone WD boards don't pass the checksum test.
219 * Danpex boards for one.
220 */
221 for (sum = 0, i = 0; i < 8; ++i)
222 sum += ed_asic_inb(sc, ED_WD_PROM + i);
223
224 if (sum != totalsum) {
225
226 /*
227 * Checksum is invalid. This often happens with cheap WD8003E
228 * clones. In this case, the checksum byte (the eighth byte)
229 * seems to always be zero.
230 */
231 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
232 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
233 return (ENXIO);
234 }
235 /* reset card to force it into a known state. */
236 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
237 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
238 else
239 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
240
241 DELAY(100);
242 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
243 /* wait in the case this card is reading its EEROM */
244 DELAY(5000);
245
246 sc->vendor = ED_VENDOR_WD_SMC;
247 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
248
249 /*
250 * Set initial values for width/size.
251 */
252 memsize = 8192;
253 isa16bit = 0;
254 switch (sc->type) {
255 case ED_TYPE_WD8003S:
256 sc->type_str = "WD8003S";
257 break;
258 case ED_TYPE_WD8003E:
259 sc->type_str = "WD8003E";
260 break;
261 case ED_TYPE_WD8003EB:
262 sc->type_str = "WD8003EB";
263 break;
264 case ED_TYPE_WD8003W:
265 sc->type_str = "WD8003W";
266 break;
267 case ED_TYPE_WD8013EBT:
268 sc->type_str = "WD8013EBT";
269 memsize = 16384;
270 isa16bit = 1;
271 break;
272 case ED_TYPE_WD8013W:
273 sc->type_str = "WD8013W";
274 memsize = 16384;
275 isa16bit = 1;
276 break;
277 case ED_TYPE_WD8013EP: /* also WD8003EP */
278 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
279 isa16bit = 1;
280 memsize = 16384;
281 sc->type_str = "WD8013EP";
282 } else {
283 sc->type_str = "WD8003EP";
284 }
285 break;
286 case ED_TYPE_WD8013WC:
287 sc->type_str = "WD8013WC";
288 memsize = 16384;
289 isa16bit = 1;
290 break;
291 case ED_TYPE_WD8013EBP:
292 sc->type_str = "WD8013EBP";
293 memsize = 16384;
294 isa16bit = 1;
295 break;
296 case ED_TYPE_WD8013EPC:
297 sc->type_str = "WD8013EPC";
298 memsize = 16384;
299 isa16bit = 1;
300 break;
301 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
302 case ED_TYPE_SMC8216T:
303 if (sc->type == ED_TYPE_SMC8216C) {
304 sc->type_str = "SMC8216/SMC8216C";
305 } else {
306 sc->type_str = "SMC8216T";
307 }
308
309 ed_asic_outb(sc, ED_WD790_HWR,
310 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
311 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
312 case ED_WD790_RAR_SZ64:
313 memsize = 65536;
314 break;
315 case ED_WD790_RAR_SZ32:
316 memsize = 32768;
317 break;
318 case ED_WD790_RAR_SZ16:
319 memsize = 16384;
320 break;
321 case ED_WD790_RAR_SZ8:
322 /* 8216 has 16K shared mem -- 8416 has 8K */
323 if (sc->type == ED_TYPE_SMC8216C) {
324 sc->type_str = "SMC8416C/SMC8416BT";
325 } else {
326 sc->type_str = "SMC8416T";
327 }
328 memsize = 8192;
329 break;
330 }
331 ed_asic_outb(sc, ED_WD790_HWR,
332 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
333
334 isa16bit = 1;
335 sc->chip_type = ED_CHIP_TYPE_WD790;
336 break;
337 case ED_TYPE_TOSHIBA1:
338 sc->type_str = "Toshiba1";
339 memsize = 32768;
340 isa16bit = 1;
341 break;
342 case ED_TYPE_TOSHIBA4:
343 sc->type_str = "Toshiba4";
344 memsize = 32768;
345 isa16bit = 1;
346 break;
347 default:
348 sc->type_str = "";
349 break;
350 }
351
352 /*
353 * Make some adjustments to initial values depending on what is found
354 * in the ICR.
355 */
356 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
357 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
358 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
359 isa16bit = 0;
360 memsize = 8192;
361 }
362
363 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
364 &conf_maddr, &conf_msize);
365 if (error)
366 return (error);
367
368#if ED_DEBUG
369 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
370 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
371 for (i = 0; i < 8; i++)
372 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
373#endif
374
375 /*
376 * Allow the user to override the autoconfiguration
377 */
378 if (conf_msize > 1)
379 memsize = conf_msize;
380
381 maddr = conf_maddr;
382 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
383 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
384 maddr, maddr + memsize);
385 return (ENXIO);
386 }
387
388 /*
389 * (note that if the user specifies both of the following flags that
390 * '8bit' mode intentionally has precedence)
391 */
392 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
393 isa16bit = 1;
394 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
395 isa16bit = 0;
396
397 /*
398 * If possible, get the assigned interrupt number from the card and
399 * use it.
400 */
401 if ((sc->type & ED_WD_SOFTCONFIG) &&
402 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
403
404 /*
405 * Assemble together the encoded interrupt number.
406 */
407 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
408 ((ed_asic_inb(sc, ED_WD_IRR) &
409 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
410
411 /*
412 * If no interrupt specified (or "?"), use what the board tells us.
413 */
414 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
415 &irq, &junk);
416 if (error && intr_vals[0] != NULL) {
417 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
418 intr_vals[0][iptr], 1);
419 }
420 if (error)
421 return (error);
422
423 /*
424 * Enable the interrupt.
425 */
426 ed_asic_outb(sc, ED_WD_IRR,
427 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
428 }
429 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
430 ed_asic_outb(sc, ED_WD790_HWR,
431 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
432 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
433 (ed_asic_inb(sc, ED_WD790_GCR) &
434 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
435 ed_asic_outb(sc, ED_WD790_HWR,
436 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
437
438 /*
439 * If no interrupt specified (or "?"), use what the board tells us.
440 */
441 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
442 &irq, &junk);
443 if (error && intr_vals[1] != NULL) {
444 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
445 intr_vals[1][iptr], 1);
446 }
447 if (error)
448 return (error);
449
450 /*
451 * Enable interrupts.
452 */
453 ed_asic_outb(sc, ED_WD790_ICR,
454 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
455 }
456 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
457 &irq, &junk);
458 if (error) {
459 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
460 sc->type_str);
461 return (ENXIO);
462 }
463 sc->isa16bit = isa16bit;
464 sc->mem_shared = 1;
465
466 error = ed_alloc_memory(dev, 0, memsize);
467 if (error) {
468 printf("*** ed_alloc_memory() failed! (%d)\n", error);
469 return (error);
470 }
471 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
472
473 /*
474 * allocate one xmit buffer if < 16k, two buffers otherwise
475 */
476 if ((memsize < 16384) ||
477 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
478 sc->txb_cnt = 1;
479 } else {
480 sc->txb_cnt = 2;
481 }
482 sc->tx_page_start = ED_WD_PAGE_OFFSET;
483 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
484 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
485 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
486 sc->mem_size = memsize;
487 sc->mem_end = sc->mem_start + memsize;
488
489 /*
490 * Get station address from on-board ROM
491 */
492 for (i = 0; i < ETHER_ADDR_LEN; ++i)
493 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
494
495 /*
496 * Set upper address bits and 8/16 bit access to shared memory.
497 */
498 if (isa16bit) {
499 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
500 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
501 } else {
502 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
503 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
504 }
505 /*
506 * Enable 16bit access
507 */
508 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
509 ED_WD_LAAR_M16EN);
510 } else {
511 if (((sc->type & ED_WD_SOFTCONFIG) ||
512 (sc->type == ED_TYPE_TOSHIBA1) ||
513 (sc->type == ED_TYPE_TOSHIBA4) ||
514 (sc->type == ED_TYPE_WD8013EBT)) &&
515 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
516 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
517 ED_WD_LAAR_ADDRHI;
518 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
519 }
520 }
521
522 /*
523 * Set address and enable interface shared memory.
524 */
525 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
526 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
527 ed_asic_outb(sc, ED_WD_MSR + 1,
528 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
529 ed_asic_outb(sc, ED_WD_MSR + 2,
530 ((kvtop(sc->mem_start) >> 16) & 0x0f));
531 ed_asic_outb(sc, ED_WD_MSR,
532 ED_WD_MSR_MENB | ED_WD_MSR_POW);
533 } else {
534 ed_asic_outb(sc, ED_WD_MSR,
535 ((kvtop(sc->mem_start) >> 13) &
536 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
537 }
538 sc->cr_proto = ED_CR_RD2;
539 } else {
540 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
541 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
542 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
543 ((kvtop(sc->mem_start) >> 11) & 0x40) |
544 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
545 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
546 sc->cr_proto = 0;
547 }
548
549#if 0
550 printf("starting memory performance test at 0x%x, size %d...\n",
551 sc->mem_start, memsize*16384);
552 for (i = 0; i < 16384; i++)
553 bzero(sc->mem_start, memsize);
554 printf("***DONE***\n");
555#endif
556
557 /*
558 * Now zero memory and verify that it is clear
559 */
560 bzero(sc->mem_start, memsize);
561
562 for (i = 0; i < memsize; ++i) {
563 if (sc->mem_start[i]) {
564 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
565 kvtop(sc->mem_start + i));
566
567 /*
568 * Disable 16 bit access to shared memory
569 */
570 if (isa16bit) {
571 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
572 ed_asic_outb(sc, ED_WD_MSR, 0x00);
573 }
574 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
575 ~ED_WD_LAAR_M16EN);
576 }
577 return (ENXIO);
578 }
579 }
580
581 /*
582 * Disable 16bit access to shared memory - we leave it
583 * disabled so that 1) machines reboot properly when the board
584 * is set 16 bit mode and there are conflicting 8bit
585 * devices/ROMS in the same 128k address space as this boards
586 * shared memory. and 2) so that other 8 bit devices with
587 * shared memory can be used in this 128k region, too.
588 */
589 if (isa16bit) {
590 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
591 ed_asic_outb(sc, ED_WD_MSR, 0x00);
592 }
593 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
594 ~ED_WD_LAAR_M16EN);
595 }
596 return (0);
597}
598
599int
600ed_probe_WD80x3(dev, port_rid, flags)
601 device_t dev;
602 int port_rid;
603 int flags;
604{
605 struct ed_softc *sc = device_get_softc(dev);
606 int error;
607 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
608
609 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
610 if (error)
611 return (error);
612
613 sc->asic_offset = ED_WD_ASIC_OFFSET;
614 sc->nic_offset = ED_WD_NIC_OFFSET;
615
616 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
617}
618
619/*
620 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
621 */
622int
623ed_probe_3Com(dev, port_rid, flags)
624 device_t dev;
625 int port_rid;
626 int flags;
627{
628 struct ed_softc *sc = device_get_softc(dev);
629 int error;
630 int i;
631 u_int memsize;
632 u_char isa16bit;
633 u_long conf_maddr, conf_msize, irq, junk;
634
635 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
636 if (error)
637 return (error);
638
639 sc->asic_offset = ED_3COM_ASIC_OFFSET;
640 sc->nic_offset = ED_3COM_NIC_OFFSET;
641
642 /*
643 * Verify that the kernel configured I/O address matches the board
644 * configured address
645 */
646 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
647 case ED_3COM_BCFR_300:
648 if (rman_get_start(sc->port_res) != 0x300)
649 return (ENXIO);
650 break;
651 case ED_3COM_BCFR_310:
652 if (rman_get_start(sc->port_res) != 0x310)
653 return (ENXIO);
654 break;
655 case ED_3COM_BCFR_330:
656 if (rman_get_start(sc->port_res) != 0x330)
657 return (ENXIO);
658 break;
659 case ED_3COM_BCFR_350:
660 if (rman_get_start(sc->port_res) != 0x350)
661 return (ENXIO);
662 break;
663 case ED_3COM_BCFR_250:
664 if (rman_get_start(sc->port_res) != 0x250)
665 return (ENXIO);
666 break;
667 case ED_3COM_BCFR_280:
668 if (rman_get_start(sc->port_res) != 0x280)
669 return (ENXIO);
670 break;
671 case ED_3COM_BCFR_2A0:
672 if (rman_get_start(sc->port_res) != 0x2a0)
673 return (ENXIO);
674 break;
675 case ED_3COM_BCFR_2E0:
676 if (rman_get_start(sc->port_res) != 0x2e0)
677 return (ENXIO);
678 break;
679 default:
680 return (ENXIO);
681 }
682
683 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
684 &conf_maddr, &conf_msize);
685 if (error)
686 return (error);
687
688 /*
689 * Verify that the kernel shared memory address matches the board
690 * configured address.
691 */
692 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
693 case ED_3COM_PCFR_DC000:
694 if (conf_maddr != 0xdc000)
695 return (ENXIO);
696 break;
697 case ED_3COM_PCFR_D8000:
698 if (conf_maddr != 0xd8000)
699 return (ENXIO);
700 break;
701 case ED_3COM_PCFR_CC000:
702 if (conf_maddr != 0xcc000)
703 return (ENXIO);
704 break;
705 case ED_3COM_PCFR_C8000:
706 if (conf_maddr != 0xc8000)
707 return (ENXIO);
708 break;
709 default:
710 return (ENXIO);
711 }
712
713
714 /*
715 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
716 * sequence because it'll lock up if the cable isn't connected if we
717 * don't.
718 */
719 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
720
721 /*
722 * Wait for a while, then un-reset it
723 */
724 DELAY(50);
725
726 /*
727 * The 3Com ASIC defaults to rather strange settings for the CR after
728 * a reset - it's important to set it again after the following outb
729 * (this is done when we map the PROM below).
730 */
731 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
732
733 /*
734 * Wait a bit for the NIC to recover from the reset
735 */
736 DELAY(5000);
737
738 sc->vendor = ED_VENDOR_3COM;
739 sc->type_str = "3c503";
740 sc->mem_shared = 1;
741 sc->cr_proto = ED_CR_RD2;
742
743 /*
744 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
745 * to it.
746 */
747 memsize = 8192;
748
749 /*
750 * Get station address from on-board ROM
751 */
752
753 /*
754 * First, map ethernet address PROM over the top of where the NIC
755 * registers normally appear.
756 */
757 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
758
759 for (i = 0; i < ETHER_ADDR_LEN; ++i)
760 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
761
762 /*
763 * Unmap PROM - select NIC registers. The proper setting of the
764 * tranceiver is set in ed_init so that the attach code is given a
765 * chance to set the default based on a compile-time config option
766 */
767 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
768
769 /*
770 * Determine if this is an 8bit or 16bit board
771 */
772
773 /*
774 * select page 0 registers
775 */
776 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
777
778 /*
779 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
780 * board.
781 */
782 ed_nic_outb(sc, ED_P0_DCR, 0);
783
784 /*
785 * select page 2 registers
786 */
787 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
788
789 /*
790 * The 3c503 forces the WTS bit to a one if this is a 16bit board
791 */
792 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
793 isa16bit = 1;
794 else
795 isa16bit = 0;
796
797 /*
798 * select page 0 registers
799 */
800 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
801
802 error = ed_alloc_memory(dev, 0, memsize);
803 if (error)
804 return (error);
805
806 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
807 sc->mem_size = memsize;
808 sc->mem_end = sc->mem_start + memsize;
809
810 /*
811 * We have an entire 8k window to put the transmit buffers on the
812 * 16bit boards. But since the 16bit 3c503's shared memory is only
813 * fast enough to overlap the loading of one full-size packet, trying
814 * to load more than 2 buffers can actually leave the transmitter idle
815 * during the load. So 2 seems the best value. (Although a mix of
816 * variable-sized packets might change this assumption. Nonetheless,
817 * we optimize for linear transfers of same-size packets.)
818 */
819 if (isa16bit) {
820 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
821 sc->txb_cnt = 1;
822 else
823 sc->txb_cnt = 2;
824
825 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
826 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
827 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
828 ED_3COM_RX_PAGE_OFFSET_16BIT;
829 sc->mem_ring = sc->mem_start;
830 } else {
831 sc->txb_cnt = 1;
832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
833 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
834 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
835 ED_3COM_TX_PAGE_OFFSET_8BIT;
836 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
837 }
838
839 sc->isa16bit = isa16bit;
840
841 /*
842 * Initialize GA page start/stop registers. Probably only needed if
843 * doing DMA, but what the hell.
844 */
845 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
846 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
847
848 /*
849 * Set IRQ. 3c503 only allows a choice of irq 2-5.
850 */
851 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
852 if (error)
853 return (error);
854
855 switch (irq) {
856 case 2:
857 case 9:
858 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
859 break;
860 case 3:
861 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
862 break;
863 case 4:
864 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
865 break;
866 case 5:
867 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
868 break;
869 default:
870 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
871 irq);
872 return (ENXIO);
873 }
874
875 /*
876 * Initialize GA configuration register. Set bank and enable shared
877 * mem.
878 */
879 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
880 ED_3COM_GACFR_MBS0);
881
882 /*
883 * Initialize "Vector Pointer" registers. These gawd-awful things are
884 * compared to 20 bits of the address on ISA, and if they match, the
885 * shared memory is disabled. We set them to 0xffff0...allegedly the
886 * reset vector.
887 */
888 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
889 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
890 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
891
892 /*
893 * Zero memory and verify that it is clear
894 */
895 bzero(sc->mem_start, memsize);
896
897 for (i = 0; i < memsize; ++i)
898 if (sc->mem_start[i]) {
899 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
900 kvtop(sc->mem_start + i));
901 return (ENXIO);
902 }
903 return (0);
904}
905
906/*
907 * Probe and vendor-specific initialization routine for NE1000/2000 boards
908 */
909int
910ed_probe_Novell_generic(dev, flags)
911 device_t dev;
912 int flags;
913{
914 struct ed_softc *sc = device_get_softc(dev);
915 u_int memsize, n;
916 u_char romdata[16], tmp;
917 static char test_pattern[32] = "THIS is A memory TEST pattern";
918 char test_buffer[32];
919
920 /* XXX - do Novell-specific probe here */
921
922 /* Reset the board */
923 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
924 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
925 DELAY(200);
926 }
927 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
928
929 /*
930 * I don't know if this is necessary; probably cruft leftover from
931 * Clarkson packet driver code. Doesn't do a thing on the boards I've
932 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
933 * non-invasive...but some boards don't seem to reset and I don't have
934 * complete documentation on what the 'right' thing to do is...so we
935 * do the invasive thing for now. Yuck.]
936 */
937 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
938 DELAY(5000);
939
940 /*
941 * This is needed because some NE clones apparently don't reset the
942 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
943 * - this makes the probe invasive! ...Done against my better
944 * judgement. -DLG
945 */
946 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
947
948 DELAY(5000);
949
950 /* Make sure that we really have an 8390 based board */
951 if (!ed_probe_generic8390(sc))
952 return (ENXIO);
953
954 sc->vendor = ED_VENDOR_NOVELL;
955 sc->mem_shared = 0;
956 sc->cr_proto = ED_CR_RD2;
957
958 /*
959 * Test the ability to read and write to the NIC memory. This has the
960 * side affect of determining if this is an NE1000 or an NE2000.
961 */
962
963 /*
964 * This prevents packets from being stored in the NIC memory when the
965 * readmem routine turns on the start bit in the CR.
966 */
967 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
968
969 /* Temporarily initialize DCR for byte operations */
970 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
971
972 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
973 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
974
975 sc->isa16bit = 0;
976
977 /*
978 * Write a test pattern in byte mode. If this fails, then there
979 * probably isn't any memory at 8k - which likely means that the board
980 * is an NE2000.
981 */
982 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
983 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
984
985 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
986 sc->type = ED_TYPE_NE1000;
987 sc->type_str = "NE1000";
988 } else {
989
990 /* neither an NE1000 nor a Linksys - try NE2000 */
991 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
992 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
993 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
994
995 sc->isa16bit = 1;
996
997 /*
998 * Write a test pattern in word mode. If this also fails, then
999 * we don't know what this board is.
1000 */
1001 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1002 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1003 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1004 sc->type = ED_TYPE_NE2000;
1005 sc->type_str = "NE2000";
1006 } else {
1007 return (ENXIO);
1008 }
1009 }
1010
1011
1012 /* 8k of memory plus an additional 8k if 16bit */
1013 memsize = 8192 + sc->isa16bit * 8192;
1014
1015#if 0 /* probably not useful - NE boards only come two ways */
1016 /* allow kernel config file overrides */
1017 if (isa_dev->id_msize)
1018 memsize = isa_dev->id_msize;
1019#endif
1020
1021 sc->mem_size = memsize;
1022
1023 /* NIC memory doesn't start at zero on an NE board */
1024 /* The start address is tied to the bus width */
1025 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1026 sc->mem_end = sc->mem_start + memsize;
1027 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1028
1029 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1030 int x, i, mstart = 0, msize = 0;
1031 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1032
1033 for (i = 0; i < ED_PAGE_SIZE; i++)
1034 pbuf0[i] = 0;
1035
1036 /* Clear all the memory. */
1037 for (x = 1; x < 256; x++)
1038 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1039
1040 /* Search for the start of RAM. */
1041 for (x = 1; x < 256; x++) {
1042 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1043 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1044 for (i = 0; i < ED_PAGE_SIZE; i++)
1045 pbuf[i] = 255 - x;
1046 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1047 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1048 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1049 mstart = x * ED_PAGE_SIZE;
1050 msize = ED_PAGE_SIZE;
1051 break;
1052 }
1053 }
1054 }
1055
1056 if (mstart == 0) {
1057 device_printf(dev, "Cannot find start of RAM.\n");
1058 return (ENXIO);
1059 }
1060 /* Search for the start of RAM. */
1061 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1062 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1063 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1064 for (i = 0; i < ED_PAGE_SIZE; i++)
1065 pbuf[i] = 255 - x;
1066 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1067 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1068 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1069 msize += ED_PAGE_SIZE;
1070 else {
1071 break;
1072 }
1073 } else {
1074 break;
1075 }
1076 }
1077
1078 if (msize == 0) {
1079 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1080 return (ENXIO);
1081 }
1082 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1083
1084 sc->mem_size = msize;
1085 sc->mem_start = (caddr_t) mstart;
1086 sc->mem_end = (caddr_t) (msize + mstart);
1087 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1088 }
1089
1090 /*
1091 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1092 * otherwise).
1093 */
1094 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1095 sc->txb_cnt = 1;
1096 else
1097 sc->txb_cnt = 2;
1098
1099 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1100 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1101
1102 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1103
1104 ed_pio_readmem(sc, 0, romdata, 16);
1105 for (n = 0; n < ETHER_ADDR_LEN; n++)
1106 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1107
1108 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1109 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1110 sc->type_str = "Gateway AT";
1111 }
1112
1113 /* clear any pending interrupts that might have occurred above */
1114 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1115
1116 return (0);
1117}
1118
1119int
1120ed_probe_Novell(dev, port_rid, flags)
1121 device_t dev;
1122 int port_rid;
1123 int flags;
1124{
1125 struct ed_softc *sc = device_get_softc(dev);
1126 int error;
1127
1128 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1129 if (error)
1130 return (error);
1131
1132 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1133 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1134
1135 return ed_probe_Novell_generic(dev, flags);
1136}
1137
1138#define ED_HPP_TEST_SIZE 16
1139
1140/*
1141 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1142 * (HP Part nos: 27247B and 27252A).
1143 *
1144 * The card has an asic wrapper around a DS8390 core. The asic handles
1145 * host accesses and offers both standard register IO and memory mapped
1146 * IO. Memory mapped I/O allows better performance at the expense of greater
1147 * chance of an incompatibility with existing ISA cards.
1148 *
1149 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1150 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1151 * don't allow 32 bit accesses; these are indicated by a bit in the software
1152 * ID register (see if_edreg.h).
1153 *
1154 * Other caveats are: we should read the MAC address only when the card
1155 * is inactive.
1156 *
1157 * For more information; please consult the CRYNWR packet driver.
1158 *
1159 * The AUI port is turned on using the "link2" option on the ifconfig
1160 * command line.
1161 */
1162int
1163ed_probe_HP_pclanp(dev, port_rid, flags)
1164 device_t dev;
1165 int port_rid;
1166 int flags;
1167{
1168 struct ed_softc *sc = device_get_softc(dev);
1169 int error;
1170 int n; /* temp var */
1171 int memsize; /* mem on board */
1172 u_char checksum; /* checksum of board address */
1173 u_char irq; /* board configured IRQ */
1174 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1175 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1176 u_long conf_maddr, conf_msize, conf_irq, junk;
1177
1178 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1179 if (error)
1180 return (error);
1181
1182 /* Fill in basic information */
1183 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1184 sc->nic_offset = ED_HPP_NIC_OFFSET;
1185
1186 sc->chip_type = ED_CHIP_TYPE_DP8390;
1187 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1188
1189 /*
1190 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1191 */
1192
1193 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1194 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1195 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1196 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1197 return ENXIO;
1198
1199 /*
1200 * Read the MAC address and verify checksum on the address.
1201 */
1202
1203 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1204 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1205 checksum += (sc->arpcom.ac_enaddr[n] =
1206 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1207
1208 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1209
1210 if (checksum != 0xFF)
1211 return ENXIO;
1212
1213 /*
1214 * Verify that the software model number is 0.
1215 */
1216
1217 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1218 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1219 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1220 return ENXIO;
1221
1222 /*
1223 * Read in and save the current options configured on card.
1224 */
1225
1226 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1227
1228 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1229 ED_HPP_OPTION_CHIP_RESET |
1230 ED_HPP_OPTION_ENABLE_IRQ);
1231
1232 /*
1233 * Reset the chip. This requires writing to the option register
1234 * so take care to preserve the other bits.
1235 */
1236
1237 ed_asic_outw(sc, ED_HPP_OPTION,
1238 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1239 ED_HPP_OPTION_CHIP_RESET)));
1240
1241 DELAY(5000); /* wait for chip reset to complete */
1242
1243 ed_asic_outw(sc, ED_HPP_OPTION,
1244 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1245 ED_HPP_OPTION_CHIP_RESET |
1246 ED_HPP_OPTION_ENABLE_IRQ)));
1247
1248 DELAY(5000);
1249
1250 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1251 return ENXIO; /* reset did not complete */
1252
1253 /*
1254 * Read out configuration information.
1255 */
1256
1257 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1258
1259 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1260
1261 /*
1262 * Check for impossible IRQ.
1263 */
1264
1265 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1266 return ENXIO;
1267
1268 /*
1269 * If the kernel IRQ was specified with a '?' use the cards idea
1270 * of the IRQ. If the kernel IRQ was explicitly specified, it
1271 * should match that of the hardware.
1272 */
1273 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1274 &conf_irq, &junk);
1275 if (error) {
1276 bus_set_resource(dev, SYS_RES_IRQ, 0,
1277 ed_hpp_intr_val[irq], 1);
1278 } else {
1279 if (conf_irq != ed_hpp_intr_val[irq])
1280 return (ENXIO);
1281 }
1282
1283 /*
1284 * Fill in softconfig info.
1285 */
1286
1287 sc->vendor = ED_VENDOR_HP;
1288 sc->type = ED_TYPE_HP_PCLANPLUS;
1289 sc->type_str = "HP-PCLAN+";
1290
1291 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1292 sc->mem_start = 0; /* we use offsets inside the card RAM */
1293
1294 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1295
1296 /*
1297 * The board has 32KB of memory. Is there a way to determine
1298 * this programmatically?
1299 */
1300
1301 memsize = 32768;
1302
1303 /*
1304 * Check if memory mapping of the I/O registers possible.
1305 */
1306
1307 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1308 {
1309 u_long mem_addr;
1310
1311 /*
1312 * determine the memory address from the board.
1313 */
1314
1315 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1316 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1317
1318 /*
1319 * Check that the kernel specified start of memory and
1320 * hardware's idea of it match.
1321 */
1322 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1323 &conf_maddr, &conf_msize);
1324 if (error)
1325 return (error);
1326
1327 if (mem_addr != conf_maddr)
1328 return ENXIO;
1329
1330 error = ed_alloc_memory(dev, 0, memsize);
1331 if (error)
1332 return (error);
1333
1334 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1335 }
1336
1337 /*
1338 * Fill in the rest of the soft config structure.
1339 */
1340
1341 /*
1342 * The transmit page index.
1343 */
1344
1345 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1346
1347 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1348 sc->txb_cnt = 1;
1349 else
1350 sc->txb_cnt = 2;
1351
1352 /*
1353 * Memory description
1354 */
1355
1356 sc->mem_size = memsize;
1357 sc->mem_ring = sc->mem_start +
1358 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1359 sc->mem_end = sc->mem_start + sc->mem_size;
1360
1361 /*
1362 * Receive area starts after the transmit area and
1363 * continues till the end of memory.
1364 */
1365
1366 sc->rec_page_start = sc->tx_page_start +
1367 (sc->txb_cnt * ED_TXBUF_SIZE);
1368 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1369
1370
1371 sc->cr_proto = 0; /* value works */
1372
1373 /*
1374 * Set the wrap registers for string I/O reads.
1375 */
1376
1377 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1378 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1379 ((sc->rec_page_start / ED_PAGE_SIZE) |
1380 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1381
1382 /*
1383 * Reset the register page to normal operation.
1384 */
1385
1386 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1387
1388 /*
1389 * Verify that we can read/write from adapter memory.
1390 * Create test pattern.
1391 */
1392
1393 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1394 {
1395 test_pattern[n] = (n*n) ^ ~n;
1396 }
1397
1398#undef ED_HPP_TEST_SIZE
1399
1400 /*
1401 * Check that the memory is accessible thru the I/O ports.
1402 * Write out the contents of "test_pattern", read back
1403 * into "test_buffer" and compare the two for any
1404 * mismatch.
1405 */
1406
1407 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1408
1409 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1410 sizeof(test_pattern));
1411 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1412 test_buffer, sizeof(test_pattern));
1413
1414 if (bcmp(test_pattern, test_buffer,
1415 sizeof(test_pattern)))
1416 return ENXIO;
1417 }
1418
1419 return (ED_HPP_IO_PORTS);
1420
1421}
1422
1423/*
1424 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1425 */
1426
1427void
1428ed_hpp_set_physical_link(struct ed_softc *sc)
1429{
1430 struct ifnet *ifp = &sc->arpcom.ac_if;
1431 int lan_page;
1432
1433 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1434 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1435
1436 if (ifp->if_flags & IFF_ALTPHYS) {
1437
1438 /*
1439 * Use the AUI port.
1440 */
1441
1442 lan_page |= ED_HPP_LAN_AUI;
1443
1444 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1445 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1446
1447
1448 } else {
1449
1450 /*
1451 * Use the ThinLan interface
1452 */
1453
1454 lan_page &= ~ED_HPP_LAN_AUI;
1455
1456 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1457 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1458
1459 }
1460
1461 /*
1462 * Wait for the lan card to re-initialize itself
1463 */
1464
1465 DELAY(150000); /* wait 150 ms */
1466
1467 /*
1468 * Restore normal pages.
1469 */
1470
1471 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1472
1473}
1474
1475/*
1476 * Allocate a port resource with the given resource id.
1477 */
1478int
1479ed_alloc_port(dev, rid, size)
1480 device_t dev;
1481 int rid;
1482 int size;
1483{
1484 struct ed_softc *sc = device_get_softc(dev);
1485 struct resource *res;
1486
1487 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1488 0ul, ~0ul, size, RF_ACTIVE);
1489 if (res) {
1490 sc->port_rid = rid;
1491 sc->port_res = res;
1492 sc->port_used = size;
1493 return (0);
1494 } else {
1495 return (ENOENT);
1496 }
1497}
1498
1499/*
1500 * Allocate a memory resource with the given resource id.
1501 */
1502int
1503ed_alloc_memory(dev, rid, size)
1504 device_t dev;
1505 int rid;
1506 int size;
1507{
1508 struct ed_softc *sc = device_get_softc(dev);
1509 struct resource *res;
1510
1511 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1512 0ul, ~0ul, size, RF_ACTIVE);
1513 if (res) {
1514 sc->mem_rid = rid;
1515 sc->mem_res = res;
1516 sc->mem_used = size;
1517 return (0);
1518 } else {
1519 return (ENOENT);
1520 }
1521}
1522
1523/*
1524 * Allocate an irq resource with the given resource id.
1525 */
1526int
1527ed_alloc_irq(dev, rid, flags)
1528 device_t dev;
1529 int rid;
1530 int flags;
1531{
1532 struct ed_softc *sc = device_get_softc(dev);
1533 struct resource *res;
1534
1535 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1536 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1537 if (res) {
1538 sc->irq_rid = rid;
1539 sc->irq_res = res;
1540 return (0);
1541 } else {
1542 return (ENOENT);
1543 }
1544}
1545
1546/*
1547 * Release all resources
1548 */
1549void
1550ed_release_resources(dev)
1551 device_t dev;
1552{
1553 struct ed_softc *sc = device_get_softc(dev);
1554
1555 if (sc->port_res) {
1556 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1557 sc->port_rid, sc->port_res);
1558 bus_release_resource(dev, SYS_RES_IOPORT,
1559 sc->port_rid, sc->port_res);
1560 sc->port_res = 0;
1561 }
1562 if (sc->mem_res) {
1563 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1564 sc->mem_rid, sc->mem_res);
1565 bus_release_resource(dev, SYS_RES_MEMORY,
1566 sc->mem_rid, sc->mem_res);
1567 sc->mem_res = 0;
1568 }
1569 if (sc->irq_res) {
1570 bus_deactivate_resource(dev, SYS_RES_IRQ,
1571 sc->irq_rid, sc->irq_res);
1572 bus_release_resource(dev, SYS_RES_IRQ,
1573 sc->irq_rid, sc->irq_res);
1574 sc->irq_res = 0;
1575 }
1576}
1577
1578/*
1579 * Install interface into kernel networking data structures
1580 */
1581int
1582ed_attach(sc, unit, flags)
1583 struct ed_softc *sc;
1584 int unit;
1585 int flags;
1586{
1587 struct ifnet *ifp = &sc->arpcom.ac_if;
1588
1589 /*
1590 * Set interface to stopped condition (reset)
1591 */
1592 ed_stop(sc);
1593
1594 if (!ifp->if_name) {
1595 /*
1596 * Initialize ifnet structure
1597 */
1598 ifp->if_softc = sc;
1599 ifp->if_unit = unit;
1600 ifp->if_name = "ed";
1601 ifp->if_output = ether_output;
1602 ifp->if_start = ed_start;
1603 ifp->if_ioctl = ed_ioctl;
1604 ifp->if_watchdog = ed_watchdog;
1605 ifp->if_init = ed_init;
1606 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1607 ifp->if_linkmib = &sc->mibdata;
1608 ifp->if_linkmiblen = sizeof sc->mibdata;
1609 /*
1610 * XXX - should do a better job.
1611 */
1612 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1613 sc->mibdata.dot3StatsEtherChipSet =
1614 DOT3CHIPSET(dot3VendorWesternDigital,
1615 dot3ChipSetWesternDigital83C790);
1616 else
1617 sc->mibdata.dot3StatsEtherChipSet =
1618 DOT3CHIPSET(dot3VendorNational,
1619 dot3ChipSetNational8390);
1620 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1621
1622 /*
1623 * Set default state for ALTPHYS flag (used to disable the
1624 * tranceiver for AUI operation), based on compile-time
1625 * config option.
1626 */
1627 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1628 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1629 IFF_MULTICAST | IFF_ALTPHYS);
1630 else
1631 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1632 IFF_MULTICAST);
1633
1634 /*
1635 * Attach the interface
1636 */
1637 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1638 }
1639 /* device attach does transition from UNCONFIGURED to IDLE state */
1640
1641 /*
1642 * Print additional info when attached
1643 */
1644 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1645 sc->arpcom.ac_enaddr, ":");
1646
1647 if (sc->type_str && (*sc->type_str != 0))
1648 printf("type %s ", sc->type_str);
1649 else
1650 printf("type unknown (0x%x) ", sc->type);
1651
1652 if (sc->vendor == ED_VENDOR_HP)
1653 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1654 "16-bit" : "32-bit",
1655 sc->hpp_mem_start ? "memory mapped" : "regular");
1656 else
1657 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1658
1659 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1660 (sc->vendor == ED_VENDOR_HP)) &&
1661 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1662
1663 return (0);
1664}
1665
1666/*
1667 * Reset interface.
1668 */
1669static void
1670ed_reset(ifp)
1671 struct ifnet *ifp;
1672{
1673 struct ed_softc *sc = ifp->if_softc;
1674 int s;
1675
1676 if (sc->gone)
1677 return;
1678 s = splimp();
1679
1680 /*
1681 * Stop interface and re-initialize.
1682 */
1683 ed_stop(sc);
1684 ed_init(sc);
1685
1686 (void) splx(s);
1687}
1688
1689/*
1690 * Take interface offline.
1691 */
1692void
1693ed_stop(sc)
1694 struct ed_softc *sc;
1695{
1696 int n = 5000;
1697
1698 if (sc->gone)
1699 return;
1700 /*
1701 * Stop everything on the interface, and select page 0 registers.
1702 */
1703 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1704
1705 /*
1706 * Wait for interface to enter stopped state, but limit # of checks to
1707 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1708 * just in case it's an old one.
1709 */
1710 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1711 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1712}
1713
1714/*
1715 * Device timeout/watchdog routine. Entered if the device neglects to
1716 * generate an interrupt after a transmit has been started on it.
1717 */
1718static void
1719ed_watchdog(ifp)
1720 struct ifnet *ifp;
1721{
1722 struct ed_softc *sc = ifp->if_softc;
1723
1724 if (sc->gone)
1725 return;
1726 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1727 ifp->if_oerrors++;
1728
1729 ed_reset(ifp);
1730}
1731
1732/*
1733 * Initialize device.
1734 */
1735static void
1736ed_init(xsc)
1737 void *xsc;
1738{
1739 struct ed_softc *sc = xsc;
1740 struct ifnet *ifp = &sc->arpcom.ac_if;
1741 int i, s;
1742
1743 if (sc->gone)
1744 return;
1745
1746 /* address not known */
1747 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1748 return;
1749
1750 /*
1751 * Initialize the NIC in the exact order outlined in the NS manual.
1752 * This init procedure is "mandatory"...don't change what or when
1753 * things happen.
1754 */
1755 s = splimp();
1756
1757 /* reset transmitter flags */
1758 sc->xmit_busy = 0;
1759 ifp->if_timer = 0;
1760
1761 sc->txb_inuse = 0;
1762 sc->txb_new = 0;
1763 sc->txb_next_tx = 0;
1764
1765 /* This variable is used below - don't move this assignment */
1766 sc->next_packet = sc->rec_page_start + 1;
1767
1768 /*
1769 * Set interface for page 0, Remote DMA complete, Stopped
1770 */
1771 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1772
1773 if (sc->isa16bit) {
1774
1775 /*
1776 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1777 * order=80x86, word-wide DMA xfers,
1778 */
1779 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1780 } else {
1781
1782 /*
1783 * Same as above, but byte-wide DMA xfers
1784 */
1785 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1786 }
1787
1788 /*
1789 * Clear Remote Byte Count Registers
1790 */
1791 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1792 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1793
1794 /*
1795 * For the moment, don't store incoming packets in memory.
1796 */
1797 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1798
1799 /*
1800 * Place NIC in internal loopback mode
1801 */
1802 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1803
1804 /*
1805 * Initialize transmit/receive (ring-buffer) Page Start
1806 */
1807 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1808 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1809 /* Set lower bits of byte addressable framing to 0 */
1810 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1811 ed_nic_outb(sc, 0x09, 0);
1812
1813 /*
1814 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1815 */
1816 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1817 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1818
1819 /*
1820 * Clear all interrupts. A '1' in each bit position clears the
1821 * corresponding flag.
1822 */
1823 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1824
1825 /*
1826 * Enable the following interrupts: receive/transmit complete,
1827 * receive/transmit error, and Receiver OverWrite.
1828 *
1829 * Counter overflow and Remote DMA complete are *not* enabled.
1830 */
1831 ed_nic_outb(sc, ED_P0_IMR,
1832 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1833
1834 /*
1835 * Program Command Register for page 1
1836 */
1837 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1838
1839 /*
1840 * Copy out our station address
1841 */
1842 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1843 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1844
1845 /*
1846 * Set Current Page pointer to next_packet (initialized above)
1847 */
1848 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1849
1850 /*
1851 * Program Receiver Configuration Register and multicast filter. CR is
1852 * set to page 0 on return.
1853 */
1854 ed_setrcr(sc);
1855
1856 /*
1857 * Take interface out of loopback
1858 */
1859 ed_nic_outb(sc, ED_P0_TCR, 0);
1860
1861 /*
1862 * If this is a 3Com board, the tranceiver must be software enabled
1863 * (there is no settable hardware default).
1864 */
1865 if (sc->vendor == ED_VENDOR_3COM) {
1866 if (ifp->if_flags & IFF_ALTPHYS) {
1867 ed_asic_outb(sc, ED_3COM_CR, 0);
1868 } else {
1869 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1870 }
1871 }
1872
1873 /*
1874 * Set 'running' flag, and clear output active flag.
1875 */
1876 ifp->if_flags |= IFF_RUNNING;
1877 ifp->if_flags &= ~IFF_OACTIVE;
1878
1879 /*
1880 * ...and attempt to start output
1881 */
1882 ed_start(ifp);
1883
1884 (void) splx(s);
1885}
1886
1887/*
1888 * This routine actually starts the transmission on the interface
1889 */
1890static __inline void
1891ed_xmit(sc)
1892 struct ed_softc *sc;
1893{
1894 struct ifnet *ifp = (struct ifnet *)sc;
1895 unsigned short len;
1896
1897 if (sc->gone)
1898 return;
1899 len = sc->txb_len[sc->txb_next_tx];
1900
1901 /*
1902 * Set NIC for page 0 register access
1903 */
1904 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1905
1906 /*
1907 * Set TX buffer start page
1908 */
1909 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1910 sc->txb_next_tx * ED_TXBUF_SIZE);
1911
1912 /*
1913 * Set TX length
1914 */
1915 ed_nic_outb(sc, ED_P0_TBCR0, len);
1916 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1917
1918 /*
1919 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1920 */
1921 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1922 sc->xmit_busy = 1;
1923
1924 /*
1925 * Point to next transmit buffer slot and wrap if necessary.
1926 */
1927 sc->txb_next_tx++;
1928 if (sc->txb_next_tx == sc->txb_cnt)
1929 sc->txb_next_tx = 0;
1930
1931 /*
1932 * Set a timer just in case we never hear from the board again
1933 */
1934 ifp->if_timer = 2;
1935}
1936
1937/*
1938 * Start output on interface.
1939 * We make two assumptions here:
1940 * 1) that the current priority is set to splimp _before_ this code
1941 * is called *and* is returned to the appropriate priority after
1942 * return
1943 * 2) that the IFF_OACTIVE flag is checked before this code is called
1944 * (i.e. that the output part of the interface is idle)
1945 */
1946static void
1947ed_start(ifp)
1948 struct ifnet *ifp;
1949{
1950 struct ed_softc *sc = ifp->if_softc;
1951 struct mbuf *m0, *m;
1952 caddr_t buffer;
1953 int len;
1954
1955 if (sc->gone) {
1956 printf("ed_start(%p) GONE\n",ifp);
1957 return;
1958 }
1959outloop:
1960
1961 /*
1962 * First, see if there are buffered packets and an idle transmitter -
1963 * should never happen at this point.
1964 */
1965 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1966 printf("ed: packets buffered, but transmitter idle\n");
1967 ed_xmit(sc);
1968 }
1969
1970 /*
1971 * See if there is room to put another packet in the buffer.
1972 */
1973 if (sc->txb_inuse == sc->txb_cnt) {
1974
1975 /*
1976 * No room. Indicate this to the outside world and exit.
1977 */
1978 ifp->if_flags |= IFF_OACTIVE;
1979 return;
1980 }
1981 IF_DEQUEUE(&ifp->if_snd, m);
1982 if (m == 0) {
1983
1984 /*
1985 * We are using the !OACTIVE flag to indicate to the outside
1986 * world that we can accept an additional packet rather than
1987 * that the transmitter is _actually_ active. Indeed, the
1988 * transmitter may be active, but if we haven't filled all the
1989 * buffers with data then we still want to accept more.
1990 */
1991 ifp->if_flags &= ~IFF_OACTIVE;
1992 return;
1993 }
1994
1995 /*
1996 * Copy the mbuf chain into the transmit buffer
1997 */
1998
1999 m0 = m;
2000
2001 /* txb_new points to next open buffer slot */
2002 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2003
2004 if (sc->mem_shared) {
2005
2006 /*
2007 * Special case setup for 16 bit boards...
2008 */
2009 if (sc->isa16bit) {
2010 switch (sc->vendor) {
2011
2012 /*
2013 * For 16bit 3Com boards (which have 16k of
2014 * memory), we have the xmit buffers in a
2015 * different page of memory ('page 0') - so
2016 * change pages.
2017 */
2018 case ED_VENDOR_3COM:
2019 ed_asic_outb(sc, ED_3COM_GACFR,
2020 ED_3COM_GACFR_RSEL);
2021 break;
2022
2023 /*
2024 * Enable 16bit access to shared memory on
2025 * WD/SMC boards.
2026 */
2027 case ED_VENDOR_WD_SMC:
2028 ed_asic_outb(sc, ED_WD_LAAR,
2029 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2030 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2031 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2032 }
2033 break;
2034 }
2035 }
2036 for (len = 0; m != 0; m = m->m_next) {
2037 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2038 buffer += m->m_len;
2039 len += m->m_len;
2040 }
2041
2042 /*
2043 * Restore previous shared memory access
2044 */
2045 if (sc->isa16bit) {
2046 switch (sc->vendor) {
2047 case ED_VENDOR_3COM:
2048 ed_asic_outb(sc, ED_3COM_GACFR,
2049 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2050 break;
2051 case ED_VENDOR_WD_SMC:
2052 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2053 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2054 }
2055 ed_asic_outb(sc, ED_WD_LAAR,
2056 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2057 break;
2058 }
2059 }
2060 } else {
2061 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2062 if (len == 0)
2063 goto outloop;
2064 }
2065
2066 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2067
2068 sc->txb_inuse++;
2069
2070 /*
2071 * Point to next buffer slot and wrap if necessary.
2072 */
2073 sc->txb_new++;
2074 if (sc->txb_new == sc->txb_cnt)
2075 sc->txb_new = 0;
2076
2077 if (sc->xmit_busy == 0)
2078 ed_xmit(sc);
2079
2080 /*
2081 * Tap off here if there is a bpf listener.
2082 */
2083 if (ifp->if_bpf) {
2084 bpf_mtap(ifp, m0);
2085 }
2086
2087 m_freem(m0);
2088
2089 /*
2090 * Loop back to the top to possibly buffer more packets
2091 */
2092 goto outloop;
2093}
2094
2095/*
2096 * Ethernet interface receiver interrupt.
2097 */
2098static __inline void
2099ed_rint(sc)
2100 struct ed_softc *sc;
2101{
2102 struct ifnet *ifp = &sc->arpcom.ac_if;
2103 u_char boundry;
2104 u_short len;
2105 struct ed_ring packet_hdr;
2106 char *packet_ptr;
2107
2108 if (sc->gone)
2109 return;
2110
2111 /*
2112 * Set NIC to page 1 registers to get 'current' pointer
2113 */
2114 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2115
2116 /*
2117 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2118 * i.e. it points to where new data has been buffered. The 'CURR'
2119 * (current) register points to the logical end of the ring-buffer -
2120 * i.e. it points to where additional new data will be added. We loop
2121 * here until the logical beginning equals the logical end (or in
2122 * other words, until the ring-buffer is empty).
2123 */
2124 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2125
2126 /* get pointer to this buffer's header structure */
2127 packet_ptr = sc->mem_ring +
2128 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2129
2130 /*
2131 * The byte count includes a 4 byte header that was added by
2132 * the NIC.
2133 */
2134 if (sc->mem_shared)
2135 packet_hdr = *(struct ed_ring *) packet_ptr;
2136 else
2137 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2138 sizeof(packet_hdr));
2139 len = packet_hdr.count;
2140 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2141 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2142 /*
2143 * Length is a wild value. There's a good chance that
2144 * this was caused by the NIC being old and buggy.
2145 * The bug is that the length low byte is duplicated in
2146 * the high byte. Try to recalculate the length based on
2147 * the pointer to the next packet.
2148 */
2149 /*
2150 * NOTE: sc->next_packet is pointing at the current packet.
2151 */
2152 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2153 if (packet_hdr.next_packet >= sc->next_packet) {
2154 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2155 } else {
2156 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2157 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2158 }
2159 /*
2160 * because buffers are aligned on 256-byte boundary,
2161 * the length computed above is off by 256 in almost
2162 * all cases. Fix it...
2163 */
2164 if (len & 0xff)
2165 len -= 256 ;
2166 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2167 + sizeof(struct ed_ring)))
2168 sc->mibdata.dot3StatsFrameTooLongs++;
2169 }
2170 /*
2171 * Be fairly liberal about what we allow as a "reasonable" length
2172 * so that a [crufty] packet will make it to BPF (and can thus
2173 * be analyzed). Note that all that is really important is that
2174 * we have a length that will fit into one mbuf cluster or less;
2175 * the upper layer protocols can then figure out the length from
2176 * their own length field(s).
2177 * But make sure that we have at least a full ethernet header
2178 * or we would be unable to call ether_input() later.
2179 */
2180 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2181 (len <= MCLBYTES) &&
2182 (packet_hdr.next_packet >= sc->rec_page_start) &&
2183 (packet_hdr.next_packet < sc->rec_page_stop)) {
2184 /*
2185 * Go get packet.
2186 */
2187 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2188 len - sizeof(struct ed_ring));
2189 ifp->if_ipackets++;
2190 } else {
2191 /*
2192 * Really BAD. The ring pointers are corrupted.
2193 */
2194 log(LOG_ERR,
2195 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2196 ifp->if_unit, len);
2197 ifp->if_ierrors++;
2198 ed_reset(ifp);
2199 return;
2200 }
2201
2202 /*
2203 * Update next packet pointer
2204 */
2205 sc->next_packet = packet_hdr.next_packet;
2206
2207 /*
2208 * Update NIC boundry pointer - being careful to keep it one
2209 * buffer behind. (as recommended by NS databook)
2210 */
2211 boundry = sc->next_packet - 1;
2212 if (boundry < sc->rec_page_start)
2213 boundry = sc->rec_page_stop - 1;
2214
2215 /*
2216 * Set NIC to page 0 registers to update boundry register
2217 */
2218 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2219
2220 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2221
2222 /*
2223 * Set NIC to page 1 registers before looping to top (prepare
2224 * to get 'CURR' current pointer)
2225 */
2226 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2227 }
2228}
2229
2230/*
2231 * Ethernet interface interrupt processor
2232 */
2233void
2234edintr(arg)
2235 void *arg;
2236{
2237 struct ed_softc *sc = (struct ed_softc*) arg;
2238 struct ifnet *ifp = (struct ifnet *)sc;
2239 u_char isr;
2240
2241 if (sc->gone)
2242 return;
2243 /*
2244 * Set NIC to page 0 registers
2245 */
2246 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2247
2248 /*
2249 * loop until there are no more new interrupts
2250 */
2251 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0) {
2252
2253 /*
2254 * reset all the bits that we are 'acknowledging' by writing a
2255 * '1' to each bit position that was set (writing a '1'
2256 * *clears* the bit)
2257 */
2258 ed_nic_outb(sc, ED_P0_ISR, isr);
2259
2260 /* XXX workaround for AX88190 */
2261 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2262 while (ed_nic_inb(sc, ED_P0_ISR) & isr) {
2263 ed_nic_outb(sc, ED_P0_ISR,0);
2264 ed_nic_outb(sc, ED_P0_ISR,isr);
2265 }
2266 }
2267
2268 /*
2269 * Handle transmitter interrupts. Handle these first because
2270 * the receiver will reset the board under some conditions.
2271 */
2272 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2273 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2274
2275 /*
2276 * Check for transmit error. If a TX completed with an
2277 * error, we end up throwing the packet away. Really
2278 * the only error that is possible is excessive
2279 * collisions, and in this case it is best to allow
2280 * the automatic mechanisms of TCP to backoff the
2281 * flow. Of course, with UDP we're screwed, but this
2282 * is expected when a network is heavily loaded.
2283 */
2284 (void) ed_nic_inb(sc, ED_P0_TSR);
2285 if (isr & ED_ISR_TXE) {
2286 u_char tsr;
2287
2288 /*
2289 * Excessive collisions (16)
2290 */
2291 tsr = ed_nic_inb(sc, ED_P0_TSR);
2292 if ((tsr & ED_TSR_ABT)
2293 && (collisions == 0)) {
2294
2295 /*
2296 * When collisions total 16, the
2297 * P0_NCR will indicate 0, and the
2298 * TSR_ABT is set.
2299 */
2300 collisions = 16;
2301 sc->mibdata.dot3StatsExcessiveCollisions++;
2302 sc->mibdata.dot3StatsCollFrequencies[15]++;
2303 }
2304 if (tsr & ED_TSR_OWC)
2305 sc->mibdata.dot3StatsLateCollisions++;
2306 if (tsr & ED_TSR_CDH)
2307 sc->mibdata.dot3StatsSQETestErrors++;
2308 if (tsr & ED_TSR_CRS)
2309 sc->mibdata.dot3StatsCarrierSenseErrors++;
2310 if (tsr & ED_TSR_FU)
2311 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2312
2313 /*
2314 * update output errors counter
2315 */
2316 ifp->if_oerrors++;
2317 } else {
2318
2319 /*
2320 * Update total number of successfully
2321 * transmitted packets.
2322 */
2323 ifp->if_opackets++;
2324 }
2325
2326 /*
2327 * reset tx busy and output active flags
2328 */
2329 sc->xmit_busy = 0;
2330 ifp->if_flags &= ~IFF_OACTIVE;
2331
2332 /*
2333 * clear watchdog timer
2334 */
2335 ifp->if_timer = 0;
2336
2337 /*
2338 * Add in total number of collisions on last
2339 * transmission.
2340 */
2341 ifp->if_collisions += collisions;
2342 switch(collisions) {
2343 case 0:
2344 case 16:
2345 break;
2346 case 1:
2347 sc->mibdata.dot3StatsSingleCollisionFrames++;
2348 sc->mibdata.dot3StatsCollFrequencies[0]++;
2349 break;
2350 default:
2351 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2352 sc->mibdata.
2353 dot3StatsCollFrequencies[collisions-1]
2354 ++;
2355 break;
2356 }
2357
2358 /*
2359 * Decrement buffer in-use count if not zero (can only
2360 * be zero if a transmitter interrupt occured while
2361 * not actually transmitting). If data is ready to
2362 * transmit, start it transmitting, otherwise defer
2363 * until after handling receiver
2364 */
2365 if (sc->txb_inuse && --sc->txb_inuse)
2366 ed_xmit(sc);
2367 }
2368
2369 /*
2370 * Handle receiver interrupts
2371 */
2372 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2373
2374 /*
2375 * Overwrite warning. In order to make sure that a
2376 * lockup of the local DMA hasn't occurred, we reset
2377 * and re-init the NIC. The NSC manual suggests only a
2378 * partial reset/re-init is necessary - but some chips
2379 * seem to want more. The DMA lockup has been seen
2380 * only with early rev chips - Methinks this bug was
2381 * fixed in later revs. -DG
2382 */
2383 if (isr & ED_ISR_OVW) {
2384 ifp->if_ierrors++;
2385#ifdef DIAGNOSTIC
2386 log(LOG_WARNING,
2387 "ed%d: warning - receiver ring buffer overrun\n",
2388 ifp->if_unit);
2389#endif
2390
2391 /*
2392 * Stop/reset/re-init NIC
2393 */
2394 ed_reset(ifp);
2395 } else {
2396
2397 /*
2398 * Receiver Error. One or more of: CRC error,
2399 * frame alignment error FIFO overrun, or
2400 * missed packet.
2401 */
2402 if (isr & ED_ISR_RXE) {
2403 u_char rsr;
2404 rsr = ed_nic_inb(sc, ED_P0_RSR);
2405 if (rsr & ED_RSR_CRC)
2406 sc->mibdata.dot3StatsFCSErrors++;
2407 if (rsr & ED_RSR_FAE)
2408 sc->mibdata.dot3StatsAlignmentErrors++;
2409 if (rsr & ED_RSR_FO)
2410 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2411 ifp->if_ierrors++;
2412#ifdef ED_DEBUG
2413 printf("ed%d: receive error %x\n", ifp->if_unit,
2414 ed_nic_inb(sc, ED_P0_RSR));
2415#endif
2416 }
2417
2418 /*
2419 * Go get the packet(s) XXX - Doing this on an
2420 * error is dubious because there shouldn't be
2421 * any data to get (we've configured the
2422 * interface to not accept packets with
2423 * errors).
2424 */
2425
2426 /*
2427 * Enable 16bit access to shared memory first
2428 * on WD/SMC boards.
2429 */
2430 if (sc->isa16bit &&
2431 (sc->vendor == ED_VENDOR_WD_SMC)) {
2432
2433 ed_asic_outb(sc, ED_WD_LAAR,
2434 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2435 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2436 ed_asic_outb(sc, ED_WD_MSR,
2437 ED_WD_MSR_MENB);
2438 }
2439 }
2440 ed_rint(sc);
2441
2442 /* disable 16bit access */
2443 if (sc->isa16bit &&
2444 (sc->vendor == ED_VENDOR_WD_SMC)) {
2445
2446 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2447 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2448 }
2449 ed_asic_outb(sc, ED_WD_LAAR,
2450 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2451 }
2452 }
2453 }
2454
2455 /*
2456 * If it looks like the transmitter can take more data,
2457 * attempt to start output on the interface. This is done
2458 * after handling the receiver to give the receiver priority.
2459 */
2460 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2461 ed_start(ifp);
2462
2463 /*
2464 * return NIC CR to standard state: page 0, remote DMA
2465 * complete, start (toggling the TXP bit off, even if was just
2466 * set in the transmit routine, is *okay* - it is 'edge'
2467 * triggered from low to high)
2468 */
2469 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2470
2471 /*
2472 * If the Network Talley Counters overflow, read them to reset
2473 * them. It appears that old 8390's won't clear the ISR flag
2474 * otherwise - resulting in an infinite loop.
2475 */
2476 if (isr & ED_ISR_CNT) {
2477 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2478 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2479 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2480 }
2481 }
2482}
2483
2484/*
2485 * Process an ioctl request. This code needs some work - it looks
2486 * pretty ugly.
2487 */
2488static int
2489ed_ioctl(ifp, command, data)
2490 register struct ifnet *ifp;
2491 u_long command;
2492 caddr_t data;
2493{
2494 struct ed_softc *sc = ifp->if_softc;
2495 int s, error = 0;
2496
2497 if (sc == NULL || sc->gone) {
2498 ifp->if_flags &= ~IFF_RUNNING;
2499 return ENXIO;
2500 }
2501 s = splimp();
2502
2503 switch (command) {
2504
2505 case SIOCSIFADDR:
2506 case SIOCGIFADDR:
2507 case SIOCSIFMTU:
2508 error = ether_ioctl(ifp, command, data);
2509 break;
2510
2511 case SIOCSIFFLAGS:
2512
2513 /*
2514 * If the interface is marked up and stopped, then start it.
2515 * If it is marked down and running, then stop it.
2516 */
2517 if (ifp->if_flags & IFF_UP) {
2518 if ((ifp->if_flags & IFF_RUNNING) == 0)
2519 ed_init(sc);
2520 } else {
2521 if (ifp->if_flags & IFF_RUNNING) {
2522 ed_stop(sc);
2523 ifp->if_flags &= ~IFF_RUNNING;
2524 }
2525 }
2526
2527 /*
2528 * Promiscuous flag may have changed, so reprogram the RCR.
2529 */
2530 ed_setrcr(sc);
2531
2532 /*
2533 * An unfortunate hack to provide the (required) software
2534 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2535 * disables the tranceiver if set.
2536 */
2537 if (sc->vendor == ED_VENDOR_3COM) {
2538 if (ifp->if_flags & IFF_ALTPHYS) {
2539 ed_asic_outb(sc, ED_3COM_CR, 0);
2540 } else {
2541 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2542 }
2543 } else if (sc->vendor == ED_VENDOR_HP)
2544 ed_hpp_set_physical_link(sc);
2545 break;
2546
2547 case SIOCADDMULTI:
2548 case SIOCDELMULTI:
2549 /*
2550 * Multicast list has changed; set the hardware filter
2551 * accordingly.
2552 */
2553 ed_setrcr(sc);
2554 error = 0;
2555 break;
2556
2557 default:
2558 error = EINVAL;
2559 }
2560 (void) splx(s);
2561 return (error);
2562}
2563
2564/*
2565 * Given a source and destination address, copy 'amount' of a packet from
2566 * the ring buffer into a linear destination buffer. Takes into account
2567 * ring-wrap.
2568 */
2569static __inline char *
2570ed_ring_copy(sc, src, dst, amount)
2571 struct ed_softc *sc;
2572 char *src;
2573 char *dst;
2574 u_short amount;
2575{
2576 u_short tmp_amount;
2577
2578 /* does copy wrap to lower addr in ring buffer? */
2579 if (src + amount > sc->mem_end) {
2580 tmp_amount = sc->mem_end - src;
2581
2582 /* copy amount up to end of NIC memory */
2583 if (sc->mem_shared)
2584 bcopy(src, dst, tmp_amount);
2585 else
2586 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2587
2588 amount -= tmp_amount;
2589 src = sc->mem_ring;
2590 dst += tmp_amount;
2591 }
2592 if (sc->mem_shared)
2593 bcopy(src, dst, amount);
2594 else
2595 ed_pio_readmem(sc, (int)src, dst, amount);
2596
2597 return (src + amount);
2598}
2599
2600/*
2601 * Retreive packet from shared memory and send to the next level up via
2602 * ether_input().
2603 */
2604static void
2605ed_get_packet(sc, buf, len)
2606 struct ed_softc *sc;
2607 char *buf;
2608 u_short len;
2609{
2610 struct ether_header *eh;
2611 struct mbuf *m;
2612
2613 /* Allocate a header mbuf */
2614 MGETHDR(m, M_DONTWAIT, MT_DATA);
2615 if (m == NULL)
2616 return;
2617 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2618 m->m_pkthdr.len = m->m_len = len;
2619
2620 /*
2621 * We always put the received packet in a single buffer -
2622 * either with just an mbuf header or in a cluster attached
2623 * to the header. The +2 is to compensate for the alignment
2624 * fixup below.
2625 */
2626 if ((len + 2) > MHLEN) {
2627 /* Attach an mbuf cluster */
2628 MCLGET(m, M_DONTWAIT);
2629
2630 /* Insist on getting a cluster */
2631 if ((m->m_flags & M_EXT) == 0) {
2632 m_freem(m);
2633 return;
2634 }
2635 }
2636
2637 /*
2638 * The +2 is to longword align the start of the real packet.
2639 * This is important for NFS.
2640 */
2641 m->m_data += 2;
2642 eh = mtod(m, struct ether_header *);
2643
2644#ifdef BRIDGE
2645 /*
2646 * Don't read in the entire packet if we know we're going to drop it
2647 * and no bpf is active.
2648 */
2649 if (!sc->arpcom.ac_if.if_bpf &&
2650 do_bridge && BDG_USED( (&sc->arpcom.ac_if) ) ) {
2651 struct ifnet *bif;
2652
2653 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2654 bif = bridge_in(&sc->arpcom.ac_if, eh) ;
2655 if (bif == BDG_DROP) {
2656 m_freem(m);
2657 return;
2658 }
2659 if (len > ETHER_HDR_LEN)
2660 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2661 (char *)(eh + 1), len - ETHER_HDR_LEN);
2662 } else
2663#endif
2664 /*
2665 * Get packet, including link layer address, from interface.
2666 */
2667 ed_ring_copy(sc, buf, (char *)eh, len);
2668
2669 /*
2670 * Remove link layer address.
2671 */
2672 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2673 m->m_data += sizeof(struct ether_header);
2674
2675 ether_input(&sc->arpcom.ac_if, eh, m);
2676}
2677
2678/*
2679 * Supporting routines
2680 */
2681
2682/*
2683 * Given a NIC memory source address and a host memory destination
2684 * address, copy 'amount' from NIC to host using Programmed I/O.
2685 * The 'amount' is rounded up to a word - okay as long as mbufs
2686 * are word sized.
2687 * This routine is currently Novell-specific.
2688 */
2689void
2690ed_pio_readmem(sc, src, dst, amount)
2691 struct ed_softc *sc;
2692 int src;
2693 unsigned char *dst;
2694 unsigned short amount;
2695{
2696 /* HP PC Lan+ cards need special handling */
2697 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2698 ed_hpp_readmem(sc, src, dst, amount);
2699 return;
2700 }
2701
2702 /* Regular Novell cards */
2703 /* select page 0 registers */
2704 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2705
2706 /* round up to a word */
2707 if (amount & 1)
2708 ++amount;
2709
2710 /* set up DMA byte count */
2711 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2712 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2713
2714 /* set up source address in NIC mem */
2715 ed_nic_outb(sc, ED_P0_RSAR0, src);
2716 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2717
2718 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2719
2720 if (sc->isa16bit) {
2721 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2722 } else {
2723 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2724 }
2725}
2726
2727/*
2728 * Stripped down routine for writing a linear buffer to NIC memory.
2729 * Only used in the probe routine to test the memory. 'len' must
2730 * be even.
2731 */
2732void
2733ed_pio_writemem(sc, src, dst, len)
2734 struct ed_softc *sc;
2735 char *src;
2736 unsigned short dst;
2737 unsigned short len;
2738{
2739 int maxwait = 200; /* about 240us */
2740
2741 /* select page 0 registers */
2742 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2743
2744 /* reset remote DMA complete flag */
2745 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2746
2747 /* set up DMA byte count */
2748 ed_nic_outb(sc, ED_P0_RBCR0, len);
2749 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2750
2751 /* set up destination address in NIC mem */
2752 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2753 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2754
2755 /* set remote DMA write */
2756 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2757
2758 if (sc->isa16bit) {
2759 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2760 } else {
2761 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2762 }
2763
2764 /*
2765 * Wait for remote DMA complete. This is necessary because on the
2766 * transmit side, data is handled internally by the NIC in bursts and
2767 * we can't start another remote DMA until this one completes. Not
2768 * waiting causes really bad things to happen - like the NIC
2769 * irrecoverably jamming the ISA bus.
2770 */
2771 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2772}
2773
2774/*
2775 * Write an mbuf chain to the destination NIC memory address using
2776 * programmed I/O.
2777 */
2778static u_short
2779ed_pio_write_mbufs(sc, m, dst)
2780 struct ed_softc *sc;
2781 struct mbuf *m;
2782 int dst;
2783{
2784 struct ifnet *ifp = (struct ifnet *)sc;
2785 unsigned short total_len, dma_len;
2786 struct mbuf *mp;
2787 int maxwait = 200; /* about 240us */
2788
2789 /* HP PC Lan+ cards need special handling */
2790 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2791 return ed_hpp_write_mbufs(sc, m, dst);
2792 }
2793
2794 /* Regular Novell cards */
2795 /* First, count up the total number of bytes to copy */
2796 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2797 total_len += mp->m_len;
2798
2799 dma_len = total_len;
2800 if (sc->isa16bit && (dma_len & 1))
2801 dma_len++;
2802
2803 /* select page 0 registers */
2804 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2805
2806 /* reset remote DMA complete flag */
2807 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2808
2809 /* set up DMA byte count */
2810 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2811 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2812
2813 /* set up destination address in NIC mem */
2814 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2815 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2816
2817 /* set remote DMA write */
2818 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2819
2820 /*
2821 * Transfer the mbuf chain to the NIC memory.
2822 * 16-bit cards require that data be transferred as words, and only words.
2823 * So that case requires some extra code to patch over odd-length mbufs.
2824 */
2825
2826 if (!sc->isa16bit) {
2827 /* NE1000s are easy */
2828 while (m) {
2829 if (m->m_len) {
2830 ed_asic_outsb(sc, ED_NOVELL_DATA,
2831 m->m_data, m->m_len);
2832 }
2833 m = m->m_next;
2834 }
2835 } else {
2836 /* NE2000s are a pain */
2837 unsigned char *data;
2838 int len, wantbyte;
2839 unsigned char savebyte[2];
2840
2841 wantbyte = 0;
2842
2843 while (m) {
2844 len = m->m_len;
2845 if (len) {
2846 data = mtod(m, caddr_t);
2847 /* finish the last word */
2848 if (wantbyte) {
2849 savebyte[1] = *data;
2850 ed_asic_outw(sc, ED_NOVELL_DATA,
2851 *(u_short *)savebyte);
2852 data++;
2853 len--;
2854 wantbyte = 0;
2855 }
2856 /* output contiguous words */
2857 if (len > 1) {
2858 ed_asic_outsw(sc, ED_NOVELL_DATA,
2859 data, len >> 1);
2860 data += len & ~1;
2861 len &= 1;
2862 }
2863 /* save last byte, if necessary */
2864 if (len == 1) {
2865 savebyte[0] = *data;
2866 wantbyte = 1;
2867 }
2868 }
2869 m = m->m_next;
2870 }
2871 /* spit last byte */
2872 if (wantbyte) {
2873 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2874 }
2875 }
2876
2877 /*
2878 * Wait for remote DMA complete. This is necessary because on the
2879 * transmit side, data is handled internally by the NIC in bursts and
2880 * we can't start another remote DMA until this one completes. Not
2881 * waiting causes really bad things to happen - like the NIC
2882 * irrecoverably jamming the ISA bus.
2883 */
2884 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2885
2886 if (!maxwait) {
2887 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2888 ifp->if_unit);
2889 ed_reset(ifp);
2890 return(0);
2891 }
2892 return (total_len);
2893}
2894
2895/*
2896 * Support routines to handle the HP PC Lan+ card.
2897 */
2898
2899/*
2900 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2901 * IO.
2902 */
2903
2904static void
2905ed_hpp_readmem(sc, src, dst, amount)
2906 struct ed_softc *sc;
2907 unsigned short src;
2908 unsigned char *dst;
2909 unsigned short amount;
2910{
2911
2912 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2913
2914
2915 /* Program the source address in RAM */
2916 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2917
2918 /*
2919 * The HP PC Lan+ card supports word reads as well as
2920 * a memory mapped i/o port that is aliased to every
2921 * even address on the board.
2922 */
2923
2924 if (sc->hpp_mem_start) {
2925
2926 /* Enable memory mapped access. */
2927 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2928 ~(ED_HPP_OPTION_MEM_DISABLE |
2929 ED_HPP_OPTION_BOOT_ROM_ENB));
2930
2931 if (use_32bit_access && (amount > 3)) {
2932 u_int32_t *dl = (u_int32_t *) dst;
2933 volatile u_int32_t *const sl =
2934 (u_int32_t *) sc->hpp_mem_start;
2935 u_int32_t *const fence = dl + (amount >> 2);
2936
2937 /* Copy out NIC data. We could probably write this
2938 as a `movsl'. The currently generated code is lousy.
2939 */
2940
2941 while (dl < fence)
2942 *dl++ = *sl;
2943
2944 dst += (amount & ~3);
2945 amount &= 3;
2946
2947 }
2948
2949 /* Finish off any words left, as a series of short reads */
2950 if (amount > 1) {
2951 u_short *d = (u_short *) dst;
2952 volatile u_short *const s =
2953 (u_short *) sc->hpp_mem_start;
2954 u_short *const fence = d + (amount >> 1);
2955
2956 /* Copy out NIC data. */
2957
2958 while (d < fence)
2959 *d++ = *s;
2960
2961 dst += (amount & ~1);
2962 amount &= 1;
2963 }
2964
2965 /*
2966 * read in a byte; however we need to always read 16 bits
2967 * at a time or the hardware gets into a funny state
2968 */
2969
2970 if (amount == 1) {
2971 /* need to read in a short and copy LSB */
2972 volatile u_short *const s =
2973 (volatile u_short *) sc->hpp_mem_start;
2974
2975 *dst = (*s) & 0xFF;
2976 }
2977
2978 /* Restore Boot ROM access. */
2979
2980 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
2981
2982
2983 } else {
2984 /* Read in data using the I/O port */
2985 if (use_32bit_access && (amount > 3)) {
2986 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
2987 dst += (amount & ~3);
2988 amount &= 3;
2989 }
2990 if (amount > 1) {
2991 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
2992 dst += (amount & ~1);
2993 amount &= 1;
2994 }
2995 if (amount == 1) { /* read in a short and keep the LSB */
2996 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
2997 }
2998 }
2999}
3000
3001/*
3002 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3003 * IO.
3004 * Only used in the probe routine to test the memory. 'len' must
3005 * be even.
3006 */
3007void
3008ed_hpp_writemem(sc, src, dst, len)
3009 struct ed_softc *sc;
3010 unsigned char *src;
3011 unsigned short dst;
3012 unsigned short len;
3013{
3014 /* reset remote DMA complete flag */
3015 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3016
3017 /* program the write address in RAM */
3018 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3019
3020 if (sc->hpp_mem_start) {
3021 u_short *s = (u_short *) src;
3022 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3023 u_short *const fence = s + (len >> 1);
3024
3025 /*
3026 * Enable memory mapped access.
3027 */
3028
3029 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3030 ~(ED_HPP_OPTION_MEM_DISABLE |
3031 ED_HPP_OPTION_BOOT_ROM_ENB));
3032
3033 /*
3034 * Copy to NIC memory.
3035 */
3036
3037 while (s < fence)
3038 *d = *s++;
3039
3040 /*
3041 * Restore Boot ROM access.
3042 */
3043
3044 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3045
3046 } else {
3047 /* write data using I/O writes */
3048 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3049 }
3050}
3051
3052/*
3053 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3054 * outsw() or via the memory mapped interface to the same register.
3055 * Writes have to be in word units; byte accesses won't work and may cause
3056 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3057 * allows it.
3058 */
3059
3060static u_short
3061ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3062{
3063 int len, wantbyte;
3064 unsigned short total_len;
3065 unsigned char savebyte[2];
3066 volatile u_short * const d =
3067 (volatile u_short *) sc->hpp_mem_start;
3068 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3069
3070 /* select page 0 registers */
3071 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3072
3073 /* reset remote DMA complete flag */
3074 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3075
3076 /* program the write address in RAM */
3077 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3078
3079 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3080 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3081 ~(ED_HPP_OPTION_MEM_DISABLE |
3082 ED_HPP_OPTION_BOOT_ROM_ENB));
3083
3084 wantbyte = 0;
3085 total_len = 0;
3086
3087 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3088 while (m) {
3089 total_len += (len = m->m_len);
3090 if (len) {
3091 caddr_t data = mtod(m, caddr_t);
3092 /* finish the last word of the previous mbuf */
3093 if (wantbyte) {
3094 savebyte[1] = *data;
3095 *d = *((ushort *) savebyte);
3096 data++; len--; wantbyte = 0;
3097 }
3098 /* output contiguous words */
3099 if ((len > 3) && (use_32bit_accesses)) {
3100 volatile u_int32_t *const dl =
3101 (volatile u_int32_t *) d;
3102 u_int32_t *sl = (u_int32_t *) data;
3103 u_int32_t *fence = sl + (len >> 2);
3104
3105 while (sl < fence)
3106 *dl = *sl++;
3107
3108 data += (len & ~3);
3109 len &= 3;
3110 }
3111 /* finish off remain 16 bit writes */
3112 if (len > 1) {
3113 u_short *s = (u_short *) data;
3114 u_short *fence = s + (len >> 1);
3115
3116 while (s < fence)
3117 *d = *s++;
3118
3119 data += (len & ~1);
3120 len &= 1;
3121 }
3122 /* save last byte if needed */
3123 if ((wantbyte = (len == 1)) != 0)
3124 savebyte[0] = *data;
3125 }
3126 m = m->m_next; /* to next mbuf */
3127 }
3128 if (wantbyte) /* write last byte */
3129 *d = *((u_short *) savebyte);
3130 } else {
3131 /* use programmed I/O */
3132 while (m) {
3133 total_len += (len = m->m_len);
3134 if (len) {
3135 caddr_t data = mtod(m, caddr_t);
3136 /* finish the last word of the previous mbuf */
3137 if (wantbyte) {
3138 savebyte[1] = *data;
3139 ed_asic_outw(sc, ED_HPP_PAGE_4,
3140 *((u_short *)savebyte));
3141 data++;
3142 len--;
3143 wantbyte = 0;
3144 }
3145 /* output contiguous words */
3146 if ((len > 3) && use_32bit_accesses) {
3147 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3148 data, len >> 2);
3149 data += (len & ~3);
3150 len &= 3;
3151 }
3152 /* finish off remaining 16 bit accesses */
3153 if (len > 1) {
3154 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3155 data, len >> 1);
3156 data += (len & ~1);
3157 len &= 1;
3158 }
3159 if ((wantbyte = (len == 1)) != 0)
3160 savebyte[0] = *data;
3161
3162 } /* if len != 0 */
3163 m = m->m_next;
3164 }
3165 if (wantbyte) /* spit last byte */
3166 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3167
3168 }
3169
3170 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3171 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3172
3173 return (total_len);
3174}
3175
3176static void
3177ed_setrcr(sc)
3178 struct ed_softc *sc;
3179{
3180 struct ifnet *ifp = (struct ifnet *)sc;
3181 int i;
3182 u_char reg1;
3183
3184 /* Bit 6 in AX88190 RCR register must be set. */
3185 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3186 reg1 = ED_RCR_INTT;
3187 else
3188 reg1 = 0x00;
3189
3190 /* set page 1 registers */
3191 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3192
3193 if (ifp->if_flags & IFF_PROMISC) {
3194
3195 /*
3196 * Reconfigure the multicast filter.
3197 */
3198 for (i = 0; i < 8; i++)
3199 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3200
3201 /*
3202 * And turn on promiscuous mode. Also enable reception of
3203 * runts and packets with CRC & alignment errors.
3204 */
3205 /* Set page 0 registers */
3206 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3207
3208 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3209 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3210 } else {
3211 /* set up multicast addresses and filter modes */
3212 if (ifp->if_flags & IFF_MULTICAST) {
3213 u_int32_t mcaf[2];
3214
3215 if (ifp->if_flags & IFF_ALLMULTI) {
3216 mcaf[0] = 0xffffffff;
3217 mcaf[1] = 0xffffffff;
3218 } else
3219 ds_getmcaf(sc, mcaf);
3220
3221 /*
3222 * Set multicast filter on chip.
3223 */
3224 for (i = 0; i < 8; i++)
3225 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3226
3227 /* Set page 0 registers */
3228 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3229
3230 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3231 } else {
3232
3233 /*
3234 * Initialize multicast address hashing registers to
3235 * not accept multicasts.
3236 */
3237 for (i = 0; i < 8; ++i)
3238 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3239
3240 /* Set page 0 registers */
3241 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3242
3243 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3244 }
3245 }
3246
3247 /*
3248 * Start interface.
3249 */
3250 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3251}
3252
3253/*
3254 * Compute crc for ethernet address
3255 */
3256static u_int32_t
3257ds_crc(ep)
3258 u_char *ep;
3259{
3260#define POLYNOMIAL 0x04c11db6
3261 register u_int32_t crc = 0xffffffff;
3262 register int carry, i, j;
3263 register u_char b;
3264
3265 for (i = 6; --i >= 0;) {
3266 b = *ep++;
3267 for (j = 8; --j >= 0;) {
3268 carry = ((crc & 0x80000000) ? 1 : 0) ^ (b & 0x01);
3269 crc <<= 1;
3270 b >>= 1;
3271 if (carry)
3272 crc = (crc ^ POLYNOMIAL) | carry;
3273 }
3274 }
3275 return crc;
3276#undef POLYNOMIAL
3277}
3278
3279/*
3280 * Compute the multicast address filter from the
3281 * list of multicast addresses we need to listen to.
3282 */
3283static void
3284ds_getmcaf(sc, mcaf)
3285 struct ed_softc *sc;
3286 u_int32_t *mcaf;
3287{
3288 register u_int32_t index;
3289 register u_char *af = (u_char *) mcaf;
3290 struct ifmultiaddr *ifma;
3291
3292 mcaf[0] = 0;
3293 mcaf[1] = 0;
3294
3295 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
3296 if (ifma->ifma_addr->sa_family != AF_LINK)
3297 continue;
3298 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3299 >> 26;
3300 af[index >> 3] |= 1 << (index & 7);
3301 }
3302}