1/*
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_ed.c,v 1.139 1998/04/15 17:45:15 bde Exp $
28 */
29
30/*
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
33 *
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
37 *
38 */
39
40#include "ed.h"
41#include "bpfilter.h"
42#include "pnp.h"
43
44#ifndef EXTRA_ED
45# if NPNP > 0
46# define EXTRA_ED 8
47# else
48# define EXTRA_ED 0
49# endif
50#endif
51
52#define NEDTOT (NED + EXTRA_ED)
53
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/conf.h>
57#include <sys/sockio.h>
58#include <sys/malloc.h>
59#include <sys/mbuf.h>
60#include <sys/socket.h>
61#include <sys/syslog.h>
62
63#include <net/ethernet.h>
64#include <net/if.h>
65#include <net/if_arp.h>
66#include <net/if_dl.h>
67#include <net/if_mib.h>
68
69#if NBPFILTER > 0
70#include <net/bpf.h>
71#endif
72
73#if NPNP > 0
74#include <i386/isa/pnp.h>
75#endif
76
77#include <machine/clock.h>
78#include <machine/md_var.h>
79
80#include <i386/isa/isa_device.h>
81#include <i386/isa/icu.h>
82#include <i386/isa/if_edreg.h>
83
84/*
85 * ed_softc: per line info and status
86 */
87struct ed_softc {
88 struct arpcom arpcom; /* ethernet common */
89
90 char *type_str; /* pointer to type string */
91 u_char vendor; /* interface vendor */
92 u_char type; /* interface type code */
93 u_char gone; /* HW missing, presumed having a good time */
94
95 u_short asic_addr; /* ASIC I/O bus address */
96 u_short nic_addr; /* NIC (DS8390) I/O bus address */
97
98/*
99 * The following 'proto' variable is part of a work-around for 8013EBT asics
100 * being write-only. It's sort of a prototype/shadow of the real thing.
101 */
102 u_char wd_laar_proto;
103 u_char cr_proto;
104 u_char isa16bit; /* width of access to card 0=8 or 1=16 */
105 int is790; /* set by the probe code if the card is 790
106 * based */
107
108/*
109 * HP PC LAN PLUS card support.
110 */
111
112 u_short hpp_options; /* flags controlling behaviour of the HP card */
113 u_short hpp_id; /* software revision and other fields */
114 caddr_t hpp_mem_start; /* Memory-mapped IO register address */
115
116 caddr_t mem_start; /* NIC memory start address */
117 caddr_t mem_end; /* NIC memory end address */
118 u_long mem_size; /* total NIC memory size */
119 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
120
121 u_char mem_shared; /* NIC memory is shared with host */
122 u_char xmit_busy; /* transmitter is busy */
123 u_char txb_cnt; /* number of transmit buffers */
124 u_char txb_inuse; /* number of TX buffers currently in-use */
125
126 u_char txb_new; /* pointer to where new buffer will be added */
127 u_char txb_next_tx; /* pointer to next buffer ready to xmit */
128 u_short txb_len[8]; /* buffered xmit buffer lengths */
129 u_char tx_page_start; /* first page of TX buffer area */
130 u_char rec_page_start; /* first page of RX ring-buffer */
131 u_char rec_page_stop; /* last page of RX ring-buffer */
132 u_char next_packet; /* pointer to next unread RX packet */
133 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
134};
135
136static struct ed_softc ed_softc[NEDTOT];
137
138static int ed_attach __P((struct ed_softc *, int, int));
139static int ed_attach_isa __P((struct isa_device *));
140
141static void ed_init __P((void *));
142static int ed_ioctl __P((struct ifnet *, int, caddr_t));
143static int ed_probe __P((struct isa_device *));
144static void ed_start __P((struct ifnet *));
145static void ed_reset __P((struct ifnet *));
146static void ed_watchdog __P((struct ifnet *));
147
148static void ed_stop __P((struct ed_softc *));
149static int ed_probe_generic8390 __P((struct ed_softc *));
150static int ed_probe_WD80x3 __P((struct isa_device *));
151static int ed_probe_3Com __P((struct isa_device *));
152static int ed_probe_Novell __P((struct isa_device *));
153static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
154static int ed_probe_HP_pclanp __P((struct isa_device *));
155
156#include "pci.h"
157#if NPCI > 0
158void *ed_attach_NE2000_pci __P((int, int));
159#endif
160
161#include "card.h"
162#if NCARD > 0
163static int ed_probe_pccard __P((struct isa_device *, u_char *));
164#endif
165
166static void ds_getmcaf __P((struct ed_softc *, u_long *));
167
168static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int));
169
170static __inline void ed_rint __P((struct ed_softc *));
171static __inline void ed_xmit __P((struct ed_softc *));
172static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
173 /* u_short */ int));
174static void ed_hpp_set_physical_link __P((struct ed_softc *));
175static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
176 /* u_short */ int));
177static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
178 int));
179
180static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
181 /* u_short */ int));
182static void ed_pio_writemem __P((struct ed_softc *, char *,
183 /* u_short */ int, /* u_short */ int));
184static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
185 int));
186void edintr_sc __P((struct ed_softc *));
187
188static void ed_setrcr __P((struct ed_softc *));
189
190static u_long ds_crc __P((u_char *ep));
191
192#if (NCARD > 0) || (NPNP > 0)
193#include <sys/kernel.h>
194#endif
195#if NCARD > 0
196#include <sys/select.h>
197#include <pccard/cardinfo.h>
198#include <pccard/slot.h>
199
200/*
201 * PC-Card (PCMCIA) specific code.
202 */
203static int edinit __P((struct pccard_devinfo *));
204static void edunload __P((struct pccard_devinfo *));
205static int card_intr __P((struct pccard_devinfo *));
206
207static struct pccard_device ed_info = {
208 "ed",
209 edinit,
210 edunload,
211 card_intr,
212 0, /* Attributes - presently unused */
213 &net_imask /* Interrupt mask for device */
214 /* XXX - Should this also include net_imask? */
215};
216
217DATA_SET(pccarddrv_set, ed_info);
218
219/*
220 * Initialize the device - called from Slot manager.
221 */
222static int
223edinit(struct pccard_devinfo *devi)
224{
225 int i;
226 u_char e;
227 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
228
229 /* validate unit number. */
230 if (devi->isahd.id_unit >= NEDTOT)
231 return(ENODEV);
232 /*
233 * Probe the device. If a value is returned, the
234 * device was found at the location.
235 */
236 sc->gone = 0;
237 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0)
238 return(ENXIO);
239 e = 0;
240 for (i = 0; i < ETHER_ADDR_LEN; ++i)
241 e |= devi->misc[i];
242 if (e)
243 for (i = 0; i < ETHER_ADDR_LEN; ++i)
244 sc->arpcom.ac_enaddr[i] = devi->misc[i];
245 if (ed_attach_isa(&devi->isahd) == 0)
246 return(ENXIO);
247
248 return(0);
249}
250
251/*
252 * edunload - unload the driver and clear the table.
253 * XXX TODO:
254 * This is usually called when the card is ejected, but
255 * can be caused by a modunload of a controller driver.
256 * The idea is to reset the driver's view of the device
257 * and ensure that any driver entry points such as
258 * read and write do not hang.
259 */
260static void
261edunload(struct pccard_devinfo *devi)
262{
263 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
264 struct ifnet *ifp = &sc->arpcom.ac_if;
265
266 if (sc->gone) {
267 printf("ed%d: already unloaded\n", devi->isahd.id_unit);
268 return;
269 }
270 ifp->if_flags &= ~IFF_RUNNING;
271 if_down(ifp);
272 sc->gone = 1;
273 printf("ed%d: unload\n", devi->isahd.id_unit);
274}
275
276/*
277 * card_intr - Shared interrupt called from
278 * front end of PC-Card handler.
279 */
280static int
281card_intr(struct pccard_devinfo *devi)
282{
283 edintr_sc(&ed_softc[devi->isahd.id_unit]);
284 return(1);
285}
286#endif /* NCARD > 0 */
287
288struct isa_driver eddriver = {
289 ed_probe,
290 ed_attach_isa,
291 "ed",
292 1 /* We are ultra sensitive */
293};
294
295/*
296 * Interrupt conversion table for WD/SMC ASIC/83C584
297 * (IRQ* are defined in icu.h)
298 */
299static unsigned short ed_intr_mask[] = {
300 IRQ9,
301 IRQ3,
302 IRQ5,
303 IRQ7,
304 IRQ10,
305 IRQ11,
306 IRQ15,
307 IRQ4
308};
309
310/*
311 * Interrupt conversion table for 83C790
312 */
313static unsigned short ed_790_intr_mask[] = {
314 0,
315 IRQ9,
316 IRQ3,
317 IRQ5,
318 IRQ7,
319 IRQ10,
320 IRQ11,
321 IRQ15
322};
323
324/*
325 * Interrupt conversion table for the HP PC LAN+
326 */
327
328static unsigned short ed_hpp_intr_mask[] = {
329 0, /* 0 */
330 0, /* 1 */
331 0, /* 2 */
332 IRQ3, /* 3 */
333 IRQ4, /* 4 */
334 IRQ5, /* 5 */
335 IRQ6, /* 6 */
336 IRQ7, /* 7 */
337 0, /* 8 */
338 IRQ9, /* 9 */
339 IRQ10, /* 10 */
340 IRQ11, /* 11 */
341 IRQ12, /* 12 */
342 0, /* 13 */
343 0, /* 14 */
344 IRQ15 /* 15 */
345};
346
347/*
348 * Determine if the device is present
349 *
350 * on entry:
351 * a pointer to an isa_device struct
352 * on exit:
353 * NULL if device not found
354 * or # of i/o addresses used (if found)
355 */
356static int
357ed_probe(isa_dev)
358 struct isa_device *isa_dev;
359{
360 int nports;
361
362 nports = ed_probe_WD80x3(isa_dev);
363 if (nports)
364 return (nports);
365
366 nports = ed_probe_3Com(isa_dev);
367 if (nports)
368 return (nports);
369
370 nports = ed_probe_Novell(isa_dev);
371 if (nports)
372 return (nports);
373
374 nports = ed_probe_HP_pclanp(isa_dev);
375 if (nports)
376 return (nports);
377
378 return (0);
379}
380
381/*
382 * Generic probe routine for testing for the existance of a DS8390.
383 * Must be called after the NIC has just been reset. This routine
384 * works by looking at certain register values that are guaranteed
385 * to be initialized a certain way after power-up or reset. Seems
386 * not to currently work on the 83C690.
387 *
388 * Specifically:
389 *
390 * Register reset bits set bits
391 * Command Register (CR) TXP, STA RD2, STP
392 * Interrupt Status (ISR) RST
393 * Interrupt Mask (IMR) All bits
394 * Data Control (DCR) LAS
395 * Transmit Config. (TCR) LB1, LB0
396 *
397 * We only look at the CR and ISR registers, however, because looking at
398 * the others would require changing register pages (which would be
399 * intrusive if this isn't an 8390).
400 *
401 * Return 1 if 8390 was found, 0 if not.
402 */
403
404static int
405ed_probe_generic8390(sc)
406 struct ed_softc *sc;
407{
408 if ((inb(sc->nic_addr + ED_P0_CR) &
409 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
410 (ED_CR_RD2 | ED_CR_STP))
411 return (0);
412 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
413 return (0);
414
415 return (1);
416}
417
418/*
419 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
420 */
421static int
422ed_probe_WD80x3(isa_dev)
423 struct isa_device *isa_dev;
424{
425 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
426 int i;
427 u_int memsize, maddr;
428 u_char iptr, isa16bit, sum;
429
430 sc->asic_addr = isa_dev->id_iobase;
431 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
432 sc->is790 = 0;
433
434#ifdef TOSH_ETHER
435 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
436 DELAY(10000);
437#endif
438
439 /*
440 * Attempt to do a checksum over the station address PROM. If it
441 * fails, it's probably not a SMC/WD board. There is a problem with
442 * this, though: some clone WD boards don't pass the checksum test.
443 * Danpex boards for one.
444 */
445 for (sum = 0, i = 0; i < 8; ++i)
446 sum += inb(sc->asic_addr + ED_WD_PROM + i);
447
448 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
449
450 /*
451 * Checksum is invalid. This often happens with cheap WD8003E
452 * clones. In this case, the checksum byte (the eighth byte)
453 * seems to always be zero.
454 */
455 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
456 inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
457 return (0);
458 }
459 /* reset card to force it into a known state. */
460#ifdef TOSH_ETHER
461 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
462#else
463 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
464#endif
465 DELAY(100);
466 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
467 /* wait in the case this card is reading its EEROM */
468 DELAY(5000);
469
470 sc->vendor = ED_VENDOR_WD_SMC;
471 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
472
473 /*
474 * Set initial values for width/size.
475 */
476 memsize = 8192;
477 isa16bit = 0;
478 switch (sc->type) {
479 case ED_TYPE_WD8003S:
480 sc->type_str = "WD8003S";
481 break;
482 case ED_TYPE_WD8003E:
483 sc->type_str = "WD8003E";
484 break;
485 case ED_TYPE_WD8003EB:
486 sc->type_str = "WD8003EB";
487 break;
488 case ED_TYPE_WD8003W:
489 sc->type_str = "WD8003W";
490 break;
491 case ED_TYPE_WD8013EBT:
492 sc->type_str = "WD8013EBT";
493 memsize = 16384;
494 isa16bit = 1;
495 break;
496 case ED_TYPE_WD8013W:
497 sc->type_str = "WD8013W";
498 memsize = 16384;
499 isa16bit = 1;
500 break;
501 case ED_TYPE_WD8013EP: /* also WD8003EP */
502 if (inb(sc->asic_addr + ED_WD_ICR)
503 & ED_WD_ICR_16BIT) {
504 isa16bit = 1;
505 memsize = 16384;
506 sc->type_str = "WD8013EP";
507 } else {
508 sc->type_str = "WD8003EP";
509 }
510 break;
511 case ED_TYPE_WD8013WC:
512 sc->type_str = "WD8013WC";
513 memsize = 16384;
514 isa16bit = 1;
515 break;
516 case ED_TYPE_WD8013EBP:
517 sc->type_str = "WD8013EBP";
518 memsize = 16384;
519 isa16bit = 1;
520 break;
521 case ED_TYPE_WD8013EPC:
522 sc->type_str = "WD8013EPC";
523 memsize = 16384;
524 isa16bit = 1;
525 break;
526 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
527 case ED_TYPE_SMC8216T:
528 if (sc->type == ED_TYPE_SMC8216C) {
529 sc->type_str = "SMC8216/SMC8216C";
530 } else {
531 sc->type_str = "SMC8216T";
532 }
533
534 outb(sc->asic_addr + ED_WD790_HWR,
535 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
536 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
537 case ED_WD790_RAR_SZ64:
538 memsize = 65536;
539 break;
540 case ED_WD790_RAR_SZ32:
541 memsize = 32768;
542 break;
543 case ED_WD790_RAR_SZ16:
544 memsize = 16384;
545 break;
546 case ED_WD790_RAR_SZ8:
547 /* 8216 has 16K shared mem -- 8416 has 8K */
548 if (sc->type == ED_TYPE_SMC8216C) {
549 sc->type_str = "SMC8416C/SMC8416BT";
550 } else {
551 sc->type_str = "SMC8416T";
552 }
553 memsize = 8192;
554 break;
555 }
556 outb(sc->asic_addr + ED_WD790_HWR,
557 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
558
559 isa16bit = 1;
560 sc->is790 = 1;
561 break;
562#ifdef TOSH_ETHER
563 case ED_TYPE_TOSHIBA1:
564 sc->type_str = "Toshiba1";
565 memsize = 32768;
566 isa16bit = 1;
567 break;
568 case ED_TYPE_TOSHIBA4:
569 sc->type_str = "Toshiba4";
570 memsize = 32768;
571 isa16bit = 1;
572 break;
573#endif
574 default:
575 sc->type_str = "";
576 break;
577 }
578
579 /*
580 * Make some adjustments to initial values depending on what is found
581 * in the ICR.
582 */
583 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
584#ifdef TOSH_ETHER
585 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
586#endif
587 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
588 isa16bit = 0;
589 memsize = 8192;
590 }
591
592#if ED_DEBUG
593 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
594 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
595 for (i = 0; i < 8; i++)
596 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
597#endif
598
599 /*
600 * Allow the user to override the autoconfiguration
601 */
602 if (isa_dev->id_msize)
603 memsize = isa_dev->id_msize;
604
605 maddr = (u_int) isa_dev->id_maddr & 0xffffff;
606 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
607 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n",
608 isa_dev->id_unit, maddr, maddr + memsize);
609 return 0;
610 }
611
612 /*
613 * (note that if the user specifies both of the following flags that
614 * '8bit' mode intentionally has precedence)
615 */
616 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
617 isa16bit = 1;
618 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
619 isa16bit = 0;
620
621 /*
622 * If possible, get the assigned interrupt number from the card and
623 * use it.
624 */
625 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
626
627 /*
628 * Assemble together the encoded interrupt number.
629 */
630 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
631 ((inb(isa_dev->id_iobase + ED_WD_IRR) &
632 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
633
634 /*
635 * If no interrupt specified (or "?"), use what the board tells us.
636 */
637 if (isa_dev->id_irq <= 0)
638 isa_dev->id_irq = ed_intr_mask[iptr];
639
640 /*
641 * Enable the interrupt.
642 */
643 outb(isa_dev->id_iobase + ED_WD_IRR,
644 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
645 }
646 if (sc->is790) {
647 outb(isa_dev->id_iobase + ED_WD790_HWR,
648 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
649 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
650 (inb(isa_dev->id_iobase + ED_WD790_GCR) &
651 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
652 outb(isa_dev->id_iobase + ED_WD790_HWR,
653 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
654
655 /*
656 * If no interrupt specified (or "?"), use what the board tells us.
657 */
658 if (isa_dev->id_irq <= 0)
659 isa_dev->id_irq = ed_790_intr_mask[iptr];
660
661 /*
662 * Enable interrupts.
663 */
664 outb(isa_dev->id_iobase + ED_WD790_ICR,
665 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
666 }
667 if (isa_dev->id_irq <= 0) {
668 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
669 isa_dev->id_unit, sc->type_str);
670 return (0);
671 }
672 sc->isa16bit = isa16bit;
673 sc->mem_shared = 1;
674 isa_dev->id_msize = memsize;
675 sc->mem_start = (caddr_t) isa_dev->id_maddr;
676
677 /*
678 * allocate one xmit buffer if < 16k, two buffers otherwise
679 */
680 if ((memsize < 16384) ||
681 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
682 sc->txb_cnt = 1;
683 } else {
684 sc->txb_cnt = 2;
685 }
686 sc->tx_page_start = ED_WD_PAGE_OFFSET;
687 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
688 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
689 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
690 sc->mem_size = memsize;
691 sc->mem_end = sc->mem_start + memsize;
692
693 /*
694 * Get station address from on-board ROM
695 */
696 for (i = 0; i < ETHER_ADDR_LEN; ++i)
697 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
698
699 /*
700 * Set upper address bits and 8/16 bit access to shared memory.
701 */
702 if (isa16bit) {
703 if (sc->is790) {
704 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
705 } else {
706 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
707 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
708 }
709 /*
710 * Enable 16bit access
711 */
712 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
713 ED_WD_LAAR_M16EN);
714 } else {
715 if (((sc->type & ED_WD_SOFTCONFIG) ||
716#ifdef TOSH_ETHER
717 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
718#endif
719 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
720 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
721 ED_WD_LAAR_ADDRHI;
722 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
723 }
724 }
725
726 /*
727 * Set address and enable interface shared memory.
728 */
729 if (!sc->is790) {
730#ifdef TOSH_ETHER
731 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
732 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
733 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
734
735#else
736 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
737 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
738#endif
739 sc->cr_proto = ED_CR_RD2;
740 } else {
741 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
742 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
743 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
744 ((kvtop(sc->mem_start) >> 11) & 0x40) |
745 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
746 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
747 sc->cr_proto = 0;
748 }
749
750#if 0
751 printf("starting memory performance test at 0x%x, size %d...\n",
752 sc->mem_start, memsize*16384);
753 for (i = 0; i < 16384; i++)
754 bzero(sc->mem_start, memsize);
755 printf("***DONE***\n");
756#endif
757
758 /*
759 * Now zero memory and verify that it is clear
760 */
761 bzero(sc->mem_start, memsize);
762
763 for (i = 0; i < memsize; ++i) {
764 if (sc->mem_start[i]) {
765 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
766 isa_dev->id_unit, kvtop(sc->mem_start + i));
767
768 /*
769 * Disable 16 bit access to shared memory
770 */
771 if (isa16bit) {
772 if (sc->is790) {
773 outb(sc->asic_addr + ED_WD_MSR, 0x00);
774 }
775 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
776 ~ED_WD_LAAR_M16EN);
777 }
778 return (0);
779 }
780 }
781
782 /*
783 * Disable 16bit access to shared memory - we leave it
784 * disabled so that 1) machines reboot properly when the board
785 * is set 16 bit mode and there are conflicting 8bit
786 * devices/ROMS in the same 128k address space as this boards
787 * shared memory. and 2) so that other 8 bit devices with
788 * shared memory can be used in this 128k region, too.
789 */
790 if (isa16bit) {
791 if (sc->is790) {
792 outb(sc->asic_addr + ED_WD_MSR, 0x00);
793 }
794 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
795 ~ED_WD_LAAR_M16EN);
796 }
797 return (ED_WD_IO_PORTS);
798}
799
800/*
801 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
802 */
803static int
804ed_probe_3Com(isa_dev)
805 struct isa_device *isa_dev;
806{
807 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
808 int i;
809 u_int memsize;
810 u_char isa16bit;
811
812 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
813 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
814
815 /*
816 * Verify that the kernel configured I/O address matches the board
817 * configured address
818 */
819 switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
820 case ED_3COM_BCFR_300:
821 if (isa_dev->id_iobase != 0x300)
822 return (0);
823 break;
824 case ED_3COM_BCFR_310:
825 if (isa_dev->id_iobase != 0x310)
826 return (0);
827 break;
828 case ED_3COM_BCFR_330:
829 if (isa_dev->id_iobase != 0x330)
830 return (0);
831 break;
832 case ED_3COM_BCFR_350:
833 if (isa_dev->id_iobase != 0x350)
834 return (0);
835 break;
836 case ED_3COM_BCFR_250:
837 if (isa_dev->id_iobase != 0x250)
838 return (0);
839 break;
840 case ED_3COM_BCFR_280:
841 if (isa_dev->id_iobase != 0x280)
842 return (0);
843 break;
844 case ED_3COM_BCFR_2A0:
845 if (isa_dev->id_iobase != 0x2a0)
846 return (0);
847 break;
848 case ED_3COM_BCFR_2E0:
849 if (isa_dev->id_iobase != 0x2e0)
850 return (0);
851 break;
852 default:
853 return (0);
854 }
855
856 /*
857 * Verify that the kernel shared memory address matches the board
858 * configured address.
859 */
860 switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
861 case ED_3COM_PCFR_DC000:
862 if (kvtop(isa_dev->id_maddr) != 0xdc000)
863 return (0);
864 break;
865 case ED_3COM_PCFR_D8000:
866 if (kvtop(isa_dev->id_maddr) != 0xd8000)
867 return (0);
868 break;
869 case ED_3COM_PCFR_CC000:
870 if (kvtop(isa_dev->id_maddr) != 0xcc000)
871 return (0);
872 break;
873 case ED_3COM_PCFR_C8000:
874 if (kvtop(isa_dev->id_maddr) != 0xc8000)
875 return (0);
876 break;
877 default:
878 return (0);
879 }
880
881
882 /*
883 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
884 * sequence because it'll lock up if the cable isn't connected if we
885 * don't.
886 */
887 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
888
889 /*
890 * Wait for a while, then un-reset it
891 */
892 DELAY(50);
893
894 /*
895 * The 3Com ASIC defaults to rather strange settings for the CR after
896 * a reset - it's important to set it again after the following outb
897 * (this is done when we map the PROM below).
898 */
899 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
900
901 /*
902 * Wait a bit for the NIC to recover from the reset
903 */
904 DELAY(5000);
905
906 sc->vendor = ED_VENDOR_3COM;
907 sc->type_str = "3c503";
908 sc->mem_shared = 1;
909 sc->cr_proto = ED_CR_RD2;
910
911 /*
912 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
913 * to it.
914 */
915 memsize = 8192;
916
917 /*
918 * Get station address from on-board ROM
919 */
920
921 /*
922 * First, map ethernet address PROM over the top of where the NIC
923 * registers normally appear.
924 */
925 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
926
927 for (i = 0; i < ETHER_ADDR_LEN; ++i)
928 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
929
930 /*
931 * Unmap PROM - select NIC registers. The proper setting of the
932 * tranceiver is set in ed_init so that the attach code is given a
933 * chance to set the default based on a compile-time config option
934 */
935 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
936
937 /*
938 * Determine if this is an 8bit or 16bit board
939 */
940
941 /*
942 * select page 0 registers
943 */
944 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
945
946 /*
947 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
948 * board.
949 */
950 outb(sc->nic_addr + ED_P0_DCR, 0);
951
952 /*
953 * select page 2 registers
954 */
955 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
956
957 /*
958 * The 3c503 forces the WTS bit to a one if this is a 16bit board
959 */
960 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
961 isa16bit = 1;
962 else
963 isa16bit = 0;
964
965 /*
966 * select page 0 registers
967 */
968 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
969
970 sc->mem_start = (caddr_t) isa_dev->id_maddr;
971 sc->mem_size = memsize;
972 sc->mem_end = sc->mem_start + memsize;
973
974 /*
975 * We have an entire 8k window to put the transmit buffers on the
976 * 16bit boards. But since the 16bit 3c503's shared memory is only
977 * fast enough to overlap the loading of one full-size packet, trying
978 * to load more than 2 buffers can actually leave the transmitter idle
979 * during the load. So 2 seems the best value. (Although a mix of
980 * variable-sized packets might change this assumption. Nonetheless,
981 * we optimize for linear transfers of same-size packets.)
982 */
983 if (isa16bit) {
984 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
985 sc->txb_cnt = 1;
986 else
987 sc->txb_cnt = 2;
988
989 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
990 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
991 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
992 ED_3COM_RX_PAGE_OFFSET_16BIT;
993 sc->mem_ring = sc->mem_start;
994 } else {
995 sc->txb_cnt = 1;
996 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
997 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
998 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
999 ED_3COM_TX_PAGE_OFFSET_8BIT;
1000 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
1001 }
1002
1003 sc->isa16bit = isa16bit;
1004
1005 /*
1006 * Initialize GA page start/stop registers. Probably only needed if
1007 * doing DMA, but what the hell.
1008 */
1009 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
1010 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
1011
1012 /*
1013 * Set IRQ. 3c503 only allows a choice of irq 2-5.
1014 */
1015 switch (isa_dev->id_irq) {
1016 case IRQ2:
1017 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
1018 break;
1019 case IRQ3:
1020 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
1021 break;
1022 case IRQ4:
1023 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
1024 break;
1025 case IRQ5:
1026 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
1027 break;
1028 default:
1029 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
1030 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
1031 return (0);
1032 }
1033
1034 /*
1035 * Initialize GA configuration register. Set bank and enable shared
1036 * mem.
1037 */
1038 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
1039 ED_3COM_GACFR_MBS0);
1040
1041 /*
1042 * Initialize "Vector Pointer" registers. These gawd-awful things are
1043 * compared to 20 bits of the address on ISA, and if they match, the
1044 * shared memory is disabled. We set them to 0xffff0...allegedly the
1045 * reset vector.
1046 */
1047 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
1048 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
1049 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
1050
1051 /*
1052 * Zero memory and verify that it is clear
1053 */
1054 bzero(sc->mem_start, memsize);
1055
1056 for (i = 0; i < memsize; ++i)
1057 if (sc->mem_start[i]) {
1058 printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
1059 isa_dev->id_unit, kvtop(sc->mem_start + i));
1060 return (0);
1061 }
1062 isa_dev->id_msize = memsize;
1063 return (ED_3COM_IO_PORTS);
1064}
1065
1066/*
1067 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1068 */
1069static int
1070ed_probe_Novell_generic(sc, port, unit, flags)
1071 struct ed_softc *sc;
1072 int port;
1073 int unit;
1074 int flags;
1075{
1076 u_int memsize, n;
1077 u_char romdata[16], tmp;
1078 static char test_pattern[32] = "THIS is A memory TEST pattern";
1079 char test_buffer[32];
1080
1081 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
1082 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
1083
1084 /* XXX - do Novell-specific probe here */
1085
1086 /* Reset the board */
1087#ifdef GWETHER
1088 outb(sc->asic_addr + ED_NOVELL_RESET, 0);
1089 DELAY(200);
1090#endif /* GWETHER */
1091 tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
1092
1093 /*
1094 * I don't know if this is necessary; probably cruft leftover from
1095 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1096 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
1097 * non-invasive...but some boards don't seem to reset and I don't have
1098 * complete documentation on what the 'right' thing to do is...so we
1099 * do the invasive thing for now. Yuck.]
1100 */
1101 outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
1102 DELAY(5000);
1103
1104 /*
1105 * This is needed because some NE clones apparently don't reset the
1106 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1107 * - this makes the probe invasive! ...Done against my better
1108 * judgement. -DLG
1109 */
1110 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1111
1112 DELAY(5000);
1113
1114 /* Make sure that we really have an 8390 based board */
1115 if (!ed_probe_generic8390(sc))
1116 return (0);
1117
1118 sc->vendor = ED_VENDOR_NOVELL;
1119 sc->mem_shared = 0;
1120 sc->cr_proto = ED_CR_RD2;
1121
1122 /*
1123 * Test the ability to read and write to the NIC memory. This has the
1124 * side affect of determining if this is an NE1000 or an NE2000.
1125 */
1126
1127 /*
1128 * This prevents packets from being stored in the NIC memory when the
1129 * readmem routine turns on the start bit in the CR.
1130 */
1131 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1132
1133 /* Temporarily initialize DCR for byte operations */
1134 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1135
1136 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1137 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1138
1139 sc->isa16bit = 0;
1140
1141 /*
1142 * Write a test pattern in byte mode. If this fails, then there
1143 * probably isn't any memory at 8k - which likely means that the board
1144 * is an NE2000.
1145 */
1146 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1147 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1148
1149 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
1150 /* not an NE1000 - try NE2000 */
1151
1152 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1153 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1154 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1155
1156 sc->isa16bit = 1;
1157
1158 /*
1159 * Write a test pattern in word mode. If this also fails, then
1160 * we don't know what this board is.
1161 */
1162 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1163 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1164
1165 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
1166 return (0); /* not an NE2000 either */
1167
1168 sc->type = ED_TYPE_NE2000;
1169 sc->type_str = "NE2000";
1170 } else {
1171 sc->type = ED_TYPE_NE1000;
1172 sc->type_str = "NE1000";
1173 }
1174
1175 /* 8k of memory plus an additional 8k if 16bit */
1176 memsize = 8192 + sc->isa16bit * 8192;
1177
1178#if 0 /* probably not useful - NE boards only come two ways */
1179 /* allow kernel config file overrides */
1180 if (isa_dev->id_msize)
1181 memsize = isa_dev->id_msize;
1182#endif
1183
1184 sc->mem_size = memsize;
1185
1186 /* NIC memory doesn't start at zero on an NE board */
1187 /* The start address is tied to the bus width */
1188 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1189 sc->mem_end = sc->mem_start + memsize;
1190 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1191
1192#ifdef GWETHER
1193 {
1194 int x, i, mstart = 0, msize = 0;
1195 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1196
1197 for (i = 0; i < ED_PAGE_SIZE; i++)
1198 pbuf0[i] = 0;
1199
1200 /* Clear all the memory. */
1201 for (x = 1; x < 256; x++)
1202 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1203
1204 /* Search for the start of RAM. */
1205 for (x = 1; x < 256; x++) {
1206 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1207 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1208 for (i = 0; i < ED_PAGE_SIZE; i++)
1209 pbuf[i] = 255 - x;
1210 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1211 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1212 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1213 mstart = x * ED_PAGE_SIZE;
1214 msize = ED_PAGE_SIZE;
1215 break;
1216 }
1217 }
1218 }
1219
1220 if (mstart == 0) {
1221 printf("ed%d: Cannot find start of RAM.\n", unit);
1222 return 0;
1223 }
1224 /* Search for the start of RAM. */
1225 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1227 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1228 for (i = 0; i < ED_PAGE_SIZE; i++)
1229 pbuf[i] = 255 - x;
1230 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1231 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1232 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1233 msize += ED_PAGE_SIZE;
1234 else {
1235 break;
1236 }
1237 } else {
1238 break;
1239 }
1240 }
1241
1242 if (msize == 0) {
1243 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
1244 return 0;
1245 }
1246 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
1247
1248 sc->mem_size = msize;
1249 sc->mem_start = (char *) mstart;
1250 sc->mem_end = (char *) (msize + mstart);
1251 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1252 }
1253#endif /* GWETHER */
1254
1255 /*
1256 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1257 * otherwise).
1258 */
1259 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1260 sc->txb_cnt = 1;
1261 else
1262 sc->txb_cnt = 2;
1263
1264 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1265 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1266
1267 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1268
1269 ed_pio_readmem(sc, 0, romdata, 16);
1270 for (n = 0; n < ETHER_ADDR_LEN; n++)
1271 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1272
1273#ifdef GWETHER
1274 if (sc->arpcom.ac_enaddr[2] == 0x86) {
1275 sc->type_str = "Gateway AT";
1276 }
1277#endif /* GWETHER */
1278
1279 /* clear any pending interrupts that might have occurred above */
1280 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1281
1282 return (ED_NOVELL_IO_PORTS);
1283}
1284
1285static int
1286ed_probe_Novell(isa_dev)
1287 struct isa_device *isa_dev;
1288{
1289 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1290
1291 isa_dev->id_maddr = 0;
1292 return ed_probe_Novell_generic(sc, isa_dev->id_iobase,
1293 isa_dev->id_unit, isa_dev->id_flags);
1294}
1295
1296#if NCARD > 0
1297/*
1298 * Probe framework for pccards. Replicates the standard framework,
1299 * minus the pccard driver registration and ignores the ether address
1300 * supplied (from the CIS), relying on the probe to find it instead.
1301 */
1302static int
1303ed_probe_pccard(isa_dev, ether)
1304 struct isa_device *isa_dev;
1305 u_char *ether;
1306{
1307 int nports;
1308
1309 nports = ed_probe_WD80x3(isa_dev);
1310 if (nports)
1311 return (nports);
1312
1313 nports = ed_probe_Novell(isa_dev);
1314 if (nports)
1315 return (nports);
1316
1317 return (0);
1318}
1319
1320#endif /* NCARD > 0 */
1321
1322#define ED_HPP_TEST_SIZE 16
1323
1324/*
1325 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1326 * (HP Part nos: 27247B and 27252A).
1327 *
1328 * The card has an asic wrapper around a DS8390 core. The asic handles
1329 * host accesses and offers both standard register IO and memory mapped
1330 * IO. Memory mapped I/O allows better performance at the expense of greater
1331 * chance of an incompatibility with existing ISA cards.
1332 *
1333 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1334 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1335 * don't allow 32 bit accesses; these are indicated by a bit in the software
1336 * ID register (see if_edreg.h).
1337 *
1338 * Other caveats are: we should read the MAC address only when the card
1339 * is inactive.
1340 *
1341 * For more information; please consult the CRYNWR packet driver.
1342 *
1343 * The AUI port is turned on using the "link2" option on the ifconfig
1344 * command line.
1345 */
1346static int
1347ed_probe_HP_pclanp(isa_dev)
1348 struct isa_device *isa_dev;
1349{
1350 struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
1351 int n; /* temp var */
1352 int memsize; /* mem on board */
1353 u_char checksum; /* checksum of board address */
1354 u_char irq; /* board configured IRQ */
1355 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1356 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1357
1358
1359 /* Fill in basic information */
1360 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
1361 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
1362 sc->is790 = 0;
1363 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1364
1365 /*
1366 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1367 */
1368
1369 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) ||
1370 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
1371 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
1372 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
1373 return 0;
1374
1375 /*
1376 * Read the MAC address and verify checksum on the address.
1377 */
1378
1379 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1380 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1381 checksum += (sc->arpcom.ac_enaddr[n] =
1382 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
1383
1384 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1385
1386 if (checksum != 0xFF)
1387 return 0;
1388
1389 /*
1390 * Verify that the software model number is 0.
1391 */
1392
1393 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
1394 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) &
1395 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1396 return 0;
1397
1398 /*
1399 * Read in and save the current options configured on card.
1400 */
1401
1402 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
1403
1404 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1405 ED_HPP_OPTION_CHIP_RESET |
1406 ED_HPP_OPTION_ENABLE_IRQ);
1407
1408 /*
1409 * Reset the chip. This requires writing to the option register
1410 * so take care to preserve the other bits.
1411 */
1412
1413 outw(sc->asic_addr + ED_HPP_OPTION,
1414 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1415 ED_HPP_OPTION_CHIP_RESET)));
1416
1417 DELAY(5000); /* wait for chip reset to complete */
1418
1419 outw(sc->asic_addr + ED_HPP_OPTION,
1420 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1421 ED_HPP_OPTION_CHIP_RESET |
1422 ED_HPP_OPTION_ENABLE_IRQ)));
1423
1424 DELAY(5000);
1425
1426 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
1427 return 0; /* reset did not complete */
1428
1429 /*
1430 * Read out configuration information.
1431 */
1432
1433 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1434
1435 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
1436
1437 /*
1438 * Check for impossible IRQ.
1439 */
1440
1441 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
1442 return 0;
1443
1444 /*
1445 * If the kernel IRQ was specified with a '?' use the cards idea
1446 * of the IRQ. If the kernel IRQ was explicitly specified, it
1447 * should match that of the hardware.
1448 */
1449
1450 if (isa_dev->id_irq <= 0)
1451 isa_dev->id_irq = ed_hpp_intr_mask[irq];
1452 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
1453 return 0;
1454
1455 /*
1456 * Fill in softconfig info.
1457 */
1458
1459 sc->vendor = ED_VENDOR_HP;
1460 sc->type = ED_TYPE_HP_PCLANPLUS;
1461 sc->type_str = "HP-PCLAN+";
1462
1463 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1464 sc->mem_start = 0; /* we use offsets inside the card RAM */
1465
1466 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1467
1468 /*
1469 * Check if memory mapping of the I/O registers possible.
1470 */
1471
1472 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1473 {
1474 u_long mem_addr;
1475
1476 /*
1477 * determine the memory address from the board.
1478 */
1479
1480 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1481 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
1482
1483 /*
1484 * Check that the kernel specified start of memory and
1485 * hardware's idea of it match.
1486 */
1487
1488 if (mem_addr != kvtop(isa_dev->id_maddr))
1489 return 0;
1490
1491 sc->hpp_mem_start = isa_dev->id_maddr;
1492 }
1493
1494 /*
1495 * The board has 32KB of memory. Is there a way to determine
1496 * this programmatically?
1497 */
1498
1499 memsize = 32768;
1500
1501 /*
1502 * Fill in the rest of the soft config structure.
1503 */
1504
1505 /*
1506 * The transmit page index.
1507 */
1508
1509 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1510
1511 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
1512 sc->txb_cnt = 1;
1513 else
1514 sc->txb_cnt = 2;
1515
1516 /*
1517 * Memory description
1518 */
1519
1520 sc->mem_size = memsize;
1521 sc->mem_ring = sc->mem_start +
1522 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1523 sc->mem_end = sc->mem_start + sc->mem_size;
1524
1525 /*
1526 * Receive area starts after the transmit area and
1527 * continues till the end of memory.
1528 */
1529
1530 sc->rec_page_start = sc->tx_page_start +
1531 (sc->txb_cnt * ED_TXBUF_SIZE);
1532 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1533
1534
1535 sc->cr_proto = 0; /* value works */
1536
1537 /*
1538 * Set the wrap registers for string I/O reads.
1539 */
1540
1541 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
1542 outw(sc->asic_addr + ED_HPP_HW_WRAP,
1543 ((sc->rec_page_start / ED_PAGE_SIZE) |
1544 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1545
1546 /*
1547 * Reset the register page to normal operation.
1548 */
1549
1550 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1551
1552 /*
1553 * Verify that we can read/write from adapter memory.
1554 * Create test pattern.
1555 */
1556
1557 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1558 {
1559 test_pattern[n] = (n*n) ^ ~n;
1560 }
1561
1562#undef ED_HPP_TEST_SIZE
1563
1564 /*
1565 * Check that the memory is accessible thru the I/O ports.
1566 * Write out the contents of "test_pattern", read back
1567 * into "test_buffer" and compare the two for any
1568 * mismatch.
1569 */
1570
1571 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1572
1573 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1574 sizeof(test_pattern));
1575 ed_pio_readmem(sc, (n * ED_PAGE_SIZE),
1576 test_buffer, sizeof(test_pattern));
1577
1578 if (bcmp(test_pattern, test_buffer,
1579 sizeof(test_pattern)))
1580 return 0;
1581 }
1582
1583 return (ED_HPP_IO_PORTS);
1584
1585}
1586
1587/*
1588 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1589 */
1590
1591void
1592ed_hpp_set_physical_link(struct ed_softc *sc)
1593{
1594 struct ifnet *ifp = &sc->arpcom.ac_if;
1595 int lan_page;
1596
1597 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1598 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
1599
1600 if (ifp->if_flags & IFF_ALTPHYS) {
1601
1602 /*
1603 * Use the AUI port.
1604 */
1605
1606 lan_page |= ED_HPP_LAN_AUI;
1607
1608 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1609 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1610
1611
1612 } else {
1613
1614 /*
1615 * Use the ThinLan interface
1616 */
1617
1618 lan_page &= ~ED_HPP_LAN_AUI;
1619
1620 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1621 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
1622
1623 }
1624
1625 /*
1626 * Wait for the lan card to re-initialize itself
1627 */
1628
1629 DELAY(150000); /* wait 150 ms */
1630
1631 /*
1632 * Restore normal pages.
1633 */
1634
1635 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1636
1637}
1638
1639
1640/*
1641 * Install interface into kernel networking data structures
1642 */
1643static int
1644ed_attach(sc, unit, flags)
1645 struct ed_softc *sc;
1646 int unit;
1647 int flags;
1648{
1649 struct ifnet *ifp = &sc->arpcom.ac_if;
1650
1651 /*
1652 * Set interface to stopped condition (reset)
1653 */
1654 ed_stop(sc);
1655
1656 if (!ifp->if_name) {
1657 /*
1658 * Initialize ifnet structure
1659 */
1660 ifp->if_softc = sc;
1661 ifp->if_unit = unit;
1662 ifp->if_name = "ed";
1663 ifp->if_output = ether_output;
1664 ifp->if_start = ed_start;
1665 ifp->if_ioctl = ed_ioctl;
1666 ifp->if_watchdog = ed_watchdog;
1667 ifp->if_init = ed_init;
1668 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1669 ifp->if_linkmib = &sc->mibdata;
1670 ifp->if_linkmiblen = sizeof sc->mibdata;
1671 /*
1672 * XXX - should do a better job.
1673 */
1674 if (sc->is790)
1675 sc->mibdata.dot3StatsEtherChipSet =
1676 DOT3CHIPSET(dot3VendorWesternDigital,
1677 dot3ChipSetWesternDigital83C790);
1678 else
1679 sc->mibdata.dot3StatsEtherChipSet =
1680 DOT3CHIPSET(dot3VendorNational,
1681 dot3ChipSetNational8390);
1682 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1683
1684 /*
1685 * Set default state for ALTPHYS flag (used to disable the
1686 * tranceiver for AUI operation), based on compile-time
1687 * config option.
1688 */
1689 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1690 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1691 IFF_MULTICAST | IFF_ALTPHYS);
1692 else
1693 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1694 IFF_MULTICAST);
1695
1696 /*
1697 * Attach the interface
1698 */
1699 if_attach(ifp);
1700 ether_ifattach(ifp);
1701 }
1702 /* device attach does transition from UNCONFIGURED to IDLE state */
1703
1704 /*
1705 * Print additional info when attached
1706 */
1707 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1708 sc->arpcom.ac_enaddr, ":");
1709
1710 if (sc->type_str && (*sc->type_str != 0))
1711 printf("type %s ", sc->type_str);
1712 else
1713 printf("type unknown (0x%x) ", sc->type);
1714
1715 if (sc->vendor == ED_VENDOR_HP)
1716 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1717 "16-bit" : "32-bit",
1718 sc->hpp_mem_start ? "memory mapped" : "regular");
1719 else
1720 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1721
1722 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1723 (sc->vendor == ED_VENDOR_HP)) &&
1724 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1725
1726 /*
1727 * If BPF is in the kernel, call the attach for it
1728 */
1729#if NBPFILTER > 0
1730 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1731#endif
1732 return 1;
1733}
1734
1735static int
1736ed_attach_isa(isa_dev)
1737 struct isa_device *isa_dev;
1738{
1739 int unit = isa_dev->id_unit;
1740 struct ed_softc *sc = &ed_softc[unit];
1741 int flags = isa_dev->id_flags;
1742
1743 return ed_attach(sc, unit, flags);
1744}
1745
1746#if NPCI > 0
1747void *
1748ed_attach_NE2000_pci(unit, port)
1749 int unit;
1750 int port;
1751{
1752 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
1753 int isa_flags = 0;
1754
1755 if (!sc)
1756 return sc;
1757
1758 bzero(sc, sizeof *sc);
1759 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
1760 || ed_attach(sc, unit, isa_flags) == 0) {
1761 free(sc, M_DEVBUF);
1762 return NULL;
1763 }
1764 return sc;
1765}
1766#endif
1767
1768/*
1769 * Reset interface.
1770 */
1771static void
1772ed_reset(ifp)
1773 struct ifnet *ifp;
1774{
1775 struct ed_softc *sc = ifp->if_softc;
1776 int s;
1777
1778 if (sc->gone)
1779 return;
1780 s = splimp();
1781
1782 /*
1783 * Stop interface and re-initialize.
1784 */
1785 ed_stop(sc);
1786 ed_init(sc);
1787
1788 (void) splx(s);
1789}
1790
1791/*
1792 * Take interface offline.
1793 */
1794static void
1795ed_stop(sc)
1796 struct ed_softc *sc;
1797{
1798 int n = 5000;
1799
1800 if (sc->gone)
1801 return;
1802 /*
1803 * Stop everything on the interface, and select page 0 registers.
1804 */
1805 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1806
1807 /*
1808 * Wait for interface to enter stopped state, but limit # of checks to
1809 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1810 * just in case it's an old one.
1811 */
1812 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1813}
1814
1815/*
1816 * Device timeout/watchdog routine. Entered if the device neglects to
1817 * generate an interrupt after a transmit has been started on it.
1818 */
1819static void
1820ed_watchdog(ifp)
1821 struct ifnet *ifp;
1822{
1823 struct ed_softc *sc = ifp->if_softc;
1824
1825 if (sc->gone)
1826 return;
1827 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1828 ifp->if_oerrors++;
1829
1830 ed_reset(ifp);
1831}
1832
1833/*
1834 * Initialize device.
1835 */
1836static void
1837ed_init(xsc)
1838 void *xsc;
1839{
1840 struct ed_softc *sc = xsc;
1841 struct ifnet *ifp = &sc->arpcom.ac_if;
1842 int i, s;
1843
1844 if (sc->gone)
1845 return;
1846
1847 /* address not known */
1848 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1849 return;
1850
1851 /*
1852 * Initialize the NIC in the exact order outlined in the NS manual.
1853 * This init procedure is "mandatory"...don't change what or when
1854 * things happen.
1855 */
1856 s = splimp();
1857
1858 /* reset transmitter flags */
1859 sc->xmit_busy = 0;
1860 ifp->if_timer = 0;
1861
1862 sc->txb_inuse = 0;
1863 sc->txb_new = 0;
1864 sc->txb_next_tx = 0;
1865
1866 /* This variable is used below - don't move this assignment */
1867 sc->next_packet = sc->rec_page_start + 1;
1868
1869 /*
1870 * Set interface for page 0, Remote DMA complete, Stopped
1871 */
1872 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
1873
1874 if (sc->isa16bit) {
1875
1876 /*
1877 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1878 * order=80x86, word-wide DMA xfers,
1879 */
1880 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1881 } else {
1882
1883 /*
1884 * Same as above, but byte-wide DMA xfers
1885 */
1886 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1887 }
1888
1889 /*
1890 * Clear Remote Byte Count Registers
1891 */
1892 outb(sc->nic_addr + ED_P0_RBCR0, 0);
1893 outb(sc->nic_addr + ED_P0_RBCR1, 0);
1894
1895 /*
1896 * For the moment, don't store incoming packets in memory.
1897 */
1898 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
1899
1900 /*
1901 * Place NIC in internal loopback mode
1902 */
1903 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
1904
1905 /*
1906 * Initialize transmit/receive (ring-buffer) Page Start
1907 */
1908 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
1909 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
1910 /* Set lower bits of byte addressable framing to 0 */
1911 if (sc->is790)
1912 outb(sc->nic_addr + 0x09, 0);
1913
1914 /*
1915 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1916 */
1917 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
1918 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
1919
1920 /*
1921 * Clear all interrupts. A '1' in each bit position clears the
1922 * corresponding flag.
1923 */
1924 outb(sc->nic_addr + ED_P0_ISR, 0xff);
1925
1926 /*
1927 * Enable the following interrupts: receive/transmit complete,
1928 * receive/transmit error, and Receiver OverWrite.
1929 *
1930 * Counter overflow and Remote DMA complete are *not* enabled.
1931 */
1932 outb(sc->nic_addr + ED_P0_IMR,
1933 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1934
1935 /*
1936 * Program Command Register for page 1
1937 */
1938 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1939
1940 /*
1941 * Copy out our station address
1942 */
1943 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1944 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1945
1946 /*
1947 * Set Current Page pointer to next_packet (initialized above)
1948 */
1949 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
1950
1951 /*
1952 * Program Receiver Configuration Register and multicast filter. CR is
1953 * set to page 0 on return.
1954 */
1955 ed_setrcr(sc);
1956
1957 /*
1958 * Take interface out of loopback
1959 */
1960 outb(sc->nic_addr + ED_P0_TCR, 0);
1961
1962 /*
1963 * If this is a 3Com board, the tranceiver must be software enabled
1964 * (there is no settable hardware default).
1965 */
1966 if (sc->vendor == ED_VENDOR_3COM) {
1967 if (ifp->if_flags & IFF_ALTPHYS) {
1968 outb(sc->asic_addr + ED_3COM_CR, 0);
1969 } else {
1970 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
1971 }
1972 }
1973
1974 /*
1975 * Set 'running' flag, and clear output active flag.
1976 */
1977 ifp->if_flags |= IFF_RUNNING;
1978 ifp->if_flags &= ~IFF_OACTIVE;
1979
1980 /*
1981 * ...and attempt to start output
1982 */
1983 ed_start(ifp);
1984
1985 (void) splx(s);
1986}
1987
1988/*
1989 * This routine actually starts the transmission on the interface
1990 */
1991static __inline void
1992ed_xmit(sc)
1993 struct ed_softc *sc;
1994{
1995 struct ifnet *ifp = (struct ifnet *)sc;
1996 unsigned short len;
1997
1998 if (sc->gone)
1999 return;
2000 len = sc->txb_len[sc->txb_next_tx];
2001
2002 /*
2003 * Set NIC for page 0 register access
2004 */
2005 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2006
2007 /*
2008 * Set TX buffer start page
2009 */
2010 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
2011 sc->txb_next_tx * ED_TXBUF_SIZE);
2012
2013 /*
2014 * Set TX length
2015 */
2016 outb(sc->nic_addr + ED_P0_TBCR0, len);
2017 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
2018
2019 /*
2020 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2021 */
2022 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2023 sc->xmit_busy = 1;
2024
2025 /*
2026 * Point to next transmit buffer slot and wrap if necessary.
2027 */
2028 sc->txb_next_tx++;
2029 if (sc->txb_next_tx == sc->txb_cnt)
2030 sc->txb_next_tx = 0;
2031
2032 /*
2033 * Set a timer just in case we never hear from the board again
2034 */
2035 ifp->if_timer = 2;
2036}
2037
2038/*
2039 * Start output on interface.
2040 * We make two assumptions here:
2041 * 1) that the current priority is set to splimp _before_ this code
2042 * is called *and* is returned to the appropriate priority after
2043 * return
2044 * 2) that the IFF_OACTIVE flag is checked before this code is called
2045 * (i.e. that the output part of the interface is idle)
2046 */
2047static void
2048ed_start(ifp)
2049 struct ifnet *ifp;
2050{
2051 struct ed_softc *sc = ifp->if_softc;
2052 struct mbuf *m0, *m;
2053 caddr_t buffer;
2054 int len;
2055
2056 if (sc->gone) {
2057 printf("ed_start(%p) GONE\n",ifp);
2058 return;
2059 }
2060outloop:
2061
2062 /*
2063 * First, see if there are buffered packets and an idle transmitter -
2064 * should never happen at this point.
2065 */
2066 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2067 printf("ed: packets buffered, but transmitter idle\n");
2068 ed_xmit(sc);
2069 }
2070
2071 /*
2072 * See if there is room to put another packet in the buffer.
2073 */
2074 if (sc->txb_inuse == sc->txb_cnt) {
2075
2076 /*
2077 * No room. Indicate this to the outside world and exit.
2078 */
2079 ifp->if_flags |= IFF_OACTIVE;
2080 return;
2081 }
2082 IF_DEQUEUE(&ifp->if_snd, m);
2083 if (m == 0) {
2084
2085 /*
2086 * We are using the !OACTIVE flag to indicate to the outside
2087 * world that we can accept an additional packet rather than
2088 * that the transmitter is _actually_ active. Indeed, the
2089 * transmitter may be active, but if we haven't filled all the
2090 * buffers with data then we still want to accept more.
2091 */
2092 ifp->if_flags &= ~IFF_OACTIVE;
2093 return;
2094 }
2095
2096 /*
2097 * Copy the mbuf chain into the transmit buffer
2098 */
2099
2100 m0 = m;
2101
2102 /* txb_new points to next open buffer slot */
2103 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2104
2105 if (sc->mem_shared) {
2106
2107 /*
2108 * Special case setup for 16 bit boards...
2109 */
2110 if (sc->isa16bit) {
2111 switch (sc->vendor) {
2112
2113 /*
2114 * For 16bit 3Com boards (which have 16k of
2115 * memory), we have the xmit buffers in a
2116 * different page of memory ('page 0') - so
2117 * change pages.
2118 */
2119 case ED_VENDOR_3COM:
2120 outb(sc->asic_addr + ED_3COM_GACFR,
2121 ED_3COM_GACFR_RSEL);
2122 break;
2123
2124 /*
2125 * Enable 16bit access to shared memory on
2126 * WD/SMC boards.
2127 */
2128 case ED_VENDOR_WD_SMC:{
2129 outb(sc->asic_addr + ED_WD_LAAR,
2130 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2131 if (sc->is790) {
2132 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
2133 }
2134 break;
2135 }
2136 }
2137 }
2138 for (len = 0; m != 0; m = m->m_next) {
2139 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2140 buffer += m->m_len;
2141 len += m->m_len;
2142 }
2143
2144 /*
2145 * Restore previous shared memory access
2146 */
2147 if (sc->isa16bit) {
2148 switch (sc->vendor) {
2149 case ED_VENDOR_3COM:
2150 outb(sc->asic_addr + ED_3COM_GACFR,
2151 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2152 break;
2153 case ED_VENDOR_WD_SMC:{
2154 if (sc->is790) {
2155 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2156 }
2157 outb(sc->asic_addr + ED_WD_LAAR,
2158 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2159 break;
2160 }
2161 }
2162 }
2163 } else {
2164 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2165 if (len == 0)
2166 goto outloop;
2167 }
2168
2169 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2170
2171 sc->txb_inuse++;
2172
2173 /*
2174 * Point to next buffer slot and wrap if necessary.
2175 */
2176 sc->txb_new++;
2177 if (sc->txb_new == sc->txb_cnt)
2178 sc->txb_new = 0;
2179
2180 if (sc->xmit_busy == 0)
2181 ed_xmit(sc);
2182
2183 /*
2184 * Tap off here if there is a bpf listener.
2185 */
2186#if NBPFILTER > 0
2187 if (ifp->if_bpf) {
2188 bpf_mtap(ifp, m0);
2189 }
2190#endif
2191
2192 m_freem(m0);
2193
2194 /*
2195 * Loop back to the top to possibly buffer more packets
2196 */
2197 goto outloop;
2198}
2199
2200/*
2201 * Ethernet interface receiver interrupt.
2202 */
2203static __inline void
2204ed_rint(sc)
2205 struct ed_softc *sc;
2206{
2207 struct ifnet *ifp = &sc->arpcom.ac_if;
2208 u_char boundry;
2209 u_short len;
2210 struct ed_ring packet_hdr;
2211 char *packet_ptr;
2212
2213 if (sc->gone)
2214 return;
2215
2216 /*
2217 * Set NIC to page 1 registers to get 'current' pointer
2218 */
2219 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2220
2221 /*
2222 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2223 * i.e. it points to where new data has been buffered. The 'CURR'
2224 * (current) register points to the logical end of the ring-buffer -
2225 * i.e. it points to where additional new data will be added. We loop
2226 * here until the logical beginning equals the logical end (or in
2227 * other words, until the ring-buffer is empty).
2228 */
2229 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
2230
2231 /* get pointer to this buffer's header structure */
2232 packet_ptr = sc->mem_ring +
2233 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2234
2235 /*
2236 * The byte count includes a 4 byte header that was added by
2237 * the NIC.
2238 */
2239 if (sc->mem_shared)
2240 packet_hdr = *(struct ed_ring *) packet_ptr;
2241 else
2242 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2243 sizeof(packet_hdr));
2244 len = packet_hdr.count;
2245 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2246 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2247 /*
2248 * Length is a wild value. There's a good chance that
2249 * this was caused by the NIC being old and buggy.
2250 * The bug is that the length low byte is duplicated in
2251 * the high byte. Try to recalculate the length based on
2252 * the pointer to the next packet.
2253 */
2254 /*
2255 * NOTE: sc->next_packet is pointing at the current packet.
2256 */
2257 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2258 if (packet_hdr.next_packet >= sc->next_packet) {
2259 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2260 } else {
2261 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2262 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2263 }
2264 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2265 + sizeof(struct ed_ring)))
2266 sc->mibdata.dot3StatsFrameTooLongs++;
2267 }
2268 /*
2269 * Be fairly liberal about what we allow as a "reasonable" length
2270 * so that a [crufty] packet will make it to BPF (and can thus
2271 * be analyzed). Note that all that is really important is that
2272 * we have a length that will fit into one mbuf cluster or less;
2273 * the upper layer protocols can then figure out the length from
2274 * their own length field(s).
2275 */
2276 if ((len > sizeof(struct ed_ring)) &&
2277 (len <= MCLBYTES) &&
2278 (packet_hdr.next_packet >= sc->rec_page_start) &&
2279 (packet_hdr.next_packet < sc->rec_page_stop)) {
2280 /*
2281 * Go get packet.
2282 */
2283 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2284 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
2285 ifp->if_ipackets++;
2286 } else {
2287 /*
2288 * Really BAD. The ring pointers are corrupted.
2289 */
2290 log(LOG_ERR,
2291 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2292 ifp->if_unit, len);
2293 ifp->if_ierrors++;
2294 ed_reset(ifp);
2295 return;
2296 }
2297
2298 /*
2299 * Update next packet pointer
2300 */
2301 sc->next_packet = packet_hdr.next_packet;
2302
2303 /*
2304 * Update NIC boundry pointer - being careful to keep it one
2305 * buffer behind. (as recommended by NS databook)
2306 */
2307 boundry = sc->next_packet - 1;
2308 if (boundry < sc->rec_page_start)
2309 boundry = sc->rec_page_stop - 1;
2310
2311 /*
2312 * Set NIC to page 0 registers to update boundry register
2313 */
2314 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2315
2316 outb(sc->nic_addr + ED_P0_BNRY, boundry);
2317
2318 /*
2319 * Set NIC to page 1 registers before looping to top (prepare
2320 * to get 'CURR' current pointer)
2321 */
2322 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2323 }
2324}
2325
2326/*
2327 * Ethernet interface interrupt processor
2328 */
2329void
2330edintr_sc(sc)
2331 struct ed_softc *sc;
2332{
2333 struct ifnet *ifp = (struct ifnet *)sc;
2334 u_char isr;
2335
2336 if (sc->gone)
2337 return;
2338 /*
2339 * Set NIC to page 0 registers
2340 */
2341 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2342
2343 /*
2344 * loop until there are no more new interrupts
2345 */
2346 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
2347
2348 /*
2349 * reset all the bits that we are 'acknowledging' by writing a
2350 * '1' to each bit position that was set (writing a '1'
2351 * *clears* the bit)
2352 */
2353 outb(sc->nic_addr + ED_P0_ISR, isr);
2354
2355 /*
2356 * Handle transmitter interrupts. Handle these first because
2357 * the receiver will reset the board under some conditions.
2358 */
2359 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2360 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
2361
2362 /*
2363 * Check for transmit error. If a TX completed with an
2364 * error, we end up throwing the packet away. Really
2365 * the only error that is possible is excessive
2366 * collisions, and in this case it is best to allow
2367 * the automatic mechanisms of TCP to backoff the
2368 * flow. Of course, with UDP we're screwed, but this
2369 * is expected when a network is heavily loaded.
2370 */
2371 (void) inb(sc->nic_addr + ED_P0_TSR);
2372 if (isr & ED_ISR_TXE) {
2373 u_char tsr;
2374
2375 /*
2376 * Excessive collisions (16)
2377 */
2378 tsr = inb(sc->nic_addr + ED_P0_TSR);
2379 if ((tsr & ED_TSR_ABT)
2380 && (collisions == 0)) {
2381
2382 /*
2383 * When collisions total 16, the
2384 * P0_NCR will indicate 0, and the
2385 * TSR_ABT is set.
2386 */
2387 collisions = 16;
2388 sc->mibdata.dot3StatsExcessiveCollisions++;
2389 sc->mibdata.dot3StatsCollFrequencies[15]++;
2390 }
2391 if (tsr & ED_TSR_OWC)
2392 sc->mibdata.dot3StatsLateCollisions++;
2393 if (tsr & ED_TSR_CDH)
2394 sc->mibdata.dot3StatsSQETestErrors++;
2395 if (tsr & ED_TSR_CRS)
2396 sc->mibdata.dot3StatsCarrierSenseErrors++;
2397 if (tsr & ED_TSR_FU)
2398 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2399
2400 /*
2401 * update output errors counter
2402 */
2403 ifp->if_oerrors++;
2404 } else {
2405
2406 /*
2407 * Update total number of successfully
2408 * transmitted packets.
2409 */
2410 ifp->if_opackets++;
2411 }
2412
2413 /*
2414 * reset tx busy and output active flags
2415 */
2416 sc->xmit_busy = 0;
2417 ifp->if_flags &= ~IFF_OACTIVE;
2418
2419 /*
2420 * clear watchdog timer
2421 */
2422 ifp->if_timer = 0;
2423
2424 /*
2425 * Add in total number of collisions on last
2426 * transmission.
2427 */
2428 ifp->if_collisions += collisions;
2429 switch(collisions) {
2430 case 0:
2431 case 16:
2432 break;
2433 case 1:
2434 sc->mibdata.dot3StatsSingleCollisionFrames++;
2435 sc->mibdata.dot3StatsCollFrequencies[0]++;
2436 break;
2437 default:
2438 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2439 sc->mibdata.
2440 dot3StatsCollFrequencies[collisions-1]
2441 ++;
2442 break;
2443 }
2444
2445 /*
2446 * Decrement buffer in-use count if not zero (can only
2447 * be zero if a transmitter interrupt occured while
2448 * not actually transmitting). If data is ready to
2449 * transmit, start it transmitting, otherwise defer
2450 * until after handling receiver
2451 */
2452 if (sc->txb_inuse && --sc->txb_inuse)
2453 ed_xmit(sc);
2454 }
2455
2456 /*
2457 * Handle receiver interrupts
2458 */
2459 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2460
2461 /*
2462 * Overwrite warning. In order to make sure that a
2463 * lockup of the local DMA hasn't occurred, we reset
2464 * and re-init the NIC. The NSC manual suggests only a
2465 * partial reset/re-init is necessary - but some chips
2466 * seem to want more. The DMA lockup has been seen
2467 * only with early rev chips - Methinks this bug was
2468 * fixed in later revs. -DG
2469 */
2470 if (isr & ED_ISR_OVW) {
2471 ifp->if_ierrors++;
2472#ifdef DIAGNOSTIC
2473 log(LOG_WARNING,
2474 "ed%d: warning - receiver ring buffer overrun\n",
2475 ifp->if_unit);
2476#endif
2477
2478 /*
2479 * Stop/reset/re-init NIC
2480 */
2481 ed_reset(ifp);
2482 } else {
2483
2484 /*
2485 * Receiver Error. One or more of: CRC error,
2486 * frame alignment error FIFO overrun, or
2487 * missed packet.
2488 */
2489 if (isr & ED_ISR_RXE) {
2490 u_char rsr;
2491 rsr = inb(sc->nic_addr + ED_P0_RSR);
2492 if (rsr & ED_RSR_CRC)
2493 sc->mibdata.dot3StatsFCSErrors++;
2494 if (rsr & ED_RSR_FAE)
2495 sc->mibdata.dot3StatsAlignmentErrors++;
2496 if (rsr & ED_RSR_FO)
2497 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2498 ifp->if_ierrors++;
2499#ifdef ED_DEBUG
2500 printf("ed%d: receive error %x\n", ifp->if_unit,
2501 inb(sc->nic_addr + ED_P0_RSR));
2502#endif
2503 }
2504
2505 /*
2506 * Go get the packet(s) XXX - Doing this on an
2507 * error is dubious because there shouldn't be
2508 * any data to get (we've configured the
2509 * interface to not accept packets with
2510 * errors).
2511 */
2512
2513 /*
2514 * Enable 16bit access to shared memory first
2515 * on WD/SMC boards.
2516 */
2517 if (sc->isa16bit &&
2518 (sc->vendor == ED_VENDOR_WD_SMC)) {
2519
2520 outb(sc->asic_addr + ED_WD_LAAR,
2521 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2522 if (sc->is790) {
2523 outb(sc->asic_addr + ED_WD_MSR,
2524 ED_WD_MSR_MENB);
2525 }
2526 }
2527 ed_rint(sc);
2528
2529 /* disable 16bit access */
2530 if (sc->isa16bit &&
2531 (sc->vendor == ED_VENDOR_WD_SMC)) {
2532
2533 if (sc->is790) {
2534 outb(sc->asic_addr + ED_WD_MSR, 0x00);
2535 }
2536 outb(sc->asic_addr + ED_WD_LAAR,
2537 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2538 }
2539 }
2540 }
2541
2542 /*
2543 * If it looks like the transmitter can take more data,
2544 * attempt to start output on the interface. This is done
2545 * after handling the receiver to give the receiver priority.
2546 */
2547 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2548 ed_start(ifp);
2549
2550 /*
2551 * return NIC CR to standard state: page 0, remote DMA
2552 * complete, start (toggling the TXP bit off, even if was just
2553 * set in the transmit routine, is *okay* - it is 'edge'
2554 * triggered from low to high)
2555 */
2556 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
2557
2558 /*
2559 * If the Network Talley Counters overflow, read them to reset
2560 * them. It appears that old 8390's won't clear the ISR flag
2561 * otherwise - resulting in an infinite loop.
2562 */
2563 if (isr & ED_ISR_CNT) {
2564 (void) inb(sc->nic_addr + ED_P0_CNTR0);
2565 (void) inb(sc->nic_addr + ED_P0_CNTR1);
2566 (void) inb(sc->nic_addr + ED_P0_CNTR2);
2567 }
2568 }
2569}
2570
2571void
2572edintr(unit)
2573 int unit;
2574{
2575 edintr_sc (&ed_softc[unit]);
2576}
2577
2578/*
2579 * Process an ioctl request. This code needs some work - it looks
2580 * pretty ugly.
2581 */
2582static int
2583ed_ioctl(ifp, command, data)
2584 register struct ifnet *ifp;
2585 int command;
2586 caddr_t data;
2587{
2588 struct ed_softc *sc = ifp->if_softc;
2589 int s, error = 0;
2590
2591 if (sc->gone) {
2592 ifp->if_flags &= ~IFF_RUNNING;
2593 return ENXIO;
2594 }
2595 s = splimp();
2596
2597 switch (command) {
2598
2599 case SIOCSIFADDR:
2600 case SIOCGIFADDR:
2601 case SIOCSIFMTU:
2602 error = ether_ioctl(ifp, command, data);
2603 break;
2604
2605 case SIOCSIFFLAGS:
2606
2607 /*
2608 * If the interface is marked up and stopped, then start it.
2609 * If it is marked down and running, then stop it.
2610 */
2611 if (ifp->if_flags & IFF_UP) {
2612 if ((ifp->if_flags & IFF_RUNNING) == 0)
2613 ed_init(sc);
2614 } else {
2615 if (ifp->if_flags & IFF_RUNNING) {
2616 ed_stop(sc);
2617 ifp->if_flags &= ~IFF_RUNNING;
2618 }
2619 }
2620
2621#if NBPFILTER > 0
2622
2623 /*
2624 * Promiscuous flag may have changed, so reprogram the RCR.
2625 */
2626 ed_setrcr(sc);
2627#endif
2628
2629 /*
2630 * An unfortunate hack to provide the (required) software
2631 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2632 * disables the tranceiver if set.
2633 */
2634 if (sc->vendor == ED_VENDOR_3COM) {
2635 if (ifp->if_flags & IFF_ALTPHYS) {
2636 outb(sc->asic_addr + ED_3COM_CR, 0);
2637 } else {
2638 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
2639 }
2640 } else if (sc->vendor == ED_VENDOR_HP)
2641 ed_hpp_set_physical_link(sc);
2642 break;
2643
2644 case SIOCADDMULTI:
2645 case SIOCDELMULTI:
2646 /*
2647 * Multicast list has changed; set the hardware filter
2648 * accordingly.
2649 */
2650 ed_setrcr(sc);
2651 error = 0;
2652 break;
2653
2654 default:
2655 error = EINVAL;
2656 }
2657 (void) splx(s);
2658 return (error);
2659}
2660
2661/*
2662 * Given a source and destination address, copy 'amount' of a packet from
2663 * the ring buffer into a linear destination buffer. Takes into account
2664 * ring-wrap.
2665 */
2666static __inline char *
2667ed_ring_copy(sc, src, dst, amount)
2668 struct ed_softc *sc;
2669 char *src;
2670 char *dst;
2671 u_short amount;
2672{
2673 u_short tmp_amount;
2674
2675 /* does copy wrap to lower addr in ring buffer? */
2676 if (src + amount > sc->mem_end) {
2677 tmp_amount = sc->mem_end - src;
2678
2679 /* copy amount up to end of NIC memory */
2680 if (sc->mem_shared)
2681 bcopy(src, dst, tmp_amount);
2682 else
2683 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2684
2685 amount -= tmp_amount;
2686 src = sc->mem_ring;
2687 dst += tmp_amount;
2688 }
2689 if (sc->mem_shared)
2690 bcopy(src, dst, amount);
2691 else
2692 ed_pio_readmem(sc, (int)src, dst, amount);
2693
2694 return (src + amount);
2695}
2696
2697/*
2698 * Retreive packet from shared memory and send to the next level up via
2699 * ether_input(). If there is a BPF listener, give a copy to BPF, too.
2700 */
2701static void
2702ed_get_packet(sc, buf, len, multicast)
2703 struct ed_softc *sc;
2704 char *buf;
2705 u_short len;
2706 int multicast;
2707{
2708 struct ether_header *eh;
2709 struct mbuf *m;
2710
2711 /* Allocate a header mbuf */
2712 MGETHDR(m, M_DONTWAIT, MT_DATA);
2713 if (m == NULL)
2714 return;
2715 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2716 m->m_pkthdr.len = m->m_len = len;
2717
2718 /*
2719 * We always put the received packet in a single buffer -
2720 * either with just an mbuf header or in a cluster attached
2721 * to the header. The +2 is to compensate for the alignment
2722 * fixup below.
2723 */
2724 if ((len + 2) > MHLEN) {
2725 /* Attach an mbuf cluster */
2726 MCLGET(m, M_DONTWAIT);
2727
2728 /* Insist on getting a cluster */
2729 if ((m->m_flags & M_EXT) == 0) {
2730 m_freem(m);
2731 return;
2732 }
2733 }
2734
2735 /*
2736 * The +2 is to longword align the start of the real packet.
2737 * This is important for NFS.
2738 */
2739 m->m_data += 2;
2740 eh = mtod(m, struct ether_header *);
2741
2742 /*
2743 * Get packet, including link layer address, from interface.
2744 */
2745 ed_ring_copy(sc, buf, (char *)eh, len);
2746
2747#if NBPFILTER > 0
2748
2749 /*
2750 * Check if there's a BPF listener on this interface. If so, hand off
2751 * the raw packet to bpf.
2752 */
2753 if (sc->arpcom.ac_if.if_bpf) {
2754 bpf_mtap(&sc->arpcom.ac_if, m);
2755
2756 /*
2757 * Note that the interface cannot be in promiscuous mode if
2758 * there are no BPF listeners. And if we are in promiscuous
2759 * mode, we have to check if this packet is really ours.
2760 */
2761 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
2762 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
2763 sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
2764 m_freem(m);
2765 return;
2766 }
2767 }
2768#endif
2769
2770 /*
2771 * Remove link layer address.
2772 */
2773 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2774 m->m_data += sizeof(struct ether_header);
2775
2776 ether_input(&sc->arpcom.ac_if, eh, m);
2777 return;
2778}
2779
2780/*
2781 * Supporting routines
2782 */
2783
2784/*
2785 * Given a NIC memory source address and a host memory destination
2786 * address, copy 'amount' from NIC to host using Programmed I/O.
2787 * The 'amount' is rounded up to a word - okay as long as mbufs
2788 * are word sized.
2789 * This routine is currently Novell-specific.
2790 */
2791static void
2792ed_pio_readmem(sc, src, dst, amount)
2793 struct ed_softc *sc;
2794 int src;
2795 unsigned char *dst;
2796 unsigned short amount;
2797{
2798 /* HP cards need special handling */
2799 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2800 ed_hpp_readmem(sc, src, dst, amount);
2801 return;
2802 }
2803
2804 /* Regular Novell cards */
2805 /* select page 0 registers */
2806 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2807
2808 /* round up to a word */
2809 if (amount & 1)
2810 ++amount;
2811
2812 /* set up DMA byte count */
2813 outb(sc->nic_addr + ED_P0_RBCR0, amount);
2814 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
2815
2816 /* set up source address in NIC mem */
2817 outb(sc->nic_addr + ED_P0_RSAR0, src);
2818 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
2819
2820 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2821
2822 if (sc->isa16bit) {
2823 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
2824 } else
2825 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
2826
2827}
2828
2829/*
2830 * Stripped down routine for writing a linear buffer to NIC memory.
2831 * Only used in the probe routine to test the memory. 'len' must
2832 * be even.
2833 */
2834static void
2835ed_pio_writemem(sc, src, dst, len)
2836 struct ed_softc *sc;
2837 char *src;
2838 unsigned short dst;
2839 unsigned short len;
2840{
2841 int maxwait = 200; /* about 240us */
2842
2843 if (sc->vendor == ED_VENDOR_NOVELL) {
2844
2845 /* select page 0 registers */
2846 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2847
2848 /* reset remote DMA complete flag */
2849 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2850
2851 /* set up DMA byte count */
2852 outb(sc->nic_addr + ED_P0_RBCR0, len);
2853 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
2854
2855 /* set up destination address in NIC mem */
2856 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2857 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2858
2859 /* set remote DMA write */
2860 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2861
2862 if (sc->isa16bit)
2863 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
2864 else
2865 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
2866
2867 /*
2868 * Wait for remote DMA complete. This is necessary because on the
2869 * transmit side, data is handled internally by the NIC in bursts and
2870 * we can't start another remote DMA until this one completes. Not
2871 * waiting causes really bad things to happen - like the NIC
2872 * irrecoverably jamming the ISA bus.
2873 */
2874 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2875
2876 } else if ((sc->vendor == ED_VENDOR_HP) &&
2877 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2878
2879 /* HP PCLAN+ */
2880
2881 /* reset remote DMA complete flag */
2882 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2883
2884 /* program the write address in RAM */
2885 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
2886
2887 if (sc->hpp_mem_start) {
2888 u_short *s = (u_short *) src;
2889 volatile u_short *d = (u_short *) sc->hpp_mem_start;
2890 u_short *const fence = s + (len >> 1);
2891
2892 /*
2893 * Enable memory mapped access.
2894 */
2895
2896 outw(sc->asic_addr + ED_HPP_OPTION,
2897 sc->hpp_options &
2898 ~(ED_HPP_OPTION_MEM_DISABLE |
2899 ED_HPP_OPTION_BOOT_ROM_ENB));
2900
2901 /*
2902 * Copy to NIC memory.
2903 */
2904
2905 while (s < fence)
2906 *d = *s++;
2907
2908 /*
2909 * Restore Boot ROM access.
2910 */
2911
2912 outw(sc->asic_addr + ED_HPP_OPTION,
2913 sc->hpp_options);
2914
2915 } else {
2916 /* write data using I/O writes */
2917 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
2918 }
2919
2920 }
2921}
2922
2923/*
2924 * Write an mbuf chain to the destination NIC memory address using
2925 * programmed I/O.
2926 */
2927static u_short
2928ed_pio_write_mbufs(sc, m, dst)
2929 struct ed_softc *sc;
2930 struct mbuf *m;
2931 int dst;
2932{
2933 struct ifnet *ifp = (struct ifnet *)sc;
2934 unsigned short total_len, dma_len;
2935 struct mbuf *mp;
2936 int maxwait = 200; /* about 240us */
2937
2938 /* HP PC Lan+ cards need special handling */
2939 if ((sc->vendor == ED_VENDOR_HP) &&
2940 (sc->type == ED_TYPE_HP_PCLANPLUS)) {
2941 return ed_hpp_write_mbufs(sc, m, dst);
2942 }
2943
2944 /* First, count up the total number of bytes to copy */
2945 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2946 total_len += mp->m_len;
2947
2948 dma_len = total_len;
2949 if (sc->isa16bit && (dma_len & 1))
2950 dma_len++;
2951
2952 /* select page 0 registers */
2953 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2954
2955 /* reset remote DMA complete flag */
2956 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
2957
2958 /* set up DMA byte count */
2959 outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
2960 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
2961
2962 /* set up destination address in NIC mem */
2963 outb(sc->nic_addr + ED_P0_RSAR0, dst);
2964 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
2965
2966 /* set remote DMA write */
2967 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2968
2969 /*
2970 * Transfer the mbuf chain to the NIC memory.
2971 * 16-bit cards require that data be transferred as words, and only words.
2972 * So that case requires some extra code to patch over odd-length mbufs.
2973 */
2974
2975 if (!sc->isa16bit) {
2976 /* NE1000s are easy */
2977 while (m) {
2978 if (m->m_len) {
2979 outsb(sc->asic_addr + ED_NOVELL_DATA,
2980 m->m_data, m->m_len);
2981 }
2982 m = m->m_next;
2983 }
2984 } else {
2985 /* NE2000s are a pain */
2986 unsigned char *data;
2987 int len, wantbyte;
2988 unsigned char savebyte[2];
2989
2990 wantbyte = 0;
2991
2992 while (m) {
2993 len = m->m_len;
2994 if (len) {
2995 data = mtod(m, caddr_t);
2996 /* finish the last word */
2997 if (wantbyte) {
2998 savebyte[1] = *data;
2999 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3000 data++;
3001 len--;
3002 wantbyte = 0;
3003 }
3004 /* output contiguous words */
3005 if (len > 1) {
3006 outsw(sc->asic_addr + ED_NOVELL_DATA,
3007 data, len >> 1);
3008 data += len & ~1;
3009 len &= 1;
3010 }
3011 /* save last byte, if necessary */
3012 if (len == 1) {
3013 savebyte[0] = *data;
3014 wantbyte = 1;
3015 }
3016 }
3017 m = m->m_next;
3018 }
3019 /* spit last byte */
3020 if (wantbyte) {
3021 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
3022 }
3023 }
3024
3025 /*
3026 * Wait for remote DMA complete. This is necessary because on the
3027 * transmit side, data is handled internally by the NIC in bursts and
3028 * we can't start another remote DMA until this one completes. Not
3029 * waiting causes really bad things to happen - like the NIC
3030 * irrecoverably jamming the ISA bus.
3031 */
3032 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3033
3034 if (!maxwait) {
3035 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
3036 ifp->if_unit);
3037 ed_reset(ifp);
3038 return(0);
3039 }
3040 return (total_len);
3041}
3042
3043/*
3044 * Support routines to handle the HP PC Lan+ card.
3045 */
3046
3047/*
3048 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3049 * IO.
3050 */
3051
3052static void
3053ed_hpp_readmem(sc, src, dst, amount)
3054 struct ed_softc *sc;
3055 unsigned short src;
3056 unsigned char *dst;
3057 unsigned short amount;
3058{
3059
3060 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3061
3062
3063 /* Program the source address in RAM */
3064 outw(sc->asic_addr + ED_HPP_PAGE_2, src);
3065
3066 /*
3067 * The HP PC Lan+ card supports word reads as well as
3068 * a memory mapped i/o port that is aliased to every
3069 * even address on the board.
3070 */
3071
3072 if (sc->hpp_mem_start) {
3073
3074 /* Enable memory mapped access. */
3075 outw(sc->asic_addr + ED_HPP_OPTION,
3076 sc->hpp_options &
3077 ~(ED_HPP_OPTION_MEM_DISABLE |
3078 ED_HPP_OPTION_BOOT_ROM_ENB));
3079
3080 if (use_32bit_access && (amount > 3)) {
3081 u_long *dl = (u_long *) dst;
3082 volatile u_long *const sl =
3083 (u_long *) sc->hpp_mem_start;
3084 u_long *const fence = dl + (amount >> 2);
3085
3086 /* Copy out NIC data. We could probably write this
3087 as a `movsl'. The currently generated code is lousy.
3088 */
3089
3090 while (dl < fence)
3091 *dl++ = *sl;
3092
3093 dst += (amount & ~3);
3094 amount &= 3;
3095
3096 }
3097
3098 /* Finish off any words left, as a series of short reads */
3099 if (amount > 1) {
3100 u_short *d = (u_short *) dst;
3101 volatile u_short *const s =
3102 (u_short *) sc->hpp_mem_start;
3103 u_short *const fence = d + (amount >> 1);
3104
3105 /* Copy out NIC data. */
3106
3107 while (d < fence)
3108 *d++ = *s;
3109
3110 dst += (amount & ~1);
3111 amount &= 1;
3112 }
3113
3114 /*
3115 * read in a byte; however we need to always read 16 bits
3116 * at a time or the hardware gets into a funny state
3117 */
3118
3119 if (amount == 1) {
3120 /* need to read in a short and copy LSB */
3121 volatile u_short *const s =
3122 (volatile u_short *) sc->hpp_mem_start;
3123
3124 *dst = (*s) & 0xFF;
3125 }
3126
3127 /* Restore Boot ROM access. */
3128
3129 outw(sc->asic_addr + ED_HPP_OPTION,
3130 sc->hpp_options);
3131
3132
3133 } else {
3134 /* Read in data using the I/O port */
3135 if (use_32bit_access && (amount > 3)) {
3136 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
3137 dst += (amount & ~3);
3138 amount &= 3;
3139 }
3140 if (amount > 1) {
3141 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
3142 dst += (amount & ~1);
3143 amount &= 1;
3144 }
3145 if (amount == 1) { /* read in a short and keep the LSB */
3146 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
3147 }
3148 }
3149}
3150
3151/*
3152 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3153 * outsw() or via the memory mapped interface to the same register.
3154 * Writes have to be in word units; byte accesses won't work and may cause
3155 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3156 * allows it.
3157 */
3158
3159static u_short
3160ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3161{
3162 int len, wantbyte;
3163 unsigned short total_len;
3164 unsigned char savebyte[2];
3165 volatile u_short * const d =
3166 (volatile u_short *) sc->hpp_mem_start;
3167 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3168
3169 /* select page 0 registers */
3170 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3171
3172 /* reset remote DMA complete flag */
3173 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
3174
3175 /* program the write address in RAM */
3176 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
3177
3178 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3179 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options &
3180 ~(ED_HPP_OPTION_MEM_DISABLE |
3181 ED_HPP_OPTION_BOOT_ROM_ENB));
3182
3183 wantbyte = 0;
3184 total_len = 0;
3185
3186 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3187 while (m) {
3188 total_len += (len = m->m_len);
3189 if (len) {
3190 caddr_t data = mtod(m, caddr_t);
3191 /* finish the last word of the previous mbuf */
3192 if (wantbyte) {
3193 savebyte[1] = *data;
3194 *d = *((ushort *) savebyte);
3195 data++; len--; wantbyte = 0;
3196 }
3197 /* output contiguous words */
3198 if ((len > 3) && (use_32bit_accesses)) {
3199 volatile u_long *const dl =
3200 (volatile u_long *) d;
3201 u_long *sl = (u_long *) data;
3202 u_long *fence = sl + (len >> 2);
3203
3204 while (sl < fence)
3205 *dl = *sl++;
3206
3207 data += (len & ~3);
3208 len &= 3;
3209 }
3210 /* finish off remain 16 bit writes */
3211 if (len > 1) {
3212 u_short *s = (u_short *) data;
3213 u_short *fence = s + (len >> 1);
3214
3215 while (s < fence)
3216 *d = *s++;
3217
3218 data += (len & ~1);
3219 len &= 1;
3220 }
3221 /* save last byte if needed */
3222 if (wantbyte = (len == 1))
3223 savebyte[0] = *data;
3224 }
3225 m = m->m_next; /* to next mbuf */
3226 }
3227 if (wantbyte) /* write last byte */
3228 *d = *((u_short *) savebyte);
3229 } else {
3230 /* use programmed I/O */
3231 while (m) {
3232 total_len += (len = m->m_len);
3233 if (len) {
3234 caddr_t data = mtod(m, caddr_t);
3235 /* finish the last word of the previous mbuf */
3236 if (wantbyte) {
3237 savebyte[1] = *data;
3238 outw(sc->asic_addr + ED_HPP_PAGE_4,
3239 *((u_short *)savebyte));
3240 data++;
3241 len--;
3242 wantbyte = 0;
3243 }
3244 /* output contiguous words */
3245 if ((len > 3) && use_32bit_accesses) {
3246 outsl(sc->asic_addr + ED_HPP_PAGE_4,
3247 data, len >> 2);
3248 data += (len & ~3);
3249 len &= 3;
3250 }
3251 /* finish off remaining 16 bit accesses */
3252 if (len > 1) {
3253 outsw(sc->asic_addr + ED_HPP_PAGE_4,
3254 data, len >> 1);
3255 data += (len & ~1);
3256 len &= 1;
3257 }
3258 if (wantbyte = (len == 1))
3259 savebyte[0] = *data;
3260
3261 } /* if len != 0 */
3262 m = m->m_next;
3263 }
3264 if (wantbyte) /* spit last byte */
3265 outw(sc->asic_addr + ED_HPP_PAGE_4,
3266 *(u_short *)savebyte);
3267
3268 }
3269
3270 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3271 outw(sc->asic_addr + ED_HPP_OPTION,
3272 sc->hpp_options);
3273
3274 return (total_len);
3275}
3276
3277static void
3278ed_setrcr(sc)
3279 struct ed_softc *sc;
3280{
3281 struct ifnet *ifp = (struct ifnet *)sc;
3282 int i;
3283
3284 /* set page 1 registers */
3285 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3286
3287 if (ifp->if_flags & IFF_PROMISC) {
3288
3289 /*
3290 * Reconfigure the multicast filter.
3291 */
3292 for (i = 0; i < 8; i++)
3293 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
3294
3295 /*
3296 * And turn on promiscuous mode. Also enable reception of
3297 * runts and packets with CRC & alignment errors.
3298 */
3299 /* Set page 0 registers */
3300 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3301
3302 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3303 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
3304 } else {
3305 /* set up multicast addresses and filter modes */
3306 if (ifp->if_flags & IFF_MULTICAST) {
3307 u_long mcaf[2];
3308
3309 if (ifp->if_flags & IFF_ALLMULTI) {
3310 mcaf[0] = 0xffffffff;
3311 mcaf[1] = 0xffffffff;
3312 } else
3313 ds_getmcaf(sc, mcaf);
3314
3315 /*
3316 * Set multicast filter on chip.
3317 */
3318 for (i = 0; i < 8; i++)
3319 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
3320
3321 /* Set page 0 registers */
3322 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3323
3324 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
3325 } else {
3326
3327 /*
3328 * Initialize multicast address hashing registers to
3329 * not accept multicasts.
3330 */
3331 for (i = 0; i < 8; ++i)
3332 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
3333
3334 /* Set page 0 registers */
3335 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
3336
3337 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
3338 }
3339 }
3340
3341 /*
3342 * Start interface.
3343 */
3344 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
3345}
3346
3347/*
3348 * Compute crc for ethernet address
3349 */
3350static u_long
3351ds_crc(ep)
3352 u_char *ep;
3353{
3354#define POLYNOMIAL 0x04c11db6
3355 register u_long crc = 0xffffffffL;
3356 register int carry, i, j;
3357 register u_char b;
3358
3359 for (i = 6; --i >= 0;) {
3360 b = *ep++;
3361 for (j = 8; --j >= 0;) {
3362 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
3363 crc <<= 1;
3364 b >>= 1;
3365 if (carry)
3366 crc = ((crc ^ POLYNOMIAL) | carry);
3367 }
3368 }
3369 return crc;
3370#undef POLYNOMIAL
3371}
3372
3373/*
3374 * Compute the multicast address filter from the
3375 * list of multicast addresses we need to listen to.
3376 */
3377static void
3378ds_getmcaf(sc, mcaf)
3379 struct ed_softc *sc;
3380 u_long *mcaf;
3381{
3382 register u_int index;
3383 register u_char *af = (u_char *) mcaf;
3384 struct ifmultiaddr *ifma;
3385
3386 mcaf[0] = 0;
3387 mcaf[1] = 0;
3388
3389 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3390 ifma = ifma->ifma_link.le_next) {
3391 if (ifma->ifma_addr->sa_family != AF_LINK)
3392 continue;
3393 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3394 >> 26;
3395 af[index >> 3] |= 1 << (index & 7);
3396 }
3397}
3398
3399/*
3400 * support PnP cards if we are using 'em
3401 */
3402
3403#if NPNP > 0
3404
3405static struct edpnp_ids {
3406 u_long vend_id;
3407 char *id_str;
3408} edpnp_ids[] = {
3409 { 0x1980635e, "WSC8019"},
3410 { 0 }
3411};
3412
3413static char *edpnp_probe(u_long csn, u_long vend_id);
3414static void edpnp_attach(u_long csn, u_long vend_id, char *name,
3415 struct isa_device *dev);
3416static u_long nedpnp = NED;
3417
3418static struct pnp_device edpnp = {
3419 "edpnp",
3420 edpnp_probe,
3421 edpnp_attach,
3422 &nedpnp,
3423 &net_imask
3424};
3425DATA_SET (pnpdevice_set, edpnp);
3426
3427static char *
3428edpnp_probe(u_long csn, u_long vend_id)
3429{
3430 struct edpnp_ids *ids;
3431 char *s = NULL;
3432
3433 for(ids = edpnp_ids; ids->vend_id != 0; ids++) {
3434 if (vend_id == ids->vend_id) {
3435 s = ids->id_str;
3436 break;
3437 }
3438 }
3439
3440 if (s) {
3441 struct pnp_cinfo d;
3442 read_pnp_parms(&d, 0);
3443 if (d.enable == 0 || d.flags & 1) {
3444 printf("CSN %d is disabled.\n", csn);
3445 return (NULL);
3446 }
3447
3448 }
3449
3450 return (s);
3451}
3452
3453static void
3454edpnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
3455{
3456 struct pnp_cinfo d;
3457 struct isa_device *dvp;
3458
3459 if (dev->id_unit >= NEDTOT)
3460 return;
3461
3462 if (read_pnp_parms(&d, 0) == 0) {
3463 printf("failed to read pnp parms\n");
3464 return;
3465 }
3466
3467 write_pnp_parms(&d, 0);
3468
3469 enable_pnp_card();
3470
3471 dev->id_iobase = d.port[0];
3472 dev->id_irq = (1 << d.irq[0]);
3473 dev->id_intr = edintr;
3474 dev->id_drq = -1;
3475
3476 if (dev->id_driver == NULL) {
3477 dev->id_driver = &eddriver;
3478 dvp = find_isadev(isa_devtab_net, &eddriver, 0);
3479 if (dvp != NULL)
3480 dev->id_id = dvp->id_id;
3481 }
3482
3483 if ((dev->id_alive = ed_probe(dev)) != 0)
3484 ed_attach_isa(dev);
3485 else
3486 printf("ed%d: probe failed\n", dev->id_unit);
3487}
3488#endif