1/**************************************************************************
2
3Copyright (c) 2001-2007, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
| 1/**************************************************************************
2
3Copyright (c) 2001-2007, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
|
33/*$FreeBSD: head/sys/dev/em/if_em.h 169637 2007-05-17 00:14:03Z jfv $*/
| 33/*$FreeBSD: head/sys/dev/em/if_em.h 172138 2007-09-10 21:50:40Z jfv $*/
|
34
35#ifndef _EM_H_DEFINED_
36#define _EM_H_DEFINED_
37
38/* Tunables */
39
40/*
41 * EM_TXD: Maximum number of Transmit Descriptors
42 * Valid Range: 80-256 for 82542 and 82543-based adapters
43 * 80-4096 for others
44 * Default Value: 256
45 * This value is the number of transmit descriptors allocated by the driver.
46 * Increasing this value allows the driver to queue more transmits. Each
47 * descriptor is 16 bytes.
48 * Since TDLEN should be multiple of 128bytes, the number of transmit
49 * desscriptors should meet the following condition.
50 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
51 */
52#define EM_MIN_TXD 80
53#define EM_MAX_TXD_82543 256
54#define EM_MAX_TXD 4096
55#define EM_DEFAULT_TXD EM_MAX_TXD_82543
56
57/*
58 * EM_RXD - Maximum number of receive Descriptors
59 * Valid Range: 80-256 for 82542 and 82543-based adapters
60 * 80-4096 for others
61 * Default Value: 256
62 * This value is the number of receive descriptors allocated by the driver.
63 * Increasing this value allows the driver to buffer more incoming packets.
64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
65 * descriptor. The maximum MTU size is 16110.
66 * Since TDLEN should be multiple of 128bytes, the number of transmit
67 * desscriptors should meet the following condition.
68 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
69 */
70#define EM_MIN_RXD 80
71#define EM_MAX_RXD_82543 256
72#define EM_MAX_RXD 4096
73#define EM_DEFAULT_RXD EM_MAX_RXD_82543
74
75/*
76 * EM_TIDV - Transmit Interrupt Delay Value
77 * Valid Range: 0-65535 (0=off)
78 * Default Value: 64
79 * This value delays the generation of transmit interrupts in units of
80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
81 * efficiency if properly tuned for specific network traffic. If the
82 * system is reporting dropped transmits, this value may be set too high
83 * causing the driver to run out of available transmit descriptors.
84 */
85#define EM_TIDV 64
86
87/*
88 * EM_TADV - Transmit Absolute Interrupt Delay Value
89 * (Not valid for 82542/82543/82544)
90 * Valid Range: 0-65535 (0=off)
91 * Default Value: 64
92 * This value, in units of 1.024 microseconds, limits the delay in which a
93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
94 * this value ensures that an interrupt is generated after the initial
95 * packet is sent on the wire within the set amount of time. Proper tuning,
96 * along with EM_TIDV, may improve traffic throughput in specific
97 * network conditions.
98 */
99#define EM_TADV 64
100
101/*
102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
103 * Valid Range: 0-65535 (0=off)
104 * Default Value: 0
105 * This value delays the generation of receive interrupts in units of 1.024
106 * microseconds. Receive interrupt reduction can improve CPU efficiency if
107 * properly tuned for specific network traffic. Increasing this value adds
108 * extra latency to frame reception and can end up decreasing the throughput
109 * of TCP traffic. If the system is reporting dropped receives, this value
110 * may be set too high, causing the driver to run out of available receive
111 * descriptors.
112 *
113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
114 * may hang (stop transmitting) under certain network conditions.
115 * If this occurs a WATCHDOG message is logged in the system
116 * event log. In addition, the controller is automatically reset,
117 * restoring the network connection. To eliminate the potential
118 * for the hang ensure that EM_RDTR is set to 0.
119 */
120#define EM_RDTR 0
121
122/*
123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
124 * Valid Range: 0-65535 (0=off)
125 * Default Value: 64
126 * This value, in units of 1.024 microseconds, limits the delay in which a
127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
128 * this value ensures that an interrupt is generated after the initial
129 * packet is received within the set amount of time. Proper tuning,
130 * along with EM_RDTR, may improve traffic throughput in specific network
131 * conditions.
132 */
133#define EM_RADV 64
134
135/*
136 * This parameter controls the duration of transmit watchdog timer.
137 */
138#define EM_TX_TIMEOUT 5 /* set to 5 seconds */
139
140/*
141 * This parameter controls when the driver calls the routine to reclaim
142 * transmit descriptors.
143 */
144#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
145#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
146
147/*
148 * This parameter controls whether or not autonegotation is enabled.
149 * 0 - Disable autonegotiation
150 * 1 - Enable autonegotiation
151 */
152#define DO_AUTO_NEG 1
153
154/*
155 * This parameter control whether or not the driver will wait for
156 * autonegotiation to complete.
157 * 1 - Wait for autonegotiation to complete
158 * 0 - Don't wait for autonegotiation to complete
159 */
160#define WAIT_FOR_AUTO_NEG_DEFAULT 0
161
162/* Tunables -- End */
163
164#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
165 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
166 ADVERTISE_1000_FULL)
167
168#define AUTO_ALL_MODES 0
169
170/* PHY master/slave setting */
171#define EM_MASTER_SLAVE e1000_ms_hw_default
172
173/*
174 * Micellaneous constants
175 */
176#define EM_VENDOR_ID 0x8086
177#define EM_FLASH 0x0014
178
179#define EM_JUMBO_PBA 0x00000028
180#define EM_DEFAULT_PBA 0x00000030
181#define EM_SMARTSPEED_DOWNSHIFT 3
182#define EM_SMARTSPEED_MAX 15
183#define EM_MAX_INTR 10
| 34
35#ifndef _EM_H_DEFINED_
36#define _EM_H_DEFINED_
37
38/* Tunables */
39
40/*
41 * EM_TXD: Maximum number of Transmit Descriptors
42 * Valid Range: 80-256 for 82542 and 82543-based adapters
43 * 80-4096 for others
44 * Default Value: 256
45 * This value is the number of transmit descriptors allocated by the driver.
46 * Increasing this value allows the driver to queue more transmits. Each
47 * descriptor is 16 bytes.
48 * Since TDLEN should be multiple of 128bytes, the number of transmit
49 * desscriptors should meet the following condition.
50 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
51 */
52#define EM_MIN_TXD 80
53#define EM_MAX_TXD_82543 256
54#define EM_MAX_TXD 4096
55#define EM_DEFAULT_TXD EM_MAX_TXD_82543
56
57/*
58 * EM_RXD - Maximum number of receive Descriptors
59 * Valid Range: 80-256 for 82542 and 82543-based adapters
60 * 80-4096 for others
61 * Default Value: 256
62 * This value is the number of receive descriptors allocated by the driver.
63 * Increasing this value allows the driver to buffer more incoming packets.
64 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
65 * descriptor. The maximum MTU size is 16110.
66 * Since TDLEN should be multiple of 128bytes, the number of transmit
67 * desscriptors should meet the following condition.
68 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
69 */
70#define EM_MIN_RXD 80
71#define EM_MAX_RXD_82543 256
72#define EM_MAX_RXD 4096
73#define EM_DEFAULT_RXD EM_MAX_RXD_82543
74
75/*
76 * EM_TIDV - Transmit Interrupt Delay Value
77 * Valid Range: 0-65535 (0=off)
78 * Default Value: 64
79 * This value delays the generation of transmit interrupts in units of
80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
81 * efficiency if properly tuned for specific network traffic. If the
82 * system is reporting dropped transmits, this value may be set too high
83 * causing the driver to run out of available transmit descriptors.
84 */
85#define EM_TIDV 64
86
87/*
88 * EM_TADV - Transmit Absolute Interrupt Delay Value
89 * (Not valid for 82542/82543/82544)
90 * Valid Range: 0-65535 (0=off)
91 * Default Value: 64
92 * This value, in units of 1.024 microseconds, limits the delay in which a
93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
94 * this value ensures that an interrupt is generated after the initial
95 * packet is sent on the wire within the set amount of time. Proper tuning,
96 * along with EM_TIDV, may improve traffic throughput in specific
97 * network conditions.
98 */
99#define EM_TADV 64
100
101/*
102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
103 * Valid Range: 0-65535 (0=off)
104 * Default Value: 0
105 * This value delays the generation of receive interrupts in units of 1.024
106 * microseconds. Receive interrupt reduction can improve CPU efficiency if
107 * properly tuned for specific network traffic. Increasing this value adds
108 * extra latency to frame reception and can end up decreasing the throughput
109 * of TCP traffic. If the system is reporting dropped receives, this value
110 * may be set too high, causing the driver to run out of available receive
111 * descriptors.
112 *
113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
114 * may hang (stop transmitting) under certain network conditions.
115 * If this occurs a WATCHDOG message is logged in the system
116 * event log. In addition, the controller is automatically reset,
117 * restoring the network connection. To eliminate the potential
118 * for the hang ensure that EM_RDTR is set to 0.
119 */
120#define EM_RDTR 0
121
122/*
123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
124 * Valid Range: 0-65535 (0=off)
125 * Default Value: 64
126 * This value, in units of 1.024 microseconds, limits the delay in which a
127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
128 * this value ensures that an interrupt is generated after the initial
129 * packet is received within the set amount of time. Proper tuning,
130 * along with EM_RDTR, may improve traffic throughput in specific network
131 * conditions.
132 */
133#define EM_RADV 64
134
135/*
136 * This parameter controls the duration of transmit watchdog timer.
137 */
138#define EM_TX_TIMEOUT 5 /* set to 5 seconds */
139
140/*
141 * This parameter controls when the driver calls the routine to reclaim
142 * transmit descriptors.
143 */
144#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
145#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
146
147/*
148 * This parameter controls whether or not autonegotation is enabled.
149 * 0 - Disable autonegotiation
150 * 1 - Enable autonegotiation
151 */
152#define DO_AUTO_NEG 1
153
154/*
155 * This parameter control whether or not the driver will wait for
156 * autonegotiation to complete.
157 * 1 - Wait for autonegotiation to complete
158 * 0 - Don't wait for autonegotiation to complete
159 */
160#define WAIT_FOR_AUTO_NEG_DEFAULT 0
161
162/* Tunables -- End */
163
164#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
165 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
166 ADVERTISE_1000_FULL)
167
168#define AUTO_ALL_MODES 0
169
170/* PHY master/slave setting */
171#define EM_MASTER_SLAVE e1000_ms_hw_default
172
173/*
174 * Micellaneous constants
175 */
176#define EM_VENDOR_ID 0x8086
177#define EM_FLASH 0x0014
178
179#define EM_JUMBO_PBA 0x00000028
180#define EM_DEFAULT_PBA 0x00000030
181#define EM_SMARTSPEED_DOWNSHIFT 3
182#define EM_SMARTSPEED_MAX 15
183#define EM_MAX_INTR 10
|
184#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */
| |
185
186#define MAX_NUM_MULTICAST_ADDRESSES 128
187#define PCI_ANY_ID (~0U)
188#define ETHER_ALIGN 2
189#define EM_TX_BUFFER_SIZE ((uint32_t) 1514)
190#define EM_FC_PAUSE_TIME 0x0680
191#define EM_EEPROM_APME 0x400;
192
193/*
194 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
195 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
196 * also optimize cache line size effect. H/W supports up to cache line size 128.
197 */
198#define EM_DBA_ALIGN 128
199
200#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
201
202/* PCI Config defines */
203#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
204#define EM_BAR_TYPE_MASK 0x00000001
205#define EM_BAR_TYPE_MMEM 0x00000000
206#define EM_BAR_TYPE_IO 0x00000001
207#define EM_BAR_TYPE_FLASH 0x0014
208#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
209#define EM_BAR_MEM_TYPE_MASK 0x00000006
210#define EM_BAR_MEM_TYPE_32BIT 0x00000000
211#define EM_BAR_MEM_TYPE_64BIT 0x00000004
212#define EM_MSIX_BAR 3 /* On 82575 */
213
214/* Defines for printing debug information */
215#define DEBUG_INIT 0
216#define DEBUG_IOCTL 0
217#define DEBUG_HW 0
218
219#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
220#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
221#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
222#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
223#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
224#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
225#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
226#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
227#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
228
229#define EM_MAX_SCATTER 64
230#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */
231#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
232#define ETH_ZLEN 60
233#define ETH_ADDR_LEN 6
234#define CSUM_OFFLOAD 7 /* Offload bits in csum flags */
235
236struct adapter;
237
238struct em_int_delay_info {
239 struct adapter *adapter; /* Back-pointer to the adapter struct */
240 int offset; /* Register offset to read/write */
241 int value; /* Current value in usecs */
242};
243
244/*
245 * Bus dma allocation structure used by
246 * e1000_dma_malloc and e1000_dma_free.
247 */
248struct em_dma_alloc {
249 bus_addr_t dma_paddr;
250 caddr_t dma_vaddr;
251 bus_dma_tag_t dma_tag;
252 bus_dmamap_t dma_map;
253 bus_dma_segment_t dma_seg;
254 int dma_nseg;
255};
256
257/* Our adapter structure */
258struct adapter {
259 struct ifnet *ifp;
260 struct e1000_hw hw;
261
262 /* FreeBSD operating-system-specific structures. */
263 struct e1000_osdep osdep;
264 struct device *dev;
265 struct resource *res_memory;
266 struct resource *flash_mem;
267 struct resource *msix_mem;
268 struct resource *res_ioport;
269 struct resource *res_interrupt;
270 void *int_handler_tag;
271 struct ifmedia media;
272 struct callout timer;
273 struct callout tx_fifo_timer;
274 int watchdog_timer;
275 int io_rid;
276 int msi;
277 int if_flags;
278 struct mtx mtx;
279 int em_insert_vlan_header;
280 struct task link_task;
281 struct task rxtx_task;
282 struct taskqueue *tq; /* private task queue */
283 /* Management and WOL features */
284 int wol;
285 int has_manage;
286
287 /* Info about the board itself */
288 uint32_t part_num;
289 uint8_t link_active;
290 uint16_t link_speed;
291 uint16_t link_duplex;
292 uint32_t smartspeed;
293 struct em_int_delay_info tx_int_delay;
294 struct em_int_delay_info tx_abs_int_delay;
295 struct em_int_delay_info rx_int_delay;
296 struct em_int_delay_info rx_abs_int_delay;
297
298 /*
299 * Transmit definitions
300 *
301 * We have an array of num_tx_desc descriptors (handled
302 * by the controller) paired with an array of tx_buffers
303 * (at tx_buffer_area).
304 * The index of the next available descriptor is next_avail_tx_desc.
305 * The number of remaining tx_desc is num_tx_desc_avail.
306 */
307 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
308 struct e1000_tx_desc *tx_desc_base;
309 uint32_t next_avail_tx_desc;
310 uint32_t next_tx_to_clean;
311 volatile uint16_t num_tx_desc_avail;
312 uint16_t num_tx_desc;
313 uint32_t txd_cmd;
314 struct em_buffer *tx_buffer_area;
315 bus_dma_tag_t txtag; /* dma tag for tx */
316 uint32_t tx_tso; /* last tx was tso */
317
318 /*
319 * Transmit function pointer:
320 * legacy or advanced (82575 and later)
321 */
322 int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp);
323
324 /*
325 * Receive definitions
326 *
327 * we have an array of num_rx_desc rx_desc (handled by the
328 * controller), and paired with an array of rx_buffers
329 * (at rx_buffer_area).
330 * The next pair to check on receive is at offset next_rx_desc_to_check
331 */
332 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
333 struct e1000_rx_desc *rx_desc_base;
334 uint32_t next_rx_desc_to_check;
335 uint32_t rx_buffer_len;
336 uint16_t num_rx_desc;
337 int rx_process_limit;
338 struct em_buffer *rx_buffer_area;
339 bus_dma_tag_t rxtag;
340 bus_dmamap_t rx_sparemap;
341
342 /*
343 * First/last mbuf pointers, for
344 * collecting multisegment RX packets.
345 */
346 struct mbuf *fmp;
347 struct mbuf *lmp;
348
349 /* Misc stats maintained by the driver */
350 unsigned long dropped_pkts;
351 unsigned long mbuf_alloc_failed;
352 unsigned long mbuf_cluster_failed;
353 unsigned long no_tx_desc_avail1;
354 unsigned long no_tx_desc_avail2;
355 unsigned long no_tx_map_avail;
356 unsigned long no_tx_dma_setup;
357 unsigned long watchdog_events;
358 unsigned long rx_overruns;
359
360 /* Used in for 82547 10Mb Half workaround */
361 #define EM_PBA_BYTES_SHIFT 0xA
362 #define EM_TX_HEAD_ADDR_SHIFT 7
363 #define EM_PBA_TX_MASK 0xFFFF0000
364 #define EM_FIFO_HDR 0x10
365
366 #define EM_82547_PKT_THRESH 0x3e0
367
368 uint32_t tx_fifo_size;
369 uint32_t tx_fifo_head;
370 uint32_t tx_fifo_head_addr;
371 uint64_t tx_fifo_reset_cnt;
372 uint64_t tx_fifo_wrk_cnt;
373 uint32_t tx_head_addr;
374
375 /* For 82544 PCIX Workaround */
376 boolean_t pcix_82544;
377 boolean_t in_detach;
378
379 struct e1000_hw_stats stats;
380};
381
382/* ******************************************************************************
383 * vendor_info_array
384 *
385 * This array contains the list of Subvendor/Subdevice IDs on which the driver
386 * should load.
387 *
388 * ******************************************************************************/
389typedef struct _em_vendor_info_t {
390 unsigned int vendor_id;
391 unsigned int device_id;
392 unsigned int subvendor_id;
393 unsigned int subdevice_id;
394 unsigned int index;
395} em_vendor_info_t;
396
397
398struct em_buffer {
399 int next_eop; /* Index of the desc to watch */
400 struct mbuf *m_head;
401 bus_dmamap_t map; /* bus_dma map for packet */
402};
403
404/* For 82544 PCIX Workaround */
405typedef struct _ADDRESS_LENGTH_PAIR
406{
407 uint64_t address;
408 uint32_t length;
409} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
410
411typedef struct _DESCRIPTOR_PAIR
412{
413 ADDRESS_LENGTH_PAIR descriptor[4];
414 uint32_t elements;
415} DESC_ARRAY, *PDESC_ARRAY;
416
417#define EM_LOCK_INIT(_sc, _name) \
418 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
419#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
420#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx)
421#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
422#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
423
424#endif /* _EM_H_DEFINED_ */
| 184
185#define MAX_NUM_MULTICAST_ADDRESSES 128
186#define PCI_ANY_ID (~0U)
187#define ETHER_ALIGN 2
188#define EM_TX_BUFFER_SIZE ((uint32_t) 1514)
189#define EM_FC_PAUSE_TIME 0x0680
190#define EM_EEPROM_APME 0x400;
191
192/*
193 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
194 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
195 * also optimize cache line size effect. H/W supports up to cache line size 128.
196 */
197#define EM_DBA_ALIGN 128
198
199#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
200
201/* PCI Config defines */
202#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
203#define EM_BAR_TYPE_MASK 0x00000001
204#define EM_BAR_TYPE_MMEM 0x00000000
205#define EM_BAR_TYPE_IO 0x00000001
206#define EM_BAR_TYPE_FLASH 0x0014
207#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
208#define EM_BAR_MEM_TYPE_MASK 0x00000006
209#define EM_BAR_MEM_TYPE_32BIT 0x00000000
210#define EM_BAR_MEM_TYPE_64BIT 0x00000004
211#define EM_MSIX_BAR 3 /* On 82575 */
212
213/* Defines for printing debug information */
214#define DEBUG_INIT 0
215#define DEBUG_IOCTL 0
216#define DEBUG_HW 0
217
218#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
219#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
220#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
221#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
222#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
223#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
224#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
225#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
226#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
227
228#define EM_MAX_SCATTER 64
229#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */
230#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
231#define ETH_ZLEN 60
232#define ETH_ADDR_LEN 6
233#define CSUM_OFFLOAD 7 /* Offload bits in csum flags */
234
235struct adapter;
236
237struct em_int_delay_info {
238 struct adapter *adapter; /* Back-pointer to the adapter struct */
239 int offset; /* Register offset to read/write */
240 int value; /* Current value in usecs */
241};
242
243/*
244 * Bus dma allocation structure used by
245 * e1000_dma_malloc and e1000_dma_free.
246 */
247struct em_dma_alloc {
248 bus_addr_t dma_paddr;
249 caddr_t dma_vaddr;
250 bus_dma_tag_t dma_tag;
251 bus_dmamap_t dma_map;
252 bus_dma_segment_t dma_seg;
253 int dma_nseg;
254};
255
256/* Our adapter structure */
257struct adapter {
258 struct ifnet *ifp;
259 struct e1000_hw hw;
260
261 /* FreeBSD operating-system-specific structures. */
262 struct e1000_osdep osdep;
263 struct device *dev;
264 struct resource *res_memory;
265 struct resource *flash_mem;
266 struct resource *msix_mem;
267 struct resource *res_ioport;
268 struct resource *res_interrupt;
269 void *int_handler_tag;
270 struct ifmedia media;
271 struct callout timer;
272 struct callout tx_fifo_timer;
273 int watchdog_timer;
274 int io_rid;
275 int msi;
276 int if_flags;
277 struct mtx mtx;
278 int em_insert_vlan_header;
279 struct task link_task;
280 struct task rxtx_task;
281 struct taskqueue *tq; /* private task queue */
282 /* Management and WOL features */
283 int wol;
284 int has_manage;
285
286 /* Info about the board itself */
287 uint32_t part_num;
288 uint8_t link_active;
289 uint16_t link_speed;
290 uint16_t link_duplex;
291 uint32_t smartspeed;
292 struct em_int_delay_info tx_int_delay;
293 struct em_int_delay_info tx_abs_int_delay;
294 struct em_int_delay_info rx_int_delay;
295 struct em_int_delay_info rx_abs_int_delay;
296
297 /*
298 * Transmit definitions
299 *
300 * We have an array of num_tx_desc descriptors (handled
301 * by the controller) paired with an array of tx_buffers
302 * (at tx_buffer_area).
303 * The index of the next available descriptor is next_avail_tx_desc.
304 * The number of remaining tx_desc is num_tx_desc_avail.
305 */
306 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
307 struct e1000_tx_desc *tx_desc_base;
308 uint32_t next_avail_tx_desc;
309 uint32_t next_tx_to_clean;
310 volatile uint16_t num_tx_desc_avail;
311 uint16_t num_tx_desc;
312 uint32_t txd_cmd;
313 struct em_buffer *tx_buffer_area;
314 bus_dma_tag_t txtag; /* dma tag for tx */
315 uint32_t tx_tso; /* last tx was tso */
316
317 /*
318 * Transmit function pointer:
319 * legacy or advanced (82575 and later)
320 */
321 int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp);
322
323 /*
324 * Receive definitions
325 *
326 * we have an array of num_rx_desc rx_desc (handled by the
327 * controller), and paired with an array of rx_buffers
328 * (at rx_buffer_area).
329 * The next pair to check on receive is at offset next_rx_desc_to_check
330 */
331 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
332 struct e1000_rx_desc *rx_desc_base;
333 uint32_t next_rx_desc_to_check;
334 uint32_t rx_buffer_len;
335 uint16_t num_rx_desc;
336 int rx_process_limit;
337 struct em_buffer *rx_buffer_area;
338 bus_dma_tag_t rxtag;
339 bus_dmamap_t rx_sparemap;
340
341 /*
342 * First/last mbuf pointers, for
343 * collecting multisegment RX packets.
344 */
345 struct mbuf *fmp;
346 struct mbuf *lmp;
347
348 /* Misc stats maintained by the driver */
349 unsigned long dropped_pkts;
350 unsigned long mbuf_alloc_failed;
351 unsigned long mbuf_cluster_failed;
352 unsigned long no_tx_desc_avail1;
353 unsigned long no_tx_desc_avail2;
354 unsigned long no_tx_map_avail;
355 unsigned long no_tx_dma_setup;
356 unsigned long watchdog_events;
357 unsigned long rx_overruns;
358
359 /* Used in for 82547 10Mb Half workaround */
360 #define EM_PBA_BYTES_SHIFT 0xA
361 #define EM_TX_HEAD_ADDR_SHIFT 7
362 #define EM_PBA_TX_MASK 0xFFFF0000
363 #define EM_FIFO_HDR 0x10
364
365 #define EM_82547_PKT_THRESH 0x3e0
366
367 uint32_t tx_fifo_size;
368 uint32_t tx_fifo_head;
369 uint32_t tx_fifo_head_addr;
370 uint64_t tx_fifo_reset_cnt;
371 uint64_t tx_fifo_wrk_cnt;
372 uint32_t tx_head_addr;
373
374 /* For 82544 PCIX Workaround */
375 boolean_t pcix_82544;
376 boolean_t in_detach;
377
378 struct e1000_hw_stats stats;
379};
380
381/* ******************************************************************************
382 * vendor_info_array
383 *
384 * This array contains the list of Subvendor/Subdevice IDs on which the driver
385 * should load.
386 *
387 * ******************************************************************************/
388typedef struct _em_vendor_info_t {
389 unsigned int vendor_id;
390 unsigned int device_id;
391 unsigned int subvendor_id;
392 unsigned int subdevice_id;
393 unsigned int index;
394} em_vendor_info_t;
395
396
397struct em_buffer {
398 int next_eop; /* Index of the desc to watch */
399 struct mbuf *m_head;
400 bus_dmamap_t map; /* bus_dma map for packet */
401};
402
403/* For 82544 PCIX Workaround */
404typedef struct _ADDRESS_LENGTH_PAIR
405{
406 uint64_t address;
407 uint32_t length;
408} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
409
410typedef struct _DESCRIPTOR_PAIR
411{
412 ADDRESS_LENGTH_PAIR descriptor[4];
413 uint32_t elements;
414} DESC_ARRAY, *PDESC_ARRAY;
415
416#define EM_LOCK_INIT(_sc, _name) \
417 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
418#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
419#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx)
420#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
421#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
422
423#endif /* _EM_H_DEFINED_ */
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