1/******************************************************************************
2
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35#include "e1000_api.h"
36
37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44/* Cable length tables */
45static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
51static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 124};
60#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
63
64/**
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
67 *
68 * Setups up the function pointers to no-op functions
69 **/
70void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71{
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
74
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101}
102
103/**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 **/
107s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
108{
109 DEBUGFUNC("e1000_null_set_page");
110 return E1000_SUCCESS;
111}
112
113/**
114 * e1000_null_read_reg - No-op function, return 0
115 * @hw: pointer to the HW structure
116 **/
117s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
118{
119 DEBUGFUNC("e1000_null_read_reg");
120 return E1000_SUCCESS;
121}
122
123/**
124 * e1000_null_phy_generic - No-op function, return void
125 * @hw: pointer to the HW structure
126 **/
127void e1000_null_phy_generic(struct e1000_hw *hw)
128{
129 DEBUGFUNC("e1000_null_phy_generic");
130 return;
131}
132
133/**
134 * e1000_null_lplu_state - No-op function, return 0
135 * @hw: pointer to the HW structure
136 **/
137s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
138{
139 DEBUGFUNC("e1000_null_lplu_state");
140 return E1000_SUCCESS;
141}
142
143/**
144 * e1000_null_write_reg - No-op function, return 0
145 * @hw: pointer to the HW structure
146 **/
147s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
148{
149 DEBUGFUNC("e1000_null_write_reg");
150 return E1000_SUCCESS;
151}
152
153/**
154 * e1000_check_reset_block_generic - Check if PHY reset is blocked
155 * @hw: pointer to the HW structure
156 *
157 * Read the PHY management control register and check whether a PHY reset
158 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
159 * return E1000_BLK_PHY_RESET (12).
160 **/
161s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
162{
163 u32 manc;
164
165 DEBUGFUNC("e1000_check_reset_block");
166
167 manc = E1000_READ_REG(hw, E1000_MANC);
168
169 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
170 E1000_BLK_PHY_RESET : E1000_SUCCESS;
171}
172
173/**
174 * e1000_get_phy_id - Retrieve the PHY ID and revision
175 * @hw: pointer to the HW structure
176 *
177 * Reads the PHY registers and stores the PHY ID and possibly the PHY
178 * revision in the hardware structure.
179 **/
180s32 e1000_get_phy_id(struct e1000_hw *hw)
181{
182 struct e1000_phy_info *phy = &hw->phy;
183 s32 ret_val = E1000_SUCCESS;
184 u16 phy_id;
185 u16 retry_count = 0;
186
187 DEBUGFUNC("e1000_get_phy_id");
188
189 if (!(phy->ops.read_reg))
190 goto out;
191
192 while (retry_count < 2) {
193 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
194 if (ret_val)
195 goto out;
196
197 phy->id = (u32)(phy_id << 16);
198 usec_delay(20);
199 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
200 if (ret_val)
201 goto out;
202
203 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
204 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
205
206 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
207 goto out;
208
209 retry_count++;
210 }
211out:
212 return ret_val;
213}
214
215/**
216 * e1000_phy_reset_dsp_generic - Reset PHY DSP
217 * @hw: pointer to the HW structure
218 *
219 * Reset the digital signal processor.
220 **/
221s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
222{
223 s32 ret_val = E1000_SUCCESS;
224
225 DEBUGFUNC("e1000_phy_reset_dsp_generic");
226
227 if (!(hw->phy.ops.write_reg))
228 goto out;
229
230 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
231 if (ret_val)
232 goto out;
233
234 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
235
236out:
237 return ret_val;
238}
239
240/**
241 * e1000_read_phy_reg_mdic - Read MDI control register
242 * @hw: pointer to the HW structure
243 * @offset: register offset to be read
244 * @data: pointer to the read data
245 *
246 * Reads the MDI control register in the PHY at offset and stores the
247 * information read to data.
248 **/
249s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
250{
251 struct e1000_phy_info *phy = &hw->phy;
252 u32 i, mdic = 0;
253 s32 ret_val = E1000_SUCCESS;
254
255 DEBUGFUNC("e1000_read_phy_reg_mdic");
256
257 if (offset > MAX_PHY_REG_ADDRESS) {
258 DEBUGOUT1("PHY Address %d is out of range\n", offset);
259 return -E1000_ERR_PARAM;
260 }
261
262 /*
263 * Set up Op-code, Phy Address, and register offset in the MDI
264 * Control register. The MAC will take care of interfacing with the
265 * PHY to retrieve the desired data.
266 */
267 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
268 (phy->addr << E1000_MDIC_PHY_SHIFT) |
269 (E1000_MDIC_OP_READ));
270
271 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
272
273 /*
274 * Poll the ready bit to see if the MDI read completed
275 * Increasing the time out as testing showed failures with
276 * the lower time out
277 */
278 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
279 usec_delay(50);
280 mdic = E1000_READ_REG(hw, E1000_MDIC);
281 if (mdic & E1000_MDIC_READY)
282 break;
283 }
284 if (!(mdic & E1000_MDIC_READY)) {
285 DEBUGOUT("MDI Read did not complete\n");
286 ret_val = -E1000_ERR_PHY;
287 goto out;
288 }
289 if (mdic & E1000_MDIC_ERROR) {
290 DEBUGOUT("MDI Error\n");
291 ret_val = -E1000_ERR_PHY;
292 goto out;
293 }
294 *data = (u16) mdic;
295
296 /*
297 * Allow some time after each MDIC transaction to avoid
298 * reading duplicate data in the next MDIC transaction.
299 */
300 if (hw->mac.type == e1000_pch2lan)
301 usec_delay(100);
302
303out:
304 return ret_val;
305}
306
307/**
308 * e1000_write_phy_reg_mdic - Write MDI control register
309 * @hw: pointer to the HW structure
310 * @offset: register offset to write to
311 * @data: data to write to register at offset
312 *
313 * Writes data to MDI control register in the PHY at offset.
314 **/
315s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
316{
317 struct e1000_phy_info *phy = &hw->phy;
318 u32 i, mdic = 0;
319 s32 ret_val = E1000_SUCCESS;
320
321 DEBUGFUNC("e1000_write_phy_reg_mdic");
322
323 if (offset > MAX_PHY_REG_ADDRESS) {
324 DEBUGOUT1("PHY Address %d is out of range\n", offset);
325 return -E1000_ERR_PARAM;
326 }
327
328 /*
329 * Set up Op-code, Phy Address, and register offset in the MDI
330 * Control register. The MAC will take care of interfacing with the
331 * PHY to retrieve the desired data.
332 */
333 mdic = (((u32)data) |
334 (offset << E1000_MDIC_REG_SHIFT) |
335 (phy->addr << E1000_MDIC_PHY_SHIFT) |
336 (E1000_MDIC_OP_WRITE));
337
338 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
339
340 /*
341 * Poll the ready bit to see if the MDI read completed
342 * Increasing the time out as testing showed failures with
343 * the lower time out
344 */
345 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
346 usec_delay(50);
347 mdic = E1000_READ_REG(hw, E1000_MDIC);
348 if (mdic & E1000_MDIC_READY)
349 break;
350 }
351 if (!(mdic & E1000_MDIC_READY)) {
352 DEBUGOUT("MDI Write did not complete\n");
353 ret_val = -E1000_ERR_PHY;
354 goto out;
355 }
356 if (mdic & E1000_MDIC_ERROR) {
357 DEBUGOUT("MDI Error\n");
358 ret_val = -E1000_ERR_PHY;
359 goto out;
360 }
361
362 /*
363 * Allow some time after each MDIC transaction to avoid
364 * reading duplicate data in the next MDIC transaction.
365 */
366 if (hw->mac.type == e1000_pch2lan)
367 usec_delay(100);
368
369out:
370 return ret_val;
371}
372
373/**
374 * e1000_read_phy_reg_i2c - Read PHY register using i2c
375 * @hw: pointer to the HW structure
376 * @offset: register offset to be read
377 * @data: pointer to the read data
378 *
379 * Reads the PHY register at offset using the i2c interface and stores the
380 * retrieved information in data.
381 **/
382s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
383{
384 struct e1000_phy_info *phy = &hw->phy;
385 u32 i, i2ccmd = 0;
386
387 DEBUGFUNC("e1000_read_phy_reg_i2c");
388
389 /*
390 * Set up Op-code, Phy Address, and register address in the I2CCMD
391 * register. The MAC will take care of interfacing with the
392 * PHY to retrieve the desired data.
393 */
394 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
395 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
396 (E1000_I2CCMD_OPCODE_READ));
397
398 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
399
400 /* Poll the ready bit to see if the I2C read completed */
401 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
402 usec_delay(50);
403 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
404 if (i2ccmd & E1000_I2CCMD_READY)
405 break;
406 }
407 if (!(i2ccmd & E1000_I2CCMD_READY)) {
408 DEBUGOUT("I2CCMD Read did not complete\n");
409 return -E1000_ERR_PHY;
410 }
411 if (i2ccmd & E1000_I2CCMD_ERROR) {
412 DEBUGOUT("I2CCMD Error bit set\n");
413 return -E1000_ERR_PHY;
414 }
415
416 /* Need to byte-swap the 16-bit value. */
417 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
418
419 return E1000_SUCCESS;
420}
421
422/**
423 * e1000_write_phy_reg_i2c - Write PHY register using i2c
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
427 *
428 * Writes the data to PHY register at the offset using the i2c interface.
429 **/
430s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
431{
432 struct e1000_phy_info *phy = &hw->phy;
433 u32 i, i2ccmd = 0;
434 u16 phy_data_swapped;
435
436 DEBUGFUNC("e1000_write_phy_reg_i2c");
437
438 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
439 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
440 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
441 hw->phy.addr);
442 return -E1000_ERR_CONFIG;
443 }
444
445 /* Swap the data bytes for the I2C interface */
446 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
447
448 /*
449 * Set up Op-code, Phy Address, and register address in the I2CCMD
450 * register. The MAC will take care of interfacing with the
451 * PHY to retrieve the desired data.
452 */
453 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
454 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
455 E1000_I2CCMD_OPCODE_WRITE |
456 phy_data_swapped);
457
458 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
459
460 /* Poll the ready bit to see if the I2C read completed */
461 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
462 usec_delay(50);
463 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
464 if (i2ccmd & E1000_I2CCMD_READY)
465 break;
466 }
467 if (!(i2ccmd & E1000_I2CCMD_READY)) {
468 DEBUGOUT("I2CCMD Write did not complete\n");
469 return -E1000_ERR_PHY;
470 }
471 if (i2ccmd & E1000_I2CCMD_ERROR) {
472 DEBUGOUT("I2CCMD Error bit set\n");
473 return -E1000_ERR_PHY;
474 }
475
476 return E1000_SUCCESS;
477}
478
479/**
480 * e1000_read_sfp_data_byte - Reads SFP module data.
481 * @hw: pointer to the HW structure
482 * @offset: byte location offset to be read
483 * @data: read data buffer pointer
484 *
485 * Reads one byte from SFP module data stored
486 * in SFP resided EEPROM memory or SFP diagnostic area.
487 * Function should be called with
488 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
489 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
490 * access
491 **/
492s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
493{
494 u32 i = 0;
495 u32 i2ccmd = 0;
496 u32 data_local = 0;
497
498 DEBUGFUNC("e1000_read_sfp_data_byte");
499
500 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
501 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
502 return -E1000_ERR_PHY;
503 }
504
505 /*
506 * Set up Op-code, EEPROM Address,in the I2CCMD
507 * register. The MAC will take care of interfacing with the
508 * EEPROM to retrieve the desired data.
509 */
510 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
511 E1000_I2CCMD_OPCODE_READ);
512
513 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
514
515 /* Poll the ready bit to see if the I2C read completed */
516 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
517 usec_delay(50);
518 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
519 if (data_local & E1000_I2CCMD_READY)
520 break;
521 }
522 if (!(data_local & E1000_I2CCMD_READY)) {
523 DEBUGOUT("I2CCMD Read did not complete\n");
524 return -E1000_ERR_PHY;
525 }
526 if (data_local & E1000_I2CCMD_ERROR) {
527 DEBUGOUT("I2CCMD Error bit set\n");
528 return -E1000_ERR_PHY;
529 }
530 *data = (u8) data_local & 0xFF;
531
532 return E1000_SUCCESS;
533}
534
535/**
536 * e1000_write_sfp_data_byte - Writes SFP module data.
537 * @hw: pointer to the HW structure
538 * @offset: byte location offset to write to
539 * @data: data to write
540 *
541 * Writes one byte to SFP module data stored
542 * in SFP resided EEPROM memory or SFP diagnostic area.
543 * Function should be called with
544 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
545 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
546 * access
547 **/
548s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
549{
550 u32 i = 0;
551 u32 i2ccmd = 0;
552 u32 data_local = 0;
553
554 DEBUGFUNC("e1000_write_sfp_data_byte");
555
556 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
557 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
558 return -E1000_ERR_PHY;
559 }
560 /*
561 * The programming interface is 16 bits wide
562 * so we need to read the whole word first
563 * then update appropriate byte lane and write
564 * the updated word back.
565 */
566 /*
567 * Set up Op-code, EEPROM Address,in the I2CCMD
568 * register. The MAC will take care of interfacing
569 * with an EEPROM to write the data given.
570 */
571 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
572 E1000_I2CCMD_OPCODE_READ);
573 /* Set a command to read single word */
574 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
575 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
576 usec_delay(50);
577 /*
578 * Poll the ready bit to see if lastly
579 * launched I2C operation completed
580 */
581 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
582 if (i2ccmd & E1000_I2CCMD_READY) {
583 /* Check if this is READ or WRITE phase */
584 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
585 E1000_I2CCMD_OPCODE_READ) {
586 /*
587 * Write the selected byte
588 * lane and update whole word
589 */
590 data_local = i2ccmd & 0xFF00;
591 data_local |= data;
592 i2ccmd = ((offset <<
593 E1000_I2CCMD_REG_ADDR_SHIFT) |
594 E1000_I2CCMD_OPCODE_WRITE | data_local);
595 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
596 } else {
597 break;
598 }
599 }
600 }
601 if (!(i2ccmd & E1000_I2CCMD_READY)) {
602 DEBUGOUT("I2CCMD Write did not complete\n");
603 return -E1000_ERR_PHY;
604 }
605 if (i2ccmd & E1000_I2CCMD_ERROR) {
606 DEBUGOUT("I2CCMD Error bit set\n");
607 return -E1000_ERR_PHY;
608 }
609 return E1000_SUCCESS;
610}
611
612/**
613 * e1000_read_phy_reg_m88 - Read m88 PHY register
614 * @hw: pointer to the HW structure
615 * @offset: register offset to be read
616 * @data: pointer to the read data
617 *
618 * Acquires semaphore, if necessary, then reads the PHY register at offset
619 * and storing the retrieved information in data. Release any acquired
620 * semaphores before exiting.
621 **/
622s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
623{
624 s32 ret_val = E1000_SUCCESS;
625
626 DEBUGFUNC("e1000_read_phy_reg_m88");
627
628 if (!(hw->phy.ops.acquire))
629 goto out;
630
631 ret_val = hw->phy.ops.acquire(hw);
632 if (ret_val)
633 goto out;
634
635 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
636 data);
637
638 hw->phy.ops.release(hw);
639
640out:
641 return ret_val;
642}
643
644/**
645 * e1000_write_phy_reg_m88 - Write m88 PHY register
646 * @hw: pointer to the HW structure
647 * @offset: register offset to write to
648 * @data: data to write at register offset
649 *
650 * Acquires semaphore, if necessary, then writes the data to PHY register
651 * at the offset. Release any acquired semaphores before exiting.
652 **/
653s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
654{
655 s32 ret_val = E1000_SUCCESS;
656
657 DEBUGFUNC("e1000_write_phy_reg_m88");
658
659 if (!(hw->phy.ops.acquire))
660 goto out;
661
662 ret_val = hw->phy.ops.acquire(hw);
663 if (ret_val)
664 goto out;
665
666 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
667 data);
668
669 hw->phy.ops.release(hw);
670
671out:
672 return ret_val;
673}
674
675/**
676 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
677 * @hw: pointer to the HW structure
678 * @page: page to set (shifted left when necessary)
679 *
680 * Sets PHY page required for PHY register access. Assumes semaphore is
681 * already acquired. Note, this function sets phy.addr to 1 so the caller
682 * must set it appropriately (if necessary) after this function returns.
683 **/
684s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
685{
686 DEBUGFUNC("e1000_set_page_igp");
687
688 DEBUGOUT1("Setting page 0x%x\n", page);
689
690 hw->phy.addr = 1;
691
692 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
693}
694
695/**
696 * __e1000_read_phy_reg_igp - Read igp PHY register
697 * @hw: pointer to the HW structure
698 * @offset: register offset to be read
699 * @data: pointer to the read data
700 * @locked: semaphore has already been acquired or not
701 *
702 * Acquires semaphore, if necessary, then reads the PHY register at offset
703 * and stores the retrieved information in data. Release any acquired
704 * semaphores before exiting.
705 **/
706static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
707 bool locked)
708{
709 s32 ret_val = E1000_SUCCESS;
710
711 DEBUGFUNC("__e1000_read_phy_reg_igp");
712
713 if (!locked) {
714 if (!(hw->phy.ops.acquire))
715 goto out;
716
717 ret_val = hw->phy.ops.acquire(hw);
718 if (ret_val)
719 goto out;
720 }
721
722 if (offset > MAX_PHY_MULTI_PAGE_REG) {
723 ret_val = e1000_write_phy_reg_mdic(hw,
724 IGP01E1000_PHY_PAGE_SELECT,
725 (u16)offset);
726 if (ret_val)
727 goto release;
728 }
729
730 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
731 data);
732
733release:
734 if (!locked)
735 hw->phy.ops.release(hw);
736out:
737 return ret_val;
738}
739
740/**
741 * e1000_read_phy_reg_igp - Read igp PHY register
742 * @hw: pointer to the HW structure
743 * @offset: register offset to be read
744 * @data: pointer to the read data
745 *
746 * Acquires semaphore then reads the PHY register at offset and stores the
747 * retrieved information in data.
748 * Release the acquired semaphore before exiting.
749 **/
750s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
751{
752 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
753}
754
755/**
756 * e1000_read_phy_reg_igp_locked - Read igp PHY register
757 * @hw: pointer to the HW structure
758 * @offset: register offset to be read
759 * @data: pointer to the read data
760 *
761 * Reads the PHY register at offset and stores the retrieved information
762 * in data. Assumes semaphore already acquired.
763 **/
764s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
765{
766 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
767}
768
769/**
770 * e1000_write_phy_reg_igp - Write igp PHY register
771 * @hw: pointer to the HW structure
772 * @offset: register offset to write to
773 * @data: data to write at register offset
774 * @locked: semaphore has already been acquired or not
775 *
776 * Acquires semaphore, if necessary, then writes the data to PHY register
777 * at the offset. Release any acquired semaphores before exiting.
778 **/
779static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
780 bool locked)
781{
782 s32 ret_val = E1000_SUCCESS;
783
784 DEBUGFUNC("e1000_write_phy_reg_igp");
785
786 if (!locked) {
787 if (!(hw->phy.ops.acquire))
788 goto out;
789
790 ret_val = hw->phy.ops.acquire(hw);
791 if (ret_val)
792 goto out;
793 }
794
795 if (offset > MAX_PHY_MULTI_PAGE_REG) {
796 ret_val = e1000_write_phy_reg_mdic(hw,
797 IGP01E1000_PHY_PAGE_SELECT,
798 (u16)offset);
799 if (ret_val)
800 goto release;
801 }
802
803 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
804 data);
805
806release:
807 if (!locked)
808 hw->phy.ops.release(hw);
809
810out:
811 return ret_val;
812}
813
814/**
815 * e1000_write_phy_reg_igp - Write igp PHY register
816 * @hw: pointer to the HW structure
817 * @offset: register offset to write to
818 * @data: data to write at register offset
819 *
820 * Acquires semaphore then writes the data to PHY register
821 * at the offset. Release any acquired semaphores before exiting.
822 **/
823s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
824{
825 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
826}
827
828/**
829 * e1000_write_phy_reg_igp_locked - Write igp PHY register
830 * @hw: pointer to the HW structure
831 * @offset: register offset to write to
832 * @data: data to write at register offset
833 *
834 * Writes the data to PHY register at the offset.
835 * Assumes semaphore already acquired.
836 **/
837s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
838{
839 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
840}
841
842/**
843 * __e1000_read_kmrn_reg - Read kumeran register
844 * @hw: pointer to the HW structure
845 * @offset: register offset to be read
846 * @data: pointer to the read data
847 * @locked: semaphore has already been acquired or not
848 *
849 * Acquires semaphore, if necessary. Then reads the PHY register at offset
850 * using the kumeran interface. The information retrieved is stored in data.
851 * Release any acquired semaphores before exiting.
852 **/
853static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
854 bool locked)
855{
856 u32 kmrnctrlsta;
857 s32 ret_val = E1000_SUCCESS;
858
859 DEBUGFUNC("__e1000_read_kmrn_reg");
860
861 if (!locked) {
862 if (!(hw->phy.ops.acquire))
863 goto out;
864
865 ret_val = hw->phy.ops.acquire(hw);
866 if (ret_val)
867 goto out;
868 }
869
870 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
871 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
872 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
873 E1000_WRITE_FLUSH(hw);
874
875 usec_delay(2);
876
877 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
878 *data = (u16)kmrnctrlsta;
879
880 if (!locked)
881 hw->phy.ops.release(hw);
882
883out:
884 return ret_val;
885}
886
887/**
888 * e1000_read_kmrn_reg_generic - Read kumeran register
889 * @hw: pointer to the HW structure
890 * @offset: register offset to be read
891 * @data: pointer to the read data
892 *
893 * Acquires semaphore then reads the PHY register at offset using the
894 * kumeran interface. The information retrieved is stored in data.
895 * Release the acquired semaphore before exiting.
896 **/
897s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
898{
899 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
900}
901
902/**
903 * e1000_read_kmrn_reg_locked - Read kumeran register
904 * @hw: pointer to the HW structure
905 * @offset: register offset to be read
906 * @data: pointer to the read data
907 *
908 * Reads the PHY register at offset using the kumeran interface. The
909 * information retrieved is stored in data.
910 * Assumes semaphore already acquired.
911 **/
912s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
913{
914 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
915}
916
917/**
918 * __e1000_write_kmrn_reg - Write kumeran register
919 * @hw: pointer to the HW structure
920 * @offset: register offset to write to
921 * @data: data to write at register offset
922 * @locked: semaphore has already been acquired or not
923 *
924 * Acquires semaphore, if necessary. Then write the data to PHY register
925 * at the offset using the kumeran interface. Release any acquired semaphores
926 * before exiting.
927 **/
928static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
929 bool locked)
930{
931 u32 kmrnctrlsta;
932 s32 ret_val = E1000_SUCCESS;
933
934 DEBUGFUNC("e1000_write_kmrn_reg_generic");
935
936 if (!locked) {
937 if (!(hw->phy.ops.acquire))
938 goto out;
939
940 ret_val = hw->phy.ops.acquire(hw);
941 if (ret_val)
942 goto out;
943 }
944
945 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
946 E1000_KMRNCTRLSTA_OFFSET) | data;
947 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
948 E1000_WRITE_FLUSH(hw);
949
950 usec_delay(2);
951
952 if (!locked)
953 hw->phy.ops.release(hw);
954
955out:
956 return ret_val;
957}
958
959/**
960 * e1000_write_kmrn_reg_generic - Write kumeran register
961 * @hw: pointer to the HW structure
962 * @offset: register offset to write to
963 * @data: data to write at register offset
964 *
965 * Acquires semaphore then writes the data to the PHY register at the offset
966 * using the kumeran interface. Release the acquired semaphore before exiting.
967 **/
968s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
969{
970 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
971}
972
973/**
974 * e1000_write_kmrn_reg_locked - Write kumeran register
975 * @hw: pointer to the HW structure
976 * @offset: register offset to write to
977 * @data: data to write at register offset
978 *
979 * Write the data to PHY register at the offset using the kumeran interface.
980 * Assumes semaphore already acquired.
981 **/
982s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
983{
984 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
985}
986
987/**
988 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
989 * @hw: pointer to the HW structure
990 *
991 * Sets up Carrier-sense on Transmit and downshift values.
992 **/
993s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
994{
995 s32 ret_val;
996 u16 phy_data;
997
998 DEBUGFUNC("e1000_copper_link_setup_82577");
999
1000 if (hw->phy.type == e1000_phy_82580) {
1001 ret_val = hw->phy.ops.reset(hw);
1002 if (ret_val) {
1003 DEBUGOUT("Error resetting the PHY.\n");
1004 goto out;
1005 }
1006 }
1007
1008 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1009 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1010 if (ret_val)
1011 goto out;
1012
1013 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1014
1015 /* Enable downshift */
1016 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1017
1018 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1019 if (ret_val)
1020 goto out;
1021
1022 /* Resolve Master/Slave mode */
1023 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1024 if (ret_val)
1025 goto out;
1026
1027 /* load defaults for future use */
1028 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1029 ((phy_data & CR_1000T_MS_VALUE) ?
1030 e1000_ms_force_master :
1031 e1000_ms_force_slave) : e1000_ms_auto;
1032
1033 switch (hw->phy.ms_type) {
1034 case e1000_ms_force_master:
1035 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1036 break;
1037 case e1000_ms_force_slave:
1038 phy_data |= CR_1000T_MS_ENABLE;
1039 phy_data &= ~(CR_1000T_MS_VALUE);
1040 break;
1041 case e1000_ms_auto:
1042 phy_data &= ~CR_1000T_MS_ENABLE;
1043 default:
1044 break;
1045 }
1046
1047 ret_val = hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1048 if (ret_val)
1049 goto out;
1050
1051out:
1052 return ret_val;
1053}
1054
1055/**
1056 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1057 * @hw: pointer to the HW structure
1058 *
1059 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1060 * and downshift values are set also.
1061 **/
1062s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1063{
1064 struct e1000_phy_info *phy = &hw->phy;
1065 s32 ret_val;
1066 u16 phy_data;
1067
1068 DEBUGFUNC("e1000_copper_link_setup_m88");
1069
1070
1071 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1072 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1073 if (ret_val)
1074 goto out;
1075
1076 /* For BM PHY this bit is downshift enable */
1077 if (phy->type != e1000_phy_bm)
1078 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1079
1080 /*
1081 * Options:
1082 * MDI/MDI-X = 0 (default)
1083 * 0 - Auto for all speeds
1084 * 1 - MDI mode
1085 * 2 - MDI-X mode
1086 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1087 */
1088 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1089
1090 switch (phy->mdix) {
1091 case 1:
1092 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1093 break;
1094 case 2:
1095 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1096 break;
1097 case 3:
1098 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1099 break;
1100 case 0:
1101 default:
1102 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1103 break;
1104 }
1105
1106 /*
1107 * Options:
1108 * disable_polarity_correction = 0 (default)
1109 * Automatic Correction for Reversed Cable Polarity
1110 * 0 - Disabled
1111 * 1 - Enabled
1112 */
1113 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1114 if (phy->disable_polarity_correction == 1)
1115 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1116
1117 /* Enable downshift on BM (disabled by default) */
1118 if (phy->type == e1000_phy_bm)
1119 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1120
1121 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1122 if (ret_val)
1123 goto out;
1124
1125 if ((phy->type == e1000_phy_m88) &&
1126 (phy->revision < E1000_REVISION_4) &&
1127 (phy->id != BME1000_E_PHY_ID_R2)) {
1128 /*
1129 * Force TX_CLK in the Extended PHY Specific Control Register
1130 * to 25MHz clock.
1131 */
1132 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1133 &phy_data);
1134 if (ret_val)
1135 goto out;
1136
1137 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1138
1139 if ((phy->revision == E1000_REVISION_2) &&
1140 (phy->id == M88E1111_I_PHY_ID)) {
1141 /* 82573L PHY - set the downshift counter to 5x. */
1142 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1143 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1144 } else {
1145 /* Configure Master and Slave downshift values */
1146 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1147 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1148 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1149 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1150 }
1151 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152 phy_data);
1153 if (ret_val)
1154 goto out;
1155 }
1156
1157 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1158 /* Set PHY page 0, register 29 to 0x0003 */
1159 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1160 if (ret_val)
1161 goto out;
1162
1163 /* Set PHY page 0, register 30 to 0x0000 */
1164 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1165 if (ret_val)
1166 goto out;
1167 }
1168
1169 /* Commit the changes. */
1170 ret_val = phy->ops.commit(hw);
1171 if (ret_val) {
1172 DEBUGOUT("Error committing the PHY changes\n");
1173 goto out;
1174 }
1175
1176 if (phy->type == e1000_phy_82578) {
1177 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1178 &phy_data);
1179 if (ret_val)
1180 goto out;
1181
1182 /* 82578 PHY - set the downshift count to 1x. */
1183 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1184 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1185 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1186 phy_data);
1187 if (ret_val)
1188 goto out;
1189 }
1190
1191out:
1192 return ret_val;
1193}
1194
1195/**
1196 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1197 * @hw: pointer to the HW structure
1198 *
1199 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1200 * Also enables and sets the downshift parameters.
1201 **/
1202s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1203{
1204 struct e1000_phy_info *phy = &hw->phy;
1205 s32 ret_val;
1206 u16 phy_data;
1207
1208 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1209
1210
1211 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1212 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1213 if (ret_val)
1214 goto out;
1215
1216 /*
1217 * Options:
1218 * MDI/MDI-X = 0 (default)
1219 * 0 - Auto for all speeds
1220 * 1 - MDI mode
1221 * 2 - MDI-X mode
1222 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1223 */
1224 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1225
1226 switch (phy->mdix) {
1227 case 1:
1228 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1229 break;
1230 case 2:
1231 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1232 break;
1233 case 3:
1234 /* M88E1112 does not support this mode) */
1235 if (phy->id != M88E1112_E_PHY_ID) {
1236 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1237 break;
1238 }
1239 case 0:
1240 default:
1241 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1242 break;
1243 }
1244
1245 /*
1246 * Options:
1247 * disable_polarity_correction = 0 (default)
1248 * Automatic Correction for Reversed Cable Polarity
1249 * 0 - Disabled
1250 * 1 - Enabled
1251 */
1252 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1253 if (phy->disable_polarity_correction == 1)
1254 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1255
1256 /* Enable downshift and setting it to X6 */
1257 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1258 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1259 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1260
1261 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1262 if (ret_val)
1263 goto out;
1264
1265 /* Commit the changes. */
1266 ret_val = phy->ops.commit(hw);
1267 if (ret_val) {
1268 DEBUGOUT("Error committing the PHY changes\n");
1269 goto out;
1270 }
1271
1272out:
1273 return ret_val;
1274}
1275
1276/**
1277 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1278 * @hw: pointer to the HW structure
1279 *
1280 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1281 * igp PHY's.
1282 **/
1283s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1284{
1285 struct e1000_phy_info *phy = &hw->phy;
1286 s32 ret_val;
1287 u16 data;
1288
1289 DEBUGFUNC("e1000_copper_link_setup_igp");
1290
1291
1292 ret_val = hw->phy.ops.reset(hw);
1293 if (ret_val) {
1294 DEBUGOUT("Error resetting the PHY.\n");
1295 goto out;
1296 }
1297
1298 /*
1299 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1300 * timeout issues when LFS is enabled.
1301 */
1302 msec_delay(100);
1303
1304 /*
1305 * The NVM settings will configure LPLU in D3 for
1306 * non-IGP1 PHYs.
1307 */
1308 if (phy->type == e1000_phy_igp) {
1309 /* disable lplu d3 during driver init */
1310 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1311 if (ret_val) {
1312 DEBUGOUT("Error Disabling LPLU D3\n");
1313 goto out;
1314 }
1315 }
1316
1317 /* disable lplu d0 during driver init */
1318 if (hw->phy.ops.set_d0_lplu_state) {
1319 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1320 if (ret_val) {
1321 DEBUGOUT("Error Disabling LPLU D0\n");
1322 goto out;
1323 }
1324 }
1325 /* Configure mdi-mdix settings */
1326 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1327 if (ret_val)
1328 goto out;
1329
1330 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1331
1332 switch (phy->mdix) {
1333 case 1:
1334 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1335 break;
1336 case 2:
1337 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1338 break;
1339 case 0:
1340 default:
1341 data |= IGP01E1000_PSCR_AUTO_MDIX;
1342 break;
1343 }
1344 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1345 if (ret_val)
1346 goto out;
1347
1348 /* set auto-master slave resolution settings */
1349 if (hw->mac.autoneg) {
1350 /*
1351 * when autonegotiation advertisement is only 1000Mbps then we
1352 * should disable SmartSpeed and enable Auto MasterSlave
1353 * resolution as hardware default.
1354 */
1355 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1356 /* Disable SmartSpeed */
1357 ret_val = phy->ops.read_reg(hw,
1358 IGP01E1000_PHY_PORT_CONFIG,
1359 &data);
1360 if (ret_val)
1361 goto out;
1362
1363 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1364 ret_val = phy->ops.write_reg(hw,
1365 IGP01E1000_PHY_PORT_CONFIG,
1366 data);
1367 if (ret_val)
1368 goto out;
1369
1370 /* Set auto Master/Slave resolution process */
1371 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1372 if (ret_val)
1373 goto out;
1374
1375 data &= ~CR_1000T_MS_ENABLE;
1376 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1377 if (ret_val)
1378 goto out;
1379 }
1380
1381 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1382 if (ret_val)
1383 goto out;
1384
1385 /* load defaults for future use */
1386 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1387 ((data & CR_1000T_MS_VALUE) ?
1388 e1000_ms_force_master :
1389 e1000_ms_force_slave) :
1390 e1000_ms_auto;
1391
1392 switch (phy->ms_type) {
1393 case e1000_ms_force_master:
1394 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1395 break;
1396 case e1000_ms_force_slave:
1397 data |= CR_1000T_MS_ENABLE;
1398 data &= ~(CR_1000T_MS_VALUE);
1399 break;
1400 case e1000_ms_auto:
1401 data &= ~CR_1000T_MS_ENABLE;
1402 default:
1403 break;
1404 }
1405 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1406 if (ret_val)
1407 goto out;
1408 }
1409
1410out:
1411 return ret_val;
1412}
1413
1414/**
1415 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1416 * @hw: pointer to the HW structure
1417 *
1418 * Performs initial bounds checking on autoneg advertisement parameter, then
1419 * configure to advertise the full capability. Setup the PHY to autoneg
1420 * and restart the negotiation process between the link partner. If
1421 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1422 **/
1423s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1424{
1425 struct e1000_phy_info *phy = &hw->phy;
1426 s32 ret_val;
1427 u16 phy_ctrl;
1428
1429 DEBUGFUNC("e1000_copper_link_autoneg");
1430
1431 /*
1432 * Perform some bounds checking on the autoneg advertisement
1433 * parameter.
1434 */
1435 phy->autoneg_advertised &= phy->autoneg_mask;
1436
1437 /*
1438 * If autoneg_advertised is zero, we assume it was not defaulted
1439 * by the calling code so we set to advertise full capability.
1440 */
1441 if (phy->autoneg_advertised == 0)
1442 phy->autoneg_advertised = phy->autoneg_mask;
1443
1444 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1445 ret_val = e1000_phy_setup_autoneg(hw);
1446 if (ret_val) {
1447 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1448 goto out;
1449 }
1450 DEBUGOUT("Restarting Auto-Neg\n");
1451
1452 /*
1453 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1454 * the Auto Neg Restart bit in the PHY control register.
1455 */
1456 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1457 if (ret_val)
1458 goto out;
1459
1460 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1461 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1462 if (ret_val)
1463 goto out;
1464
1465 /*
1466 * Does the user want to wait for Auto-Neg to complete here, or
1467 * check at a later time (for example, callback routine).
1468 */
1469 if (phy->autoneg_wait_to_complete) {
1470 ret_val = hw->mac.ops.wait_autoneg(hw);
1471 if (ret_val) {
1472 DEBUGOUT("Error while waiting for autoneg to complete\n");
1473 goto out;
1474 }
1475 }
1476
1477 hw->mac.get_link_status = TRUE;
1478
1479out:
1480 return ret_val;
1481}
1482
1483/**
1484 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1485 * @hw: pointer to the HW structure
1486 *
1487 * Reads the MII auto-neg advertisement register and/or the 1000T control
1488 * register and if the PHY is already setup for auto-negotiation, then
1489 * return successful. Otherwise, setup advertisement and flow control to
1490 * the appropriate values for the wanted auto-negotiation.
1491 **/
1492s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1493{
1494 struct e1000_phy_info *phy = &hw->phy;
1495 s32 ret_val;
1496 u16 mii_autoneg_adv_reg;
1497 u16 mii_1000t_ctrl_reg = 0;
1498
1499 DEBUGFUNC("e1000_phy_setup_autoneg");
1500
1501 phy->autoneg_advertised &= phy->autoneg_mask;
1502
1503 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1504 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1505 if (ret_val)
1506 goto out;
1507
1508 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1509 /* Read the MII 1000Base-T Control Register (Address 9). */
1510 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1511 &mii_1000t_ctrl_reg);
1512 if (ret_val)
1513 goto out;
1514 }
1515
1516 /*
1517 * Need to parse both autoneg_advertised and fc and set up
1518 * the appropriate PHY registers. First we will parse for
1519 * autoneg_advertised software override. Since we can advertise
1520 * a plethora of combinations, we need to check each bit
1521 * individually.
1522 */
1523
1524 /*
1525 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1526 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1527 * the 1000Base-T Control Register (Address 9).
1528 */
1529 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1530 NWAY_AR_100TX_HD_CAPS |
1531 NWAY_AR_10T_FD_CAPS |
1532 NWAY_AR_10T_HD_CAPS);
1533 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1534
1535 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1536
1537 /* Do we want to advertise 10 Mb Half Duplex? */
1538 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1539 DEBUGOUT("Advertise 10mb Half duplex\n");
1540 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1541 }
1542
1543 /* Do we want to advertise 10 Mb Full Duplex? */
1544 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1545 DEBUGOUT("Advertise 10mb Full duplex\n");
1546 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1547 }
1548
1549 /* Do we want to advertise 100 Mb Half Duplex? */
1550 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1551 DEBUGOUT("Advertise 100mb Half duplex\n");
1552 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1553 }
1554
1555 /* Do we want to advertise 100 Mb Full Duplex? */
1556 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1557 DEBUGOUT("Advertise 100mb Full duplex\n");
1558 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1559 }
1560
1561 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1562 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1563 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1564
1565 /* Do we want to advertise 1000 Mb Full Duplex? */
1566 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1567 DEBUGOUT("Advertise 1000mb Full duplex\n");
1568 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1569 }
1570
1571 /*
1572 * Check for a software override of the flow control settings, and
1573 * setup the PHY advertisement registers accordingly. If
1574 * auto-negotiation is enabled, then software will have to set the
1575 * "PAUSE" bits to the correct value in the Auto-Negotiation
1576 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1577 * negotiation.
1578 *
1579 * The possible values of the "fc" parameter are:
1580 * 0: Flow control is completely disabled
1581 * 1: Rx flow control is enabled (we can receive pause frames
1582 * but not send pause frames).
1583 * 2: Tx flow control is enabled (we can send pause frames
1584 * but we do not support receiving pause frames).
1585 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1586 * other: No software override. The flow control configuration
1587 * in the EEPROM is used.
1588 */
1589 switch (hw->fc.current_mode) {
1590 case e1000_fc_none:
1591 /*
1592 * Flow control (Rx & Tx) is completely disabled by a
1593 * software over-ride.
1594 */
1595 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1596 break;
1597 case e1000_fc_rx_pause:
1598 /*
1599 * Rx Flow control is enabled, and Tx Flow control is
1600 * disabled, by a software over-ride.
1601 *
1602 * Since there really isn't a way to advertise that we are
1603 * capable of Rx Pause ONLY, we will advertise that we
1604 * support both symmetric and asymmetric Rx PAUSE. Later
1605 * (in e1000_config_fc_after_link_up) we will disable the
1606 * hw's ability to send PAUSE frames.
1607 */
1608 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1609 break;
1610 case e1000_fc_tx_pause:
1611 /*
1612 * Tx Flow control is enabled, and Rx Flow control is
1613 * disabled, by a software over-ride.
1614 */
1615 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1616 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1617 break;
1618 case e1000_fc_full:
1619 /*
1620 * Flow control (both Rx and Tx) is enabled by a software
1621 * over-ride.
1622 */
1623 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1624 break;
1625 default:
1626 DEBUGOUT("Flow control param set incorrectly\n");
1627 ret_val = -E1000_ERR_CONFIG;
1628 goto out;
1629 }
1630
1631 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1632 if (ret_val)
1633 goto out;
1634
1635 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1636
1637 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1638 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1639 mii_1000t_ctrl_reg);
1640 if (ret_val)
1641 goto out;
1642 }
1643
1644out:
1645 return ret_val;
1646}
1647
1648/**
1649 * e1000_setup_copper_link_generic - Configure copper link settings
1650 * @hw: pointer to the HW structure
1651 *
1652 * Calls the appropriate function to configure the link for auto-neg or forced
1653 * speed and duplex. Then we check for link, once link is established calls
1654 * to configure collision distance and flow control are called. If link is
1655 * not established, we return -E1000_ERR_PHY (-2).
1656 **/
1657s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1658{
1659 s32 ret_val;
1660 bool link;
1661
1662 DEBUGFUNC("e1000_setup_copper_link_generic");
1663
1664 if (hw->mac.autoneg) {
1665 /*
1666 * Setup autoneg and flow control advertisement and perform
1667 * autonegotiation.
1668 */
1669 ret_val = e1000_copper_link_autoneg(hw);
1670 if (ret_val)
1671 goto out;
1672 } else {
1673 /*
1674 * PHY will be set to 10H, 10F, 100H or 100F
1675 * depending on user settings.
1676 */
1677 DEBUGOUT("Forcing Speed and Duplex\n");
1678 ret_val = hw->phy.ops.force_speed_duplex(hw);
1679 if (ret_val) {
1680 DEBUGOUT("Error Forcing Speed and Duplex\n");
1681 goto out;
1682 }
1683 }
1684
1685 /*
1686 * Check link status. Wait up to 100 microseconds for link to become
1687 * valid.
1688 */
1689 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1690 &link);
1691 if (ret_val)
1692 goto out;
1693
1694 if (link) {
1695 DEBUGOUT("Valid link established!!!\n");
1696 e1000_config_collision_dist_generic(hw);
1697 ret_val = e1000_config_fc_after_link_up_generic(hw);
1698 } else {
1699 DEBUGOUT("Unable to establish link!!!\n");
1700 }
1701
1702out:
1703 return ret_val;
1704}
1705
1706/**
1707 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1708 * @hw: pointer to the HW structure
1709 *
1710 * Calls the PHY setup function to force speed and duplex. Clears the
1711 * auto-crossover to force MDI manually. Waits for link and returns
1712 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1713 **/
1714s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1715{
1716 struct e1000_phy_info *phy = &hw->phy;
1717 s32 ret_val;
1718 u16 phy_data;
1719 bool link;
1720
1721 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1722
1723 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1724 if (ret_val)
1725 goto out;
1726
1727 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1728
1729 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1730 if (ret_val)
1731 goto out;
1732
1733 /*
1734 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1735 * forced whenever speed and duplex are forced.
1736 */
1737 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1738 if (ret_val)
1739 goto out;
1740
1741 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1742 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1743
1744 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1745 if (ret_val)
1746 goto out;
1747
1748 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1749
1750 usec_delay(1);
1751
1752 if (phy->autoneg_wait_to_complete) {
1753 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1754
1755 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1756 100000, &link);
1757 if (ret_val)
1758 goto out;
1759
1760 if (!link)
1761 DEBUGOUT("Link taking longer than expected.\n");
1762
1763 /* Try once more */
1764 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1765 100000, &link);
1766 if (ret_val)
1767 goto out;
1768 }
1769
1770out:
1771 return ret_val;
1772}
1773
1774/**
1775 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1776 * @hw: pointer to the HW structure
1777 *
1778 * Calls the PHY setup function to force speed and duplex. Clears the
1779 * auto-crossover to force MDI manually. Resets the PHY to commit the
1780 * changes. If time expires while waiting for link up, we reset the DSP.
1781 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1782 * successful completion, else return corresponding error code.
1783 **/
1784s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1785{
1786 struct e1000_phy_info *phy = &hw->phy;
1787 s32 ret_val;
1788 u16 phy_data;
1789 bool link;
1790
1791 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1792
1793 /*
1794 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1795 * forced whenever speed and duplex are forced.
1796 */
1797 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1798 if (ret_val)
1799 goto out;
1800
1801 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1802 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1803 if (ret_val)
1804 goto out;
1805
1806 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1807
1808 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1809 if (ret_val)
1810 goto out;
1811
1812 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1813
1814 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 /* Reset the phy to commit changes. */
1819 ret_val = hw->phy.ops.commit(hw);
1820 if (ret_val)
1821 goto out;
1822
1823 if (phy->autoneg_wait_to_complete) {
1824 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1825
1826 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1827 100000, &link);
1828 if (ret_val)
1829 goto out;
1830
1831 if (!link) {
1832 if (hw->phy.type != e1000_phy_m88 ||
1833 hw->phy.id == I347AT4_E_PHY_ID ||
1834 hw->phy.id == M88E1340M_E_PHY_ID ||
1835 hw->phy.id == M88E1112_E_PHY_ID) {
1836 DEBUGOUT("Link taking longer than expected.\n");
1837 } else {
1838 /*
1839 * We didn't get link.
1840 * Reset the DSP and cross our fingers.
1841 */
1842 ret_val = phy->ops.write_reg(hw,
1843 M88E1000_PHY_PAGE_SELECT,
1844 0x001d);
1845 if (ret_val)
1846 goto out;
1847 ret_val = e1000_phy_reset_dsp_generic(hw);
1848 if (ret_val)
1849 goto out;
1850 }
1851 }
1852
1853 /* Try once more */
1854 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1855 100000, &link);
1856 if (ret_val)
1857 goto out;
1858 }
1859
1860 if (hw->phy.type != e1000_phy_m88 ||
1861 hw->phy.id == I347AT4_E_PHY_ID ||
1862 hw->phy.id == M88E1340M_E_PHY_ID ||
1863 hw->phy.id == M88E1112_E_PHY_ID)
1864 goto out;
1865
1866 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1867 if (ret_val)
1868 goto out;
1869
1870 /*
1871 * Resetting the phy means we need to re-force TX_CLK in the
1872 * Extended PHY Specific Control Register to 25MHz clock from
1873 * the reset value of 2.5MHz.
1874 */
1875 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1876 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1877 if (ret_val)
1878 goto out;
1879
1880 /*
1881 * In addition, we must re-enable CRS on Tx for both half and full
1882 * duplex.
1883 */
1884 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1885 if (ret_val)
1886 goto out;
1887
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1889 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1890
1891out:
1892 return ret_val;
1893}
1894
1895/**
1896 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1897 * @hw: pointer to the HW structure
1898 *
1899 * Forces the speed and duplex settings of the PHY.
1900 * This is a function pointer entry point only called by
1901 * PHY setup routines.
1902 **/
1903s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1904{
1905 struct e1000_phy_info *phy = &hw->phy;
1906 s32 ret_val;
1907 u16 data;
1908 bool link;
1909
1910 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1911
1912 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1913 if (ret_val)
1914 goto out;
1915
1916 e1000_phy_force_speed_duplex_setup(hw, &data);
1917
1918 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1919 if (ret_val)
1920 goto out;
1921
1922 /* Disable MDI-X support for 10/100 */
1923 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1924 if (ret_val)
1925 goto out;
1926
1927 data &= ~IFE_PMC_AUTO_MDIX;
1928 data &= ~IFE_PMC_FORCE_MDIX;
1929
1930 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1931 if (ret_val)
1932 goto out;
1933
1934 DEBUGOUT1("IFE PMC: %X\n", data);
1935
1936 usec_delay(1);
1937
1938 if (phy->autoneg_wait_to_complete) {
1939 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1940
1941 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1942 100000, &link);
1943 if (ret_val)
1944 goto out;
1945
1946 if (!link)
1947 DEBUGOUT("Link taking longer than expected.\n");
1948
1949 /* Try once more */
1950 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1951 100000, &link);
1952 if (ret_val)
1953 goto out;
1954 }
1955
1956out:
1957 return ret_val;
1958}
1959
1960/**
1961 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1962 * @hw: pointer to the HW structure
1963 * @phy_ctrl: pointer to current value of PHY_CONTROL
1964 *
1965 * Forces speed and duplex on the PHY by doing the following: disable flow
1966 * control, force speed/duplex on the MAC, disable auto speed detection,
1967 * disable auto-negotiation, configure duplex, configure speed, configure
1968 * the collision distance, write configuration to CTRL register. The
1969 * caller must write to the PHY_CONTROL register for these settings to
1970 * take affect.
1971 **/
1972void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1973{
1974 struct e1000_mac_info *mac = &hw->mac;
1975 u32 ctrl;
1976
1977 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1978
1979 /* Turn off flow control when forcing speed/duplex */
1980 hw->fc.current_mode = e1000_fc_none;
1981
1982 /* Force speed/duplex on the mac */
1983 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1984 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1985 ctrl &= ~E1000_CTRL_SPD_SEL;
1986
1987 /* Disable Auto Speed Detection */
1988 ctrl &= ~E1000_CTRL_ASDE;
1989
1990 /* Disable autoneg on the phy */
1991 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1992
1993 /* Forcing Full or Half Duplex? */
1994 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1995 ctrl &= ~E1000_CTRL_FD;
1996 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1997 DEBUGOUT("Half Duplex\n");
1998 } else {
1999 ctrl |= E1000_CTRL_FD;
2000 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2001 DEBUGOUT("Full Duplex\n");
2002 }
2003
2004 /* Forcing 10mb or 100mb? */
2005 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2006 ctrl |= E1000_CTRL_SPD_100;
2007 *phy_ctrl |= MII_CR_SPEED_100;
2008 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2009 DEBUGOUT("Forcing 100mb\n");
2010 } else {
2011 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2012 *phy_ctrl |= MII_CR_SPEED_10;
2013 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2014 DEBUGOUT("Forcing 10mb\n");
2015 }
2016
2017 e1000_config_collision_dist_generic(hw);
2018
2019 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2020}
2021
2022/**
2023 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2024 * @hw: pointer to the HW structure
2025 * @active: boolean used to enable/disable lplu
2026 *
2027 * Success returns 0, Failure returns 1
2028 *
2029 * The low power link up (lplu) state is set to the power management level D3
2030 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
2031 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2032 * is used during Dx states where the power conservation is most important.
2033 * During driver activity, SmartSpeed should be enabled so performance is
2034 * maintained.
2035 **/
2036s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2037{
2038 struct e1000_phy_info *phy = &hw->phy;
2039 s32 ret_val = E1000_SUCCESS;
2040 u16 data;
2041
2042 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2043
2044 if (!(hw->phy.ops.read_reg))
2045 goto out;
2046
2047 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2048 if (ret_val)
2049 goto out;
2050
2051 if (!active) {
2052 data &= ~IGP02E1000_PM_D3_LPLU;
2053 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2054 data);
2055 if (ret_val)
2056 goto out;
2057 /*
2058 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2059 * during Dx states where the power conservation is most
2060 * important. During driver activity we should enable
2061 * SmartSpeed, so performance is maintained.
2062 */
2063 if (phy->smart_speed == e1000_smart_speed_on) {
2064 ret_val = phy->ops.read_reg(hw,
2065 IGP01E1000_PHY_PORT_CONFIG,
2066 &data);
2067 if (ret_val)
2068 goto out;
2069
2070 data |= IGP01E1000_PSCFR_SMART_SPEED;
2071 ret_val = phy->ops.write_reg(hw,
2072 IGP01E1000_PHY_PORT_CONFIG,
2073 data);
2074 if (ret_val)
2075 goto out;
2076 } else if (phy->smart_speed == e1000_smart_speed_off) {
2077 ret_val = phy->ops.read_reg(hw,
2078 IGP01E1000_PHY_PORT_CONFIG,
2079 &data);
2080 if (ret_val)
2081 goto out;
2082
2083 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2084 ret_val = phy->ops.write_reg(hw,
2085 IGP01E1000_PHY_PORT_CONFIG,
2086 data);
2087 if (ret_val)
2088 goto out;
2089 }
2090 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2091 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2092 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2093 data |= IGP02E1000_PM_D3_LPLU;
2094 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2095 data);
2096 if (ret_val)
2097 goto out;
2098
2099 /* When LPLU is enabled, we should disable SmartSpeed */
2100 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2101 &data);
2102 if (ret_val)
2103 goto out;
2104
2105 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2106 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2107 data);
2108 }
2109
2110out:
2111 return ret_val;
2112}
2113
2114/**
2115 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2116 * @hw: pointer to the HW structure
2117 *
2118 * Success returns 0, Failure returns 1
2119 *
2120 * A downshift is detected by querying the PHY link health.
2121 **/
2122s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2123{
2124 struct e1000_phy_info *phy = &hw->phy;
2125 s32 ret_val;
2126 u16 phy_data, offset, mask;
2127
2128 DEBUGFUNC("e1000_check_downshift_generic");
2129
2130 switch (phy->type) {
2131 case e1000_phy_m88:
2132 case e1000_phy_gg82563:
2133 case e1000_phy_bm:
2134 case e1000_phy_82578:
2135 offset = M88E1000_PHY_SPEC_STATUS;
2136 mask = M88E1000_PSSR_DOWNSHIFT;
2137 break;
2138 case e1000_phy_igp:
2139 case e1000_phy_igp_2:
2140 case e1000_phy_igp_3:
2141 offset = IGP01E1000_PHY_LINK_HEALTH;
2142 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2143 break;
2144 default:
2145 /* speed downshift not supported */
2146 phy->speed_downgraded = FALSE;
2147 ret_val = E1000_SUCCESS;
2148 goto out;
2149 }
2150
2151 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2152
2153 if (!ret_val)
2154 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
2155
2156out:
2157 return ret_val;
2158}
2159
2160/**
2161 * e1000_check_polarity_m88 - Checks the polarity.
2162 * @hw: pointer to the HW structure
2163 *
2164 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2165 *
2166 * Polarity is determined based on the PHY specific status register.
2167 **/
2168s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2169{
2170 struct e1000_phy_info *phy = &hw->phy;
2171 s32 ret_val;
2172 u16 data;
2173
2174 DEBUGFUNC("e1000_check_polarity_m88");
2175
2176 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2177
2178 if (!ret_val)
2179 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2180 ? e1000_rev_polarity_reversed
2181 : e1000_rev_polarity_normal;
2182
2183 return ret_val;
2184}
2185
2186/**
2187 * e1000_check_polarity_igp - Checks the polarity.
2188 * @hw: pointer to the HW structure
2189 *
2190 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2191 *
2192 * Polarity is determined based on the PHY port status register, and the
2193 * current speed (since there is no polarity at 100Mbps).
2194 **/
2195s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2196{
2197 struct e1000_phy_info *phy = &hw->phy;
2198 s32 ret_val;
2199 u16 data, offset, mask;
2200
2201 DEBUGFUNC("e1000_check_polarity_igp");
2202
2203 /*
2204 * Polarity is determined based on the speed of
2205 * our connection.
2206 */
2207 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2208 if (ret_val)
2209 goto out;
2210
2211 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2212 IGP01E1000_PSSR_SPEED_1000MBPS) {
2213 offset = IGP01E1000_PHY_PCS_INIT_REG;
2214 mask = IGP01E1000_PHY_POLARITY_MASK;
2215 } else {
2216 /*
2217 * This really only applies to 10Mbps since
2218 * there is no polarity for 100Mbps (always 0).
2219 */
2220 offset = IGP01E1000_PHY_PORT_STATUS;
2221 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2222 }
2223
2224 ret_val = phy->ops.read_reg(hw, offset, &data);
2225
2226 if (!ret_val)
2227 phy->cable_polarity = (data & mask)
2228 ? e1000_rev_polarity_reversed
2229 : e1000_rev_polarity_normal;
2230
2231out:
2232 return ret_val;
2233}
2234
2235/**
2236 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2237 * @hw: pointer to the HW structure
2238 *
2239 * Polarity is determined on the polarity reversal feature being enabled.
2240 **/
2241s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2242{
2243 struct e1000_phy_info *phy = &hw->phy;
2244 s32 ret_val;
2245 u16 phy_data, offset, mask;
2246
2247 DEBUGFUNC("e1000_check_polarity_ife");
2248
2249 /*
2250 * Polarity is determined based on the reversal feature being enabled.
2251 */
2252 if (phy->polarity_correction) {
2253 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2254 mask = IFE_PESC_POLARITY_REVERSED;
2255 } else {
2256 offset = IFE_PHY_SPECIAL_CONTROL;
2257 mask = IFE_PSC_FORCE_POLARITY;
2258 }
2259
2260 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2261
2262 if (!ret_val)
2263 phy->cable_polarity = (phy_data & mask)
2264 ? e1000_rev_polarity_reversed
2265 : e1000_rev_polarity_normal;
2266
2267 return ret_val;
2268}
2269
2270/**
2271 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2272 * @hw: pointer to the HW structure
2273 *
2274 * Waits for auto-negotiation to complete or for the auto-negotiation time
2275 * limit to expire, which ever happens first.
2276 **/
2277s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2278{
2279 s32 ret_val = E1000_SUCCESS;
2280 u16 i, phy_status;
2281
2282 DEBUGFUNC("e1000_wait_autoneg_generic");
2283
2284 if (!(hw->phy.ops.read_reg))
2285 return E1000_SUCCESS;
2286
2287 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2288 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2289 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2290 if (ret_val)
2291 break;
2292 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2293 if (ret_val)
2294 break;
2295 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2296 break;
2297 msec_delay(100);
2298 }
2299
2300 /*
2301 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2302 * has completed.
2303 */
2304 return ret_val;
2305}
2306
2307/**
2308 * e1000_phy_has_link_generic - Polls PHY for link
2309 * @hw: pointer to the HW structure
2310 * @iterations: number of times to poll for link
2311 * @usec_interval: delay between polling attempts
2312 * @success: pointer to whether polling was successful or not
2313 *
2314 * Polls the PHY status register for link, 'iterations' number of times.
2315 **/
2316s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2317 u32 usec_interval, bool *success)
2318{
2319 s32 ret_val = E1000_SUCCESS;
2320 u16 i, phy_status;
2321
2322 DEBUGFUNC("e1000_phy_has_link_generic");
2323
2324 if (!(hw->phy.ops.read_reg))
2325 return E1000_SUCCESS;
2326
2327 for (i = 0; i < iterations; i++) {
2328 /*
2329 * Some PHYs require the PHY_STATUS register to be read
2330 * twice due to the link bit being sticky. No harm doing
2331 * it across the board.
2332 */
2333 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2334 if (ret_val)
2335 /*
2336 * If the first read fails, another entity may have
2337 * ownership of the resources, wait and try again to
2338 * see if they have relinquished the resources yet.
2339 */
2340 usec_delay(usec_interval);
2341 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2342 if (ret_val)
2343 break;
2344 if (phy_status & MII_SR_LINK_STATUS)
2345 break;
2346 if (usec_interval >= 1000)
2347 msec_delay_irq(usec_interval/1000);
2348 else
2349 usec_delay(usec_interval);
2350 }
2351
2352 *success = (i < iterations) ? TRUE : FALSE;
2353
2354 return ret_val;
2355}
2356
2357/**
2358 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2359 * @hw: pointer to the HW structure
2360 *
2361 * Reads the PHY specific status register to retrieve the cable length
2362 * information. The cable length is determined by averaging the minimum and
2363 * maximum values to get the "average" cable length. The m88 PHY has four
2364 * possible cable length values, which are:
2365 * Register Value Cable Length
2366 * 0 < 50 meters
2367 * 1 50 - 80 meters
2368 * 2 80 - 110 meters
2369 * 3 110 - 140 meters
2370 * 4 > 140 meters
2371 **/
2372s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2373{
2374 struct e1000_phy_info *phy = &hw->phy;
2375 s32 ret_val;
2376 u16 phy_data, index;
2377
2378 DEBUGFUNC("e1000_get_cable_length_m88");
2379
2380 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2381 if (ret_val)
2382 goto out;
2383
2384 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2385 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2386 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2387 ret_val = -E1000_ERR_PHY;
2388 goto out;
2389 }
2390
2391 phy->min_cable_length = e1000_m88_cable_length_table[index];
2392 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2393
2394 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2395
2396out:
2397 return ret_val;
2398}
2399
2400s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2401{
2402 struct e1000_phy_info *phy = &hw->phy;
2403 s32 ret_val;
2404 u16 phy_data, phy_data2, index, default_page, is_cm;
2405
2406 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2407
2408 switch (hw->phy.id) {
2409 case M88E1340M_E_PHY_ID:
2410 case I347AT4_E_PHY_ID:
2411 /* Remember the original page select and set it to 7 */
2412 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2413 &default_page);
2414 if (ret_val)
2415 goto out;
2416
2417 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2418 if (ret_val)
2419 goto out;
2420
2421 /* Get cable length from PHY Cable Diagnostics Control Reg */
2422 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2423 &phy_data);
2424 if (ret_val)
2425 goto out;
2426
2427 /* Check if the unit of cable length is meters or cm */
2428 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2429 if (ret_val)
2430 goto out;
2431
2432 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2433
2434 /* Populate the phy structure with cable length in meters */
2435 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2436 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2437 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2438
2439 /* Reset the page select to its original value */
2440 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2441 default_page);
2442 if (ret_val)
2443 goto out;
2444 break;
2445 case M88E1112_E_PHY_ID:
2446 /* Remember the original page select and set it to 5 */
2447 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2448 &default_page);
2449 if (ret_val)
2450 goto out;
2451
2452 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2453 if (ret_val)
2454 goto out;
2455
2456 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2457 &phy_data);
2458 if (ret_val)
2459 goto out;
2460
2461 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2462 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2463 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2464 ret_val = -E1000_ERR_PHY;
2465 goto out;
2466 }
2467
2468 phy->min_cable_length = e1000_m88_cable_length_table[index];
2469 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2470
2471 phy->cable_length = (phy->min_cable_length +
2472 phy->max_cable_length) / 2;
2473
2474 /* Reset the page select to its original value */
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2476 default_page);
2477 if (ret_val)
2478 goto out;
2479
2480 break;
2481 default:
2482 ret_val = -E1000_ERR_PHY;
2483 goto out;
2484 }
2485
2486out:
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2492 * @hw: pointer to the HW structure
2493 *
2494 * The automatic gain control (agc) normalizes the amplitude of the
2495 * received signal, adjusting for the attenuation produced by the
2496 * cable. By reading the AGC registers, which represent the
2497 * combination of coarse and fine gain value, the value can be put
2498 * into a lookup table to obtain the approximate cable length
2499 * for each channel.
2500 **/
2501s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2502{
2503 struct e1000_phy_info *phy = &hw->phy;
2504 s32 ret_val = E1000_SUCCESS;
2505 u16 phy_data, i, agc_value = 0;
2506 u16 cur_agc_index, max_agc_index = 0;
2507 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2508 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2509 IGP02E1000_PHY_AGC_A,
2510 IGP02E1000_PHY_AGC_B,
2511 IGP02E1000_PHY_AGC_C,
2512 IGP02E1000_PHY_AGC_D
2513 };
2514
2515 DEBUGFUNC("e1000_get_cable_length_igp_2");
2516
2517 /* Read the AGC registers for all channels */
2518 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2519 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2520 if (ret_val)
2521 goto out;
2522
2523 /*
2524 * Getting bits 15:9, which represent the combination of
2525 * coarse and fine gain values. The result is a number
2526 * that can be put into the lookup table to obtain the
2527 * approximate cable length.
2528 */
2529 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2530 IGP02E1000_AGC_LENGTH_MASK;
2531
2532 /* Array index bound check. */
2533 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2534 (cur_agc_index == 0)) {
2535 ret_val = -E1000_ERR_PHY;
2536 goto out;
2537 }
2538
2539 /* Remove min & max AGC values from calculation. */
2540 if (e1000_igp_2_cable_length_table[min_agc_index] >
2541 e1000_igp_2_cable_length_table[cur_agc_index])
2542 min_agc_index = cur_agc_index;
2543 if (e1000_igp_2_cable_length_table[max_agc_index] <
2544 e1000_igp_2_cable_length_table[cur_agc_index])
2545 max_agc_index = cur_agc_index;
2546
2547 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2548 }
2549
2550 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2551 e1000_igp_2_cable_length_table[max_agc_index]);
2552 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2553
2554 /* Calculate cable length with the error range of +/- 10 meters. */
2555 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2556 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2557 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2558
2559 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2560
2561out:
2562 return ret_val;
2563}
2564
2565/**
2566 * e1000_get_phy_info_m88 - Retrieve PHY information
2567 * @hw: pointer to the HW structure
2568 *
2569 * Valid for only copper links. Read the PHY status register (sticky read)
2570 * to verify that link is up. Read the PHY special control register to
2571 * determine the polarity and 10base-T extended distance. Read the PHY
2572 * special status register to determine MDI/MDIx and current speed. If
2573 * speed is 1000, then determine cable length, local and remote receiver.
2574 **/
2575s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2576{
2577 struct e1000_phy_info *phy = &hw->phy;
2578 s32 ret_val;
2579 u16 phy_data;
2580 bool link;
2581
2582 DEBUGFUNC("e1000_get_phy_info_m88");
2583
2584 if (phy->media_type != e1000_media_type_copper) {
2585 DEBUGOUT("Phy info is only valid for copper media\n");
2586 ret_val = -E1000_ERR_CONFIG;
2587 goto out;
2588 }
2589
2590 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2591 if (ret_val)
2592 goto out;
2593
2594 if (!link) {
2595 DEBUGOUT("Phy info is only valid if link is up\n");
2596 ret_val = -E1000_ERR_CONFIG;
2597 goto out;
2598 }
2599
2600 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2601 if (ret_val)
2602 goto out;
2603
2604 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2605 ? TRUE : FALSE;
2606
2607 ret_val = e1000_check_polarity_m88(hw);
2608 if (ret_val)
2609 goto out;
2610
2611 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2612 if (ret_val)
2613 goto out;
2614
2615 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2616
2617 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2618 ret_val = hw->phy.ops.get_cable_length(hw);
2619 if (ret_val)
2620 goto out;
2621
2622 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2623 if (ret_val)
2624 goto out;
2625
2626 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2627 ? e1000_1000t_rx_status_ok
2628 : e1000_1000t_rx_status_not_ok;
2629
2630 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2631 ? e1000_1000t_rx_status_ok
2632 : e1000_1000t_rx_status_not_ok;
2633 } else {
2634 /* Set values to "undefined" */
2635 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2636 phy->local_rx = e1000_1000t_rx_status_undefined;
2637 phy->remote_rx = e1000_1000t_rx_status_undefined;
2638 }
2639
2640out:
2641 return ret_val;
2642}
2643
2644/**
2645 * e1000_get_phy_info_igp - Retrieve igp PHY information
2646 * @hw: pointer to the HW structure
2647 *
2648 * Read PHY status to determine if link is up. If link is up, then
2649 * set/determine 10base-T extended distance and polarity correction. Read
2650 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2651 * determine on the cable length, local and remote receiver.
2652 **/
2653s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2654{
2655 struct e1000_phy_info *phy = &hw->phy;
2656 s32 ret_val;
2657 u16 data;
2658 bool link;
2659
2660 DEBUGFUNC("e1000_get_phy_info_igp");
2661
2662 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2663 if (ret_val)
2664 goto out;
2665
2666 if (!link) {
2667 DEBUGOUT("Phy info is only valid if link is up\n");
2668 ret_val = -E1000_ERR_CONFIG;
2669 goto out;
2670 }
2671
2672 phy->polarity_correction = TRUE;
2673
2674 ret_val = e1000_check_polarity_igp(hw);
2675 if (ret_val)
2676 goto out;
2677
2678 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2679 if (ret_val)
2680 goto out;
2681
2682 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2683
2684 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2685 IGP01E1000_PSSR_SPEED_1000MBPS) {
2686 ret_val = phy->ops.get_cable_length(hw);
2687 if (ret_val)
2688 goto out;
2689
2690 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2691 if (ret_val)
2692 goto out;
2693
2694 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2695 ? e1000_1000t_rx_status_ok
2696 : e1000_1000t_rx_status_not_ok;
2697
2698 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2699 ? e1000_1000t_rx_status_ok
2700 : e1000_1000t_rx_status_not_ok;
2701 } else {
2702 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2703 phy->local_rx = e1000_1000t_rx_status_undefined;
2704 phy->remote_rx = e1000_1000t_rx_status_undefined;
2705 }
2706
2707out:
2708 return ret_val;
2709}
2710
2711/**
2712 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2713 * @hw: pointer to the HW structure
2714 *
2715 * Populates "phy" structure with various feature states.
2716 **/
2717s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2718{
2719 struct e1000_phy_info *phy = &hw->phy;
2720 s32 ret_val;
2721 u16 data;
2722 bool link;
2723
2724 DEBUGFUNC("e1000_get_phy_info_ife");
2725
2726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2727 if (ret_val)
2728 goto out;
2729
2730 if (!link) {
2731 DEBUGOUT("Phy info is only valid if link is up\n");
2732 ret_val = -E1000_ERR_CONFIG;
2733 goto out;
2734 }
2735
2736 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2737 if (ret_val)
2738 goto out;
2739 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2740 ? FALSE : TRUE;
2741
2742 if (phy->polarity_correction) {
2743 ret_val = e1000_check_polarity_ife(hw);
2744 if (ret_val)
2745 goto out;
2746 } else {
2747 /* Polarity is forced */
2748 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2749 ? e1000_rev_polarity_reversed
2750 : e1000_rev_polarity_normal;
2751 }
2752
2753 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2754 if (ret_val)
2755 goto out;
2756
2757 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2758
2759 /* The following parameters are undefined for 10/100 operation. */
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2763
2764out:
2765 return ret_val;
2766}
2767
2768/**
2769 * e1000_phy_sw_reset_generic - PHY software reset
2770 * @hw: pointer to the HW structure
2771 *
2772 * Does a software reset of the PHY by reading the PHY control register and
2773 * setting/write the control register reset bit to the PHY.
2774 **/
2775s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2776{
2777 s32 ret_val = E1000_SUCCESS;
2778 u16 phy_ctrl;
2779
2780 DEBUGFUNC("e1000_phy_sw_reset_generic");
2781
2782 if (!(hw->phy.ops.read_reg))
2783 goto out;
2784
2785 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2786 if (ret_val)
2787 goto out;
2788
2789 phy_ctrl |= MII_CR_RESET;
2790 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2791 if (ret_val)
2792 goto out;
2793
2794 usec_delay(1);
2795
2796out:
2797 return ret_val;
2798}
2799
2800/**
2801 * e1000_phy_hw_reset_generic - PHY hardware reset
2802 * @hw: pointer to the HW structure
2803 *
2804 * Verify the reset block is not blocking us from resetting. Acquire
2805 * semaphore (if necessary) and read/set/write the device control reset
2806 * bit in the PHY. Wait the appropriate delay time for the device to
2807 * reset and release the semaphore (if necessary).
2808 **/
2809s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2810{
2811 struct e1000_phy_info *phy = &hw->phy;
2812 s32 ret_val = E1000_SUCCESS;
2813 u32 ctrl;
2814
2815 DEBUGFUNC("e1000_phy_hw_reset_generic");
2816
2817 ret_val = phy->ops.check_reset_block(hw);
2818 if (ret_val) {
2819 ret_val = E1000_SUCCESS;
2820 goto out;
2821 }
2822
2823 ret_val = phy->ops.acquire(hw);
2824 if (ret_val)
2825 goto out;
2826
2827 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2828 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2829 E1000_WRITE_FLUSH(hw);
2830
2831 usec_delay(phy->reset_delay_us);
2832
2833 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2834 E1000_WRITE_FLUSH(hw);
2835
2836 usec_delay(150);
2837
2838 phy->ops.release(hw);
2839
2840 ret_val = phy->ops.get_cfg_done(hw);
2841
2842out:
2843 return ret_val;
2844}
2845
2846/**
2847 * e1000_get_cfg_done_generic - Generic configuration done
2848 * @hw: pointer to the HW structure
2849 *
2850 * Generic function to wait 10 milli-seconds for configuration to complete
2851 * and return success.
2852 **/
2853s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2854{
2855 DEBUGFUNC("e1000_get_cfg_done_generic");
2856
2857 msec_delay_irq(10);
2858
2859 return E1000_SUCCESS;
2860}
2861
2862/**
2863 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2864 * @hw: pointer to the HW structure
2865 *
2866 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2867 **/
2868s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2869{
2870 DEBUGOUT("Running IGP 3 PHY init script\n");
2871
2872 /* PHY init IGP 3 */
2873 /* Enable rise/fall, 10-mode work in class-A */
2874 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2875 /* Remove all caps from Replica path filter */
2876 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2877 /* Bias trimming for ADC, AFE and Driver (Default) */
2878 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2879 /* Increase Hybrid poly bias */
2880 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2881 /* Add 4% to Tx amplitude in Gig mode */
2882 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2883 /* Disable trimming (TTT) */
2884 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2885 /* Poly DC correction to 94.6% + 2% for all channels */
2886 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2887 /* ABS DC correction to 95.9% */
2888 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2889 /* BG temp curve trim */
2890 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2891 /* Increasing ADC OPAMP stage 1 currents to max */
2892 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2893 /* Force 1000 ( required for enabling PHY regs configuration) */
2894 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2895 /* Set upd_freq to 6 */
2896 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2897 /* Disable NPDFE */
2898 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2899 /* Disable adaptive fixed FFE (Default) */
2900 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2901 /* Enable FFE hysteresis */
2902 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2903 /* Fixed FFE for short cable lengths */
2904 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2905 /* Fixed FFE for medium cable lengths */
2906 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2907 /* Fixed FFE for long cable lengths */
2908 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2909 /* Enable Adaptive Clip Threshold */
2910 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2911 /* AHT reset limit to 1 */
2912 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2913 /* Set AHT master delay to 127 msec */
2914 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2915 /* Set scan bits for AHT */
2916 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2917 /* Set AHT Preset bits */
2918 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2919 /* Change integ_factor of channel A to 3 */
2920 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2921 /* Change prop_factor of channels BCD to 8 */
2922 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2923 /* Change cg_icount + enable integbp for channels BCD */
2924 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2925 /*
2926 * Change cg_icount + enable integbp + change prop_factor_master
2927 * to 8 for channel A
2928 */
2929 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2930 /* Disable AHT in Slave mode on channel A */
2931 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2932 /*
2933 * Enable LPLU and disable AN to 1000 in non-D0a states,
2934 * Enable SPD+B2B
2935 */
2936 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2937 /* Enable restart AN on an1000_dis change */
2938 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2939 /* Enable wh_fifo read clock in 10/100 modes */
2940 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2941 /* Restart AN, Speed selection is 1000 */
2942 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2943
2944 return E1000_SUCCESS;
2945}
2946
2947/**
2948 * e1000_get_phy_type_from_id - Get PHY type from id
2949 * @phy_id: phy_id read from the phy
2950 *
2951 * Returns the phy type from the id.
2952 **/
2953enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2954{
2955 enum e1000_phy_type phy_type = e1000_phy_unknown;
2956
2957 switch (phy_id) {
2958 case M88E1000_I_PHY_ID:
2959 case M88E1000_E_PHY_ID:
2960 case M88E1111_I_PHY_ID:
2961 case M88E1011_I_PHY_ID:
2962 case I347AT4_E_PHY_ID:
2963 case M88E1112_E_PHY_ID:
2964 case M88E1340M_E_PHY_ID:
2965 phy_type = e1000_phy_m88;
2966 break;
2967 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2968 phy_type = e1000_phy_igp_2;
2969 break;
2970 case GG82563_E_PHY_ID:
2971 phy_type = e1000_phy_gg82563;
2972 break;
2973 case IGP03E1000_E_PHY_ID:
2974 phy_type = e1000_phy_igp_3;
2975 break;
2976 case IFE_E_PHY_ID:
2977 case IFE_PLUS_E_PHY_ID:
2978 case IFE_C_E_PHY_ID:
2979 phy_type = e1000_phy_ife;
2980 break;
2981 case BME1000_E_PHY_ID:
2982 case BME1000_E_PHY_ID_R2:
2983 phy_type = e1000_phy_bm;
2984 break;
2985 case I82578_E_PHY_ID:
2986 phy_type = e1000_phy_82578;
2987 break;
2988 case I82577_E_PHY_ID:
2989 phy_type = e1000_phy_82577;
2990 break;
2991 case I82579_E_PHY_ID:
2992 phy_type = e1000_phy_82579;
2993 break;
2994 case I82580_I_PHY_ID:
2995 phy_type = e1000_phy_82580;
2996 break;
2997 default:
2998 phy_type = e1000_phy_unknown;
2999 break;
3000 }
3001 return phy_type;
3002}
3003
3004/**
3005 * e1000_determine_phy_address - Determines PHY address.
3006 * @hw: pointer to the HW structure
3007 *
3008 * This uses a trial and error method to loop through possible PHY
3009 * addresses. It tests each by reading the PHY ID registers and
3010 * checking for a match.
3011 **/
3012s32 e1000_determine_phy_address(struct e1000_hw *hw)
3013{
3014 s32 ret_val = -E1000_ERR_PHY_TYPE;
3015 u32 phy_addr = 0;
3016 u32 i;
3017 enum e1000_phy_type phy_type = e1000_phy_unknown;
3018
3019 hw->phy.id = phy_type;
3020
3021 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3022 hw->phy.addr = phy_addr;
3023 i = 0;
3024
3025 do {
3026 e1000_get_phy_id(hw);
3027 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3028
3029 /*
3030 * If phy_type is valid, break - we found our
3031 * PHY address
3032 */
3033 if (phy_type != e1000_phy_unknown) {
3034 ret_val = E1000_SUCCESS;
3035 goto out;
3036 }
3037 msec_delay(1);
3038 i++;
3039 } while (i < 10);
3040 }
3041
3042out:
3043 return ret_val;
3044}
3045
3046/**
3047 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3048 * @page: page to access
3049 *
3050 * Returns the phy address for the page requested.
3051 **/
3052static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3053{
3054 u32 phy_addr = 2;
3055
3056 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3057 phy_addr = 1;
3058
3059 return phy_addr;
3060}
3061
3062/**
3063 * e1000_write_phy_reg_bm - Write BM PHY register
3064 * @hw: pointer to the HW structure
3065 * @offset: register offset to write to
3066 * @data: data to write at register offset
3067 *
3068 * Acquires semaphore, if necessary, then writes the data to PHY register
3069 * at the offset. Release any acquired semaphores before exiting.
3070 **/
3071s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3072{
3073 s32 ret_val;
3074 u32 page = offset >> IGP_PAGE_SHIFT;
3075
3076 DEBUGFUNC("e1000_write_phy_reg_bm");
3077
3078 ret_val = hw->phy.ops.acquire(hw);
3079 if (ret_val)
3080 return ret_val;
3081
3082 /* Page 800 works differently than the rest so it has its own func */
3083 if (page == BM_WUC_PAGE) {
3084 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3085 FALSE, FALSE);
3086 goto out;
3087 }
3088
3089 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3090
3091 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3092 u32 page_shift, page_select;
3093
3094 /*
3095 * Page select is register 31 for phy address 1 and 22 for
3096 * phy address 2 and 3. Page select is shifted only for
3097 * phy address 1.
3098 */
3099 if (hw->phy.addr == 1) {
3100 page_shift = IGP_PAGE_SHIFT;
3101 page_select = IGP01E1000_PHY_PAGE_SELECT;
3102 } else {
3103 page_shift = 0;
3104 page_select = BM_PHY_PAGE_SELECT;
3105 }
3106
3107 /* Page is shifted left, PHY expects (page x 32) */
3108 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3109 (page << page_shift));
3110 if (ret_val)
3111 goto out;
3112 }
3113
3114 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3115 data);
3116
3117out:
3118 hw->phy.ops.release(hw);
3119 return ret_val;
3120}
3121
3122/**
3123 * e1000_read_phy_reg_bm - Read BM PHY register
3124 * @hw: pointer to the HW structure
3125 * @offset: register offset to be read
3126 * @data: pointer to the read data
3127 *
3128 * Acquires semaphore, if necessary, then reads the PHY register at offset
3129 * and storing the retrieved information in data. Release any acquired
3130 * semaphores before exiting.
3131 **/
3132s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3133{
3134 s32 ret_val;
3135 u32 page = offset >> IGP_PAGE_SHIFT;
3136
3137 DEBUGFUNC("e1000_read_phy_reg_bm");
3138
3139 ret_val = hw->phy.ops.acquire(hw);
3140 if (ret_val)
3141 return ret_val;
3142
3143 /* Page 800 works differently than the rest so it has its own func */
3144 if (page == BM_WUC_PAGE) {
3145 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3146 TRUE, FALSE);
3147 goto out;
3148 }
3149
3150 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3151
3152 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3153 u32 page_shift, page_select;
3154
3155 /*
3156 * Page select is register 31 for phy address 1 and 22 for
3157 * phy address 2 and 3. Page select is shifted only for
3158 * phy address 1.
3159 */
3160 if (hw->phy.addr == 1) {
3161 page_shift = IGP_PAGE_SHIFT;
3162 page_select = IGP01E1000_PHY_PAGE_SELECT;
3163 } else {
3164 page_shift = 0;
3165 page_select = BM_PHY_PAGE_SELECT;
3166 }
3167
3168 /* Page is shifted left, PHY expects (page x 32) */
3169 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3170 (page << page_shift));
3171 if (ret_val)
3172 goto out;
3173 }
3174
3175 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3176 data);
3177out:
3178 hw->phy.ops.release(hw);
3179 return ret_val;
3180}
3181
3182/**
3183 * e1000_read_phy_reg_bm2 - Read BM PHY register
3184 * @hw: pointer to the HW structure
3185 * @offset: register offset to be read
3186 * @data: pointer to the read data
3187 *
3188 * Acquires semaphore, if necessary, then reads the PHY register at offset
3189 * and storing the retrieved information in data. Release any acquired
3190 * semaphores before exiting.
3191 **/
3192s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3193{
3194 s32 ret_val;
3195 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3196
3197 DEBUGFUNC("e1000_read_phy_reg_bm2");
3198
3199 ret_val = hw->phy.ops.acquire(hw);
3200 if (ret_val)
3201 return ret_val;
3202
3203 /* Page 800 works differently than the rest so it has its own func */
3204 if (page == BM_WUC_PAGE) {
3205 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3206 TRUE, FALSE);
3207 goto out;
3208 }
3209
3210 hw->phy.addr = 1;
3211
3212 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3213
3214 /* Page is shifted left, PHY expects (page x 32) */
3215 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3216 page);
3217
3218 if (ret_val)
3219 goto out;
3220 }
3221
3222 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3223 data);
3224out:
3225 hw->phy.ops.release(hw);
3226 return ret_val;
3227}
3228
3229/**
3230 * e1000_write_phy_reg_bm2 - Write BM PHY register
3231 * @hw: pointer to the HW structure
3232 * @offset: register offset to write to
3233 * @data: data to write at register offset
3234 *
3235 * Acquires semaphore, if necessary, then writes the data to PHY register
3236 * at the offset. Release any acquired semaphores before exiting.
3237 **/
3238s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3239{
3240 s32 ret_val;
3241 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3242
3243 DEBUGFUNC("e1000_write_phy_reg_bm2");
3244
3245 ret_val = hw->phy.ops.acquire(hw);
3246 if (ret_val)
3247 return ret_val;
3248
3249 /* Page 800 works differently than the rest so it has its own func */
3250 if (page == BM_WUC_PAGE) {
3251 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3252 FALSE, FALSE);
3253 goto out;
3254 }
3255
3256 hw->phy.addr = 1;
3257
3258 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3259 /* Page is shifted left, PHY expects (page x 32) */
3260 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3261 page);
3262
3263 if (ret_val)
3264 goto out;
3265 }
3266
3267 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3268 data);
3269
3270out:
3271 hw->phy.ops.release(hw);
3272 return ret_val;
3273}
3274
3275/**
3276 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3277 * @hw: pointer to the HW structure
3278 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3279 *
3280 * Assumes semaphore already acquired and phy_reg points to a valid memory
3281 * address to store contents of the BM_WUC_ENABLE_REG register.
3282 **/
3283s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3284{
3285 s32 ret_val;
3286 u16 temp;
3287
3288 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3289
3290 if (!phy_reg) {
3291 ret_val = -E1000_ERR_PARAM;
3292 goto out;
3293 }
3294
3295 /* All page select, port ctrl and wakeup registers use phy address 1 */
3296 hw->phy.addr = 1;
3297
3298 /* Select Port Control Registers page */
3299 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3300 if (ret_val) {
3301 DEBUGOUT("Could not set Port Control page\n");
3302 goto out;
3303 }
3304
3305 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3306 if (ret_val) {
3307 DEBUGOUT2("Could not read PHY register %d.%d\n",
3308 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3309 goto out;
3310 }
3311
3312 /*
3313 * Enable both PHY wakeup mode and Wakeup register page writes.
3314 * Prevent a power state change by disabling ME and Host PHY wakeup.
3315 */
3316 temp = *phy_reg;
3317 temp |= BM_WUC_ENABLE_BIT;
3318 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3319
3320 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3321 if (ret_val) {
3322 DEBUGOUT2("Could not write PHY register %d.%d\n",
3323 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3324 goto out;
3325 }
3326
3327 /* Select Host Wakeup Registers page */
3328 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3329
3330 /* caller now able to write registers on the Wakeup registers page */
3331out:
3332 return ret_val;
3333}
3334
3335/**
3336 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3337 * @hw: pointer to the HW structure
3338 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3339 *
3340 * Restore BM_WUC_ENABLE_REG to its original value.
3341 *
3342 * Assumes semaphore already acquired and *phy_reg is the contents of the
3343 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3344 * caller.
3345 **/
3346s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3347{
3348 s32 ret_val = E1000_SUCCESS;
3349
3350 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3351
3352 if (!phy_reg)
3353 return -E1000_ERR_PARAM;
3354
3355 /* Select Port Control Registers page */
3356 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3357 if (ret_val) {
3358 DEBUGOUT("Could not set Port Control page\n");
3359 goto out;
3360 }
3361
3362 /* Restore 769.17 to its original value */
3363 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3364 if (ret_val)
3365 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3366 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3367out:
3368 return ret_val;
3369}
3370
3371/**
3372 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3373 * @hw: pointer to the HW structure
3374 * @offset: register offset to be read or written
3375 * @data: pointer to the data to read or write
3376 * @read: determines if operation is read or write
3377 * @page_set: BM_WUC_PAGE already set and access enabled
3378 *
3379 * Read the PHY register at offset and store the retrieved information in
3380 * data, or write data to PHY register at offset. Note the procedure to
3381 * access the PHY wakeup registers is different than reading the other PHY
3382 * registers. It works as such:
3383 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3384 * 2) Set page to 800 for host (801 if we were manageability)
3385 * 3) Write the address using the address opcode (0x11)
3386 * 4) Read or write the data using the data opcode (0x12)
3387 * 5) Restore 769.17.2 to its original value
3388 *
3389 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3390 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3391 *
3392 * Assumes semaphore is already acquired. When page_set==TRUE, assumes
3393 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3394 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3395 **/
3396static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3397 u16 *data, bool read, bool page_set)
3398{
3399 s32 ret_val;
3400 u16 reg = BM_PHY_REG_NUM(offset);
3401 u16 phy_reg = 0;
3402
3403 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3404
3405 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3406 if ((hw->mac.type == e1000_pchlan) &&
3407 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3408 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3409 page);
3410
3411 if (!page_set) {
3412 /* Enable access to PHY wakeup registers */
3413 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3414 if (ret_val) {
3415 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3416 goto out;
3417 }
3418 }
3419
3420 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3421
3422 /* Write the Wakeup register page offset value using opcode 0x11 */
3423 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3424 if (ret_val) {
3425 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3426 goto out;
3427 }
3428
3429 if (read) {
3430 /* Read the Wakeup register page value using opcode 0x12 */
3431 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3432 data);
3433 } else {
3434 /* Write the Wakeup register page value using opcode 0x12 */
3435 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3436 *data);
3437 }
3438
3439 if (ret_val) {
3440 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3441 goto out;
3442 }
3443
3444 if (!page_set)
3445 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3446
3447out:
3448 return ret_val;
3449}
3450
3451/**
3452 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3453 * @hw: pointer to the HW structure
3454 *
3455 * In the case of a PHY power down to save power, or to turn off link during a
3456 * driver unload, or wake on lan is not enabled, restore the link to previous
3457 * settings.
3458 **/
3459void e1000_power_up_phy_copper(struct e1000_hw *hw)
3460{
3461 u16 mii_reg = 0;
3462
3463 /* The PHY will retain its settings across a power down/up cycle */
3464 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3465 mii_reg &= ~MII_CR_POWER_DOWN;
3466 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3467}
3468
3469/**
3470 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3471 * @hw: pointer to the HW structure
3472 *
3473 * In the case of a PHY power down to save power, or to turn off link during a
3474 * driver unload, or wake on lan is not enabled, restore the link to previous
3475 * settings.
3476 **/
3477void e1000_power_down_phy_copper(struct e1000_hw *hw)
3478{
3479 u16 mii_reg = 0;
3480
3481 /* The PHY will retain its settings across a power down/up cycle */
3482 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3483 mii_reg |= MII_CR_POWER_DOWN;
3484 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3485 msec_delay(1);
3486}
3487
3488/**
3489 * __e1000_read_phy_reg_hv - Read HV PHY register
3490 * @hw: pointer to the HW structure
3491 * @offset: register offset to be read
3492 * @data: pointer to the read data
3493 * @locked: semaphore has already been acquired or not
3494 *
3495 * Acquires semaphore, if necessary, then reads the PHY register at offset
3496 * and stores the retrieved information in data. Release any acquired
3497 * semaphore before exiting.
3498 **/
3499static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3500 bool locked, bool page_set)
3501{
3502 s32 ret_val;
3503 u16 page = BM_PHY_REG_PAGE(offset);
3504 u16 reg = BM_PHY_REG_NUM(offset);
3505 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3506
3507 DEBUGFUNC("__e1000_read_phy_reg_hv");
3508
3509 if (!locked) {
3510 ret_val = hw->phy.ops.acquire(hw);
3511 if (ret_val)
3512 return ret_val;
3513 }
3514
3515 /* Page 800 works differently than the rest so it has its own func */
3516 if (page == BM_WUC_PAGE) {
3517 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3518 TRUE, page_set);
3519 goto out;
3520 }
3521
3522 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3523 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3524 data, TRUE);
3525 goto out;
3526 }
3527
3528 if (!page_set) {
3529 if (page == HV_INTC_FC_PAGE_START)
3530 page = 0;
3531
3532 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3533 /* Page is shifted left, PHY expects (page x 32) */
3534 ret_val = e1000_set_page_igp(hw,
3535 (page << IGP_PAGE_SHIFT));
3536
3537 hw->phy.addr = phy_addr;
3538
3539 if (ret_val)
3540 goto out;
3541 }
3542 }
3543
3544 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3545 page << IGP_PAGE_SHIFT, reg);
3546
3547 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3548 data);
3549out:
3550 if (!locked)
3551 hw->phy.ops.release(hw);
3552
3553 return ret_val;
3554}
3555
3556/**
3557 * e1000_read_phy_reg_hv - Read HV PHY register
3558 * @hw: pointer to the HW structure
3559 * @offset: register offset to be read
3560 * @data: pointer to the read data
3561 *
3562 * Acquires semaphore then reads the PHY register at offset and stores
3563 * the retrieved information in data. Release the acquired semaphore
3564 * before exiting.
3565 **/
3566s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3567{
3568 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3569}
3570
3571/**
3572 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3573 * @hw: pointer to the HW structure
3574 * @offset: register offset to be read
3575 * @data: pointer to the read data
3576 *
3577 * Reads the PHY register at offset and stores the retrieved information
3578 * in data. Assumes semaphore already acquired.
3579 **/
3580s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3581{
3582 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3583}
3584
3585/**
3586 * e1000_read_phy_reg_page_hv - Read HV PHY register
3587 * @hw: pointer to the HW structure
3588 * @offset: register offset to write to
3589 * @data: data to write at register offset
3590 *
3591 * Reads the PHY register at offset and stores the retrieved information
3592 * in data. Assumes semaphore already acquired and page already set.
3593 **/
3594s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3595{
3596 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3597}
3598
3599/**
3600 * __e1000_write_phy_reg_hv - Write HV PHY register
3601 * @hw: pointer to the HW structure
3602 * @offset: register offset to write to
3603 * @data: data to write at register offset
3604 * @locked: semaphore has already been acquired or not
3605 *
3606 * Acquires semaphore, if necessary, then writes the data to PHY register
3607 * at the offset. Release any acquired semaphores before exiting.
3608 **/
3609static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3610 bool locked, bool page_set)
3611{
3612 s32 ret_val;
3613 u16 page = BM_PHY_REG_PAGE(offset);
3614 u16 reg = BM_PHY_REG_NUM(offset);
3615 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3616
3617 DEBUGFUNC("__e1000_write_phy_reg_hv");
3618
3619 if (!locked) {
3620 ret_val = hw->phy.ops.acquire(hw);
3621 if (ret_val)
3622 return ret_val;
3623 }
3624
3625 /* Page 800 works differently than the rest so it has its own func */
3626 if (page == BM_WUC_PAGE) {
3627 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3628 FALSE, page_set);
3629 goto out;
3630 }
3631
3632 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3633 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3634 &data, FALSE);
3635 goto out;
3636 }
3637
3638 if (!page_set) {
3639 if (page == HV_INTC_FC_PAGE_START)
3640 page = 0;
3641
3642 /*
3643 * Workaround MDIO accesses being disabled after entering IEEE
3644 * Power Down (when bit 11 of the PHY Control register is set)
3645 */
3646 if ((hw->phy.type == e1000_phy_82578) &&
3647 (hw->phy.revision >= 1) &&
3648 (hw->phy.addr == 2) &&
3649 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3650 (data & (1 << 11))) {
3651 u16 data2 = 0x7EFF;
3652 ret_val = e1000_access_phy_debug_regs_hv(hw,
3653 (1 << 6) | 0x3,
3654 &data2, FALSE);
3655 if (ret_val)
3656 goto out;
3657 }
3658
3659 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3660 /* Page is shifted left, PHY expects (page x 32) */
3661 ret_val = e1000_set_page_igp(hw,
3662 (page << IGP_PAGE_SHIFT));
3663
3664 hw->phy.addr = phy_addr;
3665
3666 if (ret_val)
3667 goto out;
3668 }
3669 }
3670
3671 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3672 page << IGP_PAGE_SHIFT, reg);
3673
3674 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3675 data);
3676
3677out:
3678 if (!locked)
3679 hw->phy.ops.release(hw);
3680
3681 return ret_val;
3682}
3683
3684/**
3685 * e1000_write_phy_reg_hv - Write HV PHY register
3686 * @hw: pointer to the HW structure
3687 * @offset: register offset to write to
3688 * @data: data to write at register offset
3689 *
3690 * Acquires semaphore then writes the data to PHY register at the offset.
3691 * Release the acquired semaphores before exiting.
3692 **/
3693s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3694{
3695 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
3696}
3697
3698/**
3699 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3700 * @hw: pointer to the HW structure
3701 * @offset: register offset to write to
3702 * @data: data to write at register offset
3703 *
3704 * Writes the data to PHY register at the offset. Assumes semaphore
3705 * already acquired.
3706 **/
3707s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3708{
3709 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3710}
3711
3712/**
3713 * e1000_write_phy_reg_page_hv - Write HV PHY register
3714 * @hw: pointer to the HW structure
3715 * @offset: register offset to write to
3716 * @data: data to write at register offset
3717 *
3718 * Writes the data to PHY register at the offset. Assumes semaphore
3719 * already acquired and page already set.
3720 **/
3721s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3722{
3723 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3724}
3725
3726/**
3727 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3728 * @page: page to be accessed
3729 **/
3730static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3731{
3732 u32 phy_addr = 2;
3733
3734 if (page >= HV_INTC_FC_PAGE_START)
3735 phy_addr = 1;
3736
3737 return phy_addr;
3738}
3739
3740/**
3741 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3742 * @hw: pointer to the HW structure
3743 * @offset: register offset to be read or written
3744 * @data: pointer to the data to be read or written
3745 * @read: determines if operation is read or write
3746 *
3747 * Reads the PHY register at offset and stores the retreived information
3748 * in data. Assumes semaphore already acquired. Note that the procedure
3749 * to access these regs uses the address port and data port to read/write.
3750 * These accesses done with PHY address 2 and without using pages.
3751 **/
3752static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3753 u16 *data, bool read)
3754{
3755 s32 ret_val;
3756 u32 addr_reg = 0;
3757 u32 data_reg = 0;
3758
3759 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3760
3761 /* This takes care of the difference with desktop vs mobile phy */
3762 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3763 I82578_ADDR_REG : I82577_ADDR_REG;
3764 data_reg = addr_reg + 1;
3765
3766 /* All operations in this function are phy address 2 */
3767 hw->phy.addr = 2;
3768
3769 /* masking with 0x3F to remove the page from offset */
3770 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3771 if (ret_val) {
3772 DEBUGOUT("Could not write the Address Offset port register\n");
3773 goto out;
3774 }
3775
3776 /* Read or write the data value next */
3777 if (read)
3778 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3779 else
3780 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3781
3782 if (ret_val) {
3783 DEBUGOUT("Could not access the Data port register\n");
3784 goto out;
3785 }
3786
3787out:
3788 return ret_val;
3789}
3790
3791/**
3792 * e1000_link_stall_workaround_hv - Si workaround
3793 * @hw: pointer to the HW structure
3794 *
3795 * This function works around a Si bug where the link partner can get
3796 * a link up indication before the PHY does. If small packets are sent
3797 * by the link partner they can be placed in the packet buffer without
3798 * being properly accounted for by the PHY and will stall preventing
3799 * further packets from being received. The workaround is to clear the
3800 * packet buffer after the PHY detects link up.
3801 **/
3802s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3803{
3804 s32 ret_val = E1000_SUCCESS;
3805 u16 data;
3806
3807 DEBUGFUNC("e1000_link_stall_workaround_hv");
3808
3809 if (hw->phy.type != e1000_phy_82578)
3810 goto out;
3811
3812 /* Do not apply workaround if in PHY loopback bit 14 set */
3813 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3814 if (data & PHY_CONTROL_LB)
3815 goto out;
3816
3817 /* check if link is up and at 1Gbps */
3818 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3819 if (ret_val)
3820 goto out;
3821
3822 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3823 BM_CS_STATUS_SPEED_MASK;
3824
3825 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3826 BM_CS_STATUS_SPEED_1000))
3827 goto out;
3828
3829 msec_delay(200);
3830
3831 /* flush the packets in the fifo buffer */
3832 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3833 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3834 HV_MUX_DATA_CTRL_FORCE_SPEED);
3835 if (ret_val)
3836 goto out;
3837
3838 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3839 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3840
3841out:
3842 return ret_val;
3843}
3844
3845/**
3846 * e1000_check_polarity_82577 - Checks the polarity.
3847 * @hw: pointer to the HW structure
3848 *
3849 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3850 *
3851 * Polarity is determined based on the PHY specific status register.
3852 **/
3853s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3854{
3855 struct e1000_phy_info *phy = &hw->phy;
3856 s32 ret_val;
3857 u16 data;
3858
3859 DEBUGFUNC("e1000_check_polarity_82577");
3860
3861 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3862
3863 if (!ret_val)
3864 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3865 ? e1000_rev_polarity_reversed
3866 : e1000_rev_polarity_normal;
3867
3868 return ret_val;
3869}
3870
3871/**
3872 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3873 * @hw: pointer to the HW structure
3874 *
3875 * Calls the PHY setup function to force speed and duplex.
3876 **/
3877s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3878{
3879 struct e1000_phy_info *phy = &hw->phy;
3880 s32 ret_val;
3881 u16 phy_data;
3882 bool link;
3883
3884 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3885
3886 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3887 if (ret_val)
3888 goto out;
3889
3890 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3891
3892 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3893 if (ret_val)
3894 goto out;
3895
3896 usec_delay(1);
3897
3898 if (phy->autoneg_wait_to_complete) {
3899 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3900
3901 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3902 100000, &link);
3903 if (ret_val)
3904 goto out;
3905
3906 if (!link)
3907 DEBUGOUT("Link taking longer than expected.\n");
3908
3909 /* Try once more */
3910 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3911 100000, &link);
3912 if (ret_val)
3913 goto out;
3914 }
3915
3916out:
3917 return ret_val;
3918}
3919
3920/**
3921 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3922 * @hw: pointer to the HW structure
3923 *
3924 * Read PHY status to determine if link is up. If link is up, then
3925 * set/determine 10base-T extended distance and polarity correction. Read
3926 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3927 * determine on the cable length, local and remote receiver.
3928 **/
3929s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3930{
3931 struct e1000_phy_info *phy = &hw->phy;
3932 s32 ret_val;
3933 u16 data;
3934 bool link;
3935
3936 DEBUGFUNC("e1000_get_phy_info_82577");
3937
3938 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3939 if (ret_val)
3940 goto out;
3941
3942 if (!link) {
3943 DEBUGOUT("Phy info is only valid if link is up\n");
3944 ret_val = -E1000_ERR_CONFIG;
3945 goto out;
3946 }
3947
3948 phy->polarity_correction = TRUE;
3949
3950 ret_val = e1000_check_polarity_82577(hw);
3951 if (ret_val)
3952 goto out;
3953
3954 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3955 if (ret_val)
3956 goto out;
3957
3958 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3959
3960 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3961 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3962 ret_val = hw->phy.ops.get_cable_length(hw);
3963 if (ret_val)
3964 goto out;
3965
3966 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3967 if (ret_val)
3968 goto out;
3969
3970 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3971 ? e1000_1000t_rx_status_ok
3972 : e1000_1000t_rx_status_not_ok;
3973
3974 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3975 ? e1000_1000t_rx_status_ok
3976 : e1000_1000t_rx_status_not_ok;
3977 } else {
3978 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3979 phy->local_rx = e1000_1000t_rx_status_undefined;
3980 phy->remote_rx = e1000_1000t_rx_status_undefined;
3981 }
3982
3983out:
3984 return ret_val;
3985}
3986
3987/**
3988 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3989 * @hw: pointer to the HW structure
3990 *
3991 * Reads the diagnostic status register and verifies result is valid before
3992 * placing it in the phy_cable_length field.
3993 **/
3994s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3995{
3996 struct e1000_phy_info *phy = &hw->phy;
3997 s32 ret_val;
3998 u16 phy_data, length;
3999
4000 DEBUGFUNC("e1000_get_cable_length_82577");
4001
4002 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4003 if (ret_val)
4004 goto out;
4005
4006 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4007 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
4008
4009 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4010 ret_val = -E1000_ERR_PHY;
4011
4012 phy->cable_length = length;
4013
4014out:
4015 return ret_val;
4016}