1/******************************************************************************
2
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
--- 13 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35#include "e1000_api.h"
36
37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
--- 48 unchanged lines hidden (view full) ---
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101}
102
103/**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 **/
107s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
--- 38 unchanged lines hidden (view full) ---
146 **/
147s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
148{
149 DEBUGFUNC("e1000_null_write_reg");
150 return E1000_SUCCESS;
151}
152
153/**
154 * e1000_check_reset_block_generic - Check if PHY reset is blocked
155 * @hw: pointer to the HW structure
156 *
157 * Read the PHY management control register and check whether a PHY reset
158 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
159 * return E1000_BLK_PHY_RESET (12).
160 **/
161s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
--- 19 unchanged lines hidden (view full) ---
181{
182 struct e1000_phy_info *phy = &hw->phy;
183 s32 ret_val = E1000_SUCCESS;
184 u16 phy_id;
185 u16 retry_count = 0;
186
187 DEBUGFUNC("e1000_get_phy_id");
188
189 if (!(phy->ops.read_reg))
190 goto out;
191
192 while (retry_count < 2) {
193 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
194 if (ret_val)
195 goto out;
196
197 phy->id = (u32)(phy_id << 16);
198 usec_delay(20);
199 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
200 if (ret_val)
201 goto out;
202
203 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
204 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
205
206 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
207 goto out;
208
209 retry_count++;
210 }
211out:
212 return ret_val;
213}
214
215/**
216 * e1000_phy_reset_dsp_generic - Reset PHY DSP
217 * @hw: pointer to the HW structure
218 *
219 * Reset the digital signal processor.
220 **/
221s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
222{
223 s32 ret_val = E1000_SUCCESS;
224
225 DEBUGFUNC("e1000_phy_reset_dsp_generic");
226
227 if (!(hw->phy.ops.write_reg))
228 goto out;
229
230 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
231 if (ret_val)
232 goto out;
233
234 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
235
236out:
237 return ret_val;
238}
239
240/**
241 * e1000_read_phy_reg_mdic - Read MDI control register
242 * @hw: pointer to the HW structure
243 * @offset: register offset to be read
244 * @data: pointer to the read data
245 *
246 * Reads the MDI control register in the PHY at offset and stores the
247 * information read to data.
248 **/
249s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
250{
251 struct e1000_phy_info *phy = &hw->phy;
252 u32 i, mdic = 0;
253 s32 ret_val = E1000_SUCCESS;
254
255 DEBUGFUNC("e1000_read_phy_reg_mdic");
256
257 if (offset > MAX_PHY_REG_ADDRESS) {
258 DEBUGOUT1("PHY Address %d is out of range\n", offset);
259 return -E1000_ERR_PARAM;
260 }
261
--- 16 unchanged lines hidden (view full) ---
278 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
279 usec_delay(50);
280 mdic = E1000_READ_REG(hw, E1000_MDIC);
281 if (mdic & E1000_MDIC_READY)
282 break;
283 }
284 if (!(mdic & E1000_MDIC_READY)) {
285 DEBUGOUT("MDI Read did not complete\n");
286 ret_val = -E1000_ERR_PHY;
287 goto out;
288 }
289 if (mdic & E1000_MDIC_ERROR) {
290 DEBUGOUT("MDI Error\n");
291 ret_val = -E1000_ERR_PHY;
292 goto out;
293 }
294 *data = (u16) mdic;
295
296 /*
297 * Allow some time after each MDIC transaction to avoid
298 * reading duplicate data in the next MDIC transaction.
299 */
300 if (hw->mac.type == e1000_pch2lan)
301 usec_delay(100);
302
303out:
304 return ret_val;
305}
306
307/**
308 * e1000_write_phy_reg_mdic - Write MDI control register
309 * @hw: pointer to the HW structure
310 * @offset: register offset to write to
311 * @data: data to write to register at offset
312 *
313 * Writes data to MDI control register in the PHY at offset.
314 **/
315s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
316{
317 struct e1000_phy_info *phy = &hw->phy;
318 u32 i, mdic = 0;
319 s32 ret_val = E1000_SUCCESS;
320
321 DEBUGFUNC("e1000_write_phy_reg_mdic");
322
323 if (offset > MAX_PHY_REG_ADDRESS) {
324 DEBUGOUT1("PHY Address %d is out of range\n", offset);
325 return -E1000_ERR_PARAM;
326 }
327
--- 17 unchanged lines hidden (view full) ---
345 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
346 usec_delay(50);
347 mdic = E1000_READ_REG(hw, E1000_MDIC);
348 if (mdic & E1000_MDIC_READY)
349 break;
350 }
351 if (!(mdic & E1000_MDIC_READY)) {
352 DEBUGOUT("MDI Write did not complete\n");
353 ret_val = -E1000_ERR_PHY;
354 goto out;
355 }
356 if (mdic & E1000_MDIC_ERROR) {
357 DEBUGOUT("MDI Error\n");
358 ret_val = -E1000_ERR_PHY;
359 goto out;
360 }
361
362 /*
363 * Allow some time after each MDIC transaction to avoid
364 * reading duplicate data in the next MDIC transaction.
365 */
366 if (hw->mac.type == e1000_pch2lan)
367 usec_delay(100);
368
369out:
370 return ret_val;
371}
372
373/**
374 * e1000_read_phy_reg_i2c - Read PHY register using i2c
375 * @hw: pointer to the HW structure
376 * @offset: register offset to be read
377 * @data: pointer to the read data
378 *
--- 237 unchanged lines hidden (view full) ---
616 * @data: pointer to the read data
617 *
618 * Acquires semaphore, if necessary, then reads the PHY register at offset
619 * and storing the retrieved information in data. Release any acquired
620 * semaphores before exiting.
621 **/
622s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
623{
624 s32 ret_val = E1000_SUCCESS;
625
626 DEBUGFUNC("e1000_read_phy_reg_m88");
627
628 if (!(hw->phy.ops.acquire))
629 goto out;
630
631 ret_val = hw->phy.ops.acquire(hw);
632 if (ret_val)
633 goto out;
634
635 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
636 data);
637
638 hw->phy.ops.release(hw);
639
640out:
641 return ret_val;
642}
643
644/**
645 * e1000_write_phy_reg_m88 - Write m88 PHY register
646 * @hw: pointer to the HW structure
647 * @offset: register offset to write to
648 * @data: data to write at register offset
649 *
650 * Acquires semaphore, if necessary, then writes the data to PHY register
651 * at the offset. Release any acquired semaphores before exiting.
652 **/
653s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
654{
655 s32 ret_val = E1000_SUCCESS;
656
657 DEBUGFUNC("e1000_write_phy_reg_m88");
658
659 if (!(hw->phy.ops.acquire))
660 goto out;
661
662 ret_val = hw->phy.ops.acquire(hw);
663 if (ret_val)
664 goto out;
665
666 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
667 data);
668
669 hw->phy.ops.release(hw);
670
671out:
672 return ret_val;
673}
674
675/**
676 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
677 * @hw: pointer to the HW structure
678 * @page: page to set (shifted left when necessary)
679 *
--- 26 unchanged lines hidden (view full) ---
706static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
707 bool locked)
708{
709 s32 ret_val = E1000_SUCCESS;
710
711 DEBUGFUNC("__e1000_read_phy_reg_igp");
712
713 if (!locked) {
714 if (!(hw->phy.ops.acquire))
715 goto out;
716
717 ret_val = hw->phy.ops.acquire(hw);
718 if (ret_val)
719 goto out;
720 }
721
722 if (offset > MAX_PHY_MULTI_PAGE_REG) {
723 ret_val = e1000_write_phy_reg_mdic(hw,
724 IGP01E1000_PHY_PAGE_SELECT,
725 (u16)offset);
726 if (ret_val)
727 goto release;
728 }
729
730 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
731 data);
732
733release:
734 if (!locked)
735 hw->phy.ops.release(hw);
736out:
737 return ret_val;
738}
739
740/**
741 * e1000_read_phy_reg_igp - Read igp PHY register
742 * @hw: pointer to the HW structure
743 * @offset: register offset to be read
744 * @data: pointer to the read data
--- 34 unchanged lines hidden (view full) ---
779static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
780 bool locked)
781{
782 s32 ret_val = E1000_SUCCESS;
783
784 DEBUGFUNC("e1000_write_phy_reg_igp");
785
786 if (!locked) {
787 if (!(hw->phy.ops.acquire))
788 goto out;
789
790 ret_val = hw->phy.ops.acquire(hw);
791 if (ret_val)
792 goto out;
793 }
794
795 if (offset > MAX_PHY_MULTI_PAGE_REG) {
796 ret_val = e1000_write_phy_reg_mdic(hw,
797 IGP01E1000_PHY_PAGE_SELECT,
798 (u16)offset);
799 if (ret_val)
800 goto release;
801 }
802
803 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
804 data);
805
806release:
807 if (!locked)
808 hw->phy.ops.release(hw);
809
810out:
811 return ret_val;
812}
813
814/**
815 * e1000_write_phy_reg_igp - Write igp PHY register
816 * @hw: pointer to the HW structure
817 * @offset: register offset to write to
818 * @data: data to write at register offset
--- 30 unchanged lines hidden (view full) ---
849 * Acquires semaphore, if necessary. Then reads the PHY register at offset
850 * using the kumeran interface. The information retrieved is stored in data.
851 * Release any acquired semaphores before exiting.
852 **/
853static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
854 bool locked)
855{
856 u32 kmrnctrlsta;
857 s32 ret_val = E1000_SUCCESS;
858
859 DEBUGFUNC("__e1000_read_kmrn_reg");
860
861 if (!locked) {
862 if (!(hw->phy.ops.acquire))
863 goto out;
864
865 ret_val = hw->phy.ops.acquire(hw);
866 if (ret_val)
867 goto out;
868 }
869
870 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
871 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
872 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
873 E1000_WRITE_FLUSH(hw);
874
875 usec_delay(2);
876
877 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
878 *data = (u16)kmrnctrlsta;
879
880 if (!locked)
881 hw->phy.ops.release(hw);
882
883out:
884 return ret_val;
885}
886
887/**
888 * e1000_read_kmrn_reg_generic - Read kumeran register
889 * @hw: pointer to the HW structure
890 * @offset: register offset to be read
891 * @data: pointer to the read data
892 *
--- 31 unchanged lines hidden (view full) ---
924 * Acquires semaphore, if necessary. Then write the data to PHY register
925 * at the offset using the kumeran interface. Release any acquired semaphores
926 * before exiting.
927 **/
928static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
929 bool locked)
930{
931 u32 kmrnctrlsta;
932 s32 ret_val = E1000_SUCCESS;
933
934 DEBUGFUNC("e1000_write_kmrn_reg_generic");
935
936 if (!locked) {
937 if (!(hw->phy.ops.acquire))
938 goto out;
939
940 ret_val = hw->phy.ops.acquire(hw);
941 if (ret_val)
942 goto out;
943 }
944
945 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
946 E1000_KMRNCTRLSTA_OFFSET) | data;
947 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
948 E1000_WRITE_FLUSH(hw);
949
950 usec_delay(2);
951
952 if (!locked)
953 hw->phy.ops.release(hw);
954
955out:
956 return ret_val;
957}
958
959/**
960 * e1000_write_kmrn_reg_generic - Write kumeran register
961 * @hw: pointer to the HW structure
962 * @offset: register offset to write to
963 * @data: data to write at register offset
964 *
--- 15 unchanged lines hidden (view full) ---
980 * Assumes semaphore already acquired.
981 **/
982s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
983{
984 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
985}
986
987/**
988 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
989 * @hw: pointer to the HW structure
990 *
991 * Sets up Carrier-sense on Transmit and downshift values.
992 **/
993s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
994{
995 s32 ret_val;
996 u16 phy_data;
997
998 DEBUGFUNC("e1000_copper_link_setup_82577");
999
1000 if (hw->phy.type == e1000_phy_82580) {
1001 ret_val = hw->phy.ops.reset(hw);
1002 if (ret_val) {
1003 DEBUGOUT("Error resetting the PHY.\n");
1004 goto out;
1005 }
1006 }
1007
1008 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1009 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1010 if (ret_val)
1011 goto out;
1012
1013 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1014
1015 /* Enable downshift */
1016 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1017
1018 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1019 if (ret_val)
1020 goto out;
1021
1022 /* Resolve Master/Slave mode */
1023 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1024 if (ret_val)
1025 goto out;
1026
1027 /* load defaults for future use */
1028 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1029 ((phy_data & CR_1000T_MS_VALUE) ?
1030 e1000_ms_force_master :
1031 e1000_ms_force_slave) : e1000_ms_auto;
1032
1033 switch (hw->phy.ms_type) {
1034 case e1000_ms_force_master:
1035 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1036 break;
1037 case e1000_ms_force_slave:
1038 phy_data |= CR_1000T_MS_ENABLE;
1039 phy_data &= ~(CR_1000T_MS_VALUE);
1040 break;
1041 case e1000_ms_auto:
1042 phy_data &= ~CR_1000T_MS_ENABLE;
1043 default:
1044 break;
1045 }
1046
1047 ret_val = hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1048 if (ret_val)
1049 goto out;
1050
1051out:
1052 return ret_val;
1053}
1054
1055/**
1056 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1057 * @hw: pointer to the HW structure
1058 *
1059 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1060 * and downshift values are set also.
--- 5 unchanged lines hidden (view full) ---
1066 u16 phy_data;
1067
1068 DEBUGFUNC("e1000_copper_link_setup_m88");
1069
1070
1071 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1072 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1073 if (ret_val)
1074 goto out;
1075
1076 /* For BM PHY this bit is downshift enable */
1077 if (phy->type != e1000_phy_bm)
1078 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1079
1080 /*
1081 * Options:
1082 * MDI/MDI-X = 0 (default)
--- 23 unchanged lines hidden (view full) ---
1106 /*
1107 * Options:
1108 * disable_polarity_correction = 0 (default)
1109 * Automatic Correction for Reversed Cable Polarity
1110 * 0 - Disabled
1111 * 1 - Enabled
1112 */
1113 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1114 if (phy->disable_polarity_correction == 1)
1115 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1116
1117 /* Enable downshift on BM (disabled by default) */
1118 if (phy->type == e1000_phy_bm)
1119 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1120
1121 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1122 if (ret_val)
1123 goto out;
1124
1125 if ((phy->type == e1000_phy_m88) &&
1126 (phy->revision < E1000_REVISION_4) &&
1127 (phy->id != BME1000_E_PHY_ID_R2)) {
1128 /*
1129 * Force TX_CLK in the Extended PHY Specific Control Register
1130 * to 25MHz clock.
1131 */
1132 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1133 &phy_data);
1134 if (ret_val)
1135 goto out;
1136
1137 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1138
1139 if ((phy->revision == E1000_REVISION_2) &&
1140 (phy->id == M88E1111_I_PHY_ID)) {
1141 /* 82573L PHY - set the downshift counter to 5x. */
1142 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1143 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1144 } else {
1145 /* Configure Master and Slave downshift values */
1146 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1147 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1148 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1149 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1150 }
1151 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152 phy_data);
1153 if (ret_val)
1154 goto out;
1155 }
1156
1157 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1158 /* Set PHY page 0, register 29 to 0x0003 */
1159 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1160 if (ret_val)
1161 goto out;
1162
1163 /* Set PHY page 0, register 30 to 0x0000 */
1164 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1165 if (ret_val)
1166 goto out;
1167 }
1168
1169 /* Commit the changes. */
1170 ret_val = phy->ops.commit(hw);
1171 if (ret_val) {
1172 DEBUGOUT("Error committing the PHY changes\n");
1173 goto out;
1174 }
1175
1176 if (phy->type == e1000_phy_82578) {
1177 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1178 &phy_data);
1179 if (ret_val)
1180 goto out;
1181
1182 /* 82578 PHY - set the downshift count to 1x. */
1183 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1184 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1185 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1186 phy_data);
1187 if (ret_val)
1188 goto out;
1189 }
1190
1191out:
1192 return ret_val;
1193}
1194
1195/**
1196 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1197 * @hw: pointer to the HW structure
1198 *
1199 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1200 * Also enables and sets the downshift parameters.
--- 5 unchanged lines hidden (view full) ---
1206 u16 phy_data;
1207
1208 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1209
1210
1211 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1212 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1213 if (ret_val)
1214 goto out;
1215
1216 /*
1217 * Options:
1218 * MDI/MDI-X = 0 (default)
1219 * 0 - Auto for all speeds
1220 * 1 - MDI mode
1221 * 2 - MDI-X mode
1222 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
--- 22 unchanged lines hidden (view full) ---
1245 /*
1246 * Options:
1247 * disable_polarity_correction = 0 (default)
1248 * Automatic Correction for Reversed Cable Polarity
1249 * 0 - Disabled
1250 * 1 - Enabled
1251 */
1252 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1253 if (phy->disable_polarity_correction == 1)
1254 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1255
1256 /* Enable downshift and setting it to X6 */
1257 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1258 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1259 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1260
1261 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1262 if (ret_val)
1263 goto out;
1264
1265 /* Commit the changes. */
1266 ret_val = phy->ops.commit(hw);
1267 if (ret_val) {
1268 DEBUGOUT("Error committing the PHY changes\n");
1269 goto out;
1270 }
1271
1272out:
1273 return ret_val;
1274}
1275
1276/**
1277 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1278 * @hw: pointer to the HW structure
1279 *
1280 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1281 * igp PHY's.
--- 5 unchanged lines hidden (view full) ---
1287 u16 data;
1288
1289 DEBUGFUNC("e1000_copper_link_setup_igp");
1290
1291
1292 ret_val = hw->phy.ops.reset(hw);
1293 if (ret_val) {
1294 DEBUGOUT("Error resetting the PHY.\n");
1295 goto out;
1296 }
1297
1298 /*
1299 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1300 * timeout issues when LFS is enabled.
1301 */
1302 msec_delay(100);
1303
1304 /*
1305 * The NVM settings will configure LPLU in D3 for
1306 * non-IGP1 PHYs.
1307 */
1308 if (phy->type == e1000_phy_igp) {
1309 /* disable lplu d3 during driver init */
1310 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1311 if (ret_val) {
1312 DEBUGOUT("Error Disabling LPLU D3\n");
1313 goto out;
1314 }
1315 }
1316
1317 /* disable lplu d0 during driver init */
1318 if (hw->phy.ops.set_d0_lplu_state) {
1319 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1320 if (ret_val) {
1321 DEBUGOUT("Error Disabling LPLU D0\n");
1322 goto out;
1323 }
1324 }
1325 /* Configure mdi-mdix settings */
1326 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1327 if (ret_val)
1328 goto out;
1329
1330 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1331
1332 switch (phy->mdix) {
1333 case 1:
1334 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1335 break;
1336 case 2:
1337 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1338 break;
1339 case 0:
1340 default:
1341 data |= IGP01E1000_PSCR_AUTO_MDIX;
1342 break;
1343 }
1344 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1345 if (ret_val)
1346 goto out;
1347
1348 /* set auto-master slave resolution settings */
1349 if (hw->mac.autoneg) {
1350 /*
1351 * when autonegotiation advertisement is only 1000Mbps then we
1352 * should disable SmartSpeed and enable Auto MasterSlave
1353 * resolution as hardware default.
1354 */
1355 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1356 /* Disable SmartSpeed */
1357 ret_val = phy->ops.read_reg(hw,
1358 IGP01E1000_PHY_PORT_CONFIG,
1359 &data);
1360 if (ret_val)
1361 goto out;
1362
1363 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1364 ret_val = phy->ops.write_reg(hw,
1365 IGP01E1000_PHY_PORT_CONFIG,
1366 data);
1367 if (ret_val)
1368 goto out;
1369
1370 /* Set auto Master/Slave resolution process */
1371 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1372 if (ret_val)
1373 goto out;
1374
1375 data &= ~CR_1000T_MS_ENABLE;
1376 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1377 if (ret_val)
1378 goto out;
1379 }
1380
1381 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1382 if (ret_val)
1383 goto out;
1384
1385 /* load defaults for future use */
1386 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1387 ((data & CR_1000T_MS_VALUE) ?
1388 e1000_ms_force_master :
1389 e1000_ms_force_slave) :
1390 e1000_ms_auto;
1391
1392 switch (phy->ms_type) {
1393 case e1000_ms_force_master:
1394 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1395 break;
1396 case e1000_ms_force_slave:
1397 data |= CR_1000T_MS_ENABLE;
1398 data &= ~(CR_1000T_MS_VALUE);
1399 break;
1400 case e1000_ms_auto:
1401 data &= ~CR_1000T_MS_ENABLE;
1402 default:
1403 break;
1404 }
1405 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1406 if (ret_val)
1407 goto out;
1408 }
1409
1410out:
1411 return ret_val;
1412}
1413
1414/**
1415 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1416 * @hw: pointer to the HW structure
1417 *
1418 * Performs initial bounds checking on autoneg advertisement parameter, then
1419 * configure to advertise the full capability. Setup the PHY to autoneg
1420 * and restart the negotiation process between the link partner. If
1421 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1422 **/
1423s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1424{
1425 struct e1000_phy_info *phy = &hw->phy;
1426 s32 ret_val;
1427 u16 phy_ctrl;
1428
1429 DEBUGFUNC("e1000_copper_link_autoneg");
1430
1431 /*
1432 * Perform some bounds checking on the autoneg advertisement
1433 * parameter.
1434 */
1435 phy->autoneg_advertised &= phy->autoneg_mask;
1436
1437 /*
1438 * If autoneg_advertised is zero, we assume it was not defaulted
1439 * by the calling code so we set to advertise full capability.
1440 */
1441 if (phy->autoneg_advertised == 0)
1442 phy->autoneg_advertised = phy->autoneg_mask;
1443
1444 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1445 ret_val = e1000_phy_setup_autoneg(hw);
1446 if (ret_val) {
1447 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1448 goto out;
1449 }
1450 DEBUGOUT("Restarting Auto-Neg\n");
1451
1452 /*
1453 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1454 * the Auto Neg Restart bit in the PHY control register.
1455 */
1456 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1457 if (ret_val)
1458 goto out;
1459
1460 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1461 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1462 if (ret_val)
1463 goto out;
1464
1465 /*
1466 * Does the user want to wait for Auto-Neg to complete here, or
1467 * check at a later time (for example, callback routine).
1468 */
1469 if (phy->autoneg_wait_to_complete) {
1470 ret_val = hw->mac.ops.wait_autoneg(hw);
1471 if (ret_val) {
1472 DEBUGOUT("Error while waiting for autoneg to complete\n");
1473 goto out;
1474 }
1475 }
1476
1477 hw->mac.get_link_status = TRUE;
1478
1479out:
1480 return ret_val;
1481}
1482
1483/**
1484 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1485 * @hw: pointer to the HW structure
1486 *
1487 * Reads the MII auto-neg advertisement register and/or the 1000T control
1488 * register and if the PHY is already setup for auto-negotiation, then
1489 * return successful. Otherwise, setup advertisement and flow control to
1490 * the appropriate values for the wanted auto-negotiation.
1491 **/
--- 6 unchanged lines hidden (view full) ---
1498
1499 DEBUGFUNC("e1000_phy_setup_autoneg");
1500
1501 phy->autoneg_advertised &= phy->autoneg_mask;
1502
1503 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1504 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1505 if (ret_val)
1506 goto out;
1507
1508 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1509 /* Read the MII 1000Base-T Control Register (Address 9). */
1510 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1511 &mii_1000t_ctrl_reg);
1512 if (ret_val)
1513 goto out;
1514 }
1515
1516 /*
1517 * Need to parse both autoneg_advertised and fc and set up
1518 * the appropriate PHY registers. First we will parse for
1519 * autoneg_advertised software override. Since we can advertise
1520 * a plethora of combinations, we need to check each bit
1521 * individually.
--- 97 unchanged lines hidden (view full) ---
1619 /*
1620 * Flow control (both Rx and Tx) is enabled by a software
1621 * over-ride.
1622 */
1623 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1624 break;
1625 default:
1626 DEBUGOUT("Flow control param set incorrectly\n");
1627 ret_val = -E1000_ERR_CONFIG;
1628 goto out;
1629 }
1630
1631 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1632 if (ret_val)
1633 goto out;
1634
1635 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1636
1637 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1638 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1639 mii_1000t_ctrl_reg);
1640 if (ret_val)
1641 goto out;
1642 }
1643
1644out:
1645 return ret_val;
1646}
1647
1648/**
1649 * e1000_setup_copper_link_generic - Configure copper link settings
1650 * @hw: pointer to the HW structure
1651 *
1652 * Calls the appropriate function to configure the link for auto-neg or forced
--- 10 unchanged lines hidden (view full) ---
1663
1664 if (hw->mac.autoneg) {
1665 /*
1666 * Setup autoneg and flow control advertisement and perform
1667 * autonegotiation.
1668 */
1669 ret_val = e1000_copper_link_autoneg(hw);
1670 if (ret_val)
1671 goto out;
1672 } else {
1673 /*
1674 * PHY will be set to 10H, 10F, 100H or 100F
1675 * depending on user settings.
1676 */
1677 DEBUGOUT("Forcing Speed and Duplex\n");
1678 ret_val = hw->phy.ops.force_speed_duplex(hw);
1679 if (ret_val) {
1680 DEBUGOUT("Error Forcing Speed and Duplex\n");
1681 goto out;
1682 }
1683 }
1684
1685 /*
1686 * Check link status. Wait up to 100 microseconds for link to become
1687 * valid.
1688 */
1689 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1690 &link);
1691 if (ret_val)
1692 goto out;
1693
1694 if (link) {
1695 DEBUGOUT("Valid link established!!!\n");
1696 e1000_config_collision_dist_generic(hw);
1697 ret_val = e1000_config_fc_after_link_up_generic(hw);
1698 } else {
1699 DEBUGOUT("Unable to establish link!!!\n");
1700 }
1701
1702out:
1703 return ret_val;
1704}
1705
1706/**
1707 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1708 * @hw: pointer to the HW structure
1709 *
1710 * Calls the PHY setup function to force speed and duplex. Clears the
--- 6 unchanged lines hidden (view full) ---
1717 s32 ret_val;
1718 u16 phy_data;
1719 bool link;
1720
1721 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1722
1723 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1724 if (ret_val)
1725 goto out;
1726
1727 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1728
1729 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1730 if (ret_val)
1731 goto out;
1732
1733 /*
1734 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1735 * forced whenever speed and duplex are forced.
1736 */
1737 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1738 if (ret_val)
1739 goto out;
1740
1741 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1742 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1743
1744 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1745 if (ret_val)
1746 goto out;
1747
1748 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1749
1750 usec_delay(1);
1751
1752 if (phy->autoneg_wait_to_complete) {
1753 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1754
1755 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1756 100000, &link);
1757 if (ret_val)
1758 goto out;
1759
1760 if (!link)
1761 DEBUGOUT("Link taking longer than expected.\n");
1762
1763 /* Try once more */
1764 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1765 100000, &link);
1766 if (ret_val)
1767 goto out;
1768 }
1769
1770out:
1771 return ret_val;
1772}
1773
1774/**
1775 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1776 * @hw: pointer to the HW structure
1777 *
1778 * Calls the PHY setup function to force speed and duplex. Clears the
--- 12 unchanged lines hidden (view full) ---
1791 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1792
1793 /*
1794 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1795 * forced whenever speed and duplex are forced.
1796 */
1797 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1798 if (ret_val)
1799 goto out;
1800
1801 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1802 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1803 if (ret_val)
1804 goto out;
1805
1806 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1807
1808 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1809 if (ret_val)
1810 goto out;
1811
1812 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1813
1814 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 /* Reset the phy to commit changes. */
1819 ret_val = hw->phy.ops.commit(hw);
1820 if (ret_val)
1821 goto out;
1822
1823 if (phy->autoneg_wait_to_complete) {
1824 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1825
1826 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1827 100000, &link);
1828 if (ret_val)
1829 goto out;
1830
1831 if (!link) {
1832 if (hw->phy.type != e1000_phy_m88 ||
1833 hw->phy.id == I347AT4_E_PHY_ID ||
1834 hw->phy.id == M88E1340M_E_PHY_ID ||
1835 hw->phy.id == M88E1112_E_PHY_ID) {
1836 DEBUGOUT("Link taking longer than expected.\n");
1837 } else {
1838 /*
1839 * We didn't get link.
1840 * Reset the DSP and cross our fingers.
1841 */
1842 ret_val = phy->ops.write_reg(hw,
1843 M88E1000_PHY_PAGE_SELECT,
1844 0x001d);
1845 if (ret_val)
1846 goto out;
1847 ret_val = e1000_phy_reset_dsp_generic(hw);
1848 if (ret_val)
1849 goto out;
1850 }
1851 }
1852
1853 /* Try once more */
1854 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1855 100000, &link);
1856 if (ret_val)
1857 goto out;
1858 }
1859
1860 if (hw->phy.type != e1000_phy_m88 ||
1861 hw->phy.id == I347AT4_E_PHY_ID ||
1862 hw->phy.id == M88E1340M_E_PHY_ID ||
1863 hw->phy.id == M88E1112_E_PHY_ID)
1864 goto out;
1865
1866 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1867 if (ret_val)
1868 goto out;
1869
1870 /*
1871 * Resetting the phy means we need to re-force TX_CLK in the
1872 * Extended PHY Specific Control Register to 25MHz clock from
1873 * the reset value of 2.5MHz.
1874 */
1875 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1876 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1877 if (ret_val)
1878 goto out;
1879
1880 /*
1881 * In addition, we must re-enable CRS on Tx for both half and full
1882 * duplex.
1883 */
1884 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1885 if (ret_val)
1886 goto out;
1887
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1889 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1890
1891out:
1892 return ret_val;
1893}
1894
1895/**
1896 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1897 * @hw: pointer to the HW structure
1898 *
1899 * Forces the speed and duplex settings of the PHY.
--- 6 unchanged lines hidden (view full) ---
1906 s32 ret_val;
1907 u16 data;
1908 bool link;
1909
1910 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1911
1912 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1913 if (ret_val)
1914 goto out;
1915
1916 e1000_phy_force_speed_duplex_setup(hw, &data);
1917
1918 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1919 if (ret_val)
1920 goto out;
1921
1922 /* Disable MDI-X support for 10/100 */
1923 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1924 if (ret_val)
1925 goto out;
1926
1927 data &= ~IFE_PMC_AUTO_MDIX;
1928 data &= ~IFE_PMC_FORCE_MDIX;
1929
1930 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1931 if (ret_val)
1932 goto out;
1933
1934 DEBUGOUT1("IFE PMC: %X\n", data);
1935
1936 usec_delay(1);
1937
1938 if (phy->autoneg_wait_to_complete) {
1939 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1940
1941 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1942 100000, &link);
1943 if (ret_val)
1944 goto out;
1945
1946 if (!link)
1947 DEBUGOUT("Link taking longer than expected.\n");
1948
1949 /* Try once more */
1950 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1951 100000, &link);
1952 if (ret_val)
1953 goto out;
1954 }
1955
1956out:
1957 return ret_val;
1958}
1959
1960/**
1961 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1962 * @hw: pointer to the HW structure
1963 * @phy_ctrl: pointer to current value of PHY_CONTROL
1964 *
1965 * Forces speed and duplex on the PHY by doing the following: disable flow
--- 43 unchanged lines hidden (view full) ---
2009 DEBUGOUT("Forcing 100mb\n");
2010 } else {
2011 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2012 *phy_ctrl |= MII_CR_SPEED_10;
2013 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2014 DEBUGOUT("Forcing 10mb\n");
2015 }
2016
2017 e1000_config_collision_dist_generic(hw);
2018
2019 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2020}
2021
2022/**
2023 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2024 * @hw: pointer to the HW structure
2025 * @active: boolean used to enable/disable lplu
--- 5 unchanged lines hidden (view full) ---
2031 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2032 * is used during Dx states where the power conservation is most important.
2033 * During driver activity, SmartSpeed should be enabled so performance is
2034 * maintained.
2035 **/
2036s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2037{
2038 struct e1000_phy_info *phy = &hw->phy;
2039 s32 ret_val = E1000_SUCCESS;
2040 u16 data;
2041
2042 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2043
2044 if (!(hw->phy.ops.read_reg))
2045 goto out;
2046
2047 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2048 if (ret_val)
2049 goto out;
2050
2051 if (!active) {
2052 data &= ~IGP02E1000_PM_D3_LPLU;
2053 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2054 data);
2055 if (ret_val)
2056 goto out;
2057 /*
2058 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2059 * during Dx states where the power conservation is most
2060 * important. During driver activity we should enable
2061 * SmartSpeed, so performance is maintained.
2062 */
2063 if (phy->smart_speed == e1000_smart_speed_on) {
2064 ret_val = phy->ops.read_reg(hw,
2065 IGP01E1000_PHY_PORT_CONFIG,
2066 &data);
2067 if (ret_val)
2068 goto out;
2069
2070 data |= IGP01E1000_PSCFR_SMART_SPEED;
2071 ret_val = phy->ops.write_reg(hw,
2072 IGP01E1000_PHY_PORT_CONFIG,
2073 data);
2074 if (ret_val)
2075 goto out;
2076 } else if (phy->smart_speed == e1000_smart_speed_off) {
2077 ret_val = phy->ops.read_reg(hw,
2078 IGP01E1000_PHY_PORT_CONFIG,
2079 &data);
2080 if (ret_val)
2081 goto out;
2082
2083 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2084 ret_val = phy->ops.write_reg(hw,
2085 IGP01E1000_PHY_PORT_CONFIG,
2086 data);
2087 if (ret_val)
2088 goto out;
2089 }
2090 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2091 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2092 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2093 data |= IGP02E1000_PM_D3_LPLU;
2094 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2095 data);
2096 if (ret_val)
2097 goto out;
2098
2099 /* When LPLU is enabled, we should disable SmartSpeed */
2100 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2101 &data);
2102 if (ret_val)
2103 goto out;
2104
2105 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2106 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2107 data);
2108 }
2109
2110out:
2111 return ret_val;
2112}
2113
2114/**
2115 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2116 * @hw: pointer to the HW structure
2117 *
2118 * Success returns 0, Failure returns 1
--- 4 unchanged lines hidden (view full) ---
2123{
2124 struct e1000_phy_info *phy = &hw->phy;
2125 s32 ret_val;
2126 u16 phy_data, offset, mask;
2127
2128 DEBUGFUNC("e1000_check_downshift_generic");
2129
2130 switch (phy->type) {
2131 case e1000_phy_m88:
2132 case e1000_phy_gg82563:
2133 case e1000_phy_bm:
2134 case e1000_phy_82578:
2135 offset = M88E1000_PHY_SPEC_STATUS;
2136 mask = M88E1000_PSSR_DOWNSHIFT;
2137 break;
2138 case e1000_phy_igp:
2139 case e1000_phy_igp_2:
2140 case e1000_phy_igp_3:
2141 offset = IGP01E1000_PHY_LINK_HEALTH;
2142 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2143 break;
2144 default:
2145 /* speed downshift not supported */
2146 phy->speed_downgraded = FALSE;
2147 ret_val = E1000_SUCCESS;
2148 goto out;
2149 }
2150
2151 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2152
2153 if (!ret_val)
2154 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
2155
2156out:
2157 return ret_val;
2158}
2159
2160/**
2161 * e1000_check_polarity_m88 - Checks the polarity.
2162 * @hw: pointer to the HW structure
2163 *
2164 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
--- 36 unchanged lines hidden (view full) ---
2201 DEBUGFUNC("e1000_check_polarity_igp");
2202
2203 /*
2204 * Polarity is determined based on the speed of
2205 * our connection.
2206 */
2207 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2208 if (ret_val)
2209 goto out;
2210
2211 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2212 IGP01E1000_PSSR_SPEED_1000MBPS) {
2213 offset = IGP01E1000_PHY_PCS_INIT_REG;
2214 mask = IGP01E1000_PHY_POLARITY_MASK;
2215 } else {
2216 /*
2217 * This really only applies to 10Mbps since
--- 5 unchanged lines hidden (view full) ---
2223
2224 ret_val = phy->ops.read_reg(hw, offset, &data);
2225
2226 if (!ret_val)
2227 phy->cable_polarity = (data & mask)
2228 ? e1000_rev_polarity_reversed
2229 : e1000_rev_polarity_normal;
2230
2231out:
2232 return ret_val;
2233}
2234
2235/**
2236 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2237 * @hw: pointer to the HW structure
2238 *
2239 * Polarity is determined on the polarity reversal feature being enabled.
--- 36 unchanged lines hidden (view full) ---
2276 **/
2277s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2278{
2279 s32 ret_val = E1000_SUCCESS;
2280 u16 i, phy_status;
2281
2282 DEBUGFUNC("e1000_wait_autoneg_generic");
2283
2284 if (!(hw->phy.ops.read_reg))
2285 return E1000_SUCCESS;
2286
2287 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2288 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2289 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2290 if (ret_val)
2291 break;
2292 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
--- 23 unchanged lines hidden (view full) ---
2316s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2317 u32 usec_interval, bool *success)
2318{
2319 s32 ret_val = E1000_SUCCESS;
2320 u16 i, phy_status;
2321
2322 DEBUGFUNC("e1000_phy_has_link_generic");
2323
2324 if (!(hw->phy.ops.read_reg))
2325 return E1000_SUCCESS;
2326
2327 for (i = 0; i < iterations; i++) {
2328 /*
2329 * Some PHYs require the PHY_STATUS register to be read
2330 * twice due to the link bit being sticky. No harm doing
2331 * it across the board.
2332 */
--- 11 unchanged lines hidden (view full) ---
2344 if (phy_status & MII_SR_LINK_STATUS)
2345 break;
2346 if (usec_interval >= 1000)
2347 msec_delay_irq(usec_interval/1000);
2348 else
2349 usec_delay(usec_interval);
2350 }
2351
2352 *success = (i < iterations) ? TRUE : FALSE;
2353
2354 return ret_val;
2355}
2356
2357/**
2358 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2359 * @hw: pointer to the HW structure
2360 *
--- 13 unchanged lines hidden (view full) ---
2374 struct e1000_phy_info *phy = &hw->phy;
2375 s32 ret_val;
2376 u16 phy_data, index;
2377
2378 DEBUGFUNC("e1000_get_cable_length_m88");
2379
2380 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2381 if (ret_val)
2382 goto out;
2383
2384 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2385 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2386 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2387 ret_val = -E1000_ERR_PHY;
2388 goto out;
2389 }
2390
2391 phy->min_cable_length = e1000_m88_cable_length_table[index];
2392 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2393
2394 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2395
2396out:
2397 return ret_val;
2398}
2399
2400s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2401{
2402 struct e1000_phy_info *phy = &hw->phy;
2403 s32 ret_val;
2404 u16 phy_data, phy_data2, index, default_page, is_cm;
2405
2406 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2407
2408 switch (hw->phy.id) {
2409 case M88E1340M_E_PHY_ID:
2410 case I347AT4_E_PHY_ID:
2411 /* Remember the original page select and set it to 7 */
2412 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2413 &default_page);
2414 if (ret_val)
2415 goto out;
2416
2417 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2418 if (ret_val)
2419 goto out;
2420
2421 /* Get cable length from PHY Cable Diagnostics Control Reg */
2422 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2423 &phy_data);
2424 if (ret_val)
2425 goto out;
2426
2427 /* Check if the unit of cable length is meters or cm */
2428 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2429 if (ret_val)
2430 goto out;
2431
2432 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2433
2434 /* Populate the phy structure with cable length in meters */
2435 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2436 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2437 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2438
2439 /* Reset the page select to its original value */
2440 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2441 default_page);
2442 if (ret_val)
2443 goto out;
2444 break;
2445 case M88E1112_E_PHY_ID:
2446 /* Remember the original page select and set it to 5 */
2447 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2448 &default_page);
2449 if (ret_val)
2450 goto out;
2451
2452 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2453 if (ret_val)
2454 goto out;
2455
2456 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2457 &phy_data);
2458 if (ret_val)
2459 goto out;
2460
2461 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2462 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2463 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2464 ret_val = -E1000_ERR_PHY;
2465 goto out;
2466 }
2467
2468 phy->min_cable_length = e1000_m88_cable_length_table[index];
2469 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2470
2471 phy->cable_length = (phy->min_cable_length +
2472 phy->max_cable_length) / 2;
2473
2474 /* Reset the page select to its original value */
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2476 default_page);
2477 if (ret_val)
2478 goto out;
2479
2480 break;
2481 default:
2482 ret_val = -E1000_ERR_PHY;
2483 goto out;
2484 }
2485
2486out:
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2492 * @hw: pointer to the HW structure
2493 *
2494 * The automatic gain control (agc) normalizes the amplitude of the
2495 * received signal, adjusting for the attenuation produced by the
2496 * cable. By reading the AGC registers, which represent the
2497 * combination of coarse and fine gain value, the value can be put
2498 * into a lookup table to obtain the approximate cable length
2499 * for each channel.
2500 **/
2501s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2502{
2503 struct e1000_phy_info *phy = &hw->phy;
2504 s32 ret_val = E1000_SUCCESS;
2505 u16 phy_data, i, agc_value = 0;
2506 u16 cur_agc_index, max_agc_index = 0;
2507 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2508 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2509 IGP02E1000_PHY_AGC_A,
2510 IGP02E1000_PHY_AGC_B,
2511 IGP02E1000_PHY_AGC_C,
2512 IGP02E1000_PHY_AGC_D
2513 };
2514
2515 DEBUGFUNC("e1000_get_cable_length_igp_2");
2516
2517 /* Read the AGC registers for all channels */
2518 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2519 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2520 if (ret_val)
2521 goto out;
2522
2523 /*
2524 * Getting bits 15:9, which represent the combination of
2525 * coarse and fine gain values. The result is a number
2526 * that can be put into the lookup table to obtain the
2527 * approximate cable length.
2528 */
2529 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2530 IGP02E1000_AGC_LENGTH_MASK;
2531
2532 /* Array index bound check. */
2533 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2534 (cur_agc_index == 0)) {
2535 ret_val = -E1000_ERR_PHY;
2536 goto out;
2537 }
2538
2539 /* Remove min & max AGC values from calculation. */
2540 if (e1000_igp_2_cable_length_table[min_agc_index] >
2541 e1000_igp_2_cable_length_table[cur_agc_index])
2542 min_agc_index = cur_agc_index;
2543 if (e1000_igp_2_cable_length_table[max_agc_index] <
2544 e1000_igp_2_cable_length_table[cur_agc_index])
2545 max_agc_index = cur_agc_index;
--- 7 unchanged lines hidden (view full) ---
2553
2554 /* Calculate cable length with the error range of +/- 10 meters. */
2555 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2556 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2557 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2558
2559 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2560
2561out:
2562 return ret_val;
2563}
2564
2565/**
2566 * e1000_get_phy_info_m88 - Retrieve PHY information
2567 * @hw: pointer to the HW structure
2568 *
2569 * Valid for only copper links. Read the PHY status register (sticky read)
2570 * to verify that link is up. Read the PHY special control register to
--- 7 unchanged lines hidden (view full) ---
2578 s32 ret_val;
2579 u16 phy_data;
2580 bool link;
2581
2582 DEBUGFUNC("e1000_get_phy_info_m88");
2583
2584 if (phy->media_type != e1000_media_type_copper) {
2585 DEBUGOUT("Phy info is only valid for copper media\n");
2586 ret_val = -E1000_ERR_CONFIG;
2587 goto out;
2588 }
2589
2590 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2591 if (ret_val)
2592 goto out;
2593
2594 if (!link) {
2595 DEBUGOUT("Phy info is only valid if link is up\n");
2596 ret_val = -E1000_ERR_CONFIG;
2597 goto out;
2598 }
2599
2600 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2601 if (ret_val)
2602 goto out;
2603
2604 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2605 ? TRUE : FALSE;
2606
2607 ret_val = e1000_check_polarity_m88(hw);
2608 if (ret_val)
2609 goto out;
2610
2611 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2612 if (ret_val)
2613 goto out;
2614
2615 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2616
2617 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2618 ret_val = hw->phy.ops.get_cable_length(hw);
2619 if (ret_val)
2620 goto out;
2621
2622 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2623 if (ret_val)
2624 goto out;
2625
2626 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2627 ? e1000_1000t_rx_status_ok
2628 : e1000_1000t_rx_status_not_ok;
2629
2630 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2631 ? e1000_1000t_rx_status_ok
2632 : e1000_1000t_rx_status_not_ok;
2633 } else {
2634 /* Set values to "undefined" */
2635 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2636 phy->local_rx = e1000_1000t_rx_status_undefined;
2637 phy->remote_rx = e1000_1000t_rx_status_undefined;
2638 }
2639
2640out:
2641 return ret_val;
2642}
2643
2644/**
2645 * e1000_get_phy_info_igp - Retrieve igp PHY information
2646 * @hw: pointer to the HW structure
2647 *
2648 * Read PHY status to determine if link is up. If link is up, then
--- 7 unchanged lines hidden (view full) ---
2656 s32 ret_val;
2657 u16 data;
2658 bool link;
2659
2660 DEBUGFUNC("e1000_get_phy_info_igp");
2661
2662 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2663 if (ret_val)
2664 goto out;
2665
2666 if (!link) {
2667 DEBUGOUT("Phy info is only valid if link is up\n");
2668 ret_val = -E1000_ERR_CONFIG;
2669 goto out;
2670 }
2671
2672 phy->polarity_correction = TRUE;
2673
2674 ret_val = e1000_check_polarity_igp(hw);
2675 if (ret_val)
2676 goto out;
2677
2678 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2679 if (ret_val)
2680 goto out;
2681
2682 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2683
2684 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2685 IGP01E1000_PSSR_SPEED_1000MBPS) {
2686 ret_val = phy->ops.get_cable_length(hw);
2687 if (ret_val)
2688 goto out;
2689
2690 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2691 if (ret_val)
2692 goto out;
2693
2694 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2695 ? e1000_1000t_rx_status_ok
2696 : e1000_1000t_rx_status_not_ok;
2697
2698 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2699 ? e1000_1000t_rx_status_ok
2700 : e1000_1000t_rx_status_not_ok;
2701 } else {
2702 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2703 phy->local_rx = e1000_1000t_rx_status_undefined;
2704 phy->remote_rx = e1000_1000t_rx_status_undefined;
2705 }
2706
2707out:
2708 return ret_val;
2709}
2710
2711/**
2712 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2713 * @hw: pointer to the HW structure
2714 *
2715 * Populates "phy" structure with various feature states.
--- 4 unchanged lines hidden (view full) ---
2720 s32 ret_val;
2721 u16 data;
2722 bool link;
2723
2724 DEBUGFUNC("e1000_get_phy_info_ife");
2725
2726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2727 if (ret_val)
2728 goto out;
2729
2730 if (!link) {
2731 DEBUGOUT("Phy info is only valid if link is up\n");
2732 ret_val = -E1000_ERR_CONFIG;
2733 goto out;
2734 }
2735
2736 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2737 if (ret_val)
2738 goto out;
2739 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2740 ? FALSE : TRUE;
2741
2742 if (phy->polarity_correction) {
2743 ret_val = e1000_check_polarity_ife(hw);
2744 if (ret_val)
2745 goto out;
2746 } else {
2747 /* Polarity is forced */
2748 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2749 ? e1000_rev_polarity_reversed
2750 : e1000_rev_polarity_normal;
2751 }
2752
2753 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2754 if (ret_val)
2755 goto out;
2756
2757 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2758
2759 /* The following parameters are undefined for 10/100 operation. */
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2763
2764out:
2765 return ret_val;
2766}
2767
2768/**
2769 * e1000_phy_sw_reset_generic - PHY software reset
2770 * @hw: pointer to the HW structure
2771 *
2772 * Does a software reset of the PHY by reading the PHY control register and
2773 * setting/write the control register reset bit to the PHY.
2774 **/
2775s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2776{
2777 s32 ret_val = E1000_SUCCESS;
2778 u16 phy_ctrl;
2779
2780 DEBUGFUNC("e1000_phy_sw_reset_generic");
2781
2782 if (!(hw->phy.ops.read_reg))
2783 goto out;
2784
2785 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2786 if (ret_val)
2787 goto out;
2788
2789 phy_ctrl |= MII_CR_RESET;
2790 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2791 if (ret_val)
2792 goto out;
2793
2794 usec_delay(1);
2795
2796out:
2797 return ret_val;
2798}
2799
2800/**
2801 * e1000_phy_hw_reset_generic - PHY hardware reset
2802 * @hw: pointer to the HW structure
2803 *
2804 * Verify the reset block is not blocking us from resetting. Acquire
2805 * semaphore (if necessary) and read/set/write the device control reset
2806 * bit in the PHY. Wait the appropriate delay time for the device to
2807 * reset and release the semaphore (if necessary).
2808 **/
2809s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2810{
2811 struct e1000_phy_info *phy = &hw->phy;
2812 s32 ret_val = E1000_SUCCESS;
2813 u32 ctrl;
2814
2815 DEBUGFUNC("e1000_phy_hw_reset_generic");
2816
2817 ret_val = phy->ops.check_reset_block(hw);
2818 if (ret_val) {
2819 ret_val = E1000_SUCCESS;
2820 goto out;
2821 }
2822
2823 ret_val = phy->ops.acquire(hw);
2824 if (ret_val)
2825 goto out;
2826
2827 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2828 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2829 E1000_WRITE_FLUSH(hw);
2830
2831 usec_delay(phy->reset_delay_us);
2832
2833 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2834 E1000_WRITE_FLUSH(hw);
2835
2836 usec_delay(150);
2837
2838 phy->ops.release(hw);
2839
2840 ret_val = phy->ops.get_cfg_done(hw);
2841
2842out:
2843 return ret_val;
2844}
2845
2846/**
2847 * e1000_get_cfg_done_generic - Generic configuration done
2848 * @hw: pointer to the HW structure
2849 *
2850 * Generic function to wait 10 milli-seconds for configuration to complete
2851 * and return success.
--- 137 unchanged lines hidden (view full) ---
2989 phy_type = e1000_phy_82577;
2990 break;
2991 case I82579_E_PHY_ID:
2992 phy_type = e1000_phy_82579;
2993 break;
2994 case I82580_I_PHY_ID:
2995 phy_type = e1000_phy_82580;
2996 break;
2997 default:
2998 phy_type = e1000_phy_unknown;
2999 break;
3000 }
3001 return phy_type;
3002}
3003
3004/**
3005 * e1000_determine_phy_address - Determines PHY address.
3006 * @hw: pointer to the HW structure
3007 *
3008 * This uses a trial and error method to loop through possible PHY
3009 * addresses. It tests each by reading the PHY ID registers and
3010 * checking for a match.
3011 **/
3012s32 e1000_determine_phy_address(struct e1000_hw *hw)
3013{
3014 s32 ret_val = -E1000_ERR_PHY_TYPE;
3015 u32 phy_addr = 0;
3016 u32 i;
3017 enum e1000_phy_type phy_type = e1000_phy_unknown;
3018
3019 hw->phy.id = phy_type;
3020
3021 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3022 hw->phy.addr = phy_addr;
3023 i = 0;
3024
3025 do {
3026 e1000_get_phy_id(hw);
3027 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3028
3029 /*
3030 * If phy_type is valid, break - we found our
3031 * PHY address
3032 */
3033 if (phy_type != e1000_phy_unknown) {
3034 ret_val = E1000_SUCCESS;
3035 goto out;
3036 }
3037 msec_delay(1);
3038 i++;
3039 } while (i < 10);
3040 }
3041
3042out:
3043 return ret_val;
3044}
3045
3046/**
3047 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3048 * @page: page to access
3049 *
3050 * Returns the phy address for the page requested.
3051 **/
--- 26 unchanged lines hidden (view full) ---
3078 ret_val = hw->phy.ops.acquire(hw);
3079 if (ret_val)
3080 return ret_val;
3081
3082 /* Page 800 works differently than the rest so it has its own func */
3083 if (page == BM_WUC_PAGE) {
3084 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3085 FALSE, FALSE);
3086 goto out;
3087 }
3088
3089 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3090
3091 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3092 u32 page_shift, page_select;
3093
3094 /*
--- 8 unchanged lines hidden (view full) ---
3103 page_shift = 0;
3104 page_select = BM_PHY_PAGE_SELECT;
3105 }
3106
3107 /* Page is shifted left, PHY expects (page x 32) */
3108 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3109 (page << page_shift));
3110 if (ret_val)
3111 goto out;
3112 }
3113
3114 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3115 data);
3116
3117out:
3118 hw->phy.ops.release(hw);
3119 return ret_val;
3120}
3121
3122/**
3123 * e1000_read_phy_reg_bm - Read BM PHY register
3124 * @hw: pointer to the HW structure
3125 * @offset: register offset to be read
--- 13 unchanged lines hidden (view full) ---
3139 ret_val = hw->phy.ops.acquire(hw);
3140 if (ret_val)
3141 return ret_val;
3142
3143 /* Page 800 works differently than the rest so it has its own func */
3144 if (page == BM_WUC_PAGE) {
3145 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3146 TRUE, FALSE);
3147 goto out;
3148 }
3149
3150 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3151
3152 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3153 u32 page_shift, page_select;
3154
3155 /*
--- 8 unchanged lines hidden (view full) ---
3164 page_shift = 0;
3165 page_select = BM_PHY_PAGE_SELECT;
3166 }
3167
3168 /* Page is shifted left, PHY expects (page x 32) */
3169 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3170 (page << page_shift));
3171 if (ret_val)
3172 goto out;
3173 }
3174
3175 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3176 data);
3177out:
3178 hw->phy.ops.release(hw);
3179 return ret_val;
3180}
3181
3182/**
3183 * e1000_read_phy_reg_bm2 - Read BM PHY register
3184 * @hw: pointer to the HW structure
3185 * @offset: register offset to be read
--- 13 unchanged lines hidden (view full) ---
3199 ret_val = hw->phy.ops.acquire(hw);
3200 if (ret_val)
3201 return ret_val;
3202
3203 /* Page 800 works differently than the rest so it has its own func */
3204 if (page == BM_WUC_PAGE) {
3205 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3206 TRUE, FALSE);
3207 goto out;
3208 }
3209
3210 hw->phy.addr = 1;
3211
3212 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3213
3214 /* Page is shifted left, PHY expects (page x 32) */
3215 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3216 page);
3217
3218 if (ret_val)
3219 goto out;
3220 }
3221
3222 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3223 data);
3224out:
3225 hw->phy.ops.release(hw);
3226 return ret_val;
3227}
3228
3229/**
3230 * e1000_write_phy_reg_bm2 - Write BM PHY register
3231 * @hw: pointer to the HW structure
3232 * @offset: register offset to write to
--- 12 unchanged lines hidden (view full) ---
3245 ret_val = hw->phy.ops.acquire(hw);
3246 if (ret_val)
3247 return ret_val;
3248
3249 /* Page 800 works differently than the rest so it has its own func */
3250 if (page == BM_WUC_PAGE) {
3251 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3252 FALSE, FALSE);
3253 goto out;
3254 }
3255
3256 hw->phy.addr = 1;
3257
3258 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3259 /* Page is shifted left, PHY expects (page x 32) */
3260 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3261 page);
3262
3263 if (ret_val)
3264 goto out;
3265 }
3266
3267 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3268 data);
3269
3270out:
3271 hw->phy.ops.release(hw);
3272 return ret_val;
3273}
3274
3275/**
3276 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3277 * @hw: pointer to the HW structure
3278 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3279 *
3280 * Assumes semaphore already acquired and phy_reg points to a valid memory
3281 * address to store contents of the BM_WUC_ENABLE_REG register.
3282 **/
3283s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3284{
3285 s32 ret_val;
3286 u16 temp;
3287
3288 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3289
3290 if (!phy_reg) {
3291 ret_val = -E1000_ERR_PARAM;
3292 goto out;
3293 }
3294
3295 /* All page select, port ctrl and wakeup registers use phy address 1 */
3296 hw->phy.addr = 1;
3297
3298 /* Select Port Control Registers page */
3299 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3300 if (ret_val) {
3301 DEBUGOUT("Could not set Port Control page\n");
3302 goto out;
3303 }
3304
3305 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3306 if (ret_val) {
3307 DEBUGOUT2("Could not read PHY register %d.%d\n",
3308 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3309 goto out;
3310 }
3311
3312 /*
3313 * Enable both PHY wakeup mode and Wakeup register page writes.
3314 * Prevent a power state change by disabling ME and Host PHY wakeup.
3315 */
3316 temp = *phy_reg;
3317 temp |= BM_WUC_ENABLE_BIT;
3318 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3319
3320 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3321 if (ret_val) {
3322 DEBUGOUT2("Could not write PHY register %d.%d\n",
3323 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3324 goto out;
3325 }
3326
3327 /* Select Host Wakeup Registers page */
3328 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3329
3330 /* caller now able to write registers on the Wakeup registers page */
3331out:
3332 return ret_val;
3333}
3334
3335/**
3336 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3337 * @hw: pointer to the HW structure
3338 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3339 *
3340 * Restore BM_WUC_ENABLE_REG to its original value.
--- 10 unchanged lines hidden (view full) ---
3351
3352 if (!phy_reg)
3353 return -E1000_ERR_PARAM;
3354
3355 /* Select Port Control Registers page */
3356 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3357 if (ret_val) {
3358 DEBUGOUT("Could not set Port Control page\n");
3359 goto out;
3360 }
3361
3362 /* Restore 769.17 to its original value */
3363 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3364 if (ret_val)
3365 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3366 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3367out:
3368 return ret_val;
3369}
3370
3371/**
3372 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3373 * @hw: pointer to the HW structure
3374 * @offset: register offset to be read or written
3375 * @data: pointer to the data to read or write
--- 32 unchanged lines hidden (view full) ---
3408 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3409 page);
3410
3411 if (!page_set) {
3412 /* Enable access to PHY wakeup registers */
3413 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3414 if (ret_val) {
3415 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3416 goto out;
3417 }
3418 }
3419
3420 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3421
3422 /* Write the Wakeup register page offset value using opcode 0x11 */
3423 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3424 if (ret_val) {
3425 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3426 goto out;
3427 }
3428
3429 if (read) {
3430 /* Read the Wakeup register page value using opcode 0x12 */
3431 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3432 data);
3433 } else {
3434 /* Write the Wakeup register page value using opcode 0x12 */
3435 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3436 *data);
3437 }
3438
3439 if (ret_val) {
3440 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3441 goto out;
3442 }
3443
3444 if (!page_set)
3445 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3446
3447out:
3448 return ret_val;
3449}
3450
3451/**
3452 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3453 * @hw: pointer to the HW structure
3454 *
3455 * In the case of a PHY power down to save power, or to turn off link during a
3456 * driver unload, or wake on lan is not enabled, restore the link to previous
3457 * settings.
3458 **/
3459void e1000_power_up_phy_copper(struct e1000_hw *hw)
3460{
3461 u16 mii_reg = 0;
3462
3463 /* The PHY will retain its settings across a power down/up cycle */
3464 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3465 mii_reg &= ~MII_CR_POWER_DOWN;
3466 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3467}
3468
3469/**
3470 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3471 * @hw: pointer to the HW structure
3472 *
3473 * In the case of a PHY power down to save power, or to turn off link during a
3474 * driver unload, or wake on lan is not enabled, restore the link to previous
3475 * settings.
3476 **/
3477void e1000_power_down_phy_copper(struct e1000_hw *hw)
3478{
3479 u16 mii_reg = 0;
3480
3481 /* The PHY will retain its settings across a power down/up cycle */
3482 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3483 mii_reg |= MII_CR_POWER_DOWN;
3484 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3485 msec_delay(1);
3486}
3487
3488/**
3489 * __e1000_read_phy_reg_hv - Read HV PHY register
3490 * @hw: pointer to the HW structure
3491 * @offset: register offset to be read
--- 149 unchanged lines hidden (view full) ---
3641
3642 /*
3643 * Workaround MDIO accesses being disabled after entering IEEE
3644 * Power Down (when bit 11 of the PHY Control register is set)
3645 */
3646 if ((hw->phy.type == e1000_phy_82578) &&
3647 (hw->phy.revision >= 1) &&
3648 (hw->phy.addr == 2) &&
3649 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3650 (data & (1 << 11))) {
3651 u16 data2 = 0x7EFF;
3652 ret_val = e1000_access_phy_debug_regs_hv(hw,
3653 (1 << 6) | 0x3,
3654 &data2, FALSE);
3655 if (ret_val)
3656 goto out;
3657 }
--- 107 unchanged lines hidden (view full) ---
3765
3766 /* All operations in this function are phy address 2 */
3767 hw->phy.addr = 2;
3768
3769 /* masking with 0x3F to remove the page from offset */
3770 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3771 if (ret_val) {
3772 DEBUGOUT("Could not write the Address Offset port register\n");
3773 goto out;
3774 }
3775
3776 /* Read or write the data value next */
3777 if (read)
3778 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3779 else
3780 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3781
3782 if (ret_val) {
3783 DEBUGOUT("Could not access the Data port register\n");
3784 goto out;
3785 }
3786
3787out:
3788 return ret_val;
3789}
3790
3791/**
3792 * e1000_link_stall_workaround_hv - Si workaround
3793 * @hw: pointer to the HW structure
3794 *
3795 * This function works around a Si bug where the link partner can get
--- 6 unchanged lines hidden (view full) ---
3802s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3803{
3804 s32 ret_val = E1000_SUCCESS;
3805 u16 data;
3806
3807 DEBUGFUNC("e1000_link_stall_workaround_hv");
3808
3809 if (hw->phy.type != e1000_phy_82578)
3810 goto out;
3811
3812 /* Do not apply workaround if in PHY loopback bit 14 set */
3813 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3814 if (data & PHY_CONTROL_LB)
3815 goto out;
3816
3817 /* check if link is up and at 1Gbps */
3818 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3819 if (ret_val)
3820 goto out;
3821
3822 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3823 BM_CS_STATUS_SPEED_MASK;
3824
3825 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3826 BM_CS_STATUS_SPEED_1000))
3827 goto out;
3828
3829 msec_delay(200);
3830
3831 /* flush the packets in the fifo buffer */
3832 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3833 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3834 HV_MUX_DATA_CTRL_FORCE_SPEED);
3835 if (ret_val)
3836 goto out;
3837
3838 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3839 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3840
3841out:
3842 return ret_val;
3843}
3844
3845/**
3846 * e1000_check_polarity_82577 - Checks the polarity.
3847 * @hw: pointer to the HW structure
3848 *
3849 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3850 *
--- 29 unchanged lines hidden (view full) ---
3880 s32 ret_val;
3881 u16 phy_data;
3882 bool link;
3883
3884 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3885
3886 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3887 if (ret_val)
3888 goto out;
3889
3890 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3891
3892 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3893 if (ret_val)
3894 goto out;
3895
3896 usec_delay(1);
3897
3898 if (phy->autoneg_wait_to_complete) {
3899 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3900
3901 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3902 100000, &link);
3903 if (ret_val)
3904 goto out;
3905
3906 if (!link)
3907 DEBUGOUT("Link taking longer than expected.\n");
3908
3909 /* Try once more */
3910 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3911 100000, &link);
3912 if (ret_val)
3913 goto out;
3914 }
3915
3916out:
3917 return ret_val;
3918}
3919
3920/**
3921 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3922 * @hw: pointer to the HW structure
3923 *
3924 * Read PHY status to determine if link is up. If link is up, then
--- 7 unchanged lines hidden (view full) ---
3932 s32 ret_val;
3933 u16 data;
3934 bool link;
3935
3936 DEBUGFUNC("e1000_get_phy_info_82577");
3937
3938 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3939 if (ret_val)
3940 goto out;
3941
3942 if (!link) {
3943 DEBUGOUT("Phy info is only valid if link is up\n");
3944 ret_val = -E1000_ERR_CONFIG;
3945 goto out;
3946 }
3947
3948 phy->polarity_correction = TRUE;
3949
3950 ret_val = e1000_check_polarity_82577(hw);
3951 if (ret_val)
3952 goto out;
3953
3954 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3955 if (ret_val)
3956 goto out;
3957
3958 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3959
3960 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3961 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3962 ret_val = hw->phy.ops.get_cable_length(hw);
3963 if (ret_val)
3964 goto out;
3965
3966 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3967 if (ret_val)
3968 goto out;
3969
3970 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3971 ? e1000_1000t_rx_status_ok
3972 : e1000_1000t_rx_status_not_ok;
3973
3974 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3975 ? e1000_1000t_rx_status_ok
3976 : e1000_1000t_rx_status_not_ok;
3977 } else {
3978 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3979 phy->local_rx = e1000_1000t_rx_status_undefined;
3980 phy->remote_rx = e1000_1000t_rx_status_undefined;
3981 }
3982
3983out:
3984 return ret_val;
3985}
3986
3987/**
3988 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3989 * @hw: pointer to the HW structure
3990 *
3991 * Reads the diagnostic status register and verifies result is valid before
3992 * placing it in the phy_cable_length field.
3993 **/
3994s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3995{
3996 struct e1000_phy_info *phy = &hw->phy;
3997 s32 ret_val;
3998 u16 phy_data, length;
3999
4000 DEBUGFUNC("e1000_get_cable_length_82577");
4001
4002 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4003 if (ret_val)
4004 goto out;
4005
4006 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4007 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
4008
4009 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4010 ret_val = -E1000_ERR_PHY;
4011
4012 phy->cable_length = length;
4013
4014out:
4015 return ret_val;
4016}
2
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
--- 13 unchanged lines hidden (view full) ---
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35#include "e1000_api.h"
36
37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
--- 48 unchanged lines hidden (view full) ---
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101}
102
103/**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 **/
107s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
--- 38 unchanged lines hidden (view full) ---
146 **/
147s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
148{
149 DEBUGFUNC("e1000_null_write_reg");
150 return E1000_SUCCESS;
151}
152
153/**
154 * e1000_check_reset_block_generic - Check if PHY reset is blocked
155 * @hw: pointer to the HW structure
156 *
157 * Read the PHY management control register and check whether a PHY reset
158 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
159 * return E1000_BLK_PHY_RESET (12).
160 **/
161s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
--- 19 unchanged lines hidden (view full) ---
181{
182 struct e1000_phy_info *phy = &hw->phy;
183 s32 ret_val = E1000_SUCCESS;
184 u16 phy_id;
185 u16 retry_count = 0;
186
187 DEBUGFUNC("e1000_get_phy_id");
188
189 if (!(phy->ops.read_reg))
190 goto out;
191
192 while (retry_count < 2) {
193 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
194 if (ret_val)
195 goto out;
196
197 phy->id = (u32)(phy_id << 16);
198 usec_delay(20);
199 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
200 if (ret_val)
201 goto out;
202
203 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
204 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
205
206 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
207 goto out;
208
209 retry_count++;
210 }
211out:
212 return ret_val;
213}
214
215/**
216 * e1000_phy_reset_dsp_generic - Reset PHY DSP
217 * @hw: pointer to the HW structure
218 *
219 * Reset the digital signal processor.
220 **/
221s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
222{
223 s32 ret_val = E1000_SUCCESS;
224
225 DEBUGFUNC("e1000_phy_reset_dsp_generic");
226
227 if (!(hw->phy.ops.write_reg))
228 goto out;
229
230 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
231 if (ret_val)
232 goto out;
233
234 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
235
236out:
237 return ret_val;
238}
239
240/**
241 * e1000_read_phy_reg_mdic - Read MDI control register
242 * @hw: pointer to the HW structure
243 * @offset: register offset to be read
244 * @data: pointer to the read data
245 *
246 * Reads the MDI control register in the PHY at offset and stores the
247 * information read to data.
248 **/
249s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
250{
251 struct e1000_phy_info *phy = &hw->phy;
252 u32 i, mdic = 0;
253 s32 ret_val = E1000_SUCCESS;
254
255 DEBUGFUNC("e1000_read_phy_reg_mdic");
256
257 if (offset > MAX_PHY_REG_ADDRESS) {
258 DEBUGOUT1("PHY Address %d is out of range\n", offset);
259 return -E1000_ERR_PARAM;
260 }
261
--- 16 unchanged lines hidden (view full) ---
278 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
279 usec_delay(50);
280 mdic = E1000_READ_REG(hw, E1000_MDIC);
281 if (mdic & E1000_MDIC_READY)
282 break;
283 }
284 if (!(mdic & E1000_MDIC_READY)) {
285 DEBUGOUT("MDI Read did not complete\n");
286 ret_val = -E1000_ERR_PHY;
287 goto out;
288 }
289 if (mdic & E1000_MDIC_ERROR) {
290 DEBUGOUT("MDI Error\n");
291 ret_val = -E1000_ERR_PHY;
292 goto out;
293 }
294 *data = (u16) mdic;
295
296 /*
297 * Allow some time after each MDIC transaction to avoid
298 * reading duplicate data in the next MDIC transaction.
299 */
300 if (hw->mac.type == e1000_pch2lan)
301 usec_delay(100);
302
303out:
304 return ret_val;
305}
306
307/**
308 * e1000_write_phy_reg_mdic - Write MDI control register
309 * @hw: pointer to the HW structure
310 * @offset: register offset to write to
311 * @data: data to write to register at offset
312 *
313 * Writes data to MDI control register in the PHY at offset.
314 **/
315s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
316{
317 struct e1000_phy_info *phy = &hw->phy;
318 u32 i, mdic = 0;
319 s32 ret_val = E1000_SUCCESS;
320
321 DEBUGFUNC("e1000_write_phy_reg_mdic");
322
323 if (offset > MAX_PHY_REG_ADDRESS) {
324 DEBUGOUT1("PHY Address %d is out of range\n", offset);
325 return -E1000_ERR_PARAM;
326 }
327
--- 17 unchanged lines hidden (view full) ---
345 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
346 usec_delay(50);
347 mdic = E1000_READ_REG(hw, E1000_MDIC);
348 if (mdic & E1000_MDIC_READY)
349 break;
350 }
351 if (!(mdic & E1000_MDIC_READY)) {
352 DEBUGOUT("MDI Write did not complete\n");
353 ret_val = -E1000_ERR_PHY;
354 goto out;
355 }
356 if (mdic & E1000_MDIC_ERROR) {
357 DEBUGOUT("MDI Error\n");
358 ret_val = -E1000_ERR_PHY;
359 goto out;
360 }
361
362 /*
363 * Allow some time after each MDIC transaction to avoid
364 * reading duplicate data in the next MDIC transaction.
365 */
366 if (hw->mac.type == e1000_pch2lan)
367 usec_delay(100);
368
369out:
370 return ret_val;
371}
372
373/**
374 * e1000_read_phy_reg_i2c - Read PHY register using i2c
375 * @hw: pointer to the HW structure
376 * @offset: register offset to be read
377 * @data: pointer to the read data
378 *
--- 237 unchanged lines hidden (view full) ---
616 * @data: pointer to the read data
617 *
618 * Acquires semaphore, if necessary, then reads the PHY register at offset
619 * and storing the retrieved information in data. Release any acquired
620 * semaphores before exiting.
621 **/
622s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
623{
624 s32 ret_val = E1000_SUCCESS;
625
626 DEBUGFUNC("e1000_read_phy_reg_m88");
627
628 if (!(hw->phy.ops.acquire))
629 goto out;
630
631 ret_val = hw->phy.ops.acquire(hw);
632 if (ret_val)
633 goto out;
634
635 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
636 data);
637
638 hw->phy.ops.release(hw);
639
640out:
641 return ret_val;
642}
643
644/**
645 * e1000_write_phy_reg_m88 - Write m88 PHY register
646 * @hw: pointer to the HW structure
647 * @offset: register offset to write to
648 * @data: data to write at register offset
649 *
650 * Acquires semaphore, if necessary, then writes the data to PHY register
651 * at the offset. Release any acquired semaphores before exiting.
652 **/
653s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
654{
655 s32 ret_val = E1000_SUCCESS;
656
657 DEBUGFUNC("e1000_write_phy_reg_m88");
658
659 if (!(hw->phy.ops.acquire))
660 goto out;
661
662 ret_val = hw->phy.ops.acquire(hw);
663 if (ret_val)
664 goto out;
665
666 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
667 data);
668
669 hw->phy.ops.release(hw);
670
671out:
672 return ret_val;
673}
674
675/**
676 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
677 * @hw: pointer to the HW structure
678 * @page: page to set (shifted left when necessary)
679 *
--- 26 unchanged lines hidden (view full) ---
706static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
707 bool locked)
708{
709 s32 ret_val = E1000_SUCCESS;
710
711 DEBUGFUNC("__e1000_read_phy_reg_igp");
712
713 if (!locked) {
714 if (!(hw->phy.ops.acquire))
715 goto out;
716
717 ret_val = hw->phy.ops.acquire(hw);
718 if (ret_val)
719 goto out;
720 }
721
722 if (offset > MAX_PHY_MULTI_PAGE_REG) {
723 ret_val = e1000_write_phy_reg_mdic(hw,
724 IGP01E1000_PHY_PAGE_SELECT,
725 (u16)offset);
726 if (ret_val)
727 goto release;
728 }
729
730 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
731 data);
732
733release:
734 if (!locked)
735 hw->phy.ops.release(hw);
736out:
737 return ret_val;
738}
739
740/**
741 * e1000_read_phy_reg_igp - Read igp PHY register
742 * @hw: pointer to the HW structure
743 * @offset: register offset to be read
744 * @data: pointer to the read data
--- 34 unchanged lines hidden (view full) ---
779static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
780 bool locked)
781{
782 s32 ret_val = E1000_SUCCESS;
783
784 DEBUGFUNC("e1000_write_phy_reg_igp");
785
786 if (!locked) {
787 if (!(hw->phy.ops.acquire))
788 goto out;
789
790 ret_val = hw->phy.ops.acquire(hw);
791 if (ret_val)
792 goto out;
793 }
794
795 if (offset > MAX_PHY_MULTI_PAGE_REG) {
796 ret_val = e1000_write_phy_reg_mdic(hw,
797 IGP01E1000_PHY_PAGE_SELECT,
798 (u16)offset);
799 if (ret_val)
800 goto release;
801 }
802
803 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
804 data);
805
806release:
807 if (!locked)
808 hw->phy.ops.release(hw);
809
810out:
811 return ret_val;
812}
813
814/**
815 * e1000_write_phy_reg_igp - Write igp PHY register
816 * @hw: pointer to the HW structure
817 * @offset: register offset to write to
818 * @data: data to write at register offset
--- 30 unchanged lines hidden (view full) ---
849 * Acquires semaphore, if necessary. Then reads the PHY register at offset
850 * using the kumeran interface. The information retrieved is stored in data.
851 * Release any acquired semaphores before exiting.
852 **/
853static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
854 bool locked)
855{
856 u32 kmrnctrlsta;
857 s32 ret_val = E1000_SUCCESS;
858
859 DEBUGFUNC("__e1000_read_kmrn_reg");
860
861 if (!locked) {
862 if (!(hw->phy.ops.acquire))
863 goto out;
864
865 ret_val = hw->phy.ops.acquire(hw);
866 if (ret_val)
867 goto out;
868 }
869
870 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
871 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
872 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
873 E1000_WRITE_FLUSH(hw);
874
875 usec_delay(2);
876
877 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
878 *data = (u16)kmrnctrlsta;
879
880 if (!locked)
881 hw->phy.ops.release(hw);
882
883out:
884 return ret_val;
885}
886
887/**
888 * e1000_read_kmrn_reg_generic - Read kumeran register
889 * @hw: pointer to the HW structure
890 * @offset: register offset to be read
891 * @data: pointer to the read data
892 *
--- 31 unchanged lines hidden (view full) ---
924 * Acquires semaphore, if necessary. Then write the data to PHY register
925 * at the offset using the kumeran interface. Release any acquired semaphores
926 * before exiting.
927 **/
928static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
929 bool locked)
930{
931 u32 kmrnctrlsta;
932 s32 ret_val = E1000_SUCCESS;
933
934 DEBUGFUNC("e1000_write_kmrn_reg_generic");
935
936 if (!locked) {
937 if (!(hw->phy.ops.acquire))
938 goto out;
939
940 ret_val = hw->phy.ops.acquire(hw);
941 if (ret_val)
942 goto out;
943 }
944
945 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
946 E1000_KMRNCTRLSTA_OFFSET) | data;
947 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
948 E1000_WRITE_FLUSH(hw);
949
950 usec_delay(2);
951
952 if (!locked)
953 hw->phy.ops.release(hw);
954
955out:
956 return ret_val;
957}
958
959/**
960 * e1000_write_kmrn_reg_generic - Write kumeran register
961 * @hw: pointer to the HW structure
962 * @offset: register offset to write to
963 * @data: data to write at register offset
964 *
--- 15 unchanged lines hidden (view full) ---
980 * Assumes semaphore already acquired.
981 **/
982s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
983{
984 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
985}
986
987/**
988 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
989 * @hw: pointer to the HW structure
990 *
991 * Sets up Carrier-sense on Transmit and downshift values.
992 **/
993s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
994{
995 s32 ret_val;
996 u16 phy_data;
997
998 DEBUGFUNC("e1000_copper_link_setup_82577");
999
1000 if (hw->phy.type == e1000_phy_82580) {
1001 ret_val = hw->phy.ops.reset(hw);
1002 if (ret_val) {
1003 DEBUGOUT("Error resetting the PHY.\n");
1004 goto out;
1005 }
1006 }
1007
1008 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1009 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1010 if (ret_val)
1011 goto out;
1012
1013 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1014
1015 /* Enable downshift */
1016 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1017
1018 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1019 if (ret_val)
1020 goto out;
1021
1022 /* Resolve Master/Slave mode */
1023 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1024 if (ret_val)
1025 goto out;
1026
1027 /* load defaults for future use */
1028 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1029 ((phy_data & CR_1000T_MS_VALUE) ?
1030 e1000_ms_force_master :
1031 e1000_ms_force_slave) : e1000_ms_auto;
1032
1033 switch (hw->phy.ms_type) {
1034 case e1000_ms_force_master:
1035 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1036 break;
1037 case e1000_ms_force_slave:
1038 phy_data |= CR_1000T_MS_ENABLE;
1039 phy_data &= ~(CR_1000T_MS_VALUE);
1040 break;
1041 case e1000_ms_auto:
1042 phy_data &= ~CR_1000T_MS_ENABLE;
1043 default:
1044 break;
1045 }
1046
1047 ret_val = hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1048 if (ret_val)
1049 goto out;
1050
1051out:
1052 return ret_val;
1053}
1054
1055/**
1056 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1057 * @hw: pointer to the HW structure
1058 *
1059 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1060 * and downshift values are set also.
--- 5 unchanged lines hidden (view full) ---
1066 u16 phy_data;
1067
1068 DEBUGFUNC("e1000_copper_link_setup_m88");
1069
1070
1071 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1072 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1073 if (ret_val)
1074 goto out;
1075
1076 /* For BM PHY this bit is downshift enable */
1077 if (phy->type != e1000_phy_bm)
1078 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1079
1080 /*
1081 * Options:
1082 * MDI/MDI-X = 0 (default)
--- 23 unchanged lines hidden (view full) ---
1106 /*
1107 * Options:
1108 * disable_polarity_correction = 0 (default)
1109 * Automatic Correction for Reversed Cable Polarity
1110 * 0 - Disabled
1111 * 1 - Enabled
1112 */
1113 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1114 if (phy->disable_polarity_correction == 1)
1115 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1116
1117 /* Enable downshift on BM (disabled by default) */
1118 if (phy->type == e1000_phy_bm)
1119 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1120
1121 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1122 if (ret_val)
1123 goto out;
1124
1125 if ((phy->type == e1000_phy_m88) &&
1126 (phy->revision < E1000_REVISION_4) &&
1127 (phy->id != BME1000_E_PHY_ID_R2)) {
1128 /*
1129 * Force TX_CLK in the Extended PHY Specific Control Register
1130 * to 25MHz clock.
1131 */
1132 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1133 &phy_data);
1134 if (ret_val)
1135 goto out;
1136
1137 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1138
1139 if ((phy->revision == E1000_REVISION_2) &&
1140 (phy->id == M88E1111_I_PHY_ID)) {
1141 /* 82573L PHY - set the downshift counter to 5x. */
1142 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1143 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1144 } else {
1145 /* Configure Master and Slave downshift values */
1146 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1147 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1148 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1149 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1150 }
1151 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152 phy_data);
1153 if (ret_val)
1154 goto out;
1155 }
1156
1157 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1158 /* Set PHY page 0, register 29 to 0x0003 */
1159 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1160 if (ret_val)
1161 goto out;
1162
1163 /* Set PHY page 0, register 30 to 0x0000 */
1164 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1165 if (ret_val)
1166 goto out;
1167 }
1168
1169 /* Commit the changes. */
1170 ret_val = phy->ops.commit(hw);
1171 if (ret_val) {
1172 DEBUGOUT("Error committing the PHY changes\n");
1173 goto out;
1174 }
1175
1176 if (phy->type == e1000_phy_82578) {
1177 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1178 &phy_data);
1179 if (ret_val)
1180 goto out;
1181
1182 /* 82578 PHY - set the downshift count to 1x. */
1183 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1184 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1185 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1186 phy_data);
1187 if (ret_val)
1188 goto out;
1189 }
1190
1191out:
1192 return ret_val;
1193}
1194
1195/**
1196 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1197 * @hw: pointer to the HW structure
1198 *
1199 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1200 * Also enables and sets the downshift parameters.
--- 5 unchanged lines hidden (view full) ---
1206 u16 phy_data;
1207
1208 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1209
1210
1211 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1212 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1213 if (ret_val)
1214 goto out;
1215
1216 /*
1217 * Options:
1218 * MDI/MDI-X = 0 (default)
1219 * 0 - Auto for all speeds
1220 * 1 - MDI mode
1221 * 2 - MDI-X mode
1222 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
--- 22 unchanged lines hidden (view full) ---
1245 /*
1246 * Options:
1247 * disable_polarity_correction = 0 (default)
1248 * Automatic Correction for Reversed Cable Polarity
1249 * 0 - Disabled
1250 * 1 - Enabled
1251 */
1252 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1253 if (phy->disable_polarity_correction == 1)
1254 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1255
1256 /* Enable downshift and setting it to X6 */
1257 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1258 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1259 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1260
1261 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1262 if (ret_val)
1263 goto out;
1264
1265 /* Commit the changes. */
1266 ret_val = phy->ops.commit(hw);
1267 if (ret_val) {
1268 DEBUGOUT("Error committing the PHY changes\n");
1269 goto out;
1270 }
1271
1272out:
1273 return ret_val;
1274}
1275
1276/**
1277 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1278 * @hw: pointer to the HW structure
1279 *
1280 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1281 * igp PHY's.
--- 5 unchanged lines hidden (view full) ---
1287 u16 data;
1288
1289 DEBUGFUNC("e1000_copper_link_setup_igp");
1290
1291
1292 ret_val = hw->phy.ops.reset(hw);
1293 if (ret_val) {
1294 DEBUGOUT("Error resetting the PHY.\n");
1295 goto out;
1296 }
1297
1298 /*
1299 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1300 * timeout issues when LFS is enabled.
1301 */
1302 msec_delay(100);
1303
1304 /*
1305 * The NVM settings will configure LPLU in D3 for
1306 * non-IGP1 PHYs.
1307 */
1308 if (phy->type == e1000_phy_igp) {
1309 /* disable lplu d3 during driver init */
1310 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1311 if (ret_val) {
1312 DEBUGOUT("Error Disabling LPLU D3\n");
1313 goto out;
1314 }
1315 }
1316
1317 /* disable lplu d0 during driver init */
1318 if (hw->phy.ops.set_d0_lplu_state) {
1319 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1320 if (ret_val) {
1321 DEBUGOUT("Error Disabling LPLU D0\n");
1322 goto out;
1323 }
1324 }
1325 /* Configure mdi-mdix settings */
1326 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1327 if (ret_val)
1328 goto out;
1329
1330 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1331
1332 switch (phy->mdix) {
1333 case 1:
1334 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1335 break;
1336 case 2:
1337 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1338 break;
1339 case 0:
1340 default:
1341 data |= IGP01E1000_PSCR_AUTO_MDIX;
1342 break;
1343 }
1344 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1345 if (ret_val)
1346 goto out;
1347
1348 /* set auto-master slave resolution settings */
1349 if (hw->mac.autoneg) {
1350 /*
1351 * when autonegotiation advertisement is only 1000Mbps then we
1352 * should disable SmartSpeed and enable Auto MasterSlave
1353 * resolution as hardware default.
1354 */
1355 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1356 /* Disable SmartSpeed */
1357 ret_val = phy->ops.read_reg(hw,
1358 IGP01E1000_PHY_PORT_CONFIG,
1359 &data);
1360 if (ret_val)
1361 goto out;
1362
1363 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1364 ret_val = phy->ops.write_reg(hw,
1365 IGP01E1000_PHY_PORT_CONFIG,
1366 data);
1367 if (ret_val)
1368 goto out;
1369
1370 /* Set auto Master/Slave resolution process */
1371 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1372 if (ret_val)
1373 goto out;
1374
1375 data &= ~CR_1000T_MS_ENABLE;
1376 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1377 if (ret_val)
1378 goto out;
1379 }
1380
1381 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1382 if (ret_val)
1383 goto out;
1384
1385 /* load defaults for future use */
1386 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1387 ((data & CR_1000T_MS_VALUE) ?
1388 e1000_ms_force_master :
1389 e1000_ms_force_slave) :
1390 e1000_ms_auto;
1391
1392 switch (phy->ms_type) {
1393 case e1000_ms_force_master:
1394 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1395 break;
1396 case e1000_ms_force_slave:
1397 data |= CR_1000T_MS_ENABLE;
1398 data &= ~(CR_1000T_MS_VALUE);
1399 break;
1400 case e1000_ms_auto:
1401 data &= ~CR_1000T_MS_ENABLE;
1402 default:
1403 break;
1404 }
1405 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1406 if (ret_val)
1407 goto out;
1408 }
1409
1410out:
1411 return ret_val;
1412}
1413
1414/**
1415 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1416 * @hw: pointer to the HW structure
1417 *
1418 * Performs initial bounds checking on autoneg advertisement parameter, then
1419 * configure to advertise the full capability. Setup the PHY to autoneg
1420 * and restart the negotiation process between the link partner. If
1421 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1422 **/
1423s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1424{
1425 struct e1000_phy_info *phy = &hw->phy;
1426 s32 ret_val;
1427 u16 phy_ctrl;
1428
1429 DEBUGFUNC("e1000_copper_link_autoneg");
1430
1431 /*
1432 * Perform some bounds checking on the autoneg advertisement
1433 * parameter.
1434 */
1435 phy->autoneg_advertised &= phy->autoneg_mask;
1436
1437 /*
1438 * If autoneg_advertised is zero, we assume it was not defaulted
1439 * by the calling code so we set to advertise full capability.
1440 */
1441 if (phy->autoneg_advertised == 0)
1442 phy->autoneg_advertised = phy->autoneg_mask;
1443
1444 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1445 ret_val = e1000_phy_setup_autoneg(hw);
1446 if (ret_val) {
1447 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1448 goto out;
1449 }
1450 DEBUGOUT("Restarting Auto-Neg\n");
1451
1452 /*
1453 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1454 * the Auto Neg Restart bit in the PHY control register.
1455 */
1456 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1457 if (ret_val)
1458 goto out;
1459
1460 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1461 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1462 if (ret_val)
1463 goto out;
1464
1465 /*
1466 * Does the user want to wait for Auto-Neg to complete here, or
1467 * check at a later time (for example, callback routine).
1468 */
1469 if (phy->autoneg_wait_to_complete) {
1470 ret_val = hw->mac.ops.wait_autoneg(hw);
1471 if (ret_val) {
1472 DEBUGOUT("Error while waiting for autoneg to complete\n");
1473 goto out;
1474 }
1475 }
1476
1477 hw->mac.get_link_status = TRUE;
1478
1479out:
1480 return ret_val;
1481}
1482
1483/**
1484 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1485 * @hw: pointer to the HW structure
1486 *
1487 * Reads the MII auto-neg advertisement register and/or the 1000T control
1488 * register and if the PHY is already setup for auto-negotiation, then
1489 * return successful. Otherwise, setup advertisement and flow control to
1490 * the appropriate values for the wanted auto-negotiation.
1491 **/
--- 6 unchanged lines hidden (view full) ---
1498
1499 DEBUGFUNC("e1000_phy_setup_autoneg");
1500
1501 phy->autoneg_advertised &= phy->autoneg_mask;
1502
1503 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1504 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1505 if (ret_val)
1506 goto out;
1507
1508 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1509 /* Read the MII 1000Base-T Control Register (Address 9). */
1510 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1511 &mii_1000t_ctrl_reg);
1512 if (ret_val)
1513 goto out;
1514 }
1515
1516 /*
1517 * Need to parse both autoneg_advertised and fc and set up
1518 * the appropriate PHY registers. First we will parse for
1519 * autoneg_advertised software override. Since we can advertise
1520 * a plethora of combinations, we need to check each bit
1521 * individually.
--- 97 unchanged lines hidden (view full) ---
1619 /*
1620 * Flow control (both Rx and Tx) is enabled by a software
1621 * over-ride.
1622 */
1623 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1624 break;
1625 default:
1626 DEBUGOUT("Flow control param set incorrectly\n");
1627 ret_val = -E1000_ERR_CONFIG;
1628 goto out;
1629 }
1630
1631 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1632 if (ret_val)
1633 goto out;
1634
1635 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1636
1637 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1638 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1639 mii_1000t_ctrl_reg);
1640 if (ret_val)
1641 goto out;
1642 }
1643
1644out:
1645 return ret_val;
1646}
1647
1648/**
1649 * e1000_setup_copper_link_generic - Configure copper link settings
1650 * @hw: pointer to the HW structure
1651 *
1652 * Calls the appropriate function to configure the link for auto-neg or forced
--- 10 unchanged lines hidden (view full) ---
1663
1664 if (hw->mac.autoneg) {
1665 /*
1666 * Setup autoneg and flow control advertisement and perform
1667 * autonegotiation.
1668 */
1669 ret_val = e1000_copper_link_autoneg(hw);
1670 if (ret_val)
1671 goto out;
1672 } else {
1673 /*
1674 * PHY will be set to 10H, 10F, 100H or 100F
1675 * depending on user settings.
1676 */
1677 DEBUGOUT("Forcing Speed and Duplex\n");
1678 ret_val = hw->phy.ops.force_speed_duplex(hw);
1679 if (ret_val) {
1680 DEBUGOUT("Error Forcing Speed and Duplex\n");
1681 goto out;
1682 }
1683 }
1684
1685 /*
1686 * Check link status. Wait up to 100 microseconds for link to become
1687 * valid.
1688 */
1689 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1690 &link);
1691 if (ret_val)
1692 goto out;
1693
1694 if (link) {
1695 DEBUGOUT("Valid link established!!!\n");
1696 e1000_config_collision_dist_generic(hw);
1697 ret_val = e1000_config_fc_after_link_up_generic(hw);
1698 } else {
1699 DEBUGOUT("Unable to establish link!!!\n");
1700 }
1701
1702out:
1703 return ret_val;
1704}
1705
1706/**
1707 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1708 * @hw: pointer to the HW structure
1709 *
1710 * Calls the PHY setup function to force speed and duplex. Clears the
--- 6 unchanged lines hidden (view full) ---
1717 s32 ret_val;
1718 u16 phy_data;
1719 bool link;
1720
1721 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1722
1723 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1724 if (ret_val)
1725 goto out;
1726
1727 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1728
1729 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1730 if (ret_val)
1731 goto out;
1732
1733 /*
1734 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1735 * forced whenever speed and duplex are forced.
1736 */
1737 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1738 if (ret_val)
1739 goto out;
1740
1741 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1742 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1743
1744 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1745 if (ret_val)
1746 goto out;
1747
1748 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1749
1750 usec_delay(1);
1751
1752 if (phy->autoneg_wait_to_complete) {
1753 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1754
1755 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1756 100000, &link);
1757 if (ret_val)
1758 goto out;
1759
1760 if (!link)
1761 DEBUGOUT("Link taking longer than expected.\n");
1762
1763 /* Try once more */
1764 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1765 100000, &link);
1766 if (ret_val)
1767 goto out;
1768 }
1769
1770out:
1771 return ret_val;
1772}
1773
1774/**
1775 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1776 * @hw: pointer to the HW structure
1777 *
1778 * Calls the PHY setup function to force speed and duplex. Clears the
--- 12 unchanged lines hidden (view full) ---
1791 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1792
1793 /*
1794 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1795 * forced whenever speed and duplex are forced.
1796 */
1797 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1798 if (ret_val)
1799 goto out;
1800
1801 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1802 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1803 if (ret_val)
1804 goto out;
1805
1806 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1807
1808 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1809 if (ret_val)
1810 goto out;
1811
1812 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1813
1814 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 /* Reset the phy to commit changes. */
1819 ret_val = hw->phy.ops.commit(hw);
1820 if (ret_val)
1821 goto out;
1822
1823 if (phy->autoneg_wait_to_complete) {
1824 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1825
1826 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1827 100000, &link);
1828 if (ret_val)
1829 goto out;
1830
1831 if (!link) {
1832 if (hw->phy.type != e1000_phy_m88 ||
1833 hw->phy.id == I347AT4_E_PHY_ID ||
1834 hw->phy.id == M88E1340M_E_PHY_ID ||
1835 hw->phy.id == M88E1112_E_PHY_ID) {
1836 DEBUGOUT("Link taking longer than expected.\n");
1837 } else {
1838 /*
1839 * We didn't get link.
1840 * Reset the DSP and cross our fingers.
1841 */
1842 ret_val = phy->ops.write_reg(hw,
1843 M88E1000_PHY_PAGE_SELECT,
1844 0x001d);
1845 if (ret_val)
1846 goto out;
1847 ret_val = e1000_phy_reset_dsp_generic(hw);
1848 if (ret_val)
1849 goto out;
1850 }
1851 }
1852
1853 /* Try once more */
1854 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1855 100000, &link);
1856 if (ret_val)
1857 goto out;
1858 }
1859
1860 if (hw->phy.type != e1000_phy_m88 ||
1861 hw->phy.id == I347AT4_E_PHY_ID ||
1862 hw->phy.id == M88E1340M_E_PHY_ID ||
1863 hw->phy.id == M88E1112_E_PHY_ID)
1864 goto out;
1865
1866 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1867 if (ret_val)
1868 goto out;
1869
1870 /*
1871 * Resetting the phy means we need to re-force TX_CLK in the
1872 * Extended PHY Specific Control Register to 25MHz clock from
1873 * the reset value of 2.5MHz.
1874 */
1875 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1876 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1877 if (ret_val)
1878 goto out;
1879
1880 /*
1881 * In addition, we must re-enable CRS on Tx for both half and full
1882 * duplex.
1883 */
1884 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1885 if (ret_val)
1886 goto out;
1887
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1889 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1890
1891out:
1892 return ret_val;
1893}
1894
1895/**
1896 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1897 * @hw: pointer to the HW structure
1898 *
1899 * Forces the speed and duplex settings of the PHY.
--- 6 unchanged lines hidden (view full) ---
1906 s32 ret_val;
1907 u16 data;
1908 bool link;
1909
1910 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1911
1912 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1913 if (ret_val)
1914 goto out;
1915
1916 e1000_phy_force_speed_duplex_setup(hw, &data);
1917
1918 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1919 if (ret_val)
1920 goto out;
1921
1922 /* Disable MDI-X support for 10/100 */
1923 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1924 if (ret_val)
1925 goto out;
1926
1927 data &= ~IFE_PMC_AUTO_MDIX;
1928 data &= ~IFE_PMC_FORCE_MDIX;
1929
1930 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1931 if (ret_val)
1932 goto out;
1933
1934 DEBUGOUT1("IFE PMC: %X\n", data);
1935
1936 usec_delay(1);
1937
1938 if (phy->autoneg_wait_to_complete) {
1939 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1940
1941 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1942 100000, &link);
1943 if (ret_val)
1944 goto out;
1945
1946 if (!link)
1947 DEBUGOUT("Link taking longer than expected.\n");
1948
1949 /* Try once more */
1950 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1951 100000, &link);
1952 if (ret_val)
1953 goto out;
1954 }
1955
1956out:
1957 return ret_val;
1958}
1959
1960/**
1961 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1962 * @hw: pointer to the HW structure
1963 * @phy_ctrl: pointer to current value of PHY_CONTROL
1964 *
1965 * Forces speed and duplex on the PHY by doing the following: disable flow
--- 43 unchanged lines hidden (view full) ---
2009 DEBUGOUT("Forcing 100mb\n");
2010 } else {
2011 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2012 *phy_ctrl |= MII_CR_SPEED_10;
2013 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2014 DEBUGOUT("Forcing 10mb\n");
2015 }
2016
2017 e1000_config_collision_dist_generic(hw);
2018
2019 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2020}
2021
2022/**
2023 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2024 * @hw: pointer to the HW structure
2025 * @active: boolean used to enable/disable lplu
--- 5 unchanged lines hidden (view full) ---
2031 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2032 * is used during Dx states where the power conservation is most important.
2033 * During driver activity, SmartSpeed should be enabled so performance is
2034 * maintained.
2035 **/
2036s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2037{
2038 struct e1000_phy_info *phy = &hw->phy;
2039 s32 ret_val = E1000_SUCCESS;
2040 u16 data;
2041
2042 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2043
2044 if (!(hw->phy.ops.read_reg))
2045 goto out;
2046
2047 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2048 if (ret_val)
2049 goto out;
2050
2051 if (!active) {
2052 data &= ~IGP02E1000_PM_D3_LPLU;
2053 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2054 data);
2055 if (ret_val)
2056 goto out;
2057 /*
2058 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2059 * during Dx states where the power conservation is most
2060 * important. During driver activity we should enable
2061 * SmartSpeed, so performance is maintained.
2062 */
2063 if (phy->smart_speed == e1000_smart_speed_on) {
2064 ret_val = phy->ops.read_reg(hw,
2065 IGP01E1000_PHY_PORT_CONFIG,
2066 &data);
2067 if (ret_val)
2068 goto out;
2069
2070 data |= IGP01E1000_PSCFR_SMART_SPEED;
2071 ret_val = phy->ops.write_reg(hw,
2072 IGP01E1000_PHY_PORT_CONFIG,
2073 data);
2074 if (ret_val)
2075 goto out;
2076 } else if (phy->smart_speed == e1000_smart_speed_off) {
2077 ret_val = phy->ops.read_reg(hw,
2078 IGP01E1000_PHY_PORT_CONFIG,
2079 &data);
2080 if (ret_val)
2081 goto out;
2082
2083 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2084 ret_val = phy->ops.write_reg(hw,
2085 IGP01E1000_PHY_PORT_CONFIG,
2086 data);
2087 if (ret_val)
2088 goto out;
2089 }
2090 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2091 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2092 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2093 data |= IGP02E1000_PM_D3_LPLU;
2094 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2095 data);
2096 if (ret_val)
2097 goto out;
2098
2099 /* When LPLU is enabled, we should disable SmartSpeed */
2100 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2101 &data);
2102 if (ret_val)
2103 goto out;
2104
2105 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2106 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2107 data);
2108 }
2109
2110out:
2111 return ret_val;
2112}
2113
2114/**
2115 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2116 * @hw: pointer to the HW structure
2117 *
2118 * Success returns 0, Failure returns 1
--- 4 unchanged lines hidden (view full) ---
2123{
2124 struct e1000_phy_info *phy = &hw->phy;
2125 s32 ret_val;
2126 u16 phy_data, offset, mask;
2127
2128 DEBUGFUNC("e1000_check_downshift_generic");
2129
2130 switch (phy->type) {
2131 case e1000_phy_m88:
2132 case e1000_phy_gg82563:
2133 case e1000_phy_bm:
2134 case e1000_phy_82578:
2135 offset = M88E1000_PHY_SPEC_STATUS;
2136 mask = M88E1000_PSSR_DOWNSHIFT;
2137 break;
2138 case e1000_phy_igp:
2139 case e1000_phy_igp_2:
2140 case e1000_phy_igp_3:
2141 offset = IGP01E1000_PHY_LINK_HEALTH;
2142 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2143 break;
2144 default:
2145 /* speed downshift not supported */
2146 phy->speed_downgraded = FALSE;
2147 ret_val = E1000_SUCCESS;
2148 goto out;
2149 }
2150
2151 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2152
2153 if (!ret_val)
2154 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
2155
2156out:
2157 return ret_val;
2158}
2159
2160/**
2161 * e1000_check_polarity_m88 - Checks the polarity.
2162 * @hw: pointer to the HW structure
2163 *
2164 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
--- 36 unchanged lines hidden (view full) ---
2201 DEBUGFUNC("e1000_check_polarity_igp");
2202
2203 /*
2204 * Polarity is determined based on the speed of
2205 * our connection.
2206 */
2207 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2208 if (ret_val)
2209 goto out;
2210
2211 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2212 IGP01E1000_PSSR_SPEED_1000MBPS) {
2213 offset = IGP01E1000_PHY_PCS_INIT_REG;
2214 mask = IGP01E1000_PHY_POLARITY_MASK;
2215 } else {
2216 /*
2217 * This really only applies to 10Mbps since
--- 5 unchanged lines hidden (view full) ---
2223
2224 ret_val = phy->ops.read_reg(hw, offset, &data);
2225
2226 if (!ret_val)
2227 phy->cable_polarity = (data & mask)
2228 ? e1000_rev_polarity_reversed
2229 : e1000_rev_polarity_normal;
2230
2231out:
2232 return ret_val;
2233}
2234
2235/**
2236 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2237 * @hw: pointer to the HW structure
2238 *
2239 * Polarity is determined on the polarity reversal feature being enabled.
--- 36 unchanged lines hidden (view full) ---
2276 **/
2277s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2278{
2279 s32 ret_val = E1000_SUCCESS;
2280 u16 i, phy_status;
2281
2282 DEBUGFUNC("e1000_wait_autoneg_generic");
2283
2284 if (!(hw->phy.ops.read_reg))
2285 return E1000_SUCCESS;
2286
2287 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2288 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2289 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2290 if (ret_val)
2291 break;
2292 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
--- 23 unchanged lines hidden (view full) ---
2316s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2317 u32 usec_interval, bool *success)
2318{
2319 s32 ret_val = E1000_SUCCESS;
2320 u16 i, phy_status;
2321
2322 DEBUGFUNC("e1000_phy_has_link_generic");
2323
2324 if (!(hw->phy.ops.read_reg))
2325 return E1000_SUCCESS;
2326
2327 for (i = 0; i < iterations; i++) {
2328 /*
2329 * Some PHYs require the PHY_STATUS register to be read
2330 * twice due to the link bit being sticky. No harm doing
2331 * it across the board.
2332 */
--- 11 unchanged lines hidden (view full) ---
2344 if (phy_status & MII_SR_LINK_STATUS)
2345 break;
2346 if (usec_interval >= 1000)
2347 msec_delay_irq(usec_interval/1000);
2348 else
2349 usec_delay(usec_interval);
2350 }
2351
2352 *success = (i < iterations) ? TRUE : FALSE;
2353
2354 return ret_val;
2355}
2356
2357/**
2358 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2359 * @hw: pointer to the HW structure
2360 *
--- 13 unchanged lines hidden (view full) ---
2374 struct e1000_phy_info *phy = &hw->phy;
2375 s32 ret_val;
2376 u16 phy_data, index;
2377
2378 DEBUGFUNC("e1000_get_cable_length_m88");
2379
2380 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2381 if (ret_val)
2382 goto out;
2383
2384 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2385 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2386 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2387 ret_val = -E1000_ERR_PHY;
2388 goto out;
2389 }
2390
2391 phy->min_cable_length = e1000_m88_cable_length_table[index];
2392 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2393
2394 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2395
2396out:
2397 return ret_val;
2398}
2399
2400s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2401{
2402 struct e1000_phy_info *phy = &hw->phy;
2403 s32 ret_val;
2404 u16 phy_data, phy_data2, index, default_page, is_cm;
2405
2406 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2407
2408 switch (hw->phy.id) {
2409 case M88E1340M_E_PHY_ID:
2410 case I347AT4_E_PHY_ID:
2411 /* Remember the original page select and set it to 7 */
2412 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2413 &default_page);
2414 if (ret_val)
2415 goto out;
2416
2417 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2418 if (ret_val)
2419 goto out;
2420
2421 /* Get cable length from PHY Cable Diagnostics Control Reg */
2422 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2423 &phy_data);
2424 if (ret_val)
2425 goto out;
2426
2427 /* Check if the unit of cable length is meters or cm */
2428 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2429 if (ret_val)
2430 goto out;
2431
2432 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2433
2434 /* Populate the phy structure with cable length in meters */
2435 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2436 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2437 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2438
2439 /* Reset the page select to its original value */
2440 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2441 default_page);
2442 if (ret_val)
2443 goto out;
2444 break;
2445 case M88E1112_E_PHY_ID:
2446 /* Remember the original page select and set it to 5 */
2447 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2448 &default_page);
2449 if (ret_val)
2450 goto out;
2451
2452 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2453 if (ret_val)
2454 goto out;
2455
2456 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2457 &phy_data);
2458 if (ret_val)
2459 goto out;
2460
2461 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2462 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2463 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2464 ret_val = -E1000_ERR_PHY;
2465 goto out;
2466 }
2467
2468 phy->min_cable_length = e1000_m88_cable_length_table[index];
2469 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2470
2471 phy->cable_length = (phy->min_cable_length +
2472 phy->max_cable_length) / 2;
2473
2474 /* Reset the page select to its original value */
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2476 default_page);
2477 if (ret_val)
2478 goto out;
2479
2480 break;
2481 default:
2482 ret_val = -E1000_ERR_PHY;
2483 goto out;
2484 }
2485
2486out:
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2492 * @hw: pointer to the HW structure
2493 *
2494 * The automatic gain control (agc) normalizes the amplitude of the
2495 * received signal, adjusting for the attenuation produced by the
2496 * cable. By reading the AGC registers, which represent the
2497 * combination of coarse and fine gain value, the value can be put
2498 * into a lookup table to obtain the approximate cable length
2499 * for each channel.
2500 **/
2501s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2502{
2503 struct e1000_phy_info *phy = &hw->phy;
2504 s32 ret_val = E1000_SUCCESS;
2505 u16 phy_data, i, agc_value = 0;
2506 u16 cur_agc_index, max_agc_index = 0;
2507 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2508 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2509 IGP02E1000_PHY_AGC_A,
2510 IGP02E1000_PHY_AGC_B,
2511 IGP02E1000_PHY_AGC_C,
2512 IGP02E1000_PHY_AGC_D
2513 };
2514
2515 DEBUGFUNC("e1000_get_cable_length_igp_2");
2516
2517 /* Read the AGC registers for all channels */
2518 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2519 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2520 if (ret_val)
2521 goto out;
2522
2523 /*
2524 * Getting bits 15:9, which represent the combination of
2525 * coarse and fine gain values. The result is a number
2526 * that can be put into the lookup table to obtain the
2527 * approximate cable length.
2528 */
2529 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2530 IGP02E1000_AGC_LENGTH_MASK;
2531
2532 /* Array index bound check. */
2533 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2534 (cur_agc_index == 0)) {
2535 ret_val = -E1000_ERR_PHY;
2536 goto out;
2537 }
2538
2539 /* Remove min & max AGC values from calculation. */
2540 if (e1000_igp_2_cable_length_table[min_agc_index] >
2541 e1000_igp_2_cable_length_table[cur_agc_index])
2542 min_agc_index = cur_agc_index;
2543 if (e1000_igp_2_cable_length_table[max_agc_index] <
2544 e1000_igp_2_cable_length_table[cur_agc_index])
2545 max_agc_index = cur_agc_index;
--- 7 unchanged lines hidden (view full) ---
2553
2554 /* Calculate cable length with the error range of +/- 10 meters. */
2555 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2556 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2557 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2558
2559 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2560
2561out:
2562 return ret_val;
2563}
2564
2565/**
2566 * e1000_get_phy_info_m88 - Retrieve PHY information
2567 * @hw: pointer to the HW structure
2568 *
2569 * Valid for only copper links. Read the PHY status register (sticky read)
2570 * to verify that link is up. Read the PHY special control register to
--- 7 unchanged lines hidden (view full) ---
2578 s32 ret_val;
2579 u16 phy_data;
2580 bool link;
2581
2582 DEBUGFUNC("e1000_get_phy_info_m88");
2583
2584 if (phy->media_type != e1000_media_type_copper) {
2585 DEBUGOUT("Phy info is only valid for copper media\n");
2586 ret_val = -E1000_ERR_CONFIG;
2587 goto out;
2588 }
2589
2590 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2591 if (ret_val)
2592 goto out;
2593
2594 if (!link) {
2595 DEBUGOUT("Phy info is only valid if link is up\n");
2596 ret_val = -E1000_ERR_CONFIG;
2597 goto out;
2598 }
2599
2600 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2601 if (ret_val)
2602 goto out;
2603
2604 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2605 ? TRUE : FALSE;
2606
2607 ret_val = e1000_check_polarity_m88(hw);
2608 if (ret_val)
2609 goto out;
2610
2611 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2612 if (ret_val)
2613 goto out;
2614
2615 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2616
2617 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2618 ret_val = hw->phy.ops.get_cable_length(hw);
2619 if (ret_val)
2620 goto out;
2621
2622 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2623 if (ret_val)
2624 goto out;
2625
2626 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2627 ? e1000_1000t_rx_status_ok
2628 : e1000_1000t_rx_status_not_ok;
2629
2630 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2631 ? e1000_1000t_rx_status_ok
2632 : e1000_1000t_rx_status_not_ok;
2633 } else {
2634 /* Set values to "undefined" */
2635 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2636 phy->local_rx = e1000_1000t_rx_status_undefined;
2637 phy->remote_rx = e1000_1000t_rx_status_undefined;
2638 }
2639
2640out:
2641 return ret_val;
2642}
2643
2644/**
2645 * e1000_get_phy_info_igp - Retrieve igp PHY information
2646 * @hw: pointer to the HW structure
2647 *
2648 * Read PHY status to determine if link is up. If link is up, then
--- 7 unchanged lines hidden (view full) ---
2656 s32 ret_val;
2657 u16 data;
2658 bool link;
2659
2660 DEBUGFUNC("e1000_get_phy_info_igp");
2661
2662 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2663 if (ret_val)
2664 goto out;
2665
2666 if (!link) {
2667 DEBUGOUT("Phy info is only valid if link is up\n");
2668 ret_val = -E1000_ERR_CONFIG;
2669 goto out;
2670 }
2671
2672 phy->polarity_correction = TRUE;
2673
2674 ret_val = e1000_check_polarity_igp(hw);
2675 if (ret_val)
2676 goto out;
2677
2678 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2679 if (ret_val)
2680 goto out;
2681
2682 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2683
2684 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2685 IGP01E1000_PSSR_SPEED_1000MBPS) {
2686 ret_val = phy->ops.get_cable_length(hw);
2687 if (ret_val)
2688 goto out;
2689
2690 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2691 if (ret_val)
2692 goto out;
2693
2694 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2695 ? e1000_1000t_rx_status_ok
2696 : e1000_1000t_rx_status_not_ok;
2697
2698 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2699 ? e1000_1000t_rx_status_ok
2700 : e1000_1000t_rx_status_not_ok;
2701 } else {
2702 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2703 phy->local_rx = e1000_1000t_rx_status_undefined;
2704 phy->remote_rx = e1000_1000t_rx_status_undefined;
2705 }
2706
2707out:
2708 return ret_val;
2709}
2710
2711/**
2712 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2713 * @hw: pointer to the HW structure
2714 *
2715 * Populates "phy" structure with various feature states.
--- 4 unchanged lines hidden (view full) ---
2720 s32 ret_val;
2721 u16 data;
2722 bool link;
2723
2724 DEBUGFUNC("e1000_get_phy_info_ife");
2725
2726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2727 if (ret_val)
2728 goto out;
2729
2730 if (!link) {
2731 DEBUGOUT("Phy info is only valid if link is up\n");
2732 ret_val = -E1000_ERR_CONFIG;
2733 goto out;
2734 }
2735
2736 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2737 if (ret_val)
2738 goto out;
2739 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2740 ? FALSE : TRUE;
2741
2742 if (phy->polarity_correction) {
2743 ret_val = e1000_check_polarity_ife(hw);
2744 if (ret_val)
2745 goto out;
2746 } else {
2747 /* Polarity is forced */
2748 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2749 ? e1000_rev_polarity_reversed
2750 : e1000_rev_polarity_normal;
2751 }
2752
2753 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2754 if (ret_val)
2755 goto out;
2756
2757 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2758
2759 /* The following parameters are undefined for 10/100 operation. */
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2763
2764out:
2765 return ret_val;
2766}
2767
2768/**
2769 * e1000_phy_sw_reset_generic - PHY software reset
2770 * @hw: pointer to the HW structure
2771 *
2772 * Does a software reset of the PHY by reading the PHY control register and
2773 * setting/write the control register reset bit to the PHY.
2774 **/
2775s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2776{
2777 s32 ret_val = E1000_SUCCESS;
2778 u16 phy_ctrl;
2779
2780 DEBUGFUNC("e1000_phy_sw_reset_generic");
2781
2782 if (!(hw->phy.ops.read_reg))
2783 goto out;
2784
2785 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2786 if (ret_val)
2787 goto out;
2788
2789 phy_ctrl |= MII_CR_RESET;
2790 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2791 if (ret_val)
2792 goto out;
2793
2794 usec_delay(1);
2795
2796out:
2797 return ret_val;
2798}
2799
2800/**
2801 * e1000_phy_hw_reset_generic - PHY hardware reset
2802 * @hw: pointer to the HW structure
2803 *
2804 * Verify the reset block is not blocking us from resetting. Acquire
2805 * semaphore (if necessary) and read/set/write the device control reset
2806 * bit in the PHY. Wait the appropriate delay time for the device to
2807 * reset and release the semaphore (if necessary).
2808 **/
2809s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2810{
2811 struct e1000_phy_info *phy = &hw->phy;
2812 s32 ret_val = E1000_SUCCESS;
2813 u32 ctrl;
2814
2815 DEBUGFUNC("e1000_phy_hw_reset_generic");
2816
2817 ret_val = phy->ops.check_reset_block(hw);
2818 if (ret_val) {
2819 ret_val = E1000_SUCCESS;
2820 goto out;
2821 }
2822
2823 ret_val = phy->ops.acquire(hw);
2824 if (ret_val)
2825 goto out;
2826
2827 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2828 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2829 E1000_WRITE_FLUSH(hw);
2830
2831 usec_delay(phy->reset_delay_us);
2832
2833 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2834 E1000_WRITE_FLUSH(hw);
2835
2836 usec_delay(150);
2837
2838 phy->ops.release(hw);
2839
2840 ret_val = phy->ops.get_cfg_done(hw);
2841
2842out:
2843 return ret_val;
2844}
2845
2846/**
2847 * e1000_get_cfg_done_generic - Generic configuration done
2848 * @hw: pointer to the HW structure
2849 *
2850 * Generic function to wait 10 milli-seconds for configuration to complete
2851 * and return success.
--- 137 unchanged lines hidden (view full) ---
2989 phy_type = e1000_phy_82577;
2990 break;
2991 case I82579_E_PHY_ID:
2992 phy_type = e1000_phy_82579;
2993 break;
2994 case I82580_I_PHY_ID:
2995 phy_type = e1000_phy_82580;
2996 break;
2997 default:
2998 phy_type = e1000_phy_unknown;
2999 break;
3000 }
3001 return phy_type;
3002}
3003
3004/**
3005 * e1000_determine_phy_address - Determines PHY address.
3006 * @hw: pointer to the HW structure
3007 *
3008 * This uses a trial and error method to loop through possible PHY
3009 * addresses. It tests each by reading the PHY ID registers and
3010 * checking for a match.
3011 **/
3012s32 e1000_determine_phy_address(struct e1000_hw *hw)
3013{
3014 s32 ret_val = -E1000_ERR_PHY_TYPE;
3015 u32 phy_addr = 0;
3016 u32 i;
3017 enum e1000_phy_type phy_type = e1000_phy_unknown;
3018
3019 hw->phy.id = phy_type;
3020
3021 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3022 hw->phy.addr = phy_addr;
3023 i = 0;
3024
3025 do {
3026 e1000_get_phy_id(hw);
3027 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3028
3029 /*
3030 * If phy_type is valid, break - we found our
3031 * PHY address
3032 */
3033 if (phy_type != e1000_phy_unknown) {
3034 ret_val = E1000_SUCCESS;
3035 goto out;
3036 }
3037 msec_delay(1);
3038 i++;
3039 } while (i < 10);
3040 }
3041
3042out:
3043 return ret_val;
3044}
3045
3046/**
3047 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3048 * @page: page to access
3049 *
3050 * Returns the phy address for the page requested.
3051 **/
--- 26 unchanged lines hidden (view full) ---
3078 ret_val = hw->phy.ops.acquire(hw);
3079 if (ret_val)
3080 return ret_val;
3081
3082 /* Page 800 works differently than the rest so it has its own func */
3083 if (page == BM_WUC_PAGE) {
3084 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3085 FALSE, FALSE);
3086 goto out;
3087 }
3088
3089 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3090
3091 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3092 u32 page_shift, page_select;
3093
3094 /*
--- 8 unchanged lines hidden (view full) ---
3103 page_shift = 0;
3104 page_select = BM_PHY_PAGE_SELECT;
3105 }
3106
3107 /* Page is shifted left, PHY expects (page x 32) */
3108 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3109 (page << page_shift));
3110 if (ret_val)
3111 goto out;
3112 }
3113
3114 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3115 data);
3116
3117out:
3118 hw->phy.ops.release(hw);
3119 return ret_val;
3120}
3121
3122/**
3123 * e1000_read_phy_reg_bm - Read BM PHY register
3124 * @hw: pointer to the HW structure
3125 * @offset: register offset to be read
--- 13 unchanged lines hidden (view full) ---
3139 ret_val = hw->phy.ops.acquire(hw);
3140 if (ret_val)
3141 return ret_val;
3142
3143 /* Page 800 works differently than the rest so it has its own func */
3144 if (page == BM_WUC_PAGE) {
3145 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3146 TRUE, FALSE);
3147 goto out;
3148 }
3149
3150 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3151
3152 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3153 u32 page_shift, page_select;
3154
3155 /*
--- 8 unchanged lines hidden (view full) ---
3164 page_shift = 0;
3165 page_select = BM_PHY_PAGE_SELECT;
3166 }
3167
3168 /* Page is shifted left, PHY expects (page x 32) */
3169 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3170 (page << page_shift));
3171 if (ret_val)
3172 goto out;
3173 }
3174
3175 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3176 data);
3177out:
3178 hw->phy.ops.release(hw);
3179 return ret_val;
3180}
3181
3182/**
3183 * e1000_read_phy_reg_bm2 - Read BM PHY register
3184 * @hw: pointer to the HW structure
3185 * @offset: register offset to be read
--- 13 unchanged lines hidden (view full) ---
3199 ret_val = hw->phy.ops.acquire(hw);
3200 if (ret_val)
3201 return ret_val;
3202
3203 /* Page 800 works differently than the rest so it has its own func */
3204 if (page == BM_WUC_PAGE) {
3205 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3206 TRUE, FALSE);
3207 goto out;
3208 }
3209
3210 hw->phy.addr = 1;
3211
3212 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3213
3214 /* Page is shifted left, PHY expects (page x 32) */
3215 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3216 page);
3217
3218 if (ret_val)
3219 goto out;
3220 }
3221
3222 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3223 data);
3224out:
3225 hw->phy.ops.release(hw);
3226 return ret_val;
3227}
3228
3229/**
3230 * e1000_write_phy_reg_bm2 - Write BM PHY register
3231 * @hw: pointer to the HW structure
3232 * @offset: register offset to write to
--- 12 unchanged lines hidden (view full) ---
3245 ret_val = hw->phy.ops.acquire(hw);
3246 if (ret_val)
3247 return ret_val;
3248
3249 /* Page 800 works differently than the rest so it has its own func */
3250 if (page == BM_WUC_PAGE) {
3251 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3252 FALSE, FALSE);
3253 goto out;
3254 }
3255
3256 hw->phy.addr = 1;
3257
3258 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3259 /* Page is shifted left, PHY expects (page x 32) */
3260 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3261 page);
3262
3263 if (ret_val)
3264 goto out;
3265 }
3266
3267 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3268 data);
3269
3270out:
3271 hw->phy.ops.release(hw);
3272 return ret_val;
3273}
3274
3275/**
3276 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3277 * @hw: pointer to the HW structure
3278 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3279 *
3280 * Assumes semaphore already acquired and phy_reg points to a valid memory
3281 * address to store contents of the BM_WUC_ENABLE_REG register.
3282 **/
3283s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3284{
3285 s32 ret_val;
3286 u16 temp;
3287
3288 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3289
3290 if (!phy_reg) {
3291 ret_val = -E1000_ERR_PARAM;
3292 goto out;
3293 }
3294
3295 /* All page select, port ctrl and wakeup registers use phy address 1 */
3296 hw->phy.addr = 1;
3297
3298 /* Select Port Control Registers page */
3299 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3300 if (ret_val) {
3301 DEBUGOUT("Could not set Port Control page\n");
3302 goto out;
3303 }
3304
3305 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3306 if (ret_val) {
3307 DEBUGOUT2("Could not read PHY register %d.%d\n",
3308 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3309 goto out;
3310 }
3311
3312 /*
3313 * Enable both PHY wakeup mode and Wakeup register page writes.
3314 * Prevent a power state change by disabling ME and Host PHY wakeup.
3315 */
3316 temp = *phy_reg;
3317 temp |= BM_WUC_ENABLE_BIT;
3318 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3319
3320 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3321 if (ret_val) {
3322 DEBUGOUT2("Could not write PHY register %d.%d\n",
3323 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3324 goto out;
3325 }
3326
3327 /* Select Host Wakeup Registers page */
3328 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3329
3330 /* caller now able to write registers on the Wakeup registers page */
3331out:
3332 return ret_val;
3333}
3334
3335/**
3336 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3337 * @hw: pointer to the HW structure
3338 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3339 *
3340 * Restore BM_WUC_ENABLE_REG to its original value.
--- 10 unchanged lines hidden (view full) ---
3351
3352 if (!phy_reg)
3353 return -E1000_ERR_PARAM;
3354
3355 /* Select Port Control Registers page */
3356 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3357 if (ret_val) {
3358 DEBUGOUT("Could not set Port Control page\n");
3359 goto out;
3360 }
3361
3362 /* Restore 769.17 to its original value */
3363 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3364 if (ret_val)
3365 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3366 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3367out:
3368 return ret_val;
3369}
3370
3371/**
3372 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3373 * @hw: pointer to the HW structure
3374 * @offset: register offset to be read or written
3375 * @data: pointer to the data to read or write
--- 32 unchanged lines hidden (view full) ---
3408 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3409 page);
3410
3411 if (!page_set) {
3412 /* Enable access to PHY wakeup registers */
3413 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3414 if (ret_val) {
3415 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3416 goto out;
3417 }
3418 }
3419
3420 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3421
3422 /* Write the Wakeup register page offset value using opcode 0x11 */
3423 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3424 if (ret_val) {
3425 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3426 goto out;
3427 }
3428
3429 if (read) {
3430 /* Read the Wakeup register page value using opcode 0x12 */
3431 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3432 data);
3433 } else {
3434 /* Write the Wakeup register page value using opcode 0x12 */
3435 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3436 *data);
3437 }
3438
3439 if (ret_val) {
3440 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3441 goto out;
3442 }
3443
3444 if (!page_set)
3445 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3446
3447out:
3448 return ret_val;
3449}
3450
3451/**
3452 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3453 * @hw: pointer to the HW structure
3454 *
3455 * In the case of a PHY power down to save power, or to turn off link during a
3456 * driver unload, or wake on lan is not enabled, restore the link to previous
3457 * settings.
3458 **/
3459void e1000_power_up_phy_copper(struct e1000_hw *hw)
3460{
3461 u16 mii_reg = 0;
3462
3463 /* The PHY will retain its settings across a power down/up cycle */
3464 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3465 mii_reg &= ~MII_CR_POWER_DOWN;
3466 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3467}
3468
3469/**
3470 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3471 * @hw: pointer to the HW structure
3472 *
3473 * In the case of a PHY power down to save power, or to turn off link during a
3474 * driver unload, or wake on lan is not enabled, restore the link to previous
3475 * settings.
3476 **/
3477void e1000_power_down_phy_copper(struct e1000_hw *hw)
3478{
3479 u16 mii_reg = 0;
3480
3481 /* The PHY will retain its settings across a power down/up cycle */
3482 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3483 mii_reg |= MII_CR_POWER_DOWN;
3484 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3485 msec_delay(1);
3486}
3487
3488/**
3489 * __e1000_read_phy_reg_hv - Read HV PHY register
3490 * @hw: pointer to the HW structure
3491 * @offset: register offset to be read
--- 149 unchanged lines hidden (view full) ---
3641
3642 /*
3643 * Workaround MDIO accesses being disabled after entering IEEE
3644 * Power Down (when bit 11 of the PHY Control register is set)
3645 */
3646 if ((hw->phy.type == e1000_phy_82578) &&
3647 (hw->phy.revision >= 1) &&
3648 (hw->phy.addr == 2) &&
3649 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3650 (data & (1 << 11))) {
3651 u16 data2 = 0x7EFF;
3652 ret_val = e1000_access_phy_debug_regs_hv(hw,
3653 (1 << 6) | 0x3,
3654 &data2, FALSE);
3655 if (ret_val)
3656 goto out;
3657 }
--- 107 unchanged lines hidden (view full) ---
3765
3766 /* All operations in this function are phy address 2 */
3767 hw->phy.addr = 2;
3768
3769 /* masking with 0x3F to remove the page from offset */
3770 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3771 if (ret_val) {
3772 DEBUGOUT("Could not write the Address Offset port register\n");
3773 goto out;
3774 }
3775
3776 /* Read or write the data value next */
3777 if (read)
3778 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3779 else
3780 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3781
3782 if (ret_val) {
3783 DEBUGOUT("Could not access the Data port register\n");
3784 goto out;
3785 }
3786
3787out:
3788 return ret_val;
3789}
3790
3791/**
3792 * e1000_link_stall_workaround_hv - Si workaround
3793 * @hw: pointer to the HW structure
3794 *
3795 * This function works around a Si bug where the link partner can get
--- 6 unchanged lines hidden (view full) ---
3802s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3803{
3804 s32 ret_val = E1000_SUCCESS;
3805 u16 data;
3806
3807 DEBUGFUNC("e1000_link_stall_workaround_hv");
3808
3809 if (hw->phy.type != e1000_phy_82578)
3810 goto out;
3811
3812 /* Do not apply workaround if in PHY loopback bit 14 set */
3813 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3814 if (data & PHY_CONTROL_LB)
3815 goto out;
3816
3817 /* check if link is up and at 1Gbps */
3818 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3819 if (ret_val)
3820 goto out;
3821
3822 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3823 BM_CS_STATUS_SPEED_MASK;
3824
3825 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3826 BM_CS_STATUS_SPEED_1000))
3827 goto out;
3828
3829 msec_delay(200);
3830
3831 /* flush the packets in the fifo buffer */
3832 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3833 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3834 HV_MUX_DATA_CTRL_FORCE_SPEED);
3835 if (ret_val)
3836 goto out;
3837
3838 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3839 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3840
3841out:
3842 return ret_val;
3843}
3844
3845/**
3846 * e1000_check_polarity_82577 - Checks the polarity.
3847 * @hw: pointer to the HW structure
3848 *
3849 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3850 *
--- 29 unchanged lines hidden (view full) ---
3880 s32 ret_val;
3881 u16 phy_data;
3882 bool link;
3883
3884 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3885
3886 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3887 if (ret_val)
3888 goto out;
3889
3890 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3891
3892 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3893 if (ret_val)
3894 goto out;
3895
3896 usec_delay(1);
3897
3898 if (phy->autoneg_wait_to_complete) {
3899 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3900
3901 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3902 100000, &link);
3903 if (ret_val)
3904 goto out;
3905
3906 if (!link)
3907 DEBUGOUT("Link taking longer than expected.\n");
3908
3909 /* Try once more */
3910 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3911 100000, &link);
3912 if (ret_val)
3913 goto out;
3914 }
3915
3916out:
3917 return ret_val;
3918}
3919
3920/**
3921 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3922 * @hw: pointer to the HW structure
3923 *
3924 * Read PHY status to determine if link is up. If link is up, then
--- 7 unchanged lines hidden (view full) ---
3932 s32 ret_val;
3933 u16 data;
3934 bool link;
3935
3936 DEBUGFUNC("e1000_get_phy_info_82577");
3937
3938 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3939 if (ret_val)
3940 goto out;
3941
3942 if (!link) {
3943 DEBUGOUT("Phy info is only valid if link is up\n");
3944 ret_val = -E1000_ERR_CONFIG;
3945 goto out;
3946 }
3947
3948 phy->polarity_correction = TRUE;
3949
3950 ret_val = e1000_check_polarity_82577(hw);
3951 if (ret_val)
3952 goto out;
3953
3954 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3955 if (ret_val)
3956 goto out;
3957
3958 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3959
3960 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3961 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3962 ret_val = hw->phy.ops.get_cable_length(hw);
3963 if (ret_val)
3964 goto out;
3965
3966 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3967 if (ret_val)
3968 goto out;
3969
3970 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3971 ? e1000_1000t_rx_status_ok
3972 : e1000_1000t_rx_status_not_ok;
3973
3974 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3975 ? e1000_1000t_rx_status_ok
3976 : e1000_1000t_rx_status_not_ok;
3977 } else {
3978 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3979 phy->local_rx = e1000_1000t_rx_status_undefined;
3980 phy->remote_rx = e1000_1000t_rx_status_undefined;
3981 }
3982
3983out:
3984 return ret_val;
3985}
3986
3987/**
3988 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3989 * @hw: pointer to the HW structure
3990 *
3991 * Reads the diagnostic status register and verifies result is valid before
3992 * placing it in the phy_cable_length field.
3993 **/
3994s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3995{
3996 struct e1000_phy_info *phy = &hw->phy;
3997 s32 ret_val;
3998 u16 phy_data, length;
3999
4000 DEBUGFUNC("e1000_get_cable_length_82577");
4001
4002 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4003 if (ret_val)
4004 goto out;
4005
4006 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4007 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
4008
4009 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4010 ret_val = -E1000_ERR_PHY;
4011
4012 phy->cable_length = length;
4013
4014out:
4015 return ret_val;
4016}