1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h>
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32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 196142 2009-08-12 12:57:02Z rnoland $");
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32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 196470 2009-08-23 14:55:57Z rnoland $"); |
33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon"
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44#define DRIVER_DATE "20080528"
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44#define DRIVER_DATE "20080613" |
45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 */ 106#define DRIVER_MAJOR 1 107#define DRIVER_MINOR 29 108#define DRIVER_PATCHLEVEL 0 109 110/* 111 * Radeon chip families 112 */ 113enum radeon_family { 114 CHIP_R100, 115 CHIP_RV100, 116 CHIP_RS100, 117 CHIP_RV200, 118 CHIP_RS200, 119 CHIP_R200, 120 CHIP_RV250, 121 CHIP_RS300, 122 CHIP_RV280, 123 CHIP_R300, 124 CHIP_R350, 125 CHIP_RV350, 126 CHIP_RV380, 127 CHIP_R420, 128 CHIP_R423, 129 CHIP_RV410, 130 CHIP_RS400, 131 CHIP_RS480, 132 CHIP_RS600, 133 CHIP_RS690, 134 CHIP_RS740, 135 CHIP_RV515, 136 CHIP_R520, 137 CHIP_RV530, 138 CHIP_RV560, 139 CHIP_RV570, 140 CHIP_R580, 141 CHIP_R600, 142 CHIP_RV610, 143 CHIP_RV630, 144 CHIP_RV620, 145 CHIP_RV635, 146 CHIP_RV670, 147 CHIP_RS780, 148 CHIP_RS880, 149 CHIP_RV770, 150 CHIP_RV740, 151 CHIP_RV730, 152 CHIP_RV710, 153 CHIP_LAST, 154}; 155 156enum radeon_cp_microcode_version { 157 UCODE_R100, 158 UCODE_R200, 159 UCODE_R300, 160}; 161 162/* 163 * Chip flags 164 */ 165enum radeon_chip_flags { 166 RADEON_FAMILY_MASK = 0x0000ffffUL, 167 RADEON_FLAGS_MASK = 0xffff0000UL, 168 RADEON_IS_MOBILITY = 0x00010000UL, 169 RADEON_IS_IGP = 0x00020000UL, 170 RADEON_SINGLE_CRTC = 0x00040000UL, 171 RADEON_IS_AGP = 0x00080000UL, 172 RADEON_HAS_HIERZ = 0x00100000UL, 173 RADEON_IS_PCIE = 0x00200000UL, 174 RADEON_NEW_MEMMAP = 0x00400000UL, 175 RADEON_IS_PCI = 0x00800000UL, 176 RADEON_IS_IGPGART = 0x01000000UL, 177}; 178 179typedef struct drm_radeon_freelist { 180 unsigned int age; 181 struct drm_buf *buf; 182 struct drm_radeon_freelist *next; 183 struct drm_radeon_freelist *prev; 184} drm_radeon_freelist_t; 185 186typedef struct drm_radeon_ring_buffer { 187 u32 *start; 188 u32 *end; 189 int size; 190 int size_l2qw; 191 192 int rptr_update; /* Double Words */ 193 int rptr_update_l2qw; /* log2 Quad Words */ 194 195 int fetch_size; /* Double Words */ 196 int fetch_size_l2ow; /* log2 Oct Words */ 197 198 u32 tail; 199 u32 tail_mask; 200 int space; 201 202 int high_mark; 203} drm_radeon_ring_buffer_t; 204 205typedef struct drm_radeon_depth_clear_t { 206 u32 rb3d_cntl; 207 u32 rb3d_zstencilcntl; 208 u32 se_cntl; 209} drm_radeon_depth_clear_t; 210 211struct drm_radeon_driver_file_fields { 212 int64_t radeon_fb_delta; 213}; 214 215struct mem_block { 216 struct mem_block *next; 217 struct mem_block *prev; 218 int start; 219 int size; 220 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 221}; 222 223struct radeon_surface { 224 int refcount; 225 u32 lower; 226 u32 upper; 227 u32 flags; 228}; 229 230struct radeon_virt_surface { 231 int surface_index; 232 u32 lower; 233 u32 upper; 234 u32 flags; 235 struct drm_file *file_priv; 236#define PCIGART_FILE_PRIV ((void *) -1L) 237}; 238
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239struct drm_radeon_kernel_chunk { 240 uint32_t chunk_id; 241 uint32_t length_dw; 242 uint32_t __user *chunk_data; 243 uint32_t *kdata; 244}; 245 246struct drm_radeon_cs_parser { 247 struct drm_device *dev; 248 struct drm_file *file_priv; 249 uint32_t num_chunks; 250 struct drm_radeon_kernel_chunk *chunks; 251 int ib_index; 252 int reloc_index; 253 uint32_t card_offset; 254 void *ib; 255}; 256 257/* command submission struct */ 258struct drm_radeon_cs_priv { 259 struct mtx cs_mutex; 260 uint32_t id_wcnt; 261 uint32_t id_scnt; 262 uint32_t id_last_wcnt; 263 uint32_t id_last_scnt; 264 265 int (*parse)(struct drm_radeon_cs_parser *parser); 266 void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id); 267 uint32_t (*id_last_get)(struct drm_device *dev); 268 /* this ib handling callback are for hidding memory manager drm 269 * from memory manager less drm, free have to emit ib discard 270 * sequence into the ring */ 271 int (*ib_get)(struct drm_radeon_cs_parser *parser); 272 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib); 273 void (*ib_free)(struct drm_radeon_cs_parser *parser, int error); 274 /* do a relocation either MM or non-MM */ 275 int (*relocate)(struct drm_radeon_cs_parser *parser, 276 uint32_t *reloc, uint64_t *offset); 277}; 278 |
279#define RADEON_FLUSH_EMITED (1 << 0) 280#define RADEON_PURGE_EMITED (1 << 1) 281 282typedef struct drm_radeon_private { 283 drm_radeon_ring_buffer_t ring; 284 drm_radeon_sarea_t *sarea_priv; 285 286 u32 fb_location; 287 u32 fb_size; 288 int new_memmap; 289 290 int gart_size; 291 u32 gart_vm_start; 292 unsigned long gart_buffers_offset; 293 294 int cp_mode; 295 int cp_running; 296 297 drm_radeon_freelist_t *head; 298 drm_radeon_freelist_t *tail; 299 int last_buf; 300 int writeback_works; 301 302 int usec_timeout; 303 304 int microcode_version; 305 306 struct { 307 u32 boxes; 308 int freelist_timeouts; 309 int freelist_loops; 310 int requested_bufs; 311 int last_frame_reads; 312 int last_clear_reads; 313 int clears; 314 int texture_uploads; 315 } stats; 316 317 int do_boxes; 318 int page_flipping; 319 320 u32 color_fmt; 321 unsigned int front_offset; 322 unsigned int front_pitch; 323 unsigned int back_offset; 324 unsigned int back_pitch; 325 326 u32 depth_fmt; 327 unsigned int depth_offset; 328 unsigned int depth_pitch; 329 330 u32 front_pitch_offset; 331 u32 back_pitch_offset; 332 u32 depth_pitch_offset; 333 334 drm_radeon_depth_clear_t depth_clear; 335 336 unsigned long ring_offset; 337 unsigned long ring_rptr_offset; 338 unsigned long buffers_offset; 339 unsigned long gart_textures_offset; 340 341 drm_local_map_t *sarea; 342 drm_local_map_t *cp_ring; 343 drm_local_map_t *ring_rptr; 344 drm_local_map_t *gart_textures; 345 346 struct mem_block *gart_heap; 347 struct mem_block *fb_heap; 348 349 /* SW interrupt */ 350 wait_queue_head_t swi_queue; 351 atomic_t swi_emitted; 352 int vblank_crtc; 353 uint32_t irq_enable_reg; 354 int irq_enabled; 355 uint32_t r500_disp_irq_reg; 356 357 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 358 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 359 360 unsigned long pcigart_offset; 361 unsigned int pcigart_offset_set; 362 struct drm_ati_pcigart_info gart_info; 363 364 u32 scratch_ages[5]; 365 366 /* starting from here on, data is preserved accross an open */ 367 uint32_t flags; /* see radeon_chip_flags */ 368 unsigned long fb_aper_offset; 369 370 int num_gb_pipes; 371 int track_flush; 372 drm_local_map_t *mmio; 373 374 /* r6xx/r7xx pipe/shader config */ 375 int r600_max_pipes; 376 int r600_max_tile_pipes; 377 int r600_max_simds; 378 int r600_max_backends; 379 int r600_max_gprs; 380 int r600_max_threads; 381 int r600_max_stack_entries; 382 int r600_max_hw_contexts; 383 int r600_max_gs_threads; 384 int r600_sx_max_export_size; 385 int r600_sx_max_export_pos_size; 386 int r600_sx_max_export_smx_size; 387 int r600_sq_num_cf_insts; 388 int r700_sx_num_of_sets; 389 int r700_sc_prim_fifo_size; 390 int r700_sc_hiz_tile_fifo_size; 391 int r700_sc_earlyz_tile_fifo_fize;
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392 /* r6xx/r7xx drm blit vertex buffer */ 393 struct drm_buf *blit_vb; |
394
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395 /* CS */ 396 struct drm_radeon_cs_priv cs; 397 struct drm_buf *cs_buf; 398 |
399} drm_radeon_private_t; 400 401typedef struct drm_radeon_buf_priv { 402 u32 age; 403} drm_radeon_buf_priv_t; 404 405typedef struct drm_radeon_kcmd_buffer { 406 int bufsz; 407 char *buf; 408 int nbox; 409 struct drm_clip_rect __user *boxes; 410} drm_radeon_kcmd_buffer_t; 411 412extern int radeon_no_wb; 413extern struct drm_ioctl_desc radeon_ioctls[]; 414extern int radeon_max_ioctl; 415 416extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 417extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 418 419#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 420#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 421 422/* Check whether the given hardware address is inside the framebuffer or the 423 * GART area. 424 */ 425static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 426 u64 off) 427{
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382 u32 fb_start = dev_priv->fb_location;
383 u32 fb_end = fb_start + dev_priv->fb_size - 1;
384 u32 gart_start = dev_priv->gart_vm_start;
385 u32 gart_end = gart_start + dev_priv->gart_size - 1;
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428 u64 fb_start = dev_priv->fb_location; 429 u64 fb_end = fb_start + dev_priv->fb_size - 1; 430 u64 gart_start = dev_priv->gart_vm_start; 431 u64 gart_end = gart_start + dev_priv->gart_size - 1; |
432 433 return ((off >= fb_start && off <= fb_end) || 434 (off >= gart_start && off <= gart_end)); 435} 436 437 /* radeon_cp.c */ 438extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 439extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 440extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 441extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 442extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 443extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 444extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 445extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 446extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 447extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 448extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 449extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 450extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); 451 452extern void radeon_freelist_reset(struct drm_device * dev); 453extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 454 455extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 456 457extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 458 459extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 460extern int radeon_presetup(struct drm_device *dev); 461extern int radeon_driver_postcleanup(struct drm_device *dev); 462 463extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 464extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 465extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 466extern void radeon_mem_takedown(struct mem_block **heap); 467extern void radeon_mem_release(struct drm_file *file_priv, 468 struct mem_block *heap); 469 470extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 471extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 472extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 473 474 /* radeon_irq.c */ 475extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 476extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 477extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 478 479extern void radeon_do_release(struct drm_device * dev); 480extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 481extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 482extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 483extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 484extern void radeon_driver_irq_preinstall(struct drm_device * dev); 485extern int radeon_driver_irq_postinstall(struct drm_device *dev); 486extern void radeon_driver_irq_uninstall(struct drm_device * dev); 487extern void radeon_enable_interrupt(struct drm_device *dev); 488extern int radeon_vblank_crtc_get(struct drm_device *dev); 489extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 490 491extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 492extern int radeon_driver_unload(struct drm_device *dev); 493extern int radeon_driver_firstopen(struct drm_device *dev); 494extern void radeon_driver_preclose(struct drm_device *dev, 495 struct drm_file *file_priv); 496extern void radeon_driver_postclose(struct drm_device *dev, 497 struct drm_file *file_priv); 498extern void radeon_driver_lastclose(struct drm_device * dev); 499extern int radeon_driver_open(struct drm_device *dev, 500 struct drm_file *file_priv); 501extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 502 unsigned long arg); 503 504/* r300_cmdbuf.c */ 505extern void r300_init_reg_flags(struct drm_device *dev); 506 507extern int r300_do_cp_cmdbuf(struct drm_device *dev, 508 struct drm_file *file_priv, 509 drm_radeon_kcmd_buffer_t *cmdbuf); 510 511/* r600_cp.c */ 512extern int r600_do_engine_reset(struct drm_device *dev); 513extern int r600_do_cleanup_cp(struct drm_device *dev); 514extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 515 struct drm_file *file_priv); 516extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 517extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 518extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 519extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 520extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 521extern int r600_cp_dispatch_indirect(struct drm_device *dev, 522 struct drm_buf *buf, int start, int end); 523extern int r600_page_table_init(struct drm_device *dev); 524extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
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525extern void r600_cp_dispatch_swap(struct drm_device * dev); 526extern int r600_cp_dispatch_texture(struct drm_device * dev, 527 struct drm_file *file_priv, 528 drm_radeon_texture_t * tex, 529 drm_radeon_tex_image_t * image); |
530
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531/* r600_blit.c */ 532extern int 533r600_prepare_blit_copy(struct drm_device *dev); 534extern void 535r600_done_blit_copy(struct drm_device *dev); 536extern void 537r600_blit_copy(struct drm_device *dev, 538 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 539 int size_bytes); 540extern void 541r600_blit_swap(struct drm_device *dev, 542 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 543 int sx, int sy, int dx, int dy, 544 int w, int h, int src_pitch, int dst_pitch, int cpp); 545 546/* radeon_state.c */ 547extern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf); 548 549/* radeon_cs.c */ 550extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 551extern int r600_cs_init(struct drm_device *dev); 552 |
553/* Flags for stats.boxes 554 */ 555#define RADEON_BOX_DMA_IDLE 0x1 556#define RADEON_BOX_RING_FULL 0x2 557#define RADEON_BOX_FLIP 0x4 558#define RADEON_BOX_WAIT_IDLE 0x8 559#define RADEON_BOX_TEXTURE_LOAD 0x10 560 561/* Register definitions, register access macros and drmAddMap constants 562 * for Radeon kernel driver. 563 */ 564#define RADEON_MM_INDEX 0x0000 565#define RADEON_MM_DATA 0x0004 566 567#define RADEON_AGP_COMMAND 0x0f60 568#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 569# define RADEON_AGP_ENABLE (1<<8) 570#define RADEON_AUX_SCISSOR_CNTL 0x26f0 571# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 572# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 573# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 574# define RADEON_SCISSOR_0_ENABLE (1 << 28) 575# define RADEON_SCISSOR_1_ENABLE (1 << 29) 576# define RADEON_SCISSOR_2_ENABLE (1 << 30) 577 578/* 579 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 580 * don't have an explicit bus mastering disable bit. It's handled 581 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 582 * handling, not bus mastering itself. 583 */ 584#define RADEON_BUS_CNTL 0x0030 585/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 586# define RADEON_BUS_MASTER_DIS (1 << 6) 587/* rs600/rs690/rs740 */ 588# define RS600_BUS_MASTER_DIS (1 << 14) 589# define RS600_MSI_REARM (1 << 20) 590/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 591 592#define RADEON_BUS_CNTL1 0x0034 593# define RADEON_PMI_BM_DIS (1 << 2) 594# define RADEON_PMI_INT_DIS (1 << 3) 595 596#define RV370_BUS_CNTL 0x004c 597# define RV370_PMI_BM_DIS (1 << 5) 598# define RV370_PMI_INT_DIS (1 << 6) 599 600#define RADEON_MSI_REARM_EN 0x0160 601/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 602# define RV370_MSI_REARM_EN (1 << 0) 603 604#define RADEON_CLOCK_CNTL_DATA 0x000c 605# define RADEON_PLL_WR_EN (1 << 7) 606#define RADEON_CLOCK_CNTL_INDEX 0x0008 607#define RADEON_CONFIG_APER_SIZE 0x0108 608#define RADEON_CONFIG_MEMSIZE 0x00f8 609#define RADEON_CRTC_OFFSET 0x0224 610#define RADEON_CRTC_OFFSET_CNTL 0x0228 611# define RADEON_CRTC_TILE_EN (1 << 15) 612# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 613#define RADEON_CRTC2_OFFSET 0x0324 614#define RADEON_CRTC2_OFFSET_CNTL 0x0328 615 616#define RADEON_PCIE_INDEX 0x0030 617#define RADEON_PCIE_DATA 0x0034 618#define RADEON_PCIE_TX_GART_CNTL 0x10 619# define RADEON_PCIE_TX_GART_EN (1 << 0) 620# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 621# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 622# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 623# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 624# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 625# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 626# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 627#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 628#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 629#define RADEON_PCIE_TX_GART_BASE 0x13 630#define RADEON_PCIE_TX_GART_START_LO 0x14 631#define RADEON_PCIE_TX_GART_START_HI 0x15 632#define RADEON_PCIE_TX_GART_END_LO 0x16 633#define RADEON_PCIE_TX_GART_END_HI 0x17 634 635#define RS480_NB_MC_INDEX 0x168 636# define RS480_NB_MC_IND_WR_EN (1 << 8) 637#define RS480_NB_MC_DATA 0x16c 638 639#define RS690_MC_INDEX 0x78 640# define RS690_MC_INDEX_MASK 0x1ff 641# define RS690_MC_INDEX_WR_EN (1 << 9) 642# define RS690_MC_INDEX_WR_ACK 0x7f 643#define RS690_MC_DATA 0x7c 644 645/* MC indirect registers */ 646#define RS480_MC_MISC_CNTL 0x18 647# define RS480_DISABLE_GTW (1 << 1) 648/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 649# define RS480_GART_INDEX_REG_EN (1 << 12) 650# define RS690_BLOCK_GFX_D3_EN (1 << 14) 651#define RS480_K8_FB_LOCATION 0x1e 652#define RS480_GART_FEATURE_ID 0x2b 653# define RS480_HANG_EN (1 << 11) 654# define RS480_TLB_ENABLE (1 << 18) 655# define RS480_P2P_ENABLE (1 << 19) 656# define RS480_GTW_LAC_EN (1 << 25) 657# define RS480_2LEVEL_GART (0 << 30) 658# define RS480_1LEVEL_GART (1 << 30) 659# define RS480_PDC_EN (1 << 31) 660#define RS480_GART_BASE 0x2c 661#define RS480_GART_CACHE_CNTRL 0x2e 662# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 663#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 664# define RS480_GART_EN (1 << 0) 665# define RS480_VA_SIZE_32MB (0 << 1) 666# define RS480_VA_SIZE_64MB (1 << 1) 667# define RS480_VA_SIZE_128MB (2 << 1) 668# define RS480_VA_SIZE_256MB (3 << 1) 669# define RS480_VA_SIZE_512MB (4 << 1) 670# define RS480_VA_SIZE_1GB (5 << 1) 671# define RS480_VA_SIZE_2GB (6 << 1) 672#define RS480_AGP_MODE_CNTL 0x39 673# define RS480_POST_GART_Q_SIZE (1 << 18) 674# define RS480_NONGART_SNOOP (1 << 19) 675# define RS480_AGP_RD_BUF_SIZE (1 << 20) 676# define RS480_REQ_TYPE_SNOOP_SHIFT 22 677# define RS480_REQ_TYPE_SNOOP_MASK 0x3 678# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 679#define RS480_MC_MISC_UMA_CNTL 0x5f 680#define RS480_MC_MCLK_CNTL 0x7a 681#define RS480_MC_UMA_DUALCH_CNTL 0x86 682 683#define RS690_MC_FB_LOCATION 0x100 684#define RS690_MC_AGP_LOCATION 0x101 685#define RS690_MC_AGP_BASE 0x102 686#define RS690_MC_AGP_BASE_2 0x103 687 688#define RS600_MC_INDEX 0x70 689# define RS600_MC_ADDR_MASK 0xffff 690# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 691# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 692# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 693# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 694# define RS600_MC_IND_AIC_RBS (1 << 20) 695# define RS600_MC_IND_CITF_ARB0 (1 << 21) 696# define RS600_MC_IND_CITF_ARB1 (1 << 22) 697# define RS600_MC_IND_WR_EN (1 << 23) 698#define RS600_MC_DATA 0x74 699 700#define RS600_MC_STATUS 0x0 701# define RS600_MC_IDLE (1 << 1) 702#define RS600_MC_FB_LOCATION 0x4 703#define RS600_MC_AGP_LOCATION 0x5 704#define RS600_AGP_BASE 0x6 705#define RS600_AGP_BASE_2 0x7 706#define RS600_MC_CNTL1 0x9 707# define RS600_ENABLE_PAGE_TABLES (1 << 26) 708#define RS600_MC_PT0_CNTL 0x100 709# define RS600_ENABLE_PT (1 << 0) 710# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 711# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 712# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 713# define RS600_INVALIDATE_L2_CACHE (1 << 29) 714#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 715# define RS600_ENABLE_PAGE_TABLE (1 << 0) 716# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 717#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 718#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 719#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 720#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 721#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 722#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 723#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 724# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 725# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 726# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 727# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 728# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 729# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 730# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 731# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 732# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 733# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 734# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 735# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 736# define RS600_INVALIDATE_L1_TLB (1 << 20) 737 738#define R520_MC_IND_INDEX 0x70 739#define R520_MC_IND_WR_EN (1 << 24) 740#define R520_MC_IND_DATA 0x74 741 742#define RV515_MC_FB_LOCATION 0x01 743#define RV515_MC_AGP_LOCATION 0x02 744#define RV515_MC_AGP_BASE 0x03 745#define RV515_MC_AGP_BASE_2 0x04 746 747#define R520_MC_FB_LOCATION 0x04 748#define R520_MC_AGP_LOCATION 0x05 749#define R520_MC_AGP_BASE 0x06 750#define R520_MC_AGP_BASE_2 0x07 751 752#define RADEON_MPP_TB_CONFIG 0x01c0 753#define RADEON_MEM_CNTL 0x0140 754#define RADEON_MEM_SDRAM_MODE_REG 0x0158 755#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 756#define RS480_AGP_BASE_2 0x0164 757#define RADEON_AGP_BASE 0x0170 758 759/* pipe config regs */ 760#define R400_GB_PIPE_SELECT 0x402c 761#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 762#define R300_GB_TILE_CONFIG 0x4018 763# define R300_ENABLE_TILING (1 << 0) 764# define R300_PIPE_COUNT_RV350 (0 << 1) 765# define R300_PIPE_COUNT_R300 (3 << 1) 766# define R300_PIPE_COUNT_R420_3P (6 << 1) 767# define R300_PIPE_COUNT_R420 (7 << 1) 768# define R300_TILE_SIZE_8 (0 << 4) 769# define R300_TILE_SIZE_16 (1 << 4) 770# define R300_TILE_SIZE_32 (2 << 4) 771# define R300_SUBPIXEL_1_12 (0 << 16) 772# define R300_SUBPIXEL_1_16 (1 << 16) 773#define R300_DST_PIPE_CONFIG 0x170c 774# define R300_PIPE_AUTO_CONFIG (1 << 31) 775#define R300_RB2D_DSTCACHE_MODE 0x3428 776# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 777# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 778 779#define RADEON_RB3D_COLOROFFSET 0x1c40 780#define RADEON_RB3D_COLORPITCH 0x1c48 781 782#define RADEON_SRC_X_Y 0x1590 783 784#define RADEON_DP_GUI_MASTER_CNTL 0x146c 785# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 786# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 787# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 788# define RADEON_GMC_BRUSH_NONE (15 << 4) 789# define RADEON_GMC_DST_16BPP (4 << 8) 790# define RADEON_GMC_DST_24BPP (5 << 8) 791# define RADEON_GMC_DST_32BPP (6 << 8) 792# define RADEON_GMC_DST_DATATYPE_SHIFT 8 793# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 794# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 795# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 796# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 797# define RADEON_GMC_WR_MSK_DIS (1 << 30) 798# define RADEON_ROP3_S 0x00cc0000 799# define RADEON_ROP3_P 0x00f00000 800#define RADEON_DP_WRITE_MASK 0x16cc 801#define RADEON_SRC_PITCH_OFFSET 0x1428 802#define RADEON_DST_PITCH_OFFSET 0x142c 803#define RADEON_DST_PITCH_OFFSET_C 0x1c80 804# define RADEON_DST_TILE_LINEAR (0 << 30) 805# define RADEON_DST_TILE_MACRO (1 << 30) 806# define RADEON_DST_TILE_MICRO (2 << 30) 807# define RADEON_DST_TILE_BOTH (3 << 30) 808 809#define RADEON_SCRATCH_REG0 0x15e0 810#define RADEON_SCRATCH_REG1 0x15e4 811#define RADEON_SCRATCH_REG2 0x15e8 812#define RADEON_SCRATCH_REG3 0x15ec 813#define RADEON_SCRATCH_REG4 0x15f0 814#define RADEON_SCRATCH_REG5 0x15f4 815#define RADEON_SCRATCH_UMSK 0x0770 816#define RADEON_SCRATCH_ADDR 0x0774 817 818#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 819 820extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 821 822#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 823 824#define R600_SCRATCH_REG0 0x8500 825#define R600_SCRATCH_REG1 0x8504 826#define R600_SCRATCH_REG2 0x8508 827#define R600_SCRATCH_REG3 0x850c 828#define R600_SCRATCH_REG4 0x8510 829#define R600_SCRATCH_REG5 0x8514 830#define R600_SCRATCH_REG6 0x8518 831#define R600_SCRATCH_REG7 0x851c 832#define R600_SCRATCH_UMSK 0x8540 833#define R600_SCRATCH_ADDR 0x8544 834 835#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 836 837#define RADEON_GEN_INT_CNTL 0x0040 838# define RADEON_CRTC_VBLANK_MASK (1 << 0) 839# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 840# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 841# define RADEON_SW_INT_ENABLE (1 << 25) 842 843#define RADEON_GEN_INT_STATUS 0x0044 844# define RADEON_CRTC_VBLANK_STAT (1 << 0) 845# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 846# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 847# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 848# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 849# define RADEON_SW_INT_TEST (1 << 25) 850# define RADEON_SW_INT_TEST_ACK (1 << 25) 851# define RADEON_SW_INT_FIRE (1 << 26) 852# define R500_DISPLAY_INT_STATUS (1 << 0) 853 854#define RADEON_HOST_PATH_CNTL 0x0130 855# define RADEON_HDP_SOFT_RESET (1 << 26) 856# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 857# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 858 859#define RADEON_ISYNC_CNTL 0x1724 860# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 861# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 862# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 863# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 864# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 865# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 866 867#define RADEON_RBBM_GUICNTL 0x172c 868# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 869# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 870# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 871# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 872 873#define RADEON_MC_AGP_LOCATION 0x014c 874#define RADEON_MC_FB_LOCATION 0x0148 875#define RADEON_MCLK_CNTL 0x0012 876# define RADEON_FORCEON_MCLKA (1 << 16) 877# define RADEON_FORCEON_MCLKB (1 << 17) 878# define RADEON_FORCEON_YCLKA (1 << 18) 879# define RADEON_FORCEON_YCLKB (1 << 19) 880# define RADEON_FORCEON_MC (1 << 20) 881# define RADEON_FORCEON_AIC (1 << 21) 882 883#define RADEON_PP_BORDER_COLOR_0 0x1d40 884#define RADEON_PP_BORDER_COLOR_1 0x1d44 885#define RADEON_PP_BORDER_COLOR_2 0x1d48 886#define RADEON_PP_CNTL 0x1c38 887# define RADEON_SCISSOR_ENABLE (1 << 1) 888#define RADEON_PP_LUM_MATRIX 0x1d00 889#define RADEON_PP_MISC 0x1c14 890#define RADEON_PP_ROT_MATRIX_0 0x1d58 891#define RADEON_PP_TXFILTER_0 0x1c54 892#define RADEON_PP_TXOFFSET_0 0x1c5c 893#define RADEON_PP_TXFILTER_1 0x1c6c 894#define RADEON_PP_TXFILTER_2 0x1c84 895 896#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 897#define R300_DSTCACHE_CTLSTAT 0x1714 898# define R300_RB2D_DC_FLUSH (3 << 0) 899# define R300_RB2D_DC_FREE (3 << 2) 900# define R300_RB2D_DC_FLUSH_ALL 0xf 901# define R300_RB2D_DC_BUSY (1 << 31) 902#define RADEON_RB3D_CNTL 0x1c3c 903# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 904# define RADEON_PLANE_MASK_ENABLE (1 << 1) 905# define RADEON_DITHER_ENABLE (1 << 2) 906# define RADEON_ROUND_ENABLE (1 << 3) 907# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 908# define RADEON_DITHER_INIT (1 << 5) 909# define RADEON_ROP_ENABLE (1 << 6) 910# define RADEON_STENCIL_ENABLE (1 << 7) 911# define RADEON_Z_ENABLE (1 << 8) 912# define RADEON_ZBLOCK16 (1 << 15) 913#define RADEON_RB3D_DEPTHOFFSET 0x1c24 914#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 915#define RADEON_RB3D_DEPTHPITCH 0x1c28 916#define RADEON_RB3D_PLANEMASK 0x1d84 917#define RADEON_RB3D_STENCILREFMASK 0x1d7c 918#define RADEON_RB3D_ZCACHE_MODE 0x3250 919#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 920# define RADEON_RB3D_ZC_FLUSH (1 << 0) 921# define RADEON_RB3D_ZC_FREE (1 << 2) 922# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 923# define RADEON_RB3D_ZC_BUSY (1 << 31) 924#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 925# define R300_ZC_FLUSH (1 << 0) 926# define R300_ZC_FREE (1 << 1) 927# define R300_ZC_BUSY (1 << 31) 928#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 929# define RADEON_RB3D_DC_FLUSH (3 << 0) 930# define RADEON_RB3D_DC_FREE (3 << 2) 931# define RADEON_RB3D_DC_FLUSH_ALL 0xf 932# define RADEON_RB3D_DC_BUSY (1 << 31) 933#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 934# define R300_RB3D_DC_FLUSH (2 << 0) 935# define R300_RB3D_DC_FREE (2 << 2) 936# define R300_RB3D_DC_FINISH (1 << 4) 937#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 938# define RADEON_Z_TEST_MASK (7 << 4) 939# define RADEON_Z_TEST_ALWAYS (7 << 4) 940# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 941# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 942# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 943# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 944# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 945# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 946# define RADEON_FORCE_Z_DIRTY (1 << 29) 947# define RADEON_Z_WRITE_ENABLE (1 << 30) 948# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 949#define RADEON_RBBM_SOFT_RESET 0x00f0 950# define RADEON_SOFT_RESET_CP (1 << 0) 951# define RADEON_SOFT_RESET_HI (1 << 1) 952# define RADEON_SOFT_RESET_SE (1 << 2) 953# define RADEON_SOFT_RESET_RE (1 << 3) 954# define RADEON_SOFT_RESET_PP (1 << 4) 955# define RADEON_SOFT_RESET_E2 (1 << 5) 956# define RADEON_SOFT_RESET_RB (1 << 6) 957# define RADEON_SOFT_RESET_HDP (1 << 7) 958/* 959 * 6:0 Available slots in the FIFO 960 * 8 Host Interface active 961 * 9 CP request active 962 * 10 FIFO request active 963 * 11 Host Interface retry active 964 * 12 CP retry active 965 * 13 FIFO retry active 966 * 14 FIFO pipeline busy 967 * 15 Event engine busy 968 * 16 CP command stream busy 969 * 17 2D engine busy 970 * 18 2D portion of render backend busy 971 * 20 3D setup engine busy 972 * 26 GA engine busy 973 * 27 CBA 2D engine busy 974 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 975 * command stream queue not empty or Ring Buffer not empty 976 */ 977#define RADEON_RBBM_STATUS 0x0e40 978/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 979/* #define RADEON_RBBM_STATUS 0x1740 */ 980/* bits 6:0 are dword slots available in the cmd fifo */ 981# define RADEON_RBBM_FIFOCNT_MASK 0x007f 982# define RADEON_HIRQ_ON_RBB (1 << 8) 983# define RADEON_CPRQ_ON_RBB (1 << 9) 984# define RADEON_CFRQ_ON_RBB (1 << 10) 985# define RADEON_HIRQ_IN_RTBUF (1 << 11) 986# define RADEON_CPRQ_IN_RTBUF (1 << 12) 987# define RADEON_CFRQ_IN_RTBUF (1 << 13) 988# define RADEON_PIPE_BUSY (1 << 14) 989# define RADEON_ENG_EV_BUSY (1 << 15) 990# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 991# define RADEON_E2_BUSY (1 << 17) 992# define RADEON_RB2D_BUSY (1 << 18) 993# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 994# define RADEON_VAP_BUSY (1 << 20) 995# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 996# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 997# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 998# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 999# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 1000# define RADEON_GA_BUSY (1 << 26) 1001# define RADEON_CBA2D_BUSY (1 << 27) 1002# define RADEON_RBBM_ACTIVE (1 << 31) 1003#define RADEON_RE_LINE_PATTERN 0x1cd0 1004#define RADEON_RE_MISC 0x26c4 1005#define RADEON_RE_TOP_LEFT 0x26c0 1006#define RADEON_RE_WIDTH_HEIGHT 0x1c44 1007#define RADEON_RE_STIPPLE_ADDR 0x1cc8 1008#define RADEON_RE_STIPPLE_DATA 0x1ccc 1009 1010#define RADEON_SCISSOR_TL_0 0x1cd8 1011#define RADEON_SCISSOR_BR_0 0x1cdc 1012#define RADEON_SCISSOR_TL_1 0x1ce0 1013#define RADEON_SCISSOR_BR_1 0x1ce4 1014#define RADEON_SCISSOR_TL_2 0x1ce8 1015#define RADEON_SCISSOR_BR_2 0x1cec 1016#define RADEON_SE_COORD_FMT 0x1c50 1017#define RADEON_SE_CNTL 0x1c4c 1018# define RADEON_FFACE_CULL_CW (0 << 0) 1019# define RADEON_BFACE_SOLID (3 << 1) 1020# define RADEON_FFACE_SOLID (3 << 3) 1021# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 1022# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 1023# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 1024# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 1025# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 1026# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 1027# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 1028# define RADEON_FOG_SHADE_FLAT (1 << 14) 1029# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 1030# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 1031# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 1032# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 1033# define RADEON_ROUND_MODE_TRUNC (0 << 28) 1034# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 1035#define RADEON_SE_CNTL_STATUS 0x2140 1036#define RADEON_SE_LINE_WIDTH 0x1db8 1037#define RADEON_SE_VPORT_XSCALE 0x1d98 1038#define RADEON_SE_ZBIAS_FACTOR 0x1db0 1039#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1040#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1041#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 1042# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 1043# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 1044#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 1045#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 1046# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 1047#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 1048#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 1049#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 1050#define RADEON_SURFACE_CNTL 0x0b00 1051# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1052# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 1053# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 1054# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 1055# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 1056# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 1057# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 1058# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 1059# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 1060#define RADEON_SURFACE0_INFO 0x0b0c 1061# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 1062# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 1063# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 1064# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 1065# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 1066# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 1067#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1068#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1069# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 1070#define RADEON_SURFACE1_INFO 0x0b1c 1071#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1072#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1073#define RADEON_SURFACE2_INFO 0x0b2c 1074#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1075#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1076#define RADEON_SURFACE3_INFO 0x0b3c 1077#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1078#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1079#define RADEON_SURFACE4_INFO 0x0b4c 1080#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1081#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1082#define RADEON_SURFACE5_INFO 0x0b5c 1083#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1084#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1085#define RADEON_SURFACE6_INFO 0x0b6c 1086#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1087#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1088#define RADEON_SURFACE7_INFO 0x0b7c 1089#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1090#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1091#define RADEON_SW_SEMAPHORE 0x013c 1092 1093#define RADEON_WAIT_UNTIL 0x1720 1094# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1095# define RADEON_WAIT_2D_IDLE (1 << 14) 1096# define RADEON_WAIT_3D_IDLE (1 << 15) 1097# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1098# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1099# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1100 1101#define RADEON_RB3D_ZMASKOFFSET 0x3234 1102#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1103# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1104# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1105 1106/* CP registers */ 1107#define RADEON_CP_ME_RAM_ADDR 0x07d4 1108#define RADEON_CP_ME_RAM_RADDR 0x07d8 1109#define RADEON_CP_ME_RAM_DATAH 0x07dc 1110#define RADEON_CP_ME_RAM_DATAL 0x07e0 1111 1112#define RADEON_CP_RB_BASE 0x0700 1113#define RADEON_CP_RB_CNTL 0x0704 1114# define RADEON_BUF_SWAP_32BIT (2 << 16) 1115# define RADEON_RB_NO_UPDATE (1 << 27) 1116# define RADEON_RB_RPTR_WR_ENA (1 << 31) 1117#define RADEON_CP_RB_RPTR_ADDR 0x070c 1118#define RADEON_CP_RB_RPTR 0x0710 1119#define RADEON_CP_RB_WPTR 0x0714 1120 1121#define RADEON_CP_RB_WPTR_DELAY 0x0718 1122# define RADEON_PRE_WRITE_TIMER_SHIFT 0 1123# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1124 1125#define RADEON_CP_IB_BASE 0x0738 1126 1127#define RADEON_CP_CSQ_CNTL 0x0740 1128# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1129# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1130# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1131# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1132# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1133# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1134# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1135 1136#define RADEON_AIC_CNTL 0x01d0 1137# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1138# define RS400_MSI_REARM (1 << 3) 1139#define RADEON_AIC_STAT 0x01d4 1140#define RADEON_AIC_PT_BASE 0x01d8 1141#define RADEON_AIC_LO_ADDR 0x01dc 1142#define RADEON_AIC_HI_ADDR 0x01e0 1143#define RADEON_AIC_TLB_ADDR 0x01e4 1144#define RADEON_AIC_TLB_DATA 0x01e8 1145 1146/* CP command packets */ 1147#define RADEON_CP_PACKET0 0x00000000 1148# define RADEON_ONE_REG_WR (1 << 15) 1149#define RADEON_CP_PACKET1 0x40000000 1150#define RADEON_CP_PACKET2 0x80000000 1151#define RADEON_CP_PACKET3 0xC0000000 1152# define RADEON_CP_NOP 0x00001000 1153# define RADEON_CP_NEXT_CHAR 0x00001900 1154# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1155# define RADEON_CP_SET_SCISSORS 0x00001E00 1156 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1157# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1158# define RADEON_WAIT_FOR_IDLE 0x00002600 1159# define RADEON_3D_DRAW_VBUF 0x00002800 1160# define RADEON_3D_DRAW_IMMD 0x00002900 1161# define RADEON_3D_DRAW_INDX 0x00002A00 1162# define RADEON_CP_LOAD_PALETTE 0x00002C00 1163# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1164# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1165# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1166# define RADEON_3D_CLEAR_ZMASK 0x00003200 1167# define RADEON_CP_INDX_BUFFER 0x00003300 1168# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1169# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1170# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1171# define RADEON_3D_CLEAR_HIZ 0x00003700 1172# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1173# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1174# define RADEON_CNTL_PAINT_MULTI 0x00009A00 1175# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1176# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1177 1178# define R600_IT_INDIRECT_BUFFER 0x00003200 1179# define R600_IT_ME_INITIALIZE 0x00004400 1180# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1181# define R600_IT_EVENT_WRITE 0x00004600 1182# define R600_IT_SET_CONFIG_REG 0x00006800 1183# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1184# define R600_SET_CONFIG_REG_END 0x0000ac00 1185 1186#define RADEON_CP_PACKET_MASK 0xC0000000 1187#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1188#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1189#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1190#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1191 1192#define RADEON_VTX_Z_PRESENT (1 << 31) 1193#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1194 1195#define RADEON_PRIM_TYPE_NONE (0 << 0) 1196#define RADEON_PRIM_TYPE_POINT (1 << 0) 1197#define RADEON_PRIM_TYPE_LINE (2 << 0) 1198#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1199#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1200#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1201#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1202#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1203#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1204#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1205#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1206#define RADEON_PRIM_TYPE_MASK 0xf 1207#define RADEON_PRIM_WALK_IND (1 << 4) 1208#define RADEON_PRIM_WALK_LIST (2 << 4) 1209#define RADEON_PRIM_WALK_RING (3 << 4) 1210#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1211#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1212#define RADEON_MAOS_ENABLE (1 << 7) 1213#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1214#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1215#define RADEON_NUM_VERTICES_SHIFT 16 1216 1217#define RADEON_COLOR_FORMAT_CI8 2 1218#define RADEON_COLOR_FORMAT_ARGB1555 3 1219#define RADEON_COLOR_FORMAT_RGB565 4 1220#define RADEON_COLOR_FORMAT_ARGB8888 6 1221#define RADEON_COLOR_FORMAT_RGB332 7 1222#define RADEON_COLOR_FORMAT_RGB8 9 1223#define RADEON_COLOR_FORMAT_ARGB4444 15 1224 1225#define RADEON_TXFORMAT_I8 0 1226#define RADEON_TXFORMAT_AI88 1 1227#define RADEON_TXFORMAT_RGB332 2 1228#define RADEON_TXFORMAT_ARGB1555 3 1229#define RADEON_TXFORMAT_RGB565 4 1230#define RADEON_TXFORMAT_ARGB4444 5 1231#define RADEON_TXFORMAT_ARGB8888 6 1232#define RADEON_TXFORMAT_RGBA8888 7 1233#define RADEON_TXFORMAT_Y8 8 1234#define RADEON_TXFORMAT_VYUY422 10 1235#define RADEON_TXFORMAT_YVYU422 11 1236#define RADEON_TXFORMAT_DXT1 12 1237#define RADEON_TXFORMAT_DXT23 14 1238#define RADEON_TXFORMAT_DXT45 15 1239 1240#define R200_PP_TXCBLEND_0 0x2f00 1241#define R200_PP_TXCBLEND_1 0x2f10 1242#define R200_PP_TXCBLEND_2 0x2f20 1243#define R200_PP_TXCBLEND_3 0x2f30 1244#define R200_PP_TXCBLEND_4 0x2f40 1245#define R200_PP_TXCBLEND_5 0x2f50 1246#define R200_PP_TXCBLEND_6 0x2f60 1247#define R200_PP_TXCBLEND_7 0x2f70 1248#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1249#define R200_PP_TFACTOR_0 0x2ee0 1250#define R200_SE_VTX_FMT_0 0x2088 1251#define R200_SE_VAP_CNTL 0x2080 1252#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1253#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1254#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1255#define R200_PP_TXFILTER_5 0x2ca0 1256#define R200_PP_TXFILTER_4 0x2c80 1257#define R200_PP_TXFILTER_3 0x2c60 1258#define R200_PP_TXFILTER_2 0x2c40 1259#define R200_PP_TXFILTER_1 0x2c20 1260#define R200_PP_TXFILTER_0 0x2c00 1261#define R200_PP_TXOFFSET_5 0x2d78 1262#define R200_PP_TXOFFSET_4 0x2d60 1263#define R200_PP_TXOFFSET_3 0x2d48 1264#define R200_PP_TXOFFSET_2 0x2d30 1265#define R200_PP_TXOFFSET_1 0x2d18 1266#define R200_PP_TXOFFSET_0 0x2d00 1267 1268#define R200_PP_CUBIC_FACES_0 0x2c18 1269#define R200_PP_CUBIC_FACES_1 0x2c38 1270#define R200_PP_CUBIC_FACES_2 0x2c58 1271#define R200_PP_CUBIC_FACES_3 0x2c78 1272#define R200_PP_CUBIC_FACES_4 0x2c98 1273#define R200_PP_CUBIC_FACES_5 0x2cb8 1274#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1275#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1276#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1277#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1278#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1279#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1280#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1281#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1282#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1283#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1284#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1285#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1286#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1287#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1288#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1289#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1290#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1291#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1292#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1293#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1294#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1295#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1296#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1297#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1298#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1299#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1300#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1301#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1302#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1303#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1304 1305#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1306#define R200_SE_VTE_CNTL 0x20b0 1307#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1308#define R200_PP_TAM_DEBUG3 0x2d9c 1309#define R200_PP_CNTL_X 0x2cc4 1310#define R200_SE_VAP_CNTL_STATUS 0x2140 1311#define R200_RE_SCISSOR_TL_0 0x1cd8 1312#define R200_RE_SCISSOR_TL_1 0x1ce0 1313#define R200_RE_SCISSOR_TL_2 0x1ce8 1314#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1315#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1316#define R200_SE_VTX_STATE_CNTL 0x2180 1317#define R200_RE_POINTSIZE 0x2648 1318#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1319 1320#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1321#define RADEON_PP_TEX_SIZE_1 0x1d0c 1322#define RADEON_PP_TEX_SIZE_2 0x1d14 1323 1324#define RADEON_PP_CUBIC_FACES_0 0x1d24 1325#define RADEON_PP_CUBIC_FACES_1 0x1d28 1326#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1327#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1328#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1329#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1330 1331#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1332 1333#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1334#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1335#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1336#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1337#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1338#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1339#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1340#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1341#define R200_3D_DRAW_IMMD_2 0xC0003500 1342#define R200_SE_VTX_FMT_1 0x208c 1343#define R200_RE_CNTL 0x1c50 1344 1345#define R200_RB3D_BLENDCOLOR 0x3218 1346 1347#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1348 1349#define R200_PP_TRI_PERF 0x2cf8 1350 1351#define R200_PP_AFS_0 0x2f80 1352#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1353 1354#define R200_VAP_PVS_CNTL_1 0x22D0 1355 1356#define RADEON_CRTC_CRNT_FRAME 0x0214 1357#define RADEON_CRTC2_CRNT_FRAME 0x0314 1358 1359#define R500_D1CRTC_STATUS 0x609c 1360#define R500_D2CRTC_STATUS 0x689c 1361#define R500_CRTC_V_BLANK (1<<0) 1362 1363#define R500_D1CRTC_FRAME_COUNT 0x60a4 1364#define R500_D2CRTC_FRAME_COUNT 0x68a4 1365 1366#define R500_D1MODE_V_COUNTER 0x6530 1367#define R500_D2MODE_V_COUNTER 0x6d30 1368 1369#define R500_D1MODE_VBLANK_STATUS 0x6534 1370#define R500_D2MODE_VBLANK_STATUS 0x6d34 1371#define R500_VBLANK_OCCURED (1<<0) 1372#define R500_VBLANK_ACK (1<<4) 1373#define R500_VBLANK_STAT (1<<12) 1374#define R500_VBLANK_INT (1<<16) 1375 1376#define R500_DxMODE_INT_MASK 0x6540 1377#define R500_D1MODE_INT_MASK (1<<0) 1378#define R500_D2MODE_INT_MASK (1<<8) 1379 1380#define R500_DISP_INTERRUPT_STATUS 0x7edc 1381#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1382#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1383 1384/* R6xx/R7xx registers */ 1385#define R600_MC_VM_FB_LOCATION 0x2180 1386#define R600_MC_VM_AGP_TOP 0x2184 1387#define R600_MC_VM_AGP_BOT 0x2188 1388#define R600_MC_VM_AGP_BASE 0x218c 1389#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1390#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1391#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1392 1393#define R700_MC_VM_FB_LOCATION 0x2024 1394#define R700_MC_VM_AGP_TOP 0x2028 1395#define R700_MC_VM_AGP_BOT 0x202c 1396#define R700_MC_VM_AGP_BASE 0x2030 1397#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1398#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1399#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1400 1401#define R600_MCD_RD_A_CNTL 0x219c 1402#define R600_MCD_RD_B_CNTL 0x21a0 1403 1404#define R600_MCD_WR_A_CNTL 0x21a4 1405#define R600_MCD_WR_B_CNTL 0x21a8 1406 1407#define R600_MCD_RD_SYS_CNTL 0x2200 1408#define R600_MCD_WR_SYS_CNTL 0x2214 1409 1410#define R600_MCD_RD_GFX_CNTL 0x21fc 1411#define R600_MCD_RD_HDP_CNTL 0x2204 1412#define R600_MCD_RD_PDMA_CNTL 0x2208 1413#define R600_MCD_RD_SEM_CNTL 0x220c 1414#define R600_MCD_WR_GFX_CNTL 0x2210 1415#define R600_MCD_WR_HDP_CNTL 0x2218 1416#define R600_MCD_WR_PDMA_CNTL 0x221c 1417#define R600_MCD_WR_SEM_CNTL 0x2220 1418 1419# define R600_MCD_L1_TLB (1 << 0) 1420# define R600_MCD_L1_FRAG_PROC (1 << 1) 1421# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1422 1423# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1424# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1425# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1426# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1427# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1428 1429# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1430# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1431 1432# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1433# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1434# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1435# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1436 1437#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1438#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1439#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1440 1441#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1442#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1443#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1444#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1445 1446# define R700_ENABLE_L1_TLB (1 << 0) 1447# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1448# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1449# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1450# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1451# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1452 1453#define R700_MC_ARB_RAMCFG 0x2760 1454# define R700_NOOFBANK_SHIFT 0 1455# define R700_NOOFBANK_MASK 0x3 1456# define R700_NOOFRANK_SHIFT 2 1457# define R700_NOOFRANK_MASK 0x1 1458# define R700_NOOFROWS_SHIFT 3 1459# define R700_NOOFROWS_MASK 0x7 1460# define R700_NOOFCOLS_SHIFT 6 1461# define R700_NOOFCOLS_MASK 0x3 1462# define R700_CHANSIZE_SHIFT 8 1463# define R700_CHANSIZE_MASK 0x1 1464# define R700_BURSTLENGTH_SHIFT 9 1465# define R700_BURSTLENGTH_MASK 0x1 1466#define R600_RAMCFG 0x2408 1467# define R600_NOOFBANK_SHIFT 0 1468# define R600_NOOFBANK_MASK 0x1 1469# define R600_NOOFRANK_SHIFT 1 1470# define R600_NOOFRANK_MASK 0x1 1471# define R600_NOOFROWS_SHIFT 2 1472# define R600_NOOFROWS_MASK 0x7 1473# define R600_NOOFCOLS_SHIFT 5 1474# define R600_NOOFCOLS_MASK 0x3 1475# define R600_CHANSIZE_SHIFT 7 1476# define R600_CHANSIZE_MASK 0x1 1477# define R600_BURSTLENGTH_SHIFT 8 1478# define R600_BURSTLENGTH_MASK 0x1 1479 1480#define R600_VM_L2_CNTL 0x1400 1481# define R600_VM_L2_CACHE_EN (1 << 0) 1482# define R600_VM_L2_FRAG_PROC (1 << 1) 1483# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1484# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1485# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1486 1487#define R600_VM_L2_CNTL2 0x1404 1488# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1489# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1490#define R600_VM_L2_CNTL3 0x1408 1491# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1492# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1493# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1494# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1495# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1496 1497#define R600_VM_L2_STATUS 0x140c 1498 1499#define R600_VM_CONTEXT0_CNTL 0x1410 1500# define R600_VM_ENABLE_CONTEXT (1 << 0) 1501# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1502 1503#define R600_VM_CONTEXT0_CNTL2 0x1430 1504#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1505#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1506#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1507#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1508#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1509#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1510 1511#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1512#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1513#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1514 1515#define R600_HDP_HOST_PATH_CNTL 0x2c00 1516 1517#define R600_GRBM_CNTL 0x8000 1518# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1519 1520#define R600_GRBM_STATUS 0x8010 1521# define R600_CMDFIFO_AVAIL_MASK 0x1f 1522# define R700_CMDFIFO_AVAIL_MASK 0xf 1523# define R600_GUI_ACTIVE (1 << 31) 1524#define R600_GRBM_STATUS2 0x8014 1525#define R600_GRBM_SOFT_RESET 0x8020 1526# define R600_SOFT_RESET_CP (1 << 0) 1527#define R600_WAIT_UNTIL 0x8040 1528 1529#define R600_CP_SEM_WAIT_TIMER 0x85bc 1530#define R600_CP_ME_CNTL 0x86d8 1531# define R600_CP_ME_HALT (1 << 28) 1532#define R600_CP_QUEUE_THRESHOLDS 0x8760 1533# define R600_ROQ_IB1_START(x) ((x) << 0) 1534# define R600_ROQ_IB2_START(x) ((x) << 8) 1535#define R600_CP_MEQ_THRESHOLDS 0x8764 1536# define R700_STQ_SPLIT(x) ((x) << 0) 1537# define R600_MEQ_END(x) ((x) << 16) 1538# define R600_ROQ_END(x) ((x) << 24) 1539#define R600_CP_PERFMON_CNTL 0x87fc 1540#define R600_CP_RB_BASE 0xc100 1541#define R600_CP_RB_CNTL 0xc104 1542# define R600_RB_BUFSZ(x) ((x) << 0) 1543# define R600_RB_BLKSZ(x) ((x) << 8) 1544# define R600_RB_NO_UPDATE (1 << 27) 1545# define R600_RB_RPTR_WR_ENA (1 << 31) 1546#define R600_CP_RB_RPTR_WR 0xc108 1547#define R600_CP_RB_RPTR_ADDR 0xc10c 1548#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1549#define R600_CP_RB_WPTR 0xc114 1550#define R600_CP_RB_WPTR_ADDR 0xc118 1551#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1552#define R600_CP_RB_RPTR 0x8700 1553#define R600_CP_RB_WPTR_DELAY 0x8704 1554#define R600_CP_PFP_UCODE_ADDR 0xc150 1555#define R600_CP_PFP_UCODE_DATA 0xc154 1556#define R600_CP_ME_RAM_RADDR 0xc158 1557#define R600_CP_ME_RAM_WADDR 0xc15c 1558#define R600_CP_ME_RAM_DATA 0xc160 1559#define R600_CP_DEBUG 0xc1fc 1560 1561#define R600_PA_CL_ENHANCE 0x8a14 1562# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1563# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1564#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1565#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1566#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1567# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1568# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1569#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1570#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1571#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1572#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1573# define R600_S0_X(x) ((x) << 0) 1574# define R600_S0_Y(x) ((x) << 4) 1575# define R600_S1_X(x) ((x) << 8) 1576# define R600_S1_Y(x) ((x) << 12) 1577# define R600_S2_X(x) ((x) << 16) 1578# define R600_S2_Y(x) ((x) << 20) 1579# define R600_S3_X(x) ((x) << 24) 1580# define R600_S3_Y(x) ((x) << 28) 1581# define R600_S4_X(x) ((x) << 0) 1582# define R600_S4_Y(x) ((x) << 4) 1583# define R600_S5_X(x) ((x) << 8) 1584# define R600_S5_Y(x) ((x) << 12) 1585# define R600_S6_X(x) ((x) << 16) 1586# define R600_S6_Y(x) ((x) << 20) 1587# define R600_S7_X(x) ((x) << 24) 1588# define R600_S7_Y(x) ((x) << 28) 1589#define R600_PA_SC_FIFO_SIZE 0x8bd0 1590# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1591# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1592# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1593#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1594# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1595# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1596# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1597#define R600_PA_SC_ENHANCE 0x8bf0 1598# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1599# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1600#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1601#define R700_PA_SC_EDGERULE 0x28230 1602#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1603#define R600_PA_SC_MODE_CNTL 0x28a4c 1604#define R600_PA_SC_AA_CONFIG 0x28c04 1605 1606#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1607# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1608# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1609# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1610#define R600_SX_DEBUG_1 0x9054 1611# define R600_SMX_EVENT_RELEASE (1 << 0) 1612# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1613#define R700_SX_DEBUG_1 0x9058 1614# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1615#define R600_SX_MISC 0x28350 1616 1617#define R600_DB_DEBUG 0x9830 1618# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1619#define R600_DB_WATERMARKS 0x9838 1620# define R600_DEPTH_FREE(x) ((x) << 0) 1621# define R600_DEPTH_FLUSH(x) ((x) << 5) 1622# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1623# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1624#define R700_DB_DEBUG3 0x98b0 1625# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1626#define RV700_DB_DEBUG4 0x9b8c 1627# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1628 1629#define R600_VGT_CACHE_INVALIDATION 0x88c4 1630# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1631# define R600_VC_ONLY 0 1632# define R600_TC_ONLY 1 1633# define R600_VC_AND_TC 2 1634# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1635# define R700_NO_AUTO 0 1636# define R700_ES_AUTO 1 1637# define R700_GS_AUTO 2 1638# define R700_ES_AND_GS_AUTO 3 1639#define R600_VGT_GS_PER_ES 0x88c8 1640#define R600_VGT_ES_PER_GS 0x88cc 1641#define R600_VGT_GS_PER_VS 0x88e8 1642#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1643#define R600_VGT_NUM_INSTANCES 0x8974 1644#define R600_VGT_STRMOUT_EN 0x28ab0 1645#define R600_VGT_EVENT_INITIATOR 0x28a90 1646# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1647#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1648# define R600_VTX_REUSE_DEPTH_MASK 0xff 1649#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1650# define R600_DEALLOC_DIST_MASK 0x7f 1651 1652#define R600_CB_COLOR0_BASE 0x28040 1653#define R600_CB_COLOR1_BASE 0x28044 1654#define R600_CB_COLOR2_BASE 0x28048 1655#define R600_CB_COLOR3_BASE 0x2804c 1656#define R600_CB_COLOR4_BASE 0x28050 1657#define R600_CB_COLOR5_BASE 0x28054 1658#define R600_CB_COLOR6_BASE 0x28058 1659#define R600_CB_COLOR7_BASE 0x2805c 1660#define R600_CB_COLOR7_FRAG 0x280fc 1661 1662#define R600_TC_CNTL 0x9608 1663# define R600_TC_L2_SIZE(x) ((x) << 5) 1664# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1665 1666#define R600_ARB_POP 0x2418 1667# define R600_ENABLE_TC128 (1 << 30) 1668#define R600_ARB_GDEC_RD_CNTL 0x246c 1669 1670#define R600_TA_CNTL_AUX 0x9508 1671# define R600_DISABLE_CUBE_WRAP (1 << 0) 1672# define R600_DISABLE_CUBE_ANISO (1 << 1) 1673# define R700_GETLOD_SELECT(x) ((x) << 2) 1674# define R600_SYNC_GRADIENT (1 << 24) 1675# define R600_SYNC_WALKER (1 << 25) 1676# define R600_SYNC_ALIGNER (1 << 26) 1677# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1678# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1679 1680#define R700_TCP_CNTL 0x9610 1681 1682#define R600_SMX_DC_CTL0 0xa020 1683# define R700_USE_HASH_FUNCTION (1 << 0) 1684# define R700_CACHE_DEPTH(x) ((x) << 1) 1685# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1686# define R700_STALL_ON_EVENT (1 << 11) 1687#define R700_SMX_EVENT_CTL 0xa02c 1688# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1689# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1690# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1691# define R700_SYNC_FLUSH_CTL (1 << 8) 1692 1693#define R600_SQ_CONFIG 0x8c00 1694# define R600_VC_ENABLE (1 << 0) 1695# define R600_EXPORT_SRC_C (1 << 1) 1696# define R600_DX9_CONSTS (1 << 2) 1697# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1698# define R600_DX10_CLAMP (1 << 4) 1699# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1700# define R600_PS_PRIO(x) ((x) << 24) 1701# define R600_VS_PRIO(x) ((x) << 26) 1702# define R600_GS_PRIO(x) ((x) << 28) 1703# define R600_ES_PRIO(x) ((x) << 30) 1704#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1705# define R600_NUM_PS_GPRS(x) ((x) << 0) 1706# define R600_NUM_VS_GPRS(x) ((x) << 16) 1707# define R700_DYN_GPR_ENABLE (1 << 27) 1708# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1709#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1710# define R600_NUM_GS_GPRS(x) ((x) << 0) 1711# define R600_NUM_ES_GPRS(x) ((x) << 16) 1712#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1713# define R600_NUM_PS_THREADS(x) ((x) << 0) 1714# define R600_NUM_VS_THREADS(x) ((x) << 8) 1715# define R600_NUM_GS_THREADS(x) ((x) << 16) 1716# define R600_NUM_ES_THREADS(x) ((x) << 24) 1717#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1718# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1719# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1720#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1721# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1722# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1723#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1724# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1725# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1726# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1727# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1728#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1729# define R700_SIMDA_RING0(x) ((x) << 0) 1730# define R700_SIMDA_RING1(x) ((x) << 8) 1731# define R700_SIMDB_RING0(x) ((x) << 16) 1732# define R700_SIMDB_RING1(x) ((x) << 24) 1733#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1734#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1735#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1736#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1737#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1738#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1739#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1740 1741#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1742# define R600_NUM_INTERP(x) ((x) << 0) 1743# define R600_POSITION_ENA (1 << 8) 1744# define R600_POSITION_CENTROID (1 << 9) 1745# define R600_POSITION_ADDR(x) ((x) << 10) 1746# define R600_PARAM_GEN(x) ((x) << 15) 1747# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1748# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1749# define R600_PERSP_GRADIENT_ENA (1 << 28) 1750# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1751# define R600_POSITION_SAMPLE (1 << 30) 1752# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1753#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1754# define R600_GEN_INDEX_PIX (1 << 0) 1755# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1756# define R600_FRONT_FACE_ENA (1 << 8) 1757# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1758# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1759# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1760# define R600_FOG_ADDR(x) ((x) << 17) 1761# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1762# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1763# define R700_POSITION_ULC (1 << 30) 1764#define R600_SPI_INPUT_Z 0x286d8 1765 1766#define R600_SPI_CONFIG_CNTL 0x9100 1767# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1768# define R600_DISABLE_INTERP_1 (1 << 5) 1769#define R600_SPI_CONFIG_CNTL_1 0x913c 1770# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1771# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1772 1773#define R600_GB_TILING_CONFIG 0x98f0 1774# define R600_PIPE_TILING(x) ((x) << 1) 1775# define R600_BANK_TILING(x) ((x) << 4) 1776# define R600_GROUP_SIZE(x) ((x) << 6) 1777# define R600_ROW_TILING(x) ((x) << 8) 1778# define R600_BANK_SWAPS(x) ((x) << 11) 1779# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1780# define R600_BACKEND_MAP(x) ((x) << 16) 1781#define R600_DCP_TILING_CONFIG 0x6ca0 1782#define R600_HDP_TILING_CONFIG 0x2f3c 1783 1784#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1785#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1786# define R600_BACKEND_DISABLE(x) ((x) << 16) 1787 1788#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1789#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1790# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1791# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1792# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1793# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1794 1795#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1796#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1797#define R700_CGTS_TCC_DISABLE 0x9148 1798#define R700_CGTS_USER_TCC_DISABLE 0x914c 1799 1800/* Constants */ 1801#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1802 1803#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1804#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1805#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1806#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1807#define RADEON_LAST_DISPATCH 1 1808 1809#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1810#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1811#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1812#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1813 1814#define RADEON_MAX_VB_AGE 0x7fffffff 1815#define RADEON_MAX_VB_VERTS (0xffff) 1816 1817#define RADEON_RING_HIGH_MARK 128 1818 1819#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1820 1821#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1822#define RADEON_WRITE(reg, val) \ 1823do { \ 1824 if (reg < 0x10000) { \ 1825 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1826 } else { \ 1827 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1828 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1829 } \ 1830} while (0) 1831#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1832#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1833 1834#define RADEON_WRITE_PLL(addr, val) \ 1835do { \ 1836 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1837 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1838 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1839} while (0) 1840 1841#define RADEON_WRITE_PCIE(addr, val) \ 1842do { \ 1843 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1844 ((addr) & 0xff)); \ 1845 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1846} while (0) 1847 1848#define R500_WRITE_MCIND(addr, val) \ 1849do { \ 1850 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1851 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1852 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1853} while (0) 1854 1855#define RS480_WRITE_MCIND(addr, val) \ 1856do { \ 1857 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1858 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1859 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1860 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1861} while (0) 1862 1863#define RS690_WRITE_MCIND(addr, val) \ 1864do { \ 1865 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1866 RADEON_WRITE(RS690_MC_DATA, val); \ 1867 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1868} while (0) 1869 1870#define RS600_WRITE_MCIND(addr, val) \ 1871do { \ 1872 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1873 RADEON_WRITE(RS600_MC_DATA, val); \ 1874} while (0) 1875 1876#define IGP_WRITE_MCIND(addr, val) \ 1877do { \ 1878 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1879 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1880 RS690_WRITE_MCIND(addr, val); \ 1881 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1882 RS600_WRITE_MCIND(addr, val); \ 1883 else \ 1884 RS480_WRITE_MCIND(addr, val); \ 1885} while (0) 1886 1887#define CP_PACKET0( reg, n ) \ 1888 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1889#define CP_PACKET0_TABLE( reg, n ) \ 1890 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1891#define CP_PACKET1( reg0, reg1 ) \ 1892 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1893#define CP_PACKET2() \ 1894 (RADEON_CP_PACKET2) 1895#define CP_PACKET3( pkt, n ) \ 1896 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1897 1898/* ================================================================ 1899 * Engine control helper macros 1900 */ 1901 1902#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
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1830 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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1903 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1904 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1905 else \ 1906 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1907 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1908 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1909} while (0) 1910 1911#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
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1836 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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1912 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1913 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1914 else \ 1915 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1916 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1917 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1918} while (0) 1919 1920#define RADEON_WAIT_UNTIL_IDLE() do { \
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1842 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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1921 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1922 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1923 else \ 1924 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1925 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1926 RADEON_WAIT_3D_IDLECLEAN | \ 1927 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1928} while (0) 1929 1930#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
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1849 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
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1931 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1932 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1933 else \ 1934 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1935 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1936} while (0) 1937 1938#define RADEON_FLUSH_CACHE() do { \ 1939 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1940 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1941 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1942 } else { \ 1943 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1944 OUT_RING(R300_RB3D_DC_FLUSH); \ 1945 } \ 1946} while (0) 1947 1948#define RADEON_PURGE_CACHE() do { \ 1949 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1950 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1951 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1952 } else { \ 1953 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1954 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1955 } \ 1956} while (0) 1957 1958#define RADEON_FLUSH_ZCACHE() do { \ 1959 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1960 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1961 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1962 } else { \ 1963 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1964 OUT_RING(R300_ZC_FLUSH); \ 1965 } \ 1966} while (0) 1967 1968#define RADEON_PURGE_ZCACHE() do { \ 1969 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1970 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1971 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1972 } else { \ 1973 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1974 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1975 } \ 1976} while (0) 1977 1978/* ================================================================ 1979 * Misc helper macros 1980 */ 1981 1982/* Perfbox functionality only. 1983 */ 1984#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1985do { \ 1986 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1987 u32 head = GET_RING_HEAD( dev_priv ); \ 1988 if (head == dev_priv->ring.tail) \ 1989 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1990 } \ 1991} while (0) 1992 1993#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1994do { \ 1995 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1996 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1997 int __ret; \ 1998 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1999 __ret = r600_do_cp_idle(dev_priv); \ 2000 else \ 2001 __ret = radeon_do_cp_idle(dev_priv); \ 2002 if ( __ret ) return __ret; \ 2003 sarea_priv->last_dispatch = 0; \ 2004 radeon_freelist_reset( dev ); \ 2005 } \ 2006} while (0) 2007 2008#define RADEON_DISPATCH_AGE( age ) do { \ 2009 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2010 OUT_RING( age ); \ 2011} while (0) 2012 2013#define RADEON_FRAME_AGE( age ) do { \ 2014 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2015 OUT_RING( age ); \ 2016} while (0) 2017 2018#define RADEON_CLEAR_AGE( age ) do { \ 2019 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2020 OUT_RING( age ); \ 2021} while (0) 2022 2023#define R600_DISPATCH_AGE(age) do { \ 2024 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2025 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2026 OUT_RING(age); \ 2027} while (0) 2028 2029#define R600_FRAME_AGE(age) do { \ 2030 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2031 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2032 OUT_RING(age); \ 2033} while (0) 2034 2035#define R600_CLEAR_AGE(age) do { \ 2036 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2037 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2038 OUT_RING(age); \ 2039} while (0) 2040 2041/* ================================================================ 2042 * Ring control 2043 */ 2044 2045#define RADEON_VERBOSE 0 2046 2047#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2048
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2049#define RADEON_RING_ALIGN 16 2050 |
2051#define BEGIN_RING( n ) do { \ 2052 if ( RADEON_VERBOSE ) { \ 2053 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2054 } \
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1968 _align_nr = (n + 0xf) & ~0xf; \
1969 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
1970 COMMIT_RING(); \
1971 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
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2055 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \ 2056 _align_nr += n; \ 2057 if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \ 2058 COMMIT_RING(); \ 2059 radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \ |
2060 } \ 2061 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2062 ring = dev_priv->ring.start; \ 2063 write = dev_priv->ring.tail; \ 2064 mask = dev_priv->ring.tail_mask; \ 2065} while (0) 2066 2067#define ADVANCE_RING() do { \ 2068 if ( RADEON_VERBOSE ) { \ 2069 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2070 write, dev_priv->ring.tail ); \ 2071 } \ 2072 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2073 DRM_ERROR( \ 2074 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2075 ((dev_priv->ring.tail + _nr) & mask), \ 2076 write, __LINE__); \ 2077 } else \ 2078 dev_priv->ring.tail = write; \ 2079} while (0) 2080 2081extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2082 2083#define COMMIT_RING() do { \ 2084 radeon_commit_ring(dev_priv); \ 2085 } while(0) 2086 2087#define OUT_RING( x ) do { \ 2088 if ( RADEON_VERBOSE ) { \ 2089 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2090 (unsigned int)(x), write ); \ 2091 } \ 2092 ring[write++] = (x); \ 2093 write &= mask; \ 2094} while (0) 2095 2096#define OUT_RING_REG( reg, val ) do { \ 2097 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2098 OUT_RING( val ); \ 2099} while (0) 2100 2101#define OUT_RING_TABLE( tab, sz ) do { \ 2102 int _size = (sz); \ 2103 int *_tab = (int *)(tab); \ 2104 \ 2105 if (write + _size > mask) { \ 2106 int _i = (mask+1) - write; \ 2107 _size -= _i; \ 2108 while (_i > 0 ) { \ 2109 *(int *)(ring + write) = *_tab++; \ 2110 write++; \ 2111 _i--; \ 2112 } \ 2113 write = 0; \ 2114 _tab += _i; \ 2115 } \ 2116 while (_size > 0) { \ 2117 *(ring + write) = *_tab++; \ 2118 write++; \ 2119 _size--; \ 2120 } \ 2121 write &= mask; \ 2122} while (0) 2123 2124#endif /* __RADEON_DRV_H__ */
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