1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
| 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
|
30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 119098 2003-08-19 02:57:31Z anholt $
| 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 119895 2003-09-09 00:24:31Z anholt $
|
31 */
32
33#ifndef __RADEON_DRV_H__
34#define __RADEON_DRV_H__
35
36#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
37#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
38
39typedef struct drm_radeon_freelist {
40 unsigned int age;
41 drm_buf_t *buf;
42 struct drm_radeon_freelist *next;
43 struct drm_radeon_freelist *prev;
44} drm_radeon_freelist_t;
45
46typedef struct drm_radeon_ring_buffer {
47 u32 *start;
48 u32 *end;
49 int size;
50 int size_l2qw;
51
52 u32 tail;
53 u32 tail_mask;
54 int space;
55
56 int high_mark;
57} drm_radeon_ring_buffer_t;
58
59typedef struct drm_radeon_depth_clear_t {
60 u32 rb3d_cntl;
61 u32 rb3d_zstencilcntl;
62 u32 se_cntl;
63} drm_radeon_depth_clear_t;
64
65
66struct mem_block {
67 struct mem_block *next;
68 struct mem_block *prev;
69 int start;
70 int size;
71 DRMFILE filp; /* 0: free, -1: heap, other: real files */
72};
73
74typedef struct drm_radeon_private {
75 drm_radeon_ring_buffer_t ring;
76 drm_radeon_sarea_t *sarea_priv;
77
| 31 */
32
33#ifndef __RADEON_DRV_H__
34#define __RADEON_DRV_H__
35
36#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
37#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
38
39typedef struct drm_radeon_freelist {
40 unsigned int age;
41 drm_buf_t *buf;
42 struct drm_radeon_freelist *next;
43 struct drm_radeon_freelist *prev;
44} drm_radeon_freelist_t;
45
46typedef struct drm_radeon_ring_buffer {
47 u32 *start;
48 u32 *end;
49 int size;
50 int size_l2qw;
51
52 u32 tail;
53 u32 tail_mask;
54 int space;
55
56 int high_mark;
57} drm_radeon_ring_buffer_t;
58
59typedef struct drm_radeon_depth_clear_t {
60 u32 rb3d_cntl;
61 u32 rb3d_zstencilcntl;
62 u32 se_cntl;
63} drm_radeon_depth_clear_t;
64
65
66struct mem_block {
67 struct mem_block *next;
68 struct mem_block *prev;
69 int start;
70 int size;
71 DRMFILE filp; /* 0: free, -1: heap, other: real files */
72};
73
74typedef struct drm_radeon_private {
75 drm_radeon_ring_buffer_t ring;
76 drm_radeon_sarea_t *sarea_priv;
77
|
78 int agp_size;
79 u32 agp_vm_start;
80 unsigned long agp_buffers_offset;
| 78 int gart_size;
79 u32 gart_vm_start;
80 unsigned long gart_buffers_offset;
|
81
82 int cp_mode;
83 int cp_running;
84
85 drm_radeon_freelist_t *head;
86 drm_radeon_freelist_t *tail;
87 int last_buf;
88 volatile u32 *scratch;
89 int writeback_works;
90
91 int usec_timeout;
92
93 int is_r200;
94
95 int is_pci;
96 unsigned long phys_pci_gart;
97 dma_addr_t bus_pci_gart;
98
99 struct {
100 u32 boxes;
101 int freelist_timeouts;
102 int freelist_loops;
103 int requested_bufs;
104 int last_frame_reads;
105 int last_clear_reads;
106 int clears;
107 int texture_uploads;
108 } stats;
109
110 int do_boxes;
111 int page_flipping;
112 int current_page;
113
114 u32 color_fmt;
115 unsigned int front_offset;
116 unsigned int front_pitch;
117 unsigned int back_offset;
118 unsigned int back_pitch;
119
120 u32 depth_fmt;
121 unsigned int depth_offset;
122 unsigned int depth_pitch;
123
124 u32 front_pitch_offset;
125 u32 back_pitch_offset;
126 u32 depth_pitch_offset;
127
128 drm_radeon_depth_clear_t depth_clear;
129
130 unsigned long fb_offset;
131 unsigned long mmio_offset;
132 unsigned long ring_offset;
133 unsigned long ring_rptr_offset;
134 unsigned long buffers_offset;
| 81
82 int cp_mode;
83 int cp_running;
84
85 drm_radeon_freelist_t *head;
86 drm_radeon_freelist_t *tail;
87 int last_buf;
88 volatile u32 *scratch;
89 int writeback_works;
90
91 int usec_timeout;
92
93 int is_r200;
94
95 int is_pci;
96 unsigned long phys_pci_gart;
97 dma_addr_t bus_pci_gart;
98
99 struct {
100 u32 boxes;
101 int freelist_timeouts;
102 int freelist_loops;
103 int requested_bufs;
104 int last_frame_reads;
105 int last_clear_reads;
106 int clears;
107 int texture_uploads;
108 } stats;
109
110 int do_boxes;
111 int page_flipping;
112 int current_page;
113
114 u32 color_fmt;
115 unsigned int front_offset;
116 unsigned int front_pitch;
117 unsigned int back_offset;
118 unsigned int back_pitch;
119
120 u32 depth_fmt;
121 unsigned int depth_offset;
122 unsigned int depth_pitch;
123
124 u32 front_pitch_offset;
125 u32 back_pitch_offset;
126 u32 depth_pitch_offset;
127
128 drm_radeon_depth_clear_t depth_clear;
129
130 unsigned long fb_offset;
131 unsigned long mmio_offset;
132 unsigned long ring_offset;
133 unsigned long ring_rptr_offset;
134 unsigned long buffers_offset;
|
135 unsigned long agp_textures_offset;
| 135 unsigned long gart_textures_offset;
|
136
137 drm_local_map_t *sarea;
138 drm_local_map_t *fb;
139 drm_local_map_t *mmio;
140 drm_local_map_t *cp_ring;
141 drm_local_map_t *ring_rptr;
142 drm_local_map_t *buffers;
| 136
137 drm_local_map_t *sarea;
138 drm_local_map_t *fb;
139 drm_local_map_t *mmio;
140 drm_local_map_t *cp_ring;
141 drm_local_map_t *ring_rptr;
142 drm_local_map_t *buffers;
|
143 drm_local_map_t *agp_textures;
| 143 drm_local_map_t *gart_textures;
|
144
| 144
|
145 struct mem_block *agp_heap;
| 145 struct mem_block *gart_heap;
|
146 struct mem_block *fb_heap;
147
148 /* SW interrupt */
149 wait_queue_head_t swi_queue;
150 atomic_t swi_emitted;
151
152} drm_radeon_private_t;
153
154typedef struct drm_radeon_buf_priv {
155 u32 age;
156} drm_radeon_buf_priv_t;
157
158 /* radeon_cp.c */
159extern int radeon_cp_init( DRM_IOCTL_ARGS );
160extern int radeon_cp_start( DRM_IOCTL_ARGS );
161extern int radeon_cp_stop( DRM_IOCTL_ARGS );
162extern int radeon_cp_reset( DRM_IOCTL_ARGS );
163extern int radeon_cp_idle( DRM_IOCTL_ARGS );
164extern int radeon_cp_resume( DRM_IOCTL_ARGS );
165extern int radeon_engine_reset( DRM_IOCTL_ARGS );
166extern int radeon_fullscreen( DRM_IOCTL_ARGS );
167extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
168
169extern void radeon_freelist_reset( drm_device_t *dev );
170extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
171
172extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
173
174extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
175extern int radeon_do_cleanup_cp( drm_device_t *dev );
176extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
177
178 /* radeon_state.c */
179extern int radeon_cp_clear( DRM_IOCTL_ARGS );
180extern int radeon_cp_swap( DRM_IOCTL_ARGS );
181extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
182extern int radeon_cp_indices( DRM_IOCTL_ARGS );
183extern int radeon_cp_texture( DRM_IOCTL_ARGS );
184extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
185extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
186extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
187extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
188extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
189extern int radeon_cp_flip( DRM_IOCTL_ARGS );
190
191extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
192extern int radeon_mem_free( DRM_IOCTL_ARGS );
193extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
194extern void radeon_mem_takedown( struct mem_block **heap );
195extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
196
197 /* radeon_irq.c */
198extern int radeon_irq_emit( DRM_IOCTL_ARGS );
199extern int radeon_irq_wait( DRM_IOCTL_ARGS );
200
201extern int radeon_emit_and_wait_irq(drm_device_t *dev);
202extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
203extern int radeon_emit_irq(drm_device_t *dev);
204
205extern void radeon_do_release(drm_device_t *dev);
206
207/* Flags for stats.boxes
208 */
209#define RADEON_BOX_DMA_IDLE 0x1
210#define RADEON_BOX_RING_FULL 0x2
211#define RADEON_BOX_FLIP 0x4
212#define RADEON_BOX_WAIT_IDLE 0x8
213#define RADEON_BOX_TEXTURE_LOAD 0x10
214
215
216
217/* Register definitions, register access macros and drmAddMap constants
218 * for Radeon kernel driver.
219 */
220
221#define RADEON_AGP_COMMAND 0x0f60
222#define RADEON_AUX_SCISSOR_CNTL 0x26f0
223# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
224# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
225# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
226# define RADEON_SCISSOR_0_ENABLE (1 << 28)
227# define RADEON_SCISSOR_1_ENABLE (1 << 29)
228# define RADEON_SCISSOR_2_ENABLE (1 << 30)
229
230#define RADEON_BUS_CNTL 0x0030
231# define RADEON_BUS_MASTER_DIS (1 << 6)
232
233#define RADEON_CLOCK_CNTL_DATA 0x000c
234# define RADEON_PLL_WR_EN (1 << 7)
235#define RADEON_CLOCK_CNTL_INDEX 0x0008
236#define RADEON_CONFIG_APER_SIZE 0x0108
237#define RADEON_CRTC_OFFSET 0x0224
238#define RADEON_CRTC_OFFSET_CNTL 0x0228
239# define RADEON_CRTC_TILE_EN (1 << 15)
240# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
241#define RADEON_CRTC2_OFFSET 0x0324
242#define RADEON_CRTC2_OFFSET_CNTL 0x0328
243
244#define RADEON_RB3D_COLORPITCH 0x1c48
245
246#define RADEON_DP_GUI_MASTER_CNTL 0x146c
247# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
248# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
249# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
250# define RADEON_GMC_BRUSH_NONE (15 << 4)
251# define RADEON_GMC_DST_16BPP (4 << 8)
252# define RADEON_GMC_DST_24BPP (5 << 8)
253# define RADEON_GMC_DST_32BPP (6 << 8)
254# define RADEON_GMC_DST_DATATYPE_SHIFT 8
255# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
256# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
257# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
258# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
259# define RADEON_GMC_WR_MSK_DIS (1 << 30)
260# define RADEON_ROP3_S 0x00cc0000
261# define RADEON_ROP3_P 0x00f00000
262#define RADEON_DP_WRITE_MASK 0x16cc
263#define RADEON_DST_PITCH_OFFSET 0x142c
264#define RADEON_DST_PITCH_OFFSET_C 0x1c80
265# define RADEON_DST_TILE_LINEAR (0 << 30)
266# define RADEON_DST_TILE_MACRO (1 << 30)
267# define RADEON_DST_TILE_MICRO (2 << 30)
268# define RADEON_DST_TILE_BOTH (3 << 30)
269
270#define RADEON_SCRATCH_REG0 0x15e0
271#define RADEON_SCRATCH_REG1 0x15e4
272#define RADEON_SCRATCH_REG2 0x15e8
273#define RADEON_SCRATCH_REG3 0x15ec
274#define RADEON_SCRATCH_REG4 0x15f0
275#define RADEON_SCRATCH_REG5 0x15f4
276#define RADEON_SCRATCH_UMSK 0x0770
277#define RADEON_SCRATCH_ADDR 0x0774
278
279#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
280
281#define GET_SCRATCH( x ) (dev_priv->writeback_works \
282 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
283 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
284
285
286#define RADEON_GEN_INT_CNTL 0x0040
287# define RADEON_CRTC_VBLANK_MASK (1 << 0)
288# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
289# define RADEON_SW_INT_ENABLE (1 << 25)
290
291#define RADEON_GEN_INT_STATUS 0x0044
292# define RADEON_CRTC_VBLANK_STAT (1 << 0)
293# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
294# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
295# define RADEON_SW_INT_TEST (1 << 25)
296# define RADEON_SW_INT_TEST_ACK (1 << 25)
297# define RADEON_SW_INT_FIRE (1 << 26)
298
299#define RADEON_HOST_PATH_CNTL 0x0130
300# define RADEON_HDP_SOFT_RESET (1 << 26)
301# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
302# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
303
304#define RADEON_ISYNC_CNTL 0x1724
305# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
306# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
307# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
308# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
309# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
310# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
311
312#define RADEON_RBBM_GUICNTL 0x172c
313# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
314# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
315# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
316# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
317
318#define RADEON_MC_AGP_LOCATION 0x014c
319#define RADEON_MC_FB_LOCATION 0x0148
320#define RADEON_MCLK_CNTL 0x0012
321# define RADEON_FORCEON_MCLKA (1 << 16)
322# define RADEON_FORCEON_MCLKB (1 << 17)
323# define RADEON_FORCEON_YCLKA (1 << 18)
324# define RADEON_FORCEON_YCLKB (1 << 19)
325# define RADEON_FORCEON_MC (1 << 20)
326# define RADEON_FORCEON_AIC (1 << 21)
327
328#define RADEON_PP_BORDER_COLOR_0 0x1d40
329#define RADEON_PP_BORDER_COLOR_1 0x1d44
330#define RADEON_PP_BORDER_COLOR_2 0x1d48
331#define RADEON_PP_CNTL 0x1c38
332# define RADEON_SCISSOR_ENABLE (1 << 1)
333#define RADEON_PP_LUM_MATRIX 0x1d00
334#define RADEON_PP_MISC 0x1c14
335#define RADEON_PP_ROT_MATRIX_0 0x1d58
336#define RADEON_PP_TXFILTER_0 0x1c54
337#define RADEON_PP_TXFILTER_1 0x1c6c
338#define RADEON_PP_TXFILTER_2 0x1c84
339
340#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
341# define RADEON_RB2D_DC_FLUSH (3 << 0)
342# define RADEON_RB2D_DC_FREE (3 << 2)
343# define RADEON_RB2D_DC_FLUSH_ALL 0xf
344# define RADEON_RB2D_DC_BUSY (1 << 31)
345#define RADEON_RB3D_CNTL 0x1c3c
346# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
347# define RADEON_PLANE_MASK_ENABLE (1 << 1)
348# define RADEON_DITHER_ENABLE (1 << 2)
349# define RADEON_ROUND_ENABLE (1 << 3)
350# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
351# define RADEON_DITHER_INIT (1 << 5)
352# define RADEON_ROP_ENABLE (1 << 6)
353# define RADEON_STENCIL_ENABLE (1 << 7)
354# define RADEON_Z_ENABLE (1 << 8)
355#define RADEON_RB3D_DEPTHOFFSET 0x1c24
356#define RADEON_RB3D_DEPTHPITCH 0x1c28
357#define RADEON_RB3D_PLANEMASK 0x1d84
358#define RADEON_RB3D_STENCILREFMASK 0x1d7c
359#define RADEON_RB3D_ZCACHE_MODE 0x3250
360#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
361# define RADEON_RB3D_ZC_FLUSH (1 << 0)
362# define RADEON_RB3D_ZC_FREE (1 << 2)
363# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
364# define RADEON_RB3D_ZC_BUSY (1 << 31)
365#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
366# define RADEON_Z_TEST_MASK (7 << 4)
367# define RADEON_Z_TEST_ALWAYS (7 << 4)
368# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
369# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
370# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
371# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
372# define RADEON_Z_WRITE_ENABLE (1 << 30)
373#define RADEON_RBBM_SOFT_RESET 0x00f0
374# define RADEON_SOFT_RESET_CP (1 << 0)
375# define RADEON_SOFT_RESET_HI (1 << 1)
376# define RADEON_SOFT_RESET_SE (1 << 2)
377# define RADEON_SOFT_RESET_RE (1 << 3)
378# define RADEON_SOFT_RESET_PP (1 << 4)
379# define RADEON_SOFT_RESET_E2 (1 << 5)
380# define RADEON_SOFT_RESET_RB (1 << 6)
381# define RADEON_SOFT_RESET_HDP (1 << 7)
382#define RADEON_RBBM_STATUS 0x0e40
383# define RADEON_RBBM_FIFOCNT_MASK 0x007f
384# define RADEON_RBBM_ACTIVE (1 << 31)
385#define RADEON_RE_LINE_PATTERN 0x1cd0
386#define RADEON_RE_MISC 0x26c4
387#define RADEON_RE_TOP_LEFT 0x26c0
388#define RADEON_RE_WIDTH_HEIGHT 0x1c44
389#define RADEON_RE_STIPPLE_ADDR 0x1cc8
390#define RADEON_RE_STIPPLE_DATA 0x1ccc
391
392#define RADEON_SCISSOR_TL_0 0x1cd8
393#define RADEON_SCISSOR_BR_0 0x1cdc
394#define RADEON_SCISSOR_TL_1 0x1ce0
395#define RADEON_SCISSOR_BR_1 0x1ce4
396#define RADEON_SCISSOR_TL_2 0x1ce8
397#define RADEON_SCISSOR_BR_2 0x1cec
398#define RADEON_SE_COORD_FMT 0x1c50
399#define RADEON_SE_CNTL 0x1c4c
400# define RADEON_FFACE_CULL_CW (0 << 0)
401# define RADEON_BFACE_SOLID (3 << 1)
402# define RADEON_FFACE_SOLID (3 << 3)
403# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
404# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
405# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
406# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
407# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
408# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
409# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
410# define RADEON_FOG_SHADE_FLAT (1 << 14)
411# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
412# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
413# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
414# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
415# define RADEON_ROUND_MODE_TRUNC (0 << 28)
416# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
417#define RADEON_SE_CNTL_STATUS 0x2140
418#define RADEON_SE_LINE_WIDTH 0x1db8
419#define RADEON_SE_VPORT_XSCALE 0x1d98
420#define RADEON_SE_ZBIAS_FACTOR 0x1db0
421#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
422#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
423#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
424# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
425# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
426#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
427#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
428# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
429#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
430#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
431#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
432#define RADEON_SURFACE_CNTL 0x0b00
433# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
434# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
435# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
436# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
437# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
438# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
439# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
440# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
441# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
442#define RADEON_SURFACE0_INFO 0x0b0c
443# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
444# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
445# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
446# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
447# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
448# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
449#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
450#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
451#define RADEON_SURFACE1_INFO 0x0b1c
452#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
453#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
454#define RADEON_SURFACE2_INFO 0x0b2c
455#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
456#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
457#define RADEON_SURFACE3_INFO 0x0b3c
458#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
459#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
460#define RADEON_SURFACE4_INFO 0x0b4c
461#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
462#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
463#define RADEON_SURFACE5_INFO 0x0b5c
464#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
465#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
466#define RADEON_SURFACE6_INFO 0x0b6c
467#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
468#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
469#define RADEON_SURFACE7_INFO 0x0b7c
470#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
471#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
472#define RADEON_SW_SEMAPHORE 0x013c
473
474#define RADEON_WAIT_UNTIL 0x1720
475# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
476# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
477# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
478# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
479
480#define RADEON_RB3D_ZMASKOFFSET 0x1c34
481#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
482# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
483# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
484
485
486/* CP registers */
487#define RADEON_CP_ME_RAM_ADDR 0x07d4
488#define RADEON_CP_ME_RAM_RADDR 0x07d8
489#define RADEON_CP_ME_RAM_DATAH 0x07dc
490#define RADEON_CP_ME_RAM_DATAL 0x07e0
491
492#define RADEON_CP_RB_BASE 0x0700
493#define RADEON_CP_RB_CNTL 0x0704
494# define RADEON_BUF_SWAP_32BIT (2 << 16)
495#define RADEON_CP_RB_RPTR_ADDR 0x070c
496#define RADEON_CP_RB_RPTR 0x0710
497#define RADEON_CP_RB_WPTR 0x0714
498
499#define RADEON_CP_RB_WPTR_DELAY 0x0718
500# define RADEON_PRE_WRITE_TIMER_SHIFT 0
501# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
502
503#define RADEON_CP_IB_BASE 0x0738
504
505#define RADEON_CP_CSQ_CNTL 0x0740
506# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
507# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
508# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
509# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
510# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
511# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
512# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
513
514#define RADEON_AIC_CNTL 0x01d0
515# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
516#define RADEON_AIC_STAT 0x01d4
517#define RADEON_AIC_PT_BASE 0x01d8
518#define RADEON_AIC_LO_ADDR 0x01dc
519#define RADEON_AIC_HI_ADDR 0x01e0
520#define RADEON_AIC_TLB_ADDR 0x01e4
521#define RADEON_AIC_TLB_DATA 0x01e8
522
523/* CP command packets */
524#define RADEON_CP_PACKET0 0x00000000
525# define RADEON_ONE_REG_WR (1 << 15)
526#define RADEON_CP_PACKET1 0x40000000
527#define RADEON_CP_PACKET2 0x80000000
528#define RADEON_CP_PACKET3 0xC0000000
529# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
530# define RADEON_WAIT_FOR_IDLE 0x00002600
531# define RADEON_3D_DRAW_VBUF 0x00002800
532# define RADEON_3D_DRAW_IMMD 0x00002900
533# define RADEON_3D_DRAW_INDX 0x00002A00
534# define RADEON_3D_LOAD_VBPNTR 0x00002F00
535# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
536# define RADEON_CNTL_PAINT_MULTI 0x00009A00
537# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
538# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
539
540#define RADEON_CP_PACKET_MASK 0xC0000000
541#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
542#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
543#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
544#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
545
546#define RADEON_VTX_Z_PRESENT (1 << 31)
547#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
548
549#define RADEON_PRIM_TYPE_NONE (0 << 0)
550#define RADEON_PRIM_TYPE_POINT (1 << 0)
551#define RADEON_PRIM_TYPE_LINE (2 << 0)
552#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
553#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
554#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
555#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
556#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
557#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
558#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
559#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
560#define RADEON_PRIM_TYPE_MASK 0xf
561#define RADEON_PRIM_WALK_IND (1 << 4)
562#define RADEON_PRIM_WALK_LIST (2 << 4)
563#define RADEON_PRIM_WALK_RING (3 << 4)
564#define RADEON_COLOR_ORDER_BGRA (0 << 6)
565#define RADEON_COLOR_ORDER_RGBA (1 << 6)
566#define RADEON_MAOS_ENABLE (1 << 7)
567#define RADEON_VTX_FMT_R128_MODE (0 << 8)
568#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
569#define RADEON_NUM_VERTICES_SHIFT 16
570
571#define RADEON_COLOR_FORMAT_CI8 2
572#define RADEON_COLOR_FORMAT_ARGB1555 3
573#define RADEON_COLOR_FORMAT_RGB565 4
574#define RADEON_COLOR_FORMAT_ARGB8888 6
575#define RADEON_COLOR_FORMAT_RGB332 7
576#define RADEON_COLOR_FORMAT_RGB8 9
577#define RADEON_COLOR_FORMAT_ARGB4444 15
578
579#define RADEON_TXFORMAT_I8 0
580#define RADEON_TXFORMAT_AI88 1
581#define RADEON_TXFORMAT_RGB332 2
582#define RADEON_TXFORMAT_ARGB1555 3
583#define RADEON_TXFORMAT_RGB565 4
584#define RADEON_TXFORMAT_ARGB4444 5
585#define RADEON_TXFORMAT_ARGB8888 6
586#define RADEON_TXFORMAT_RGBA8888 7
587#define RADEON_TXFORMAT_Y8 8
588#define RADEON_TXFORMAT_VYUY422 10
589#define RADEON_TXFORMAT_YVYU422 11
590#define RADEON_TXFORMAT_DXT1 12
591#define RADEON_TXFORMAT_DXT23 14
592#define RADEON_TXFORMAT_DXT45 15
593
594#define R200_PP_TXCBLEND_0 0x2f00
595#define R200_PP_TXCBLEND_1 0x2f10
596#define R200_PP_TXCBLEND_2 0x2f20
597#define R200_PP_TXCBLEND_3 0x2f30
598#define R200_PP_TXCBLEND_4 0x2f40
599#define R200_PP_TXCBLEND_5 0x2f50
600#define R200_PP_TXCBLEND_6 0x2f60
601#define R200_PP_TXCBLEND_7 0x2f70
602#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
603#define R200_PP_TFACTOR_0 0x2ee0
604#define R200_SE_VTX_FMT_0 0x2088
605#define R200_SE_VAP_CNTL 0x2080
606#define R200_SE_TCL_MATRIX_SEL_0 0x2230
607#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
608#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
609#define R200_PP_TXFILTER_5 0x2ca0
610#define R200_PP_TXFILTER_4 0x2c80
611#define R200_PP_TXFILTER_3 0x2c60
612#define R200_PP_TXFILTER_2 0x2c40
613#define R200_PP_TXFILTER_1 0x2c20
614#define R200_PP_TXFILTER_0 0x2c00
615#define R200_PP_TXOFFSET_5 0x2d78
616#define R200_PP_TXOFFSET_4 0x2d60
617#define R200_PP_TXOFFSET_3 0x2d48
618#define R200_PP_TXOFFSET_2 0x2d30
619#define R200_PP_TXOFFSET_1 0x2d18
620#define R200_PP_TXOFFSET_0 0x2d00
621
622#define R200_PP_CUBIC_FACES_0 0x2c18
623#define R200_PP_CUBIC_FACES_1 0x2c38
624#define R200_PP_CUBIC_FACES_2 0x2c58
625#define R200_PP_CUBIC_FACES_3 0x2c78
626#define R200_PP_CUBIC_FACES_4 0x2c98
627#define R200_PP_CUBIC_FACES_5 0x2cb8
628#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
629#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
630#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
631#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
632#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
633#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
634#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
635#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
636#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
637#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
638#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
639#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
640#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
641#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
642#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
643#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
644#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
645#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
646#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
647#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
648#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
649#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
650#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
651#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
652#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
653#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
654#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
655#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
656#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
657#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
658
659#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
660#define R200_SE_VTE_CNTL 0x20b0
661#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
662#define R200_PP_TAM_DEBUG3 0x2d9c
663#define R200_PP_CNTL_X 0x2cc4
664#define R200_SE_VAP_CNTL_STATUS 0x2140
665#define R200_RE_SCISSOR_TL_0 0x1cd8
666#define R200_RE_SCISSOR_TL_1 0x1ce0
667#define R200_RE_SCISSOR_TL_2 0x1ce8
668#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
669#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
670#define R200_SE_VTX_STATE_CNTL 0x2180
671#define R200_RE_POINTSIZE 0x2648
672#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
673
674#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
675#define RADEON_PP_TEX_SIZE_1 0x1d0c
676#define RADEON_PP_TEX_SIZE_2 0x1d14
677
678
679#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
680#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
681#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
682#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
683#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
684#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
685#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
686#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
687#define R200_3D_DRAW_IMMD_2 0xC0003500
688#define R200_SE_VTX_FMT_1 0x208c
689#define R200_RE_CNTL 0x1c50
690
691
692/* Constants */
693#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
694
695#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
696#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
697#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
698#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
699#define RADEON_LAST_DISPATCH 1
700
701#define RADEON_MAX_VB_AGE 0x7fffffff
702#define RADEON_MAX_VB_VERTS (0xffff)
703
704#define RADEON_RING_HIGH_MARK 128
705
706#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
707#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
708#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
709#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
710
711#define RADEON_WRITE_PLL( addr, val ) \
712do { \
713 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
714 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
715 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
716} while (0)
717
718extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
719
720
721#define CP_PACKET0( reg, n ) \
722 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
723#define CP_PACKET0_TABLE( reg, n ) \
724 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
725#define CP_PACKET1( reg0, reg1 ) \
726 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
727#define CP_PACKET2() \
728 (RADEON_CP_PACKET2)
729#define CP_PACKET3( pkt, n ) \
730 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
731
732
733/* ================================================================
734 * Engine control helper macros
735 */
736
737#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
738 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
739 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
740 RADEON_WAIT_HOST_IDLECLEAN) ); \
741} while (0)
742
743#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
744 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
745 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
746 RADEON_WAIT_HOST_IDLECLEAN) ); \
747} while (0)
748
749#define RADEON_WAIT_UNTIL_IDLE() do { \
750 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
751 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
752 RADEON_WAIT_3D_IDLECLEAN | \
753 RADEON_WAIT_HOST_IDLECLEAN) ); \
754} while (0)
755
756#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
757 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
758 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
759} while (0)
760
761#define RADEON_FLUSH_CACHE() do { \
762 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
763 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
764} while (0)
765
766#define RADEON_PURGE_CACHE() do { \
767 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
768 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
769} while (0)
770
771#define RADEON_FLUSH_ZCACHE() do { \
772 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
773 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
774} while (0)
775
776#define RADEON_PURGE_ZCACHE() do { \
777 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
778 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
779} while (0)
780
781
782/* ================================================================
783 * Misc helper macros
784 */
785
786/* Perfbox functionality only.
787 */
788#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
789do { \
790 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
791 u32 head = GET_RING_HEAD( dev_priv ); \
792 if (head == dev_priv->ring.tail) \
793 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
794 } \
795} while (0)
796
797#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
798do { \
799 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
800 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
801 int __ret = radeon_do_cp_idle( dev_priv ); \
802 if ( __ret ) return __ret; \
803 sarea_priv->last_dispatch = 0; \
804 radeon_freelist_reset( dev ); \
805 } \
806} while (0)
807
808#define RADEON_DISPATCH_AGE( age ) do { \
809 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
810 OUT_RING( age ); \
811} while (0)
812
813#define RADEON_FRAME_AGE( age ) do { \
814 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
815 OUT_RING( age ); \
816} while (0)
817
818#define RADEON_CLEAR_AGE( age ) do { \
819 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
820 OUT_RING( age ); \
821} while (0)
822
823
824/* ================================================================
825 * Ring control
826 */
827
828#define RADEON_VERBOSE 0
829
830#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
831
832#define BEGIN_RING( n ) do { \
833 if ( RADEON_VERBOSE ) { \
834 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
835 n, __FUNCTION__ ); \
836 } \
837 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
838 COMMIT_RING(); \
839 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
840 } \
841 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
842 ring = dev_priv->ring.start; \
843 write = dev_priv->ring.tail; \
844 mask = dev_priv->ring.tail_mask; \
845} while (0)
846
847#define ADVANCE_RING() do { \
848 if ( RADEON_VERBOSE ) { \
849 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
850 write, dev_priv->ring.tail ); \
851 } \
852 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
853 DRM_ERROR( \
854 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
855 ((dev_priv->ring.tail + _nr) & mask), \
856 write, __LINE__); \
857 } else \
858 dev_priv->ring.tail = write; \
859} while (0)
860
861#define COMMIT_RING() do { \
862 /* Flush writes to ring */ \
863 DRM_MEMORYBARRIER(); \
864 GET_RING_HEAD( dev_priv ); \
865 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
866 /* read from PCI bus to ensure correct posting */ \
867 RADEON_READ( RADEON_CP_RB_RPTR ); \
868} while (0)
869
870#define OUT_RING( x ) do { \
871 if ( RADEON_VERBOSE ) { \
872 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
873 (unsigned int)(x), write ); \
874 } \
875 ring[write++] = (x); \
876 write &= mask; \
877} while (0)
878
879#define OUT_RING_REG( reg, val ) do { \
880 OUT_RING( CP_PACKET0( reg, 0 ) ); \
881 OUT_RING( val ); \
882} while (0)
883
884
885#define OUT_RING_USER_TABLE( tab, sz ) do { \
886 int _size = (sz); \
887 int *_tab = (tab); \
888 \
889 if (write + _size > mask) { \
890 int i = (mask+1) - write; \
891 if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
892 _tab, i*4 )) \
893 return DRM_ERR(EFAULT); \
894 write = 0; \
895 _size -= i; \
896 _tab += i; \
897 } \
898 \
899 if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
900 _tab, _size*4 )) \
901 return DRM_ERR(EFAULT); \
902 \
903 write += _size; \
904 write &= mask; \
905} while (0)
906
907
908#endif /* __RADEON_DRV_H__ */
| 146 struct mem_block *fb_heap;
147
148 /* SW interrupt */
149 wait_queue_head_t swi_queue;
150 atomic_t swi_emitted;
151
152} drm_radeon_private_t;
153
154typedef struct drm_radeon_buf_priv {
155 u32 age;
156} drm_radeon_buf_priv_t;
157
158 /* radeon_cp.c */
159extern int radeon_cp_init( DRM_IOCTL_ARGS );
160extern int radeon_cp_start( DRM_IOCTL_ARGS );
161extern int radeon_cp_stop( DRM_IOCTL_ARGS );
162extern int radeon_cp_reset( DRM_IOCTL_ARGS );
163extern int radeon_cp_idle( DRM_IOCTL_ARGS );
164extern int radeon_cp_resume( DRM_IOCTL_ARGS );
165extern int radeon_engine_reset( DRM_IOCTL_ARGS );
166extern int radeon_fullscreen( DRM_IOCTL_ARGS );
167extern int radeon_cp_buffers( DRM_IOCTL_ARGS );
168
169extern void radeon_freelist_reset( drm_device_t *dev );
170extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
171
172extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
173
174extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
175extern int radeon_do_cleanup_cp( drm_device_t *dev );
176extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
177
178 /* radeon_state.c */
179extern int radeon_cp_clear( DRM_IOCTL_ARGS );
180extern int radeon_cp_swap( DRM_IOCTL_ARGS );
181extern int radeon_cp_vertex( DRM_IOCTL_ARGS );
182extern int radeon_cp_indices( DRM_IOCTL_ARGS );
183extern int radeon_cp_texture( DRM_IOCTL_ARGS );
184extern int radeon_cp_stipple( DRM_IOCTL_ARGS );
185extern int radeon_cp_indirect( DRM_IOCTL_ARGS );
186extern int radeon_cp_vertex2( DRM_IOCTL_ARGS );
187extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS );
188extern int radeon_cp_getparam( DRM_IOCTL_ARGS );
189extern int radeon_cp_flip( DRM_IOCTL_ARGS );
190
191extern int radeon_mem_alloc( DRM_IOCTL_ARGS );
192extern int radeon_mem_free( DRM_IOCTL_ARGS );
193extern int radeon_mem_init_heap( DRM_IOCTL_ARGS );
194extern void radeon_mem_takedown( struct mem_block **heap );
195extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap );
196
197 /* radeon_irq.c */
198extern int radeon_irq_emit( DRM_IOCTL_ARGS );
199extern int radeon_irq_wait( DRM_IOCTL_ARGS );
200
201extern int radeon_emit_and_wait_irq(drm_device_t *dev);
202extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
203extern int radeon_emit_irq(drm_device_t *dev);
204
205extern void radeon_do_release(drm_device_t *dev);
206
207/* Flags for stats.boxes
208 */
209#define RADEON_BOX_DMA_IDLE 0x1
210#define RADEON_BOX_RING_FULL 0x2
211#define RADEON_BOX_FLIP 0x4
212#define RADEON_BOX_WAIT_IDLE 0x8
213#define RADEON_BOX_TEXTURE_LOAD 0x10
214
215
216
217/* Register definitions, register access macros and drmAddMap constants
218 * for Radeon kernel driver.
219 */
220
221#define RADEON_AGP_COMMAND 0x0f60
222#define RADEON_AUX_SCISSOR_CNTL 0x26f0
223# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
224# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
225# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
226# define RADEON_SCISSOR_0_ENABLE (1 << 28)
227# define RADEON_SCISSOR_1_ENABLE (1 << 29)
228# define RADEON_SCISSOR_2_ENABLE (1 << 30)
229
230#define RADEON_BUS_CNTL 0x0030
231# define RADEON_BUS_MASTER_DIS (1 << 6)
232
233#define RADEON_CLOCK_CNTL_DATA 0x000c
234# define RADEON_PLL_WR_EN (1 << 7)
235#define RADEON_CLOCK_CNTL_INDEX 0x0008
236#define RADEON_CONFIG_APER_SIZE 0x0108
237#define RADEON_CRTC_OFFSET 0x0224
238#define RADEON_CRTC_OFFSET_CNTL 0x0228
239# define RADEON_CRTC_TILE_EN (1 << 15)
240# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
241#define RADEON_CRTC2_OFFSET 0x0324
242#define RADEON_CRTC2_OFFSET_CNTL 0x0328
243
244#define RADEON_RB3D_COLORPITCH 0x1c48
245
246#define RADEON_DP_GUI_MASTER_CNTL 0x146c
247# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
248# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
249# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
250# define RADEON_GMC_BRUSH_NONE (15 << 4)
251# define RADEON_GMC_DST_16BPP (4 << 8)
252# define RADEON_GMC_DST_24BPP (5 << 8)
253# define RADEON_GMC_DST_32BPP (6 << 8)
254# define RADEON_GMC_DST_DATATYPE_SHIFT 8
255# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
256# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
257# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
258# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
259# define RADEON_GMC_WR_MSK_DIS (1 << 30)
260# define RADEON_ROP3_S 0x00cc0000
261# define RADEON_ROP3_P 0x00f00000
262#define RADEON_DP_WRITE_MASK 0x16cc
263#define RADEON_DST_PITCH_OFFSET 0x142c
264#define RADEON_DST_PITCH_OFFSET_C 0x1c80
265# define RADEON_DST_TILE_LINEAR (0 << 30)
266# define RADEON_DST_TILE_MACRO (1 << 30)
267# define RADEON_DST_TILE_MICRO (2 << 30)
268# define RADEON_DST_TILE_BOTH (3 << 30)
269
270#define RADEON_SCRATCH_REG0 0x15e0
271#define RADEON_SCRATCH_REG1 0x15e4
272#define RADEON_SCRATCH_REG2 0x15e8
273#define RADEON_SCRATCH_REG3 0x15ec
274#define RADEON_SCRATCH_REG4 0x15f0
275#define RADEON_SCRATCH_REG5 0x15f4
276#define RADEON_SCRATCH_UMSK 0x0770
277#define RADEON_SCRATCH_ADDR 0x0774
278
279#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
280
281#define GET_SCRATCH( x ) (dev_priv->writeback_works \
282 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
283 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
284
285
286#define RADEON_GEN_INT_CNTL 0x0040
287# define RADEON_CRTC_VBLANK_MASK (1 << 0)
288# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
289# define RADEON_SW_INT_ENABLE (1 << 25)
290
291#define RADEON_GEN_INT_STATUS 0x0044
292# define RADEON_CRTC_VBLANK_STAT (1 << 0)
293# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
294# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
295# define RADEON_SW_INT_TEST (1 << 25)
296# define RADEON_SW_INT_TEST_ACK (1 << 25)
297# define RADEON_SW_INT_FIRE (1 << 26)
298
299#define RADEON_HOST_PATH_CNTL 0x0130
300# define RADEON_HDP_SOFT_RESET (1 << 26)
301# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
302# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
303
304#define RADEON_ISYNC_CNTL 0x1724
305# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
306# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
307# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
308# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
309# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
310# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
311
312#define RADEON_RBBM_GUICNTL 0x172c
313# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
314# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
315# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
316# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
317
318#define RADEON_MC_AGP_LOCATION 0x014c
319#define RADEON_MC_FB_LOCATION 0x0148
320#define RADEON_MCLK_CNTL 0x0012
321# define RADEON_FORCEON_MCLKA (1 << 16)
322# define RADEON_FORCEON_MCLKB (1 << 17)
323# define RADEON_FORCEON_YCLKA (1 << 18)
324# define RADEON_FORCEON_YCLKB (1 << 19)
325# define RADEON_FORCEON_MC (1 << 20)
326# define RADEON_FORCEON_AIC (1 << 21)
327
328#define RADEON_PP_BORDER_COLOR_0 0x1d40
329#define RADEON_PP_BORDER_COLOR_1 0x1d44
330#define RADEON_PP_BORDER_COLOR_2 0x1d48
331#define RADEON_PP_CNTL 0x1c38
332# define RADEON_SCISSOR_ENABLE (1 << 1)
333#define RADEON_PP_LUM_MATRIX 0x1d00
334#define RADEON_PP_MISC 0x1c14
335#define RADEON_PP_ROT_MATRIX_0 0x1d58
336#define RADEON_PP_TXFILTER_0 0x1c54
337#define RADEON_PP_TXFILTER_1 0x1c6c
338#define RADEON_PP_TXFILTER_2 0x1c84
339
340#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
341# define RADEON_RB2D_DC_FLUSH (3 << 0)
342# define RADEON_RB2D_DC_FREE (3 << 2)
343# define RADEON_RB2D_DC_FLUSH_ALL 0xf
344# define RADEON_RB2D_DC_BUSY (1 << 31)
345#define RADEON_RB3D_CNTL 0x1c3c
346# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
347# define RADEON_PLANE_MASK_ENABLE (1 << 1)
348# define RADEON_DITHER_ENABLE (1 << 2)
349# define RADEON_ROUND_ENABLE (1 << 3)
350# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
351# define RADEON_DITHER_INIT (1 << 5)
352# define RADEON_ROP_ENABLE (1 << 6)
353# define RADEON_STENCIL_ENABLE (1 << 7)
354# define RADEON_Z_ENABLE (1 << 8)
355#define RADEON_RB3D_DEPTHOFFSET 0x1c24
356#define RADEON_RB3D_DEPTHPITCH 0x1c28
357#define RADEON_RB3D_PLANEMASK 0x1d84
358#define RADEON_RB3D_STENCILREFMASK 0x1d7c
359#define RADEON_RB3D_ZCACHE_MODE 0x3250
360#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
361# define RADEON_RB3D_ZC_FLUSH (1 << 0)
362# define RADEON_RB3D_ZC_FREE (1 << 2)
363# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
364# define RADEON_RB3D_ZC_BUSY (1 << 31)
365#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
366# define RADEON_Z_TEST_MASK (7 << 4)
367# define RADEON_Z_TEST_ALWAYS (7 << 4)
368# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
369# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
370# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
371# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
372# define RADEON_Z_WRITE_ENABLE (1 << 30)
373#define RADEON_RBBM_SOFT_RESET 0x00f0
374# define RADEON_SOFT_RESET_CP (1 << 0)
375# define RADEON_SOFT_RESET_HI (1 << 1)
376# define RADEON_SOFT_RESET_SE (1 << 2)
377# define RADEON_SOFT_RESET_RE (1 << 3)
378# define RADEON_SOFT_RESET_PP (1 << 4)
379# define RADEON_SOFT_RESET_E2 (1 << 5)
380# define RADEON_SOFT_RESET_RB (1 << 6)
381# define RADEON_SOFT_RESET_HDP (1 << 7)
382#define RADEON_RBBM_STATUS 0x0e40
383# define RADEON_RBBM_FIFOCNT_MASK 0x007f
384# define RADEON_RBBM_ACTIVE (1 << 31)
385#define RADEON_RE_LINE_PATTERN 0x1cd0
386#define RADEON_RE_MISC 0x26c4
387#define RADEON_RE_TOP_LEFT 0x26c0
388#define RADEON_RE_WIDTH_HEIGHT 0x1c44
389#define RADEON_RE_STIPPLE_ADDR 0x1cc8
390#define RADEON_RE_STIPPLE_DATA 0x1ccc
391
392#define RADEON_SCISSOR_TL_0 0x1cd8
393#define RADEON_SCISSOR_BR_0 0x1cdc
394#define RADEON_SCISSOR_TL_1 0x1ce0
395#define RADEON_SCISSOR_BR_1 0x1ce4
396#define RADEON_SCISSOR_TL_2 0x1ce8
397#define RADEON_SCISSOR_BR_2 0x1cec
398#define RADEON_SE_COORD_FMT 0x1c50
399#define RADEON_SE_CNTL 0x1c4c
400# define RADEON_FFACE_CULL_CW (0 << 0)
401# define RADEON_BFACE_SOLID (3 << 1)
402# define RADEON_FFACE_SOLID (3 << 3)
403# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
404# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
405# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
406# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
407# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
408# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
409# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
410# define RADEON_FOG_SHADE_FLAT (1 << 14)
411# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
412# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
413# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
414# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
415# define RADEON_ROUND_MODE_TRUNC (0 << 28)
416# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
417#define RADEON_SE_CNTL_STATUS 0x2140
418#define RADEON_SE_LINE_WIDTH 0x1db8
419#define RADEON_SE_VPORT_XSCALE 0x1d98
420#define RADEON_SE_ZBIAS_FACTOR 0x1db0
421#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
422#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
423#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
424# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
425# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
426#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
427#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
428# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
429#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
430#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
431#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
432#define RADEON_SURFACE_CNTL 0x0b00
433# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
434# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
435# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
436# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
437# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
438# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
439# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
440# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
441# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
442#define RADEON_SURFACE0_INFO 0x0b0c
443# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
444# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
445# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
446# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
447# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
448# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
449#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
450#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
451#define RADEON_SURFACE1_INFO 0x0b1c
452#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
453#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
454#define RADEON_SURFACE2_INFO 0x0b2c
455#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
456#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
457#define RADEON_SURFACE3_INFO 0x0b3c
458#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
459#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
460#define RADEON_SURFACE4_INFO 0x0b4c
461#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
462#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
463#define RADEON_SURFACE5_INFO 0x0b5c
464#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
465#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
466#define RADEON_SURFACE6_INFO 0x0b6c
467#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
468#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
469#define RADEON_SURFACE7_INFO 0x0b7c
470#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
471#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
472#define RADEON_SW_SEMAPHORE 0x013c
473
474#define RADEON_WAIT_UNTIL 0x1720
475# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
476# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
477# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
478# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
479
480#define RADEON_RB3D_ZMASKOFFSET 0x1c34
481#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
482# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
483# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
484
485
486/* CP registers */
487#define RADEON_CP_ME_RAM_ADDR 0x07d4
488#define RADEON_CP_ME_RAM_RADDR 0x07d8
489#define RADEON_CP_ME_RAM_DATAH 0x07dc
490#define RADEON_CP_ME_RAM_DATAL 0x07e0
491
492#define RADEON_CP_RB_BASE 0x0700
493#define RADEON_CP_RB_CNTL 0x0704
494# define RADEON_BUF_SWAP_32BIT (2 << 16)
495#define RADEON_CP_RB_RPTR_ADDR 0x070c
496#define RADEON_CP_RB_RPTR 0x0710
497#define RADEON_CP_RB_WPTR 0x0714
498
499#define RADEON_CP_RB_WPTR_DELAY 0x0718
500# define RADEON_PRE_WRITE_TIMER_SHIFT 0
501# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
502
503#define RADEON_CP_IB_BASE 0x0738
504
505#define RADEON_CP_CSQ_CNTL 0x0740
506# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
507# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
508# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
509# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
510# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
511# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
512# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
513
514#define RADEON_AIC_CNTL 0x01d0
515# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
516#define RADEON_AIC_STAT 0x01d4
517#define RADEON_AIC_PT_BASE 0x01d8
518#define RADEON_AIC_LO_ADDR 0x01dc
519#define RADEON_AIC_HI_ADDR 0x01e0
520#define RADEON_AIC_TLB_ADDR 0x01e4
521#define RADEON_AIC_TLB_DATA 0x01e8
522
523/* CP command packets */
524#define RADEON_CP_PACKET0 0x00000000
525# define RADEON_ONE_REG_WR (1 << 15)
526#define RADEON_CP_PACKET1 0x40000000
527#define RADEON_CP_PACKET2 0x80000000
528#define RADEON_CP_PACKET3 0xC0000000
529# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
530# define RADEON_WAIT_FOR_IDLE 0x00002600
531# define RADEON_3D_DRAW_VBUF 0x00002800
532# define RADEON_3D_DRAW_IMMD 0x00002900
533# define RADEON_3D_DRAW_INDX 0x00002A00
534# define RADEON_3D_LOAD_VBPNTR 0x00002F00
535# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
536# define RADEON_CNTL_PAINT_MULTI 0x00009A00
537# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
538# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
539
540#define RADEON_CP_PACKET_MASK 0xC0000000
541#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
542#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
543#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
544#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
545
546#define RADEON_VTX_Z_PRESENT (1 << 31)
547#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
548
549#define RADEON_PRIM_TYPE_NONE (0 << 0)
550#define RADEON_PRIM_TYPE_POINT (1 << 0)
551#define RADEON_PRIM_TYPE_LINE (2 << 0)
552#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
553#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
554#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
555#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
556#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
557#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
558#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
559#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
560#define RADEON_PRIM_TYPE_MASK 0xf
561#define RADEON_PRIM_WALK_IND (1 << 4)
562#define RADEON_PRIM_WALK_LIST (2 << 4)
563#define RADEON_PRIM_WALK_RING (3 << 4)
564#define RADEON_COLOR_ORDER_BGRA (0 << 6)
565#define RADEON_COLOR_ORDER_RGBA (1 << 6)
566#define RADEON_MAOS_ENABLE (1 << 7)
567#define RADEON_VTX_FMT_R128_MODE (0 << 8)
568#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
569#define RADEON_NUM_VERTICES_SHIFT 16
570
571#define RADEON_COLOR_FORMAT_CI8 2
572#define RADEON_COLOR_FORMAT_ARGB1555 3
573#define RADEON_COLOR_FORMAT_RGB565 4
574#define RADEON_COLOR_FORMAT_ARGB8888 6
575#define RADEON_COLOR_FORMAT_RGB332 7
576#define RADEON_COLOR_FORMAT_RGB8 9
577#define RADEON_COLOR_FORMAT_ARGB4444 15
578
579#define RADEON_TXFORMAT_I8 0
580#define RADEON_TXFORMAT_AI88 1
581#define RADEON_TXFORMAT_RGB332 2
582#define RADEON_TXFORMAT_ARGB1555 3
583#define RADEON_TXFORMAT_RGB565 4
584#define RADEON_TXFORMAT_ARGB4444 5
585#define RADEON_TXFORMAT_ARGB8888 6
586#define RADEON_TXFORMAT_RGBA8888 7
587#define RADEON_TXFORMAT_Y8 8
588#define RADEON_TXFORMAT_VYUY422 10
589#define RADEON_TXFORMAT_YVYU422 11
590#define RADEON_TXFORMAT_DXT1 12
591#define RADEON_TXFORMAT_DXT23 14
592#define RADEON_TXFORMAT_DXT45 15
593
594#define R200_PP_TXCBLEND_0 0x2f00
595#define R200_PP_TXCBLEND_1 0x2f10
596#define R200_PP_TXCBLEND_2 0x2f20
597#define R200_PP_TXCBLEND_3 0x2f30
598#define R200_PP_TXCBLEND_4 0x2f40
599#define R200_PP_TXCBLEND_5 0x2f50
600#define R200_PP_TXCBLEND_6 0x2f60
601#define R200_PP_TXCBLEND_7 0x2f70
602#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
603#define R200_PP_TFACTOR_0 0x2ee0
604#define R200_SE_VTX_FMT_0 0x2088
605#define R200_SE_VAP_CNTL 0x2080
606#define R200_SE_TCL_MATRIX_SEL_0 0x2230
607#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
608#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
609#define R200_PP_TXFILTER_5 0x2ca0
610#define R200_PP_TXFILTER_4 0x2c80
611#define R200_PP_TXFILTER_3 0x2c60
612#define R200_PP_TXFILTER_2 0x2c40
613#define R200_PP_TXFILTER_1 0x2c20
614#define R200_PP_TXFILTER_0 0x2c00
615#define R200_PP_TXOFFSET_5 0x2d78
616#define R200_PP_TXOFFSET_4 0x2d60
617#define R200_PP_TXOFFSET_3 0x2d48
618#define R200_PP_TXOFFSET_2 0x2d30
619#define R200_PP_TXOFFSET_1 0x2d18
620#define R200_PP_TXOFFSET_0 0x2d00
621
622#define R200_PP_CUBIC_FACES_0 0x2c18
623#define R200_PP_CUBIC_FACES_1 0x2c38
624#define R200_PP_CUBIC_FACES_2 0x2c58
625#define R200_PP_CUBIC_FACES_3 0x2c78
626#define R200_PP_CUBIC_FACES_4 0x2c98
627#define R200_PP_CUBIC_FACES_5 0x2cb8
628#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
629#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
630#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
631#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
632#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
633#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
634#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
635#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
636#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
637#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
638#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
639#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
640#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
641#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
642#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
643#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
644#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
645#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
646#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
647#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
648#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
649#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
650#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
651#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
652#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
653#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
654#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
655#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
656#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
657#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
658
659#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
660#define R200_SE_VTE_CNTL 0x20b0
661#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
662#define R200_PP_TAM_DEBUG3 0x2d9c
663#define R200_PP_CNTL_X 0x2cc4
664#define R200_SE_VAP_CNTL_STATUS 0x2140
665#define R200_RE_SCISSOR_TL_0 0x1cd8
666#define R200_RE_SCISSOR_TL_1 0x1ce0
667#define R200_RE_SCISSOR_TL_2 0x1ce8
668#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
669#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
670#define R200_SE_VTX_STATE_CNTL 0x2180
671#define R200_RE_POINTSIZE 0x2648
672#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
673
674#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
675#define RADEON_PP_TEX_SIZE_1 0x1d0c
676#define RADEON_PP_TEX_SIZE_2 0x1d14
677
678
679#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
680#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
681#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
682#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
683#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
684#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
685#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
686#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
687#define R200_3D_DRAW_IMMD_2 0xC0003500
688#define R200_SE_VTX_FMT_1 0x208c
689#define R200_RE_CNTL 0x1c50
690
691
692/* Constants */
693#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
694
695#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
696#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
697#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
698#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
699#define RADEON_LAST_DISPATCH 1
700
701#define RADEON_MAX_VB_AGE 0x7fffffff
702#define RADEON_MAX_VB_VERTS (0xffff)
703
704#define RADEON_RING_HIGH_MARK 128
705
706#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
707#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
708#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
709#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
710
711#define RADEON_WRITE_PLL( addr, val ) \
712do { \
713 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
714 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
715 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
716} while (0)
717
718extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
719
720
721#define CP_PACKET0( reg, n ) \
722 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
723#define CP_PACKET0_TABLE( reg, n ) \
724 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
725#define CP_PACKET1( reg0, reg1 ) \
726 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
727#define CP_PACKET2() \
728 (RADEON_CP_PACKET2)
729#define CP_PACKET3( pkt, n ) \
730 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
731
732
733/* ================================================================
734 * Engine control helper macros
735 */
736
737#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
738 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
739 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
740 RADEON_WAIT_HOST_IDLECLEAN) ); \
741} while (0)
742
743#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
744 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
745 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
746 RADEON_WAIT_HOST_IDLECLEAN) ); \
747} while (0)
748
749#define RADEON_WAIT_UNTIL_IDLE() do { \
750 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
751 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
752 RADEON_WAIT_3D_IDLECLEAN | \
753 RADEON_WAIT_HOST_IDLECLEAN) ); \
754} while (0)
755
756#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
757 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
758 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
759} while (0)
760
761#define RADEON_FLUSH_CACHE() do { \
762 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
763 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
764} while (0)
765
766#define RADEON_PURGE_CACHE() do { \
767 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
768 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
769} while (0)
770
771#define RADEON_FLUSH_ZCACHE() do { \
772 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
773 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
774} while (0)
775
776#define RADEON_PURGE_ZCACHE() do { \
777 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
778 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
779} while (0)
780
781
782/* ================================================================
783 * Misc helper macros
784 */
785
786/* Perfbox functionality only.
787 */
788#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
789do { \
790 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
791 u32 head = GET_RING_HEAD( dev_priv ); \
792 if (head == dev_priv->ring.tail) \
793 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
794 } \
795} while (0)
796
797#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
798do { \
799 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
800 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
801 int __ret = radeon_do_cp_idle( dev_priv ); \
802 if ( __ret ) return __ret; \
803 sarea_priv->last_dispatch = 0; \
804 radeon_freelist_reset( dev ); \
805 } \
806} while (0)
807
808#define RADEON_DISPATCH_AGE( age ) do { \
809 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
810 OUT_RING( age ); \
811} while (0)
812
813#define RADEON_FRAME_AGE( age ) do { \
814 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
815 OUT_RING( age ); \
816} while (0)
817
818#define RADEON_CLEAR_AGE( age ) do { \
819 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
820 OUT_RING( age ); \
821} while (0)
822
823
824/* ================================================================
825 * Ring control
826 */
827
828#define RADEON_VERBOSE 0
829
830#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
831
832#define BEGIN_RING( n ) do { \
833 if ( RADEON_VERBOSE ) { \
834 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
835 n, __FUNCTION__ ); \
836 } \
837 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
838 COMMIT_RING(); \
839 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
840 } \
841 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
842 ring = dev_priv->ring.start; \
843 write = dev_priv->ring.tail; \
844 mask = dev_priv->ring.tail_mask; \
845} while (0)
846
847#define ADVANCE_RING() do { \
848 if ( RADEON_VERBOSE ) { \
849 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
850 write, dev_priv->ring.tail ); \
851 } \
852 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
853 DRM_ERROR( \
854 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
855 ((dev_priv->ring.tail + _nr) & mask), \
856 write, __LINE__); \
857 } else \
858 dev_priv->ring.tail = write; \
859} while (0)
860
861#define COMMIT_RING() do { \
862 /* Flush writes to ring */ \
863 DRM_MEMORYBARRIER(); \
864 GET_RING_HEAD( dev_priv ); \
865 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
866 /* read from PCI bus to ensure correct posting */ \
867 RADEON_READ( RADEON_CP_RB_RPTR ); \
868} while (0)
869
870#define OUT_RING( x ) do { \
871 if ( RADEON_VERBOSE ) { \
872 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
873 (unsigned int)(x), write ); \
874 } \
875 ring[write++] = (x); \
876 write &= mask; \
877} while (0)
878
879#define OUT_RING_REG( reg, val ) do { \
880 OUT_RING( CP_PACKET0( reg, 0 ) ); \
881 OUT_RING( val ); \
882} while (0)
883
884
885#define OUT_RING_USER_TABLE( tab, sz ) do { \
886 int _size = (sz); \
887 int *_tab = (tab); \
888 \
889 if (write + _size > mask) { \
890 int i = (mask+1) - write; \
891 if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
892 _tab, i*4 )) \
893 return DRM_ERR(EFAULT); \
894 write = 0; \
895 _size -= i; \
896 _tab += i; \
897 } \
898 \
899 if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \
900 _tab, _size*4 )) \
901 return DRM_ERR(EFAULT); \
902 \
903 write += _size; \
904 write &= mask; \
905} while (0)
906
907
908#endif /* __RADEON_DRV_H__ */
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