radeon_drv.h (196142) | radeon_drv.h (196470) |
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1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 15 unchanged lines hidden (view full) --- 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> | 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 15 unchanged lines hidden (view full) --- 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> |
32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 196142 2009-08-12 12:57:02Z rnoland $"); | 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 196470 2009-08-23 14:55:57Z rnoland $"); |
33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" | 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" |
44#define DRIVER_DATE "20080528" | 44#define DRIVER_DATE "20080613" |
45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) --- 178 unchanged lines hidden (view full) --- 231 int surface_index; 232 u32 lower; 233 u32 upper; 234 u32 flags; 235 struct drm_file *file_priv; 236#define PCIGART_FILE_PRIV ((void *) -1L) 237}; 238 | 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) --- 178 unchanged lines hidden (view full) --- 231 int surface_index; 232 u32 lower; 233 u32 upper; 234 u32 flags; 235 struct drm_file *file_priv; 236#define PCIGART_FILE_PRIV ((void *) -1L) 237}; 238 |
239struct drm_radeon_kernel_chunk { 240 uint32_t chunk_id; 241 uint32_t length_dw; 242 uint32_t __user *chunk_data; 243 uint32_t *kdata; 244}; 245 246struct drm_radeon_cs_parser { 247 struct drm_device *dev; 248 struct drm_file *file_priv; 249 uint32_t num_chunks; 250 struct drm_radeon_kernel_chunk *chunks; 251 int ib_index; 252 int reloc_index; 253 uint32_t card_offset; 254 void *ib; 255}; 256 257/* command submission struct */ 258struct drm_radeon_cs_priv { 259 struct mtx cs_mutex; 260 uint32_t id_wcnt; 261 uint32_t id_scnt; 262 uint32_t id_last_wcnt; 263 uint32_t id_last_scnt; 264 265 int (*parse)(struct drm_radeon_cs_parser *parser); 266 void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id); 267 uint32_t (*id_last_get)(struct drm_device *dev); 268 /* this ib handling callback are for hidding memory manager drm 269 * from memory manager less drm, free have to emit ib discard 270 * sequence into the ring */ 271 int (*ib_get)(struct drm_radeon_cs_parser *parser); 272 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib); 273 void (*ib_free)(struct drm_radeon_cs_parser *parser, int error); 274 /* do a relocation either MM or non-MM */ 275 int (*relocate)(struct drm_radeon_cs_parser *parser, 276 uint32_t *reloc, uint64_t *offset); 277}; 278 |
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239#define RADEON_FLUSH_EMITED (1 << 0) 240#define RADEON_PURGE_EMITED (1 << 1) 241 242typedef struct drm_radeon_private { 243 drm_radeon_ring_buffer_t ring; 244 drm_radeon_sarea_t *sarea_priv; 245 246 u32 fb_location; --- 97 unchanged lines hidden (view full) --- 344 int r600_sx_max_export_size; 345 int r600_sx_max_export_pos_size; 346 int r600_sx_max_export_smx_size; 347 int r600_sq_num_cf_insts; 348 int r700_sx_num_of_sets; 349 int r700_sc_prim_fifo_size; 350 int r700_sc_hiz_tile_fifo_size; 351 int r700_sc_earlyz_tile_fifo_fize; | 279#define RADEON_FLUSH_EMITED (1 << 0) 280#define RADEON_PURGE_EMITED (1 << 1) 281 282typedef struct drm_radeon_private { 283 drm_radeon_ring_buffer_t ring; 284 drm_radeon_sarea_t *sarea_priv; 285 286 u32 fb_location; --- 97 unchanged lines hidden (view full) --- 384 int r600_sx_max_export_size; 385 int r600_sx_max_export_pos_size; 386 int r600_sx_max_export_smx_size; 387 int r600_sq_num_cf_insts; 388 int r700_sx_num_of_sets; 389 int r700_sc_prim_fifo_size; 390 int r700_sc_hiz_tile_fifo_size; 391 int r700_sc_earlyz_tile_fifo_fize; |
392 /* r6xx/r7xx drm blit vertex buffer */ 393 struct drm_buf *blit_vb; |
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352 | 394 |
395 /* CS */ 396 struct drm_radeon_cs_priv cs; 397 struct drm_buf *cs_buf; 398 |
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353} drm_radeon_private_t; 354 355typedef struct drm_radeon_buf_priv { 356 u32 age; 357} drm_radeon_buf_priv_t; 358 359typedef struct drm_radeon_kcmd_buffer { 360 int bufsz; --- 13 unchanged lines hidden (view full) --- 374#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 375 376/* Check whether the given hardware address is inside the framebuffer or the 377 * GART area. 378 */ 379static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 380 u64 off) 381{ | 399} drm_radeon_private_t; 400 401typedef struct drm_radeon_buf_priv { 402 u32 age; 403} drm_radeon_buf_priv_t; 404 405typedef struct drm_radeon_kcmd_buffer { 406 int bufsz; --- 13 unchanged lines hidden (view full) --- 420#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 421 422/* Check whether the given hardware address is inside the framebuffer or the 423 * GART area. 424 */ 425static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 426 u64 off) 427{ |
382 u32 fb_start = dev_priv->fb_location; 383 u32 fb_end = fb_start + dev_priv->fb_size - 1; 384 u32 gart_start = dev_priv->gart_vm_start; 385 u32 gart_end = gart_start + dev_priv->gart_size - 1; | 428 u64 fb_start = dev_priv->fb_location; 429 u64 fb_end = fb_start + dev_priv->fb_size - 1; 430 u64 gart_start = dev_priv->gart_vm_start; 431 u64 gart_end = gart_start + dev_priv->gart_size - 1; |
386 387 return ((off >= fb_start && off <= fb_end) || 388 (off >= gart_start && off <= gart_end)); 389} 390 391 /* radeon_cp.c */ 392extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 393extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); --- 77 unchanged lines hidden (view full) --- 471extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 472extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 473extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 474extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 475extern int r600_cp_dispatch_indirect(struct drm_device *dev, 476 struct drm_buf *buf, int start, int end); 477extern int r600_page_table_init(struct drm_device *dev); 478extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); | 432 433 return ((off >= fb_start && off <= fb_end) || 434 (off >= gart_start && off <= gart_end)); 435} 436 437 /* radeon_cp.c */ 438extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 439extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); --- 77 unchanged lines hidden (view full) --- 517extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 518extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 519extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 520extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 521extern int r600_cp_dispatch_indirect(struct drm_device *dev, 522 struct drm_buf *buf, int start, int end); 523extern int r600_page_table_init(struct drm_device *dev); 524extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); |
525extern void r600_cp_dispatch_swap(struct drm_device * dev); 526extern int r600_cp_dispatch_texture(struct drm_device * dev, 527 struct drm_file *file_priv, 528 drm_radeon_texture_t * tex, 529 drm_radeon_tex_image_t * image); |
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479 | 530 |
531/* r600_blit.c */ 532extern int 533r600_prepare_blit_copy(struct drm_device *dev); 534extern void 535r600_done_blit_copy(struct drm_device *dev); 536extern void 537r600_blit_copy(struct drm_device *dev, 538 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 539 int size_bytes); 540extern void 541r600_blit_swap(struct drm_device *dev, 542 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 543 int sx, int sy, int dx, int dy, 544 int w, int h, int src_pitch, int dst_pitch, int cpp); 545 546/* radeon_state.c */ 547extern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf); 548 549/* radeon_cs.c */ 550extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 551extern int r600_cs_init(struct drm_device *dev); 552 |
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480/* Flags for stats.boxes 481 */ 482#define RADEON_BOX_DMA_IDLE 0x1 483#define RADEON_BOX_RING_FULL 0x2 484#define RADEON_BOX_FLIP 0x4 485#define RADEON_BOX_WAIT_IDLE 0x8 486#define RADEON_BOX_TEXTURE_LOAD 0x10 487 --- 1334 unchanged lines hidden (view full) --- 1822#define CP_PACKET3( pkt, n ) \ 1823 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1824 1825/* ================================================================ 1826 * Engine control helper macros 1827 */ 1828 1829#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ | 553/* Flags for stats.boxes 554 */ 555#define RADEON_BOX_DMA_IDLE 0x1 556#define RADEON_BOX_RING_FULL 0x2 557#define RADEON_BOX_FLIP 0x4 558#define RADEON_BOX_WAIT_IDLE 0x8 559#define RADEON_BOX_TEXTURE_LOAD 0x10 560 --- 1334 unchanged lines hidden (view full) --- 1895#define CP_PACKET3( pkt, n ) \ 1896 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1897 1898/* ================================================================ 1899 * Engine control helper macros 1900 */ 1901 1902#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ |
1830 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | 1903 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1904 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1905 else \ 1906 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1831 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1832 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1833} while (0) 1834 1835#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ | 1907 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1908 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1909} while (0) 1910 1911#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ |
1836 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | 1912 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1913 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1914 else \ 1915 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1837 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1838 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1839} while (0) 1840 1841#define RADEON_WAIT_UNTIL_IDLE() do { \ | 1916 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1917 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1918} while (0) 1919 1920#define RADEON_WAIT_UNTIL_IDLE() do { \ |
1842 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | 1921 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1922 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1923 else \ 1924 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1843 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1844 RADEON_WAIT_3D_IDLECLEAN | \ 1845 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1846} while (0) 1847 1848#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ | 1925 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1926 RADEON_WAIT_3D_IDLECLEAN | \ 1927 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1928} while (0) 1929 1930#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ |
1849 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ | 1931 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1932 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1933 else \ 1934 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ |
1850 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1851} while (0) 1852 1853#define RADEON_FLUSH_CACHE() do { \ 1854 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1855 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1856 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1857 } else { \ --- 98 unchanged lines hidden (view full) --- 1956/* ================================================================ 1957 * Ring control 1958 */ 1959 1960#define RADEON_VERBOSE 0 1961 1962#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 1963 | 1935 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1936} while (0) 1937 1938#define RADEON_FLUSH_CACHE() do { \ 1939 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1940 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1941 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1942 } else { \ --- 98 unchanged lines hidden (view full) --- 2041/* ================================================================ 2042 * Ring control 2043 */ 2044 2045#define RADEON_VERBOSE 0 2046 2047#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2048 |
2049#define RADEON_RING_ALIGN 16 2050 |
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1964#define BEGIN_RING( n ) do { \ 1965 if ( RADEON_VERBOSE ) { \ 1966 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1967 } \ | 2051#define BEGIN_RING( n ) do { \ 2052 if ( RADEON_VERBOSE ) { \ 2053 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2054 } \ |
1968 _align_nr = (n + 0xf) & ~0xf; \ 1969 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 1970 COMMIT_RING(); \ 1971 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ | 2055 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \ 2056 _align_nr += n; \ 2057 if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \ 2058 COMMIT_RING(); \ 2059 radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \ |
1972 } \ 1973 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1974 ring = dev_priv->ring.start; \ 1975 write = dev_priv->ring.tail; \ 1976 mask = dev_priv->ring.tail_mask; \ 1977} while (0) 1978 1979#define ADVANCE_RING() do { \ --- 57 unchanged lines hidden --- | 2060 } \ 2061 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2062 ring = dev_priv->ring.start; \ 2063 write = dev_priv->ring.tail; \ 2064 mask = dev_priv->ring.tail_mask; \ 2065} while (0) 2066 2067#define ADVANCE_RING() do { \ --- 57 unchanged lines hidden --- |