| radeon_drm.h (189499) | radeon_drm.h (196470) |
|---|---|
| 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a --- 17 unchanged lines hidden (view full) --- 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 */ 32 33#include <sys/cdefs.h> | 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a --- 17 unchanged lines hidden (view full) --- 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drm.h 189499 2009-03-07 21:36:57Z rnoland $"); | 34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drm.h 196470 2009-08-23 14:55:57Z rnoland $"); |
| 35 36#ifndef __RADEON_DRM_H__ 37#define __RADEON_DRM_H__ 38 39/* WARNING: If you change any of these defines, make sure to change the 40 * defines in the X server file (radeon_sarea.h) 41 */ 42#ifndef __RADEON_SAREA_DEFINES__ --- 449 unchanged lines hidden (view full) --- 492#define DRM_RADEON_INIT_HEAP 0x15 493#define DRM_RADEON_IRQ_EMIT 0x16 494#define DRM_RADEON_IRQ_WAIT 0x17 495#define DRM_RADEON_CP_RESUME 0x18 496#define DRM_RADEON_SETPARAM 0x19 497#define DRM_RADEON_SURF_ALLOC 0x1a 498#define DRM_RADEON_SURF_FREE 0x1b 499 | 35 36#ifndef __RADEON_DRM_H__ 37#define __RADEON_DRM_H__ 38 39/* WARNING: If you change any of these defines, make sure to change the 40 * defines in the X server file (radeon_sarea.h) 41 */ 42#ifndef __RADEON_SAREA_DEFINES__ --- 449 unchanged lines hidden (view full) --- 492#define DRM_RADEON_INIT_HEAP 0x15 493#define DRM_RADEON_IRQ_EMIT 0x16 494#define DRM_RADEON_IRQ_WAIT 0x17 495#define DRM_RADEON_CP_RESUME 0x18 496#define DRM_RADEON_SETPARAM 0x19 497#define DRM_RADEON_SURF_ALLOC 0x1a 498#define DRM_RADEON_SURF_FREE 0x1b 499 |
| 500#define DRM_RADEON_CS 0x26 501 |
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| 500#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 501#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 502#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 503#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 504#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 505#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 506#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 507#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) --- 11 unchanged lines hidden (view full) --- 519#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 520#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 521#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 522#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 523#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 524#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 525#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 526#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) | 502#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 503#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 504#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 505#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 506#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 507#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 508#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 509#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) --- 11 unchanged lines hidden (view full) --- 521#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 522#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 523#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 524#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 525#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 526#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 527#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 528#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) |
| 529#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) |
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| 527 528typedef struct drm_radeon_init { 529 enum { 530 RADEON_INIT_CP = 0x01, 531 RADEON_CLEANUP_CP = 0x02, 532 RADEON_INIT_R200_CP = 0x03, 533 RADEON_INIT_R300_CP = 0x04, 534 RADEON_INIT_R600_CP = 0x05, --- 215 unchanged lines hidden (view full) --- 750 751typedef struct drm_radeon_surface_free { 752 unsigned int address; 753} drm_radeon_surface_free_t; 754 755#define DRM_RADEON_VBLANK_CRTC1 1 756#define DRM_RADEON_VBLANK_CRTC2 2 757 | 530 531typedef struct drm_radeon_init { 532 enum { 533 RADEON_INIT_CP = 0x01, 534 RADEON_CLEANUP_CP = 0x02, 535 RADEON_INIT_R200_CP = 0x03, 536 RADEON_INIT_R300_CP = 0x04, 537 RADEON_INIT_R600_CP = 0x05, --- 215 unchanged lines hidden (view full) --- 753 754typedef struct drm_radeon_surface_free { 755 unsigned int address; 756} drm_radeon_surface_free_t; 757 758#define DRM_RADEON_VBLANK_CRTC1 1 759#define DRM_RADEON_VBLANK_CRTC2 2 760 |
| 761/* New interface which obsolete all previous interface. 762 */ 763#define RADEON_CHUNK_ID_RELOCS 0x01 764#define RADEON_CHUNK_ID_IB 0x02 765#define RADEON_CHUNK_ID_OLD 0xff 766 767struct drm_radeon_cs_chunk { 768 uint32_t chunk_id; 769 uint32_t length_dw; 770 uint64_t chunk_data; 771}; 772 773struct drm_radeon_cs { 774 uint32_t num_chunks; 775 uint32_t cs_id; 776 uint64_t chunks; /* this points to uint64_t * which point to 777 cs chunks */ 778}; 779 |
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| 758#endif | 780#endif |