1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drm.h 189499 2009-03-07 21:36:57Z rnoland $");
35
36#ifndef __RADEON_DRM_H__
37#define __RADEON_DRM_H__
38
39/* WARNING: If you change any of these defines, make sure to change the
40 * defines in the X server file (radeon_sarea.h)
41 */
42#ifndef __RADEON_SAREA_DEFINES__
43#define __RADEON_SAREA_DEFINES__
44
45/* Old style state flags, required for sarea interface (1.1 and 1.2
46 * clears) and 1.2 drm_vertex2 ioctl.
47 */
48#define RADEON_UPLOAD_CONTEXT 0x00000001
49#define RADEON_UPLOAD_VERTFMT 0x00000002
50#define RADEON_UPLOAD_LINE 0x00000004
51#define RADEON_UPLOAD_BUMPMAP 0x00000008
52#define RADEON_UPLOAD_MASKS 0x00000010
53#define RADEON_UPLOAD_VIEWPORT 0x00000020
54#define RADEON_UPLOAD_SETUP 0x00000040
55#define RADEON_UPLOAD_TCL 0x00000080
56#define RADEON_UPLOAD_MISC 0x00000100
57#define RADEON_UPLOAD_TEX0 0x00000200
58#define RADEON_UPLOAD_TEX1 0x00000400
59#define RADEON_UPLOAD_TEX2 0x00000800
60#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
61#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
62#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
63#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
64#define RADEON_REQUIRE_QUIESCENCE 0x00010000
65#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
66#define RADEON_UPLOAD_ALL 0x003effff
67#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
68
69/* New style per-packet identifiers for use in cmd_buffer ioctl with
70 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
71 * state bits and the packet size:
72 */
73#define RADEON_EMIT_PP_MISC 0 /* context/7 */
74#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
75#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
76#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
77#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
78#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
79#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
80#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
81#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
82#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
83#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
84#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
85#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
87#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
89#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
90#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
91#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
92#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
93#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
94#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
95#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
96#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
97#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
98#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
99#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
100#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
101#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
102#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
103#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
104#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
105#define R200_EMIT_VAP_CTL 32 /* vap/1 */
106#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
107#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
108#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
109#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
110#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
111#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
112#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
113#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
114#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
115#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
116#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
117#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
118#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
119#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
120#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
121#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
122#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
123#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
124#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
125#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
126#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
127#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
128#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
129#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
130#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
131#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
132#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
133#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
134#define R200_EMIT_PP_CUBIC_FACES_0 61
135#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
136#define R200_EMIT_PP_CUBIC_FACES_1 63
137#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
138#define R200_EMIT_PP_CUBIC_FACES_2 65
139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
140#define R200_EMIT_PP_CUBIC_FACES_3 67
141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
142#define R200_EMIT_PP_CUBIC_FACES_4 69
143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
144#define R200_EMIT_PP_CUBIC_FACES_5 71
145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
146#define RADEON_EMIT_PP_TEX_SIZE_0 73
147#define RADEON_EMIT_PP_TEX_SIZE_1 74
148#define RADEON_EMIT_PP_TEX_SIZE_2 75
149#define R200_EMIT_RB3D_BLENDCOLOR 76
150#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
151#define RADEON_EMIT_PP_CUBIC_FACES_0 78
152#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
153#define RADEON_EMIT_PP_CUBIC_FACES_1 80
154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
155#define RADEON_EMIT_PP_CUBIC_FACES_2 82
156#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
157#define R200_EMIT_PP_TRI_PERF_CNTL 84
158#define R200_EMIT_PP_AFS_0 85
159#define R200_EMIT_PP_AFS_1 86
160#define R200_EMIT_ATF_TFACTOR 87
161#define R200_EMIT_PP_TXCTLALL_0 88
162#define R200_EMIT_PP_TXCTLALL_1 89
163#define R200_EMIT_PP_TXCTLALL_2 90
164#define R200_EMIT_PP_TXCTLALL_3 91
165#define R200_EMIT_PP_TXCTLALL_4 92
166#define R200_EMIT_PP_TXCTLALL_5 93
167#define R200_EMIT_VAP_PVS_CNTL 94
168#define RADEON_MAX_STATE_PACKETS 95
169
170/* Commands understood by cmd_buffer ioctl. More can be added but
171 * obviously these can't be removed or changed:
172 */
173#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
174#define RADEON_CMD_SCALARS 2 /* emit scalar data */
175#define RADEON_CMD_VECTORS 3 /* emit vector data */
176#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
177#define RADEON_CMD_PACKET3 5 /* emit hw packet */
178#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
179#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
180#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
181 * doesn't make the cpu wait, just
182 * the graphics hardware */
183#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
184
185typedef union {
186 int i;
187 struct {
188 unsigned char cmd_type, pad0, pad1, pad2;
189 } header;
190 struct {
191 unsigned char cmd_type, packet_id, pad0, pad1;
192 } packet;
193 struct {
194 unsigned char cmd_type, offset, stride, count;
195 } scalars;
196 struct {
197 unsigned char cmd_type, offset, stride, count;
198 } vectors;
199 struct {
200 unsigned char cmd_type, addr_lo, addr_hi, count;
201 } veclinear;
202 struct {
203 unsigned char cmd_type, buf_idx, pad0, pad1;
204 } dma;
205 struct {
206 unsigned char cmd_type, flags, pad0, pad1;
207 } wait;
208} drm_radeon_cmd_header_t;
209
210#define RADEON_WAIT_2D 0x1
211#define RADEON_WAIT_3D 0x2
212
213/* Allowed parameters for R300_CMD_PACKET3
214 */
215#define R300_CMD_PACKET3_CLEAR 0
216#define R300_CMD_PACKET3_RAW 1
217
218/* Commands understood by cmd_buffer ioctl for R300.
219 * The interface has not been stabilized, so some of these may be removed
220 * and eventually reordered before stabilization.
221 */
222#define R300_CMD_PACKET0 1
223#define R300_CMD_VPU 2 /* emit vertex program upload */
224#define R300_CMD_PACKET3 3 /* emit a packet3 */
225#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
226#define R300_CMD_CP_DELAY 5
227#define R300_CMD_DMA_DISCARD 6
228#define R300_CMD_WAIT 7
229# define R300_WAIT_2D 0x1
230# define R300_WAIT_3D 0x2
231/* these two defines are DOING IT WRONG - however
232 * we have userspace which relies on using these.
233 * The wait interface is backwards compat new
234 * code should use the NEW_WAIT defines below
235 * THESE ARE NOT BIT FIELDS
236 */
237# define R300_WAIT_2D_CLEAN 0x3
238# define R300_WAIT_3D_CLEAN 0x4
239
240# define R300_NEW_WAIT_2D_3D 0x3
241# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
242# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
243# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
244
245#define R300_CMD_SCRATCH 8
246#define R300_CMD_R500FP 9
247
248typedef union {
249 unsigned int u;
250 struct {
251 unsigned char cmd_type, pad0, pad1, pad2;
252 } header;
253 struct {
254 unsigned char cmd_type, count, reglo, reghi;
255 } packet0;
256 struct {
257 unsigned char cmd_type, count, adrlo, adrhi;
258 } vpu;
259 struct {
260 unsigned char cmd_type, packet, pad0, pad1;
261 } packet3;
262 struct {
263 unsigned char cmd_type, packet;
264 unsigned short count; /* amount of packet2 to emit */
265 } delay;
266 struct {
267 unsigned char cmd_type, buf_idx, pad0, pad1;
268 } dma;
269 struct {
270 unsigned char cmd_type, flags, pad0, pad1;
271 } wait;
272 struct {
273 unsigned char cmd_type, reg, n_bufs, flags;
274 } scratch;
275 struct {
276 unsigned char cmd_type, count, adrlo, adrhi_flags;
277 } r500fp;
278} drm_r300_cmd_header_t;
279
280#define RADEON_FRONT 0x1
281#define RADEON_BACK 0x2
282#define RADEON_DEPTH 0x4
283#define RADEON_STENCIL 0x8
284#define RADEON_CLEAR_FASTZ 0x80000000
285#define RADEON_USE_HIERZ 0x40000000
286#define RADEON_USE_COMP_ZBUF 0x20000000
287
288#define R500FP_CONSTANT_TYPE (1 << 1)
289#define R500FP_CONSTANT_CLAMP (1 << 2)
290
291/* Primitive types
292 */
293#define RADEON_POINTS 0x1
294#define RADEON_LINES 0x2
295#define RADEON_LINE_STRIP 0x3
296#define RADEON_TRIANGLES 0x4
297#define RADEON_TRIANGLE_FAN 0x5
298#define RADEON_TRIANGLE_STRIP 0x6
299
300/* Vertex/indirect buffer size
301 */
302#define RADEON_BUFFER_SIZE 65536
303
304/* Byte offsets for indirect buffer data
305 */
306#define RADEON_INDEX_PRIM_OFFSET 20
307
308#define RADEON_SCRATCH_REG_OFFSET 32
309#define R600_SCRATCH_REG_OFFSET 256
310
311#define RADEON_NR_SAREA_CLIPRECTS 12
312
313/* There are 2 heaps (local/GART). Each region within a heap is a
314 * minimum of 64k, and there are at most 64 of them per heap.
315 */
316#define RADEON_LOCAL_TEX_HEAP 0
317#define RADEON_GART_TEX_HEAP 1
318#define RADEON_NR_TEX_HEAPS 2
319#define RADEON_NR_TEX_REGIONS 64
320#define RADEON_LOG_TEX_GRANULARITY 16
321
322#define RADEON_MAX_TEXTURE_LEVELS 12
323#define RADEON_MAX_TEXTURE_UNITS 3
324
325#define RADEON_MAX_SURFACES 8
326
327/* Blits have strict offset rules. All blit offset must be aligned on
328 * a 1K-byte boundary.
329 */
330#define RADEON_OFFSET_SHIFT 10
331#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
332#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
333
334#endif /* __RADEON_SAREA_DEFINES__ */
335
336typedef struct {
337 unsigned int red;
338 unsigned int green;
339 unsigned int blue;
340 unsigned int alpha;
341} radeon_color_regs_t;
342
343typedef struct {
344 /* Context state */
345 unsigned int pp_misc; /* 0x1c14 */
346 unsigned int pp_fog_color;
347 unsigned int re_solid_color;
348 unsigned int rb3d_blendcntl;
349 unsigned int rb3d_depthoffset;
350 unsigned int rb3d_depthpitch;
351 unsigned int rb3d_zstencilcntl;
352
353 unsigned int pp_cntl; /* 0x1c38 */
354 unsigned int rb3d_cntl;
355 unsigned int rb3d_coloroffset;
356 unsigned int re_width_height;
357 unsigned int rb3d_colorpitch;
358 unsigned int se_cntl;
359
360 /* Vertex format state */
361 unsigned int se_coord_fmt; /* 0x1c50 */
362
363 /* Line state */
364 unsigned int re_line_pattern; /* 0x1cd0 */
365 unsigned int re_line_state;
366
367 unsigned int se_line_width; /* 0x1db8 */
368
369 /* Bumpmap state */
370 unsigned int pp_lum_matrix; /* 0x1d00 */
371
372 unsigned int pp_rot_matrix_0; /* 0x1d58 */
373 unsigned int pp_rot_matrix_1;
374
375 /* Mask state */
376 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
377 unsigned int rb3d_ropcntl;
378 unsigned int rb3d_planemask;
379
380 /* Viewport state */
381 unsigned int se_vport_xscale; /* 0x1d98 */
382 unsigned int se_vport_xoffset;
383 unsigned int se_vport_yscale;
384 unsigned int se_vport_yoffset;
385 unsigned int se_vport_zscale;
386 unsigned int se_vport_zoffset;
387
388 /* Setup state */
389 unsigned int se_cntl_status; /* 0x2140 */
390
391 /* Misc state */
392 unsigned int re_top_left; /* 0x26c0 */
393 unsigned int re_misc;
394} drm_radeon_context_regs_t;
395
396typedef struct {
397 /* Zbias state */
398 unsigned int se_zbias_factor; /* 0x1dac */
399 unsigned int se_zbias_constant;
400} drm_radeon_context2_regs_t;
401
402/* Setup registers for each texture unit
403 */
404typedef struct {
405 unsigned int pp_txfilter;
406 unsigned int pp_txformat;
407 unsigned int pp_txoffset;
408 unsigned int pp_txcblend;
409 unsigned int pp_txablend;
410 unsigned int pp_tfactor;
411 unsigned int pp_border_color;
412} drm_radeon_texture_regs_t;
413
414typedef struct {
415 unsigned int start;
416 unsigned int finish;
417 unsigned int prim:8;
418 unsigned int stateidx:8;
419 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
420 unsigned int vc_format; /* vertex format */
421} drm_radeon_prim_t;
422
423typedef struct {
424 drm_radeon_context_regs_t context;
425 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
426 drm_radeon_context2_regs_t context2;
427 unsigned int dirty;
428} drm_radeon_state_t;
429
430typedef struct {
431 /* The channel for communication of state information to the
432 * kernel on firing a vertex buffer with either of the
433 * obsoleted vertex/index ioctls.
434 */
435 drm_radeon_context_regs_t context_state;
436 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
437 unsigned int dirty;
438 unsigned int vertsize;
439 unsigned int vc_format;
440
441 /* The current cliprects, or a subset thereof.
442 */
443 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
444 unsigned int nbox;
445
446 /* Counters for client-side throttling of rendering clients.
447 */
448 unsigned int last_frame;
449 unsigned int last_dispatch;
450 unsigned int last_clear;
451
452 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
453 1];
454 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
455 int ctx_owner;
456 int pfState; /* number of 3d windows (0,1,2ormore) */
457 int pfCurrentPage; /* which buffer is being displayed? */
458 int crtc2_base; /* CRTC2 frame offset */
459 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
460} drm_radeon_sarea_t;
461
462/* WARNING: If you change any of these defines, make sure to change the
463 * defines in the Xserver file (xf86drmRadeon.h)
464 *
465 * KW: actually it's illegal to change any of this (backwards compatibility).
466 */
467
468/* Radeon specific ioctls
469 * The device specific ioctl range is 0x40 to 0x79.
470 */
471#define DRM_RADEON_CP_INIT 0x00
472#define DRM_RADEON_CP_START 0x01
473#define DRM_RADEON_CP_STOP 0x02
474#define DRM_RADEON_CP_RESET 0x03
475#define DRM_RADEON_CP_IDLE 0x04
476#define DRM_RADEON_RESET 0x05
477#define DRM_RADEON_FULLSCREEN 0x06
478#define DRM_RADEON_SWAP 0x07
479#define DRM_RADEON_CLEAR 0x08
480#define DRM_RADEON_VERTEX 0x09
481#define DRM_RADEON_INDICES 0x0A
482#define DRM_RADEON_NOT_USED
483#define DRM_RADEON_STIPPLE 0x0C
484#define DRM_RADEON_INDIRECT 0x0D
485#define DRM_RADEON_TEXTURE 0x0E
486#define DRM_RADEON_VERTEX2 0x0F
487#define DRM_RADEON_CMDBUF 0x10
488#define DRM_RADEON_GETPARAM 0x11
489#define DRM_RADEON_FLIP 0x12
490#define DRM_RADEON_ALLOC 0x13
491#define DRM_RADEON_FREE 0x14
492#define DRM_RADEON_INIT_HEAP 0x15
493#define DRM_RADEON_IRQ_EMIT 0x16
494#define DRM_RADEON_IRQ_WAIT 0x17
495#define DRM_RADEON_CP_RESUME 0x18
496#define DRM_RADEON_SETPARAM 0x19
497#define DRM_RADEON_SURF_ALLOC 0x1a
498#define DRM_RADEON_SURF_FREE 0x1b
499
500#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
501#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
502#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
503#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
504#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
505#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
506#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
507#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
508#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
509#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
510#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
511#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
512#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
513#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
514#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
515#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
516#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
517#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
518#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
519#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
520#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
521#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
522#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
523#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
524#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
525#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
526#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
527
528typedef struct drm_radeon_init {
529 enum {
530 RADEON_INIT_CP = 0x01,
531 RADEON_CLEANUP_CP = 0x02,
532 RADEON_INIT_R200_CP = 0x03,
533 RADEON_INIT_R300_CP = 0x04,
534 RADEON_INIT_R600_CP = 0x05,
535 } func;
536 unsigned long sarea_priv_offset;
537 int is_pci; /* for overriding only */
538 int cp_mode;
539 int gart_size;
540 int ring_size;
541 int usec_timeout;
542
543 unsigned int fb_bpp;
544 unsigned int front_offset, front_pitch;
545 unsigned int back_offset, back_pitch;
546 unsigned int depth_bpp;
547 unsigned int depth_offset, depth_pitch;
548
549 unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
550 unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
551 unsigned long ring_offset;
552 unsigned long ring_rptr_offset;
553 unsigned long buffers_offset;
554 unsigned long gart_textures_offset;
555} drm_radeon_init_t;
556
557typedef struct drm_radeon_cp_stop {
558 int flush;
559 int idle;
560} drm_radeon_cp_stop_t;
561
562typedef struct drm_radeon_fullscreen {
563 enum {
564 RADEON_INIT_FULLSCREEN = 0x01,
565 RADEON_CLEANUP_FULLSCREEN = 0x02
566 } func;
567} drm_radeon_fullscreen_t;
568
569#define CLEAR_X1 0
570#define CLEAR_Y1 1
571#define CLEAR_X2 2
572#define CLEAR_Y2 3
573#define CLEAR_DEPTH 4
574
575typedef union drm_radeon_clear_rect {
576 float f[5];
577 unsigned int ui[5];
578} drm_radeon_clear_rect_t;
579
580typedef struct drm_radeon_clear {
581 unsigned int flags;
582 unsigned int clear_color;
583 unsigned int clear_depth;
584 unsigned int color_mask;
585 unsigned int depth_mask; /* misnamed field: should be stencil */
586 drm_radeon_clear_rect_t __user *depth_boxes;
587} drm_radeon_clear_t;
588
589typedef struct drm_radeon_vertex {
590 int prim;
591 int idx; /* Index of vertex buffer */
592 int count; /* Number of vertices in buffer */
593 int discard; /* Client finished with buffer? */
594} drm_radeon_vertex_t;
595
596typedef struct drm_radeon_indices {
597 int prim;
598 int idx;
599 int start;
600 int end;
601 int discard; /* Client finished with buffer? */
602} drm_radeon_indices_t;
603
604/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
605 * - allows multiple primitives and state changes in a single ioctl
606 * - supports driver change to emit native primitives
607 */
608typedef struct drm_radeon_vertex2 {
609 int idx; /* Index of vertex buffer */
610 int discard; /* Client finished with buffer? */
611 int nr_states;
612 drm_radeon_state_t __user *state;
613 int nr_prims;
614 drm_radeon_prim_t __user *prim;
615} drm_radeon_vertex2_t;
616
617/* v1.3 - obsoletes drm_radeon_vertex2
618 * - allows arbitarily large cliprect list
619 * - allows updating of tcl packet, vector and scalar state
620 * - allows memory-efficient description of state updates
621 * - allows state to be emitted without a primitive
622 * (for clears, ctx switches)
623 * - allows more than one dma buffer to be referenced per ioctl
624 * - supports tcl driver
625 * - may be extended in future versions with new cmd types, packets
626 */
627typedef struct drm_radeon_cmd_buffer {
628 int bufsz;
629 char __user *buf;
630 int nbox;
631 struct drm_clip_rect __user *boxes;
632} drm_radeon_cmd_buffer_t;
633
634typedef struct drm_radeon_tex_image {
635 unsigned int x, y; /* Blit coordinates */
636 unsigned int width, height;
637 const void __user *data;
638} drm_radeon_tex_image_t;
639
640typedef struct drm_radeon_texture {
641 unsigned int offset;
642 int pitch;
643 int format;
644 int width; /* Texture image coordinates */
645 int height;
646 drm_radeon_tex_image_t __user *image;
647} drm_radeon_texture_t;
648
649typedef struct drm_radeon_stipple {
650 unsigned int __user *mask;
651} drm_radeon_stipple_t;
652
653typedef struct drm_radeon_indirect {
654 int idx;
655 int start;
656 int end;
657 int discard;
658} drm_radeon_indirect_t;
659
660#define RADEON_INDIRECT_DISCARD (1 << 0)
661#define RADEON_INDIRECT_NOFLUSH (1 << 1)
662
663/* enum for card type parameters */
664#define RADEON_CARD_PCI 0
665#define RADEON_CARD_AGP 1
666#define RADEON_CARD_PCIE 2
667
668/* 1.3: An ioctl to get parameters that aren't available to the 3d
669 * client any other way.
670 */
671#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
672#define RADEON_PARAM_LAST_FRAME 2
673#define RADEON_PARAM_LAST_DISPATCH 3
674#define RADEON_PARAM_LAST_CLEAR 4
675/* Added with DRM version 1.6. */
676#define RADEON_PARAM_IRQ_NR 5
677#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
678/* Added with DRM version 1.8. */
679#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
680#define RADEON_PARAM_STATUS_HANDLE 8
681#define RADEON_PARAM_SAREA_HANDLE 9
682#define RADEON_PARAM_GART_TEX_HANDLE 10
683#define RADEON_PARAM_SCRATCH_OFFSET 11
684#define RADEON_PARAM_CARD_TYPE 12
685#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
686#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
687#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
688
689typedef struct drm_radeon_getparam {
690 int param;
691 void __user *value;
692} drm_radeon_getparam_t;
693
694/* 1.6: Set up a memory manager for regions of shared memory:
695 */
696#define RADEON_MEM_REGION_GART 1
697#define RADEON_MEM_REGION_FB 2
698
699typedef struct drm_radeon_mem_alloc {
700 int region;
701 int alignment;
702 int size;
703 int __user *region_offset; /* offset from start of fb or GART */
704} drm_radeon_mem_alloc_t;
705
706typedef struct drm_radeon_mem_free {
707 int region;
708 int region_offset;
709} drm_radeon_mem_free_t;
710
711typedef struct drm_radeon_mem_init_heap {
712 int region;
713 int size;
714 int start;
715} drm_radeon_mem_init_heap_t;
716
717/* 1.6: Userspace can request & wait on irq's:
718 */
719typedef struct drm_radeon_irq_emit {
720 int __user *irq_seq;
721} drm_radeon_irq_emit_t;
722
723typedef struct drm_radeon_irq_wait {
724 int irq_seq;
725} drm_radeon_irq_wait_t;
726
727/* 1.10: Clients tell the DRM where they think the framebuffer is located in
728 * the card's address space, via a new generic ioctl to set parameters
729 */
730
731typedef struct drm_radeon_setparam {
732 unsigned int param;
733 int64_t value;
734} drm_radeon_setparam_t;
735
736#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
737#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
738#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
739
740#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
741#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
742#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
743/* 1.14: Clients can allocate/free a surface
744 */
745typedef struct drm_radeon_surface_alloc {
746 unsigned int address;
747 unsigned int size;
748 unsigned int flags;
749} drm_radeon_surface_alloc_t;
750
751typedef struct drm_radeon_surface_free {
752 unsigned int address;
753} drm_radeon_surface_free_t;
754
755#define DRM_RADEON_VBLANK_CRTC1 1
756#define DRM_RADEON_VBLANK_CRTC2 2
757
758#endif
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drm.h 189499 2009-03-07 21:36:57Z rnoland $");
35
36#ifndef __RADEON_DRM_H__
37#define __RADEON_DRM_H__
38
39/* WARNING: If you change any of these defines, make sure to change the
40 * defines in the X server file (radeon_sarea.h)
41 */
42#ifndef __RADEON_SAREA_DEFINES__
43#define __RADEON_SAREA_DEFINES__
44
45/* Old style state flags, required for sarea interface (1.1 and 1.2
46 * clears) and 1.2 drm_vertex2 ioctl.
47 */
48#define RADEON_UPLOAD_CONTEXT 0x00000001
49#define RADEON_UPLOAD_VERTFMT 0x00000002
50#define RADEON_UPLOAD_LINE 0x00000004
51#define RADEON_UPLOAD_BUMPMAP 0x00000008
52#define RADEON_UPLOAD_MASKS 0x00000010
53#define RADEON_UPLOAD_VIEWPORT 0x00000020
54#define RADEON_UPLOAD_SETUP 0x00000040
55#define RADEON_UPLOAD_TCL 0x00000080
56#define RADEON_UPLOAD_MISC 0x00000100
57#define RADEON_UPLOAD_TEX0 0x00000200
58#define RADEON_UPLOAD_TEX1 0x00000400
59#define RADEON_UPLOAD_TEX2 0x00000800
60#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
61#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
62#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
63#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
64#define RADEON_REQUIRE_QUIESCENCE 0x00010000
65#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
66#define RADEON_UPLOAD_ALL 0x003effff
67#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
68
69/* New style per-packet identifiers for use in cmd_buffer ioctl with
70 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
71 * state bits and the packet size:
72 */
73#define RADEON_EMIT_PP_MISC 0 /* context/7 */
74#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
75#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
76#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
77#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
78#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
79#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
80#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
81#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
82#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
83#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
84#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
85#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
87#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
89#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
90#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
91#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
92#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
93#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
94#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
95#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
96#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
97#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
98#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
99#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
100#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
101#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
102#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
103#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
104#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
105#define R200_EMIT_VAP_CTL 32 /* vap/1 */
106#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
107#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
108#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
109#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
110#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
111#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
112#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
113#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
114#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
115#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
116#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
117#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
118#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
119#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
120#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
121#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
122#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
123#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
124#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
125#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
126#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
127#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
128#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
129#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
130#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
131#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
132#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
133#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
134#define R200_EMIT_PP_CUBIC_FACES_0 61
135#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
136#define R200_EMIT_PP_CUBIC_FACES_1 63
137#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
138#define R200_EMIT_PP_CUBIC_FACES_2 65
139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
140#define R200_EMIT_PP_CUBIC_FACES_3 67
141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
142#define R200_EMIT_PP_CUBIC_FACES_4 69
143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
144#define R200_EMIT_PP_CUBIC_FACES_5 71
145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
146#define RADEON_EMIT_PP_TEX_SIZE_0 73
147#define RADEON_EMIT_PP_TEX_SIZE_1 74
148#define RADEON_EMIT_PP_TEX_SIZE_2 75
149#define R200_EMIT_RB3D_BLENDCOLOR 76
150#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
151#define RADEON_EMIT_PP_CUBIC_FACES_0 78
152#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
153#define RADEON_EMIT_PP_CUBIC_FACES_1 80
154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
155#define RADEON_EMIT_PP_CUBIC_FACES_2 82
156#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
157#define R200_EMIT_PP_TRI_PERF_CNTL 84
158#define R200_EMIT_PP_AFS_0 85
159#define R200_EMIT_PP_AFS_1 86
160#define R200_EMIT_ATF_TFACTOR 87
161#define R200_EMIT_PP_TXCTLALL_0 88
162#define R200_EMIT_PP_TXCTLALL_1 89
163#define R200_EMIT_PP_TXCTLALL_2 90
164#define R200_EMIT_PP_TXCTLALL_3 91
165#define R200_EMIT_PP_TXCTLALL_4 92
166#define R200_EMIT_PP_TXCTLALL_5 93
167#define R200_EMIT_VAP_PVS_CNTL 94
168#define RADEON_MAX_STATE_PACKETS 95
169
170/* Commands understood by cmd_buffer ioctl. More can be added but
171 * obviously these can't be removed or changed:
172 */
173#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
174#define RADEON_CMD_SCALARS 2 /* emit scalar data */
175#define RADEON_CMD_VECTORS 3 /* emit vector data */
176#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
177#define RADEON_CMD_PACKET3 5 /* emit hw packet */
178#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
179#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
180#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
181 * doesn't make the cpu wait, just
182 * the graphics hardware */
183#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
184
185typedef union {
186 int i;
187 struct {
188 unsigned char cmd_type, pad0, pad1, pad2;
189 } header;
190 struct {
191 unsigned char cmd_type, packet_id, pad0, pad1;
192 } packet;
193 struct {
194 unsigned char cmd_type, offset, stride, count;
195 } scalars;
196 struct {
197 unsigned char cmd_type, offset, stride, count;
198 } vectors;
199 struct {
200 unsigned char cmd_type, addr_lo, addr_hi, count;
201 } veclinear;
202 struct {
203 unsigned char cmd_type, buf_idx, pad0, pad1;
204 } dma;
205 struct {
206 unsigned char cmd_type, flags, pad0, pad1;
207 } wait;
208} drm_radeon_cmd_header_t;
209
210#define RADEON_WAIT_2D 0x1
211#define RADEON_WAIT_3D 0x2
212
213/* Allowed parameters for R300_CMD_PACKET3
214 */
215#define R300_CMD_PACKET3_CLEAR 0
216#define R300_CMD_PACKET3_RAW 1
217
218/* Commands understood by cmd_buffer ioctl for R300.
219 * The interface has not been stabilized, so some of these may be removed
220 * and eventually reordered before stabilization.
221 */
222#define R300_CMD_PACKET0 1
223#define R300_CMD_VPU 2 /* emit vertex program upload */
224#define R300_CMD_PACKET3 3 /* emit a packet3 */
225#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
226#define R300_CMD_CP_DELAY 5
227#define R300_CMD_DMA_DISCARD 6
228#define R300_CMD_WAIT 7
229# define R300_WAIT_2D 0x1
230# define R300_WAIT_3D 0x2
231/* these two defines are DOING IT WRONG - however
232 * we have userspace which relies on using these.
233 * The wait interface is backwards compat new
234 * code should use the NEW_WAIT defines below
235 * THESE ARE NOT BIT FIELDS
236 */
237# define R300_WAIT_2D_CLEAN 0x3
238# define R300_WAIT_3D_CLEAN 0x4
239
240# define R300_NEW_WAIT_2D_3D 0x3
241# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
242# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
243# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
244
245#define R300_CMD_SCRATCH 8
246#define R300_CMD_R500FP 9
247
248typedef union {
249 unsigned int u;
250 struct {
251 unsigned char cmd_type, pad0, pad1, pad2;
252 } header;
253 struct {
254 unsigned char cmd_type, count, reglo, reghi;
255 } packet0;
256 struct {
257 unsigned char cmd_type, count, adrlo, adrhi;
258 } vpu;
259 struct {
260 unsigned char cmd_type, packet, pad0, pad1;
261 } packet3;
262 struct {
263 unsigned char cmd_type, packet;
264 unsigned short count; /* amount of packet2 to emit */
265 } delay;
266 struct {
267 unsigned char cmd_type, buf_idx, pad0, pad1;
268 } dma;
269 struct {
270 unsigned char cmd_type, flags, pad0, pad1;
271 } wait;
272 struct {
273 unsigned char cmd_type, reg, n_bufs, flags;
274 } scratch;
275 struct {
276 unsigned char cmd_type, count, adrlo, adrhi_flags;
277 } r500fp;
278} drm_r300_cmd_header_t;
279
280#define RADEON_FRONT 0x1
281#define RADEON_BACK 0x2
282#define RADEON_DEPTH 0x4
283#define RADEON_STENCIL 0x8
284#define RADEON_CLEAR_FASTZ 0x80000000
285#define RADEON_USE_HIERZ 0x40000000
286#define RADEON_USE_COMP_ZBUF 0x20000000
287
288#define R500FP_CONSTANT_TYPE (1 << 1)
289#define R500FP_CONSTANT_CLAMP (1 << 2)
290
291/* Primitive types
292 */
293#define RADEON_POINTS 0x1
294#define RADEON_LINES 0x2
295#define RADEON_LINE_STRIP 0x3
296#define RADEON_TRIANGLES 0x4
297#define RADEON_TRIANGLE_FAN 0x5
298#define RADEON_TRIANGLE_STRIP 0x6
299
300/* Vertex/indirect buffer size
301 */
302#define RADEON_BUFFER_SIZE 65536
303
304/* Byte offsets for indirect buffer data
305 */
306#define RADEON_INDEX_PRIM_OFFSET 20
307
308#define RADEON_SCRATCH_REG_OFFSET 32
309#define R600_SCRATCH_REG_OFFSET 256
310
311#define RADEON_NR_SAREA_CLIPRECTS 12
312
313/* There are 2 heaps (local/GART). Each region within a heap is a
314 * minimum of 64k, and there are at most 64 of them per heap.
315 */
316#define RADEON_LOCAL_TEX_HEAP 0
317#define RADEON_GART_TEX_HEAP 1
318#define RADEON_NR_TEX_HEAPS 2
319#define RADEON_NR_TEX_REGIONS 64
320#define RADEON_LOG_TEX_GRANULARITY 16
321
322#define RADEON_MAX_TEXTURE_LEVELS 12
323#define RADEON_MAX_TEXTURE_UNITS 3
324
325#define RADEON_MAX_SURFACES 8
326
327/* Blits have strict offset rules. All blit offset must be aligned on
328 * a 1K-byte boundary.
329 */
330#define RADEON_OFFSET_SHIFT 10
331#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
332#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
333
334#endif /* __RADEON_SAREA_DEFINES__ */
335
336typedef struct {
337 unsigned int red;
338 unsigned int green;
339 unsigned int blue;
340 unsigned int alpha;
341} radeon_color_regs_t;
342
343typedef struct {
344 /* Context state */
345 unsigned int pp_misc; /* 0x1c14 */
346 unsigned int pp_fog_color;
347 unsigned int re_solid_color;
348 unsigned int rb3d_blendcntl;
349 unsigned int rb3d_depthoffset;
350 unsigned int rb3d_depthpitch;
351 unsigned int rb3d_zstencilcntl;
352
353 unsigned int pp_cntl; /* 0x1c38 */
354 unsigned int rb3d_cntl;
355 unsigned int rb3d_coloroffset;
356 unsigned int re_width_height;
357 unsigned int rb3d_colorpitch;
358 unsigned int se_cntl;
359
360 /* Vertex format state */
361 unsigned int se_coord_fmt; /* 0x1c50 */
362
363 /* Line state */
364 unsigned int re_line_pattern; /* 0x1cd0 */
365 unsigned int re_line_state;
366
367 unsigned int se_line_width; /* 0x1db8 */
368
369 /* Bumpmap state */
370 unsigned int pp_lum_matrix; /* 0x1d00 */
371
372 unsigned int pp_rot_matrix_0; /* 0x1d58 */
373 unsigned int pp_rot_matrix_1;
374
375 /* Mask state */
376 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
377 unsigned int rb3d_ropcntl;
378 unsigned int rb3d_planemask;
379
380 /* Viewport state */
381 unsigned int se_vport_xscale; /* 0x1d98 */
382 unsigned int se_vport_xoffset;
383 unsigned int se_vport_yscale;
384 unsigned int se_vport_yoffset;
385 unsigned int se_vport_zscale;
386 unsigned int se_vport_zoffset;
387
388 /* Setup state */
389 unsigned int se_cntl_status; /* 0x2140 */
390
391 /* Misc state */
392 unsigned int re_top_left; /* 0x26c0 */
393 unsigned int re_misc;
394} drm_radeon_context_regs_t;
395
396typedef struct {
397 /* Zbias state */
398 unsigned int se_zbias_factor; /* 0x1dac */
399 unsigned int se_zbias_constant;
400} drm_radeon_context2_regs_t;
401
402/* Setup registers for each texture unit
403 */
404typedef struct {
405 unsigned int pp_txfilter;
406 unsigned int pp_txformat;
407 unsigned int pp_txoffset;
408 unsigned int pp_txcblend;
409 unsigned int pp_txablend;
410 unsigned int pp_tfactor;
411 unsigned int pp_border_color;
412} drm_radeon_texture_regs_t;
413
414typedef struct {
415 unsigned int start;
416 unsigned int finish;
417 unsigned int prim:8;
418 unsigned int stateidx:8;
419 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
420 unsigned int vc_format; /* vertex format */
421} drm_radeon_prim_t;
422
423typedef struct {
424 drm_radeon_context_regs_t context;
425 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
426 drm_radeon_context2_regs_t context2;
427 unsigned int dirty;
428} drm_radeon_state_t;
429
430typedef struct {
431 /* The channel for communication of state information to the
432 * kernel on firing a vertex buffer with either of the
433 * obsoleted vertex/index ioctls.
434 */
435 drm_radeon_context_regs_t context_state;
436 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
437 unsigned int dirty;
438 unsigned int vertsize;
439 unsigned int vc_format;
440
441 /* The current cliprects, or a subset thereof.
442 */
443 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
444 unsigned int nbox;
445
446 /* Counters for client-side throttling of rendering clients.
447 */
448 unsigned int last_frame;
449 unsigned int last_dispatch;
450 unsigned int last_clear;
451
452 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
453 1];
454 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
455 int ctx_owner;
456 int pfState; /* number of 3d windows (0,1,2ormore) */
457 int pfCurrentPage; /* which buffer is being displayed? */
458 int crtc2_base; /* CRTC2 frame offset */
459 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
460} drm_radeon_sarea_t;
461
462/* WARNING: If you change any of these defines, make sure to change the
463 * defines in the Xserver file (xf86drmRadeon.h)
464 *
465 * KW: actually it's illegal to change any of this (backwards compatibility).
466 */
467
468/* Radeon specific ioctls
469 * The device specific ioctl range is 0x40 to 0x79.
470 */
471#define DRM_RADEON_CP_INIT 0x00
472#define DRM_RADEON_CP_START 0x01
473#define DRM_RADEON_CP_STOP 0x02
474#define DRM_RADEON_CP_RESET 0x03
475#define DRM_RADEON_CP_IDLE 0x04
476#define DRM_RADEON_RESET 0x05
477#define DRM_RADEON_FULLSCREEN 0x06
478#define DRM_RADEON_SWAP 0x07
479#define DRM_RADEON_CLEAR 0x08
480#define DRM_RADEON_VERTEX 0x09
481#define DRM_RADEON_INDICES 0x0A
482#define DRM_RADEON_NOT_USED
483#define DRM_RADEON_STIPPLE 0x0C
484#define DRM_RADEON_INDIRECT 0x0D
485#define DRM_RADEON_TEXTURE 0x0E
486#define DRM_RADEON_VERTEX2 0x0F
487#define DRM_RADEON_CMDBUF 0x10
488#define DRM_RADEON_GETPARAM 0x11
489#define DRM_RADEON_FLIP 0x12
490#define DRM_RADEON_ALLOC 0x13
491#define DRM_RADEON_FREE 0x14
492#define DRM_RADEON_INIT_HEAP 0x15
493#define DRM_RADEON_IRQ_EMIT 0x16
494#define DRM_RADEON_IRQ_WAIT 0x17
495#define DRM_RADEON_CP_RESUME 0x18
496#define DRM_RADEON_SETPARAM 0x19
497#define DRM_RADEON_SURF_ALLOC 0x1a
498#define DRM_RADEON_SURF_FREE 0x1b
499
500#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
501#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
502#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
503#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
504#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
505#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
506#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
507#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
508#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
509#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
510#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
511#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
512#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
513#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
514#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
515#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
516#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
517#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
518#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
519#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
520#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
521#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
522#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
523#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
524#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
525#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
526#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
527
528typedef struct drm_radeon_init {
529 enum {
530 RADEON_INIT_CP = 0x01,
531 RADEON_CLEANUP_CP = 0x02,
532 RADEON_INIT_R200_CP = 0x03,
533 RADEON_INIT_R300_CP = 0x04,
534 RADEON_INIT_R600_CP = 0x05,
535 } func;
536 unsigned long sarea_priv_offset;
537 int is_pci; /* for overriding only */
538 int cp_mode;
539 int gart_size;
540 int ring_size;
541 int usec_timeout;
542
543 unsigned int fb_bpp;
544 unsigned int front_offset, front_pitch;
545 unsigned int back_offset, back_pitch;
546 unsigned int depth_bpp;
547 unsigned int depth_offset, depth_pitch;
548
549 unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
550 unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
551 unsigned long ring_offset;
552 unsigned long ring_rptr_offset;
553 unsigned long buffers_offset;
554 unsigned long gart_textures_offset;
555} drm_radeon_init_t;
556
557typedef struct drm_radeon_cp_stop {
558 int flush;
559 int idle;
560} drm_radeon_cp_stop_t;
561
562typedef struct drm_radeon_fullscreen {
563 enum {
564 RADEON_INIT_FULLSCREEN = 0x01,
565 RADEON_CLEANUP_FULLSCREEN = 0x02
566 } func;
567} drm_radeon_fullscreen_t;
568
569#define CLEAR_X1 0
570#define CLEAR_Y1 1
571#define CLEAR_X2 2
572#define CLEAR_Y2 3
573#define CLEAR_DEPTH 4
574
575typedef union drm_radeon_clear_rect {
576 float f[5];
577 unsigned int ui[5];
578} drm_radeon_clear_rect_t;
579
580typedef struct drm_radeon_clear {
581 unsigned int flags;
582 unsigned int clear_color;
583 unsigned int clear_depth;
584 unsigned int color_mask;
585 unsigned int depth_mask; /* misnamed field: should be stencil */
586 drm_radeon_clear_rect_t __user *depth_boxes;
587} drm_radeon_clear_t;
588
589typedef struct drm_radeon_vertex {
590 int prim;
591 int idx; /* Index of vertex buffer */
592 int count; /* Number of vertices in buffer */
593 int discard; /* Client finished with buffer? */
594} drm_radeon_vertex_t;
595
596typedef struct drm_radeon_indices {
597 int prim;
598 int idx;
599 int start;
600 int end;
601 int discard; /* Client finished with buffer? */
602} drm_radeon_indices_t;
603
604/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
605 * - allows multiple primitives and state changes in a single ioctl
606 * - supports driver change to emit native primitives
607 */
608typedef struct drm_radeon_vertex2 {
609 int idx; /* Index of vertex buffer */
610 int discard; /* Client finished with buffer? */
611 int nr_states;
612 drm_radeon_state_t __user *state;
613 int nr_prims;
614 drm_radeon_prim_t __user *prim;
615} drm_radeon_vertex2_t;
616
617/* v1.3 - obsoletes drm_radeon_vertex2
618 * - allows arbitarily large cliprect list
619 * - allows updating of tcl packet, vector and scalar state
620 * - allows memory-efficient description of state updates
621 * - allows state to be emitted without a primitive
622 * (for clears, ctx switches)
623 * - allows more than one dma buffer to be referenced per ioctl
624 * - supports tcl driver
625 * - may be extended in future versions with new cmd types, packets
626 */
627typedef struct drm_radeon_cmd_buffer {
628 int bufsz;
629 char __user *buf;
630 int nbox;
631 struct drm_clip_rect __user *boxes;
632} drm_radeon_cmd_buffer_t;
633
634typedef struct drm_radeon_tex_image {
635 unsigned int x, y; /* Blit coordinates */
636 unsigned int width, height;
637 const void __user *data;
638} drm_radeon_tex_image_t;
639
640typedef struct drm_radeon_texture {
641 unsigned int offset;
642 int pitch;
643 int format;
644 int width; /* Texture image coordinates */
645 int height;
646 drm_radeon_tex_image_t __user *image;
647} drm_radeon_texture_t;
648
649typedef struct drm_radeon_stipple {
650 unsigned int __user *mask;
651} drm_radeon_stipple_t;
652
653typedef struct drm_radeon_indirect {
654 int idx;
655 int start;
656 int end;
657 int discard;
658} drm_radeon_indirect_t;
659
660#define RADEON_INDIRECT_DISCARD (1 << 0)
661#define RADEON_INDIRECT_NOFLUSH (1 << 1)
662
663/* enum for card type parameters */
664#define RADEON_CARD_PCI 0
665#define RADEON_CARD_AGP 1
666#define RADEON_CARD_PCIE 2
667
668/* 1.3: An ioctl to get parameters that aren't available to the 3d
669 * client any other way.
670 */
671#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
672#define RADEON_PARAM_LAST_FRAME 2
673#define RADEON_PARAM_LAST_DISPATCH 3
674#define RADEON_PARAM_LAST_CLEAR 4
675/* Added with DRM version 1.6. */
676#define RADEON_PARAM_IRQ_NR 5
677#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
678/* Added with DRM version 1.8. */
679#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
680#define RADEON_PARAM_STATUS_HANDLE 8
681#define RADEON_PARAM_SAREA_HANDLE 9
682#define RADEON_PARAM_GART_TEX_HANDLE 10
683#define RADEON_PARAM_SCRATCH_OFFSET 11
684#define RADEON_PARAM_CARD_TYPE 12
685#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
686#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
687#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
688
689typedef struct drm_radeon_getparam {
690 int param;
691 void __user *value;
692} drm_radeon_getparam_t;
693
694/* 1.6: Set up a memory manager for regions of shared memory:
695 */
696#define RADEON_MEM_REGION_GART 1
697#define RADEON_MEM_REGION_FB 2
698
699typedef struct drm_radeon_mem_alloc {
700 int region;
701 int alignment;
702 int size;
703 int __user *region_offset; /* offset from start of fb or GART */
704} drm_radeon_mem_alloc_t;
705
706typedef struct drm_radeon_mem_free {
707 int region;
708 int region_offset;
709} drm_radeon_mem_free_t;
710
711typedef struct drm_radeon_mem_init_heap {
712 int region;
713 int size;
714 int start;
715} drm_radeon_mem_init_heap_t;
716
717/* 1.6: Userspace can request & wait on irq's:
718 */
719typedef struct drm_radeon_irq_emit {
720 int __user *irq_seq;
721} drm_radeon_irq_emit_t;
722
723typedef struct drm_radeon_irq_wait {
724 int irq_seq;
725} drm_radeon_irq_wait_t;
726
727/* 1.10: Clients tell the DRM where they think the framebuffer is located in
728 * the card's address space, via a new generic ioctl to set parameters
729 */
730
731typedef struct drm_radeon_setparam {
732 unsigned int param;
733 int64_t value;
734} drm_radeon_setparam_t;
735
736#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
737#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
738#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
739
740#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
741#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
742#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
743/* 1.14: Clients can allocate/free a surface
744 */
745typedef struct drm_radeon_surface_alloc {
746 unsigned int address;
747 unsigned int size;
748 unsigned int flags;
749} drm_radeon_surface_alloc_t;
750
751typedef struct drm_radeon_surface_free {
752 unsigned int address;
753} drm_radeon_surface_free_t;
754
755#define DRM_RADEON_VBLANK_CRTC1 1
756#define DRM_RADEON_VBLANK_CRTC2 2
757
758#endif