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radeon_cp.c (119098) radeon_cp.c (119895)
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

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22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

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22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119098 2003-08-19 02:57:31Z anholt $
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119895 2003-09-09 00:24:31Z anholt $
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38

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852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38

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852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
860 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
860 (dev_priv->gart_vm_start - 1) & 0xffff0000 );
861
861
862#if __REALLY_HAVE_AGP
862 if ( !dev_priv->is_pci ) {
863 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
863 if ( !dev_priv->is_pci ) {
864 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
864 (((dev_priv->agp_vm_start - 1 +
865 dev_priv->agp_size) & 0xffff0000) |
866 (dev_priv->agp_vm_start >> 16)) );
867 }
865 (((dev_priv->gart_vm_start - 1 +
866 dev_priv->gart_size) & 0xffff0000) |
867 (dev_priv->gart_vm_start >> 16)) );
868
868
869#if __REALLY_HAVE_AGP
870 if ( !dev_priv->is_pci )
871 ring_start = (dev_priv->cp_ring->offset
872 - dev->agp->base
869 ring_start = (dev_priv->cp_ring->offset
870 - dev->agp->base
873 + dev_priv->agp_vm_start);
874 else
871 + dev_priv->gart_vm_start);
872 } else
875#endif
876 ring_start = (dev_priv->cp_ring->offset
877 - dev->sg->handle
873#endif
874 ring_start = (dev_priv->cp_ring->offset
875 - dev->sg->handle
878 + dev_priv->agp_vm_start);
876 + dev_priv->gart_vm_start);
879
880 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
881
882 /* Set the write pointer delay */
883 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
884
885 /* Initialize the ring buffer's read and write pointers */
886 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
887 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
888 SET_RING_HEAD( dev_priv, cur_read_ptr );
889 dev_priv->ring.tail = cur_read_ptr;
890
891#if __REALLY_HAVE_AGP
892 if ( !dev_priv->is_pci ) {
893 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
894 dev_priv->ring_rptr->offset
895 - dev->agp->base
877
878 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
879
880 /* Set the write pointer delay */
881 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
882
883 /* Initialize the ring buffer's read and write pointers */
884 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
885 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
886 SET_RING_HEAD( dev_priv, cur_read_ptr );
887 dev_priv->ring.tail = cur_read_ptr;
888
889#if __REALLY_HAVE_AGP
890 if ( !dev_priv->is_pci ) {
891 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
892 dev_priv->ring_rptr->offset
893 - dev->agp->base
896 + dev_priv->agp_vm_start);
894 + dev_priv->gart_vm_start);
897 } else
898#endif
899 {
900 drm_sg_mem_t *entry = dev->sg;
901 unsigned long tmp_ofs, page_ofs;
902
903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
904 page_ofs = tmp_ofs >> PAGE_SHIFT;

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986 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
987
988 /* set PCI GART page-table base address
989 */
990 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
991
992 /* set address range for PCI address translate
993 */
895 } else
896#endif
897 {
898 drm_sg_mem_t *entry = dev->sg;
899 unsigned long tmp_ofs, page_ofs;
900
901 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
902 page_ofs = tmp_ofs >> PAGE_SHIFT;

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984 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
985
986 /* set PCI GART page-table base address
987 */
988 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
989
990 /* set address range for PCI address translate
991 */
994 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
995 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
996 + dev_priv->agp_size - 1);
992 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
993 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
994 + dev_priv->gart_size - 1);
997
995
998 /* Turn off AGP aperture -- is this required for PCIGART?
996 /* Turn off AGP aperture -- is this required for PCI GART?
999 */
1000 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1001 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1002 } else {
1003 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1004 }
1005}
1006

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1114
1115 DRM_GETSAREA();
1116
1117 dev_priv->fb_offset = init->fb_offset;
1118 dev_priv->mmio_offset = init->mmio_offset;
1119 dev_priv->ring_offset = init->ring_offset;
1120 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1121 dev_priv->buffers_offset = init->buffers_offset;
997 */
998 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
999 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1000 } else {
1001 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1002 }
1003}
1004

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1112
1113 DRM_GETSAREA();
1114
1115 dev_priv->fb_offset = init->fb_offset;
1116 dev_priv->mmio_offset = init->mmio_offset;
1117 dev_priv->ring_offset = init->ring_offset;
1118 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1119 dev_priv->buffers_offset = init->buffers_offset;
1122 dev_priv->agp_textures_offset = init->agp_textures_offset;
1120 dev_priv->gart_textures_offset = init->gart_textures_offset;
1123
1124 if(!dev_priv->sarea) {
1125 DRM_ERROR("could not find sarea!\n");
1126 dev->dev_private = (void *)dev_priv;
1127 radeon_do_cleanup_cp(dev);
1128 return DRM_ERR(EINVAL);
1129 }
1130

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1159 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1160 if(!dev_priv->buffers) {
1161 DRM_ERROR("could not find dma buffer region!\n");
1162 dev->dev_private = (void *)dev_priv;
1163 radeon_do_cleanup_cp(dev);
1164 return DRM_ERR(EINVAL);
1165 }
1166
1121
1122 if(!dev_priv->sarea) {
1123 DRM_ERROR("could not find sarea!\n");
1124 dev->dev_private = (void *)dev_priv;
1125 radeon_do_cleanup_cp(dev);
1126 return DRM_ERR(EINVAL);
1127 }
1128

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1157 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1158 if(!dev_priv->buffers) {
1159 DRM_ERROR("could not find dma buffer region!\n");
1160 dev->dev_private = (void *)dev_priv;
1161 radeon_do_cleanup_cp(dev);
1162 return DRM_ERR(EINVAL);
1163 }
1164
1167 if ( !dev_priv->is_pci ) {
1168 DRM_FIND_MAP( dev_priv->agp_textures,
1169 init->agp_textures_offset );
1170 if(!dev_priv->agp_textures) {
1171 DRM_ERROR("could not find agp texture region!\n");
1165 if ( init->gart_textures_offset ) {
1166 DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
1167 if ( !dev_priv->gart_textures ) {
1168 DRM_ERROR("could not find GART texture region!\n");
1172 dev->dev_private = (void *)dev_priv;
1173 radeon_do_cleanup_cp(dev);
1174 return DRM_ERR(EINVAL);
1175 }
1176 }
1177
1178 dev_priv->sarea_priv =
1179 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +

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1205 dev_priv->cp_ring->handle );
1206 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1207 dev_priv->ring_rptr->handle );
1208 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1209 dev_priv->buffers->handle );
1210 }
1211
1212
1169 dev->dev_private = (void *)dev_priv;
1170 radeon_do_cleanup_cp(dev);
1171 return DRM_ERR(EINVAL);
1172 }
1173 }
1174
1175 dev_priv->sarea_priv =
1176 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +

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1202 dev_priv->cp_ring->handle );
1203 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1204 dev_priv->ring_rptr->handle );
1205 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1206 dev_priv->buffers->handle );
1207 }
1208
1209
1213 dev_priv->agp_size = init->agp_size;
1214 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1210 dev_priv->gart_size = init->gart_size;
1211 dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1215#if __REALLY_HAVE_AGP
1216 if ( !dev_priv->is_pci )
1212#if __REALLY_HAVE_AGP
1213 if ( !dev_priv->is_pci )
1217 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1214 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1218 - dev->agp->base
1215 - dev->agp->base
1219 + dev_priv->agp_vm_start);
1216 + dev_priv->gart_vm_start);
1220 else
1221#endif
1217 else
1218#endif
1222 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1219 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1223 - dev->sg->handle
1220 - dev->sg->handle
1224 + dev_priv->agp_vm_start);
1221 + dev_priv->gart_vm_start);
1225
1222
1226 DRM_DEBUG( "dev_priv->agp_size %d\n",
1227 dev_priv->agp_size );
1228 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1229 dev_priv->agp_vm_start );
1230 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1231 dev_priv->agp_buffers_offset );
1223 DRM_DEBUG( "dev_priv->gart_size %d\n",
1224 dev_priv->gart_size );
1225 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1226 dev_priv->gart_vm_start );
1227 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1228 dev_priv->gart_buffers_offset );
1232
1233 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1234 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1235 + init->ring_size / sizeof(u32));
1236 dev_priv->ring.size = init->ring_size;
1237 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1238
1239 dev_priv->ring.tail_mask =

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1460 radeon_do_cp_stop( dev_priv );
1461 radeon_do_engine_reset( dev );
1462 }
1463
1464 /* Disable *all* interrupts */
1465 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1466
1467 /* Free memory heap structures */
1229
1230 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1231 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1232 + init->ring_size / sizeof(u32));
1233 dev_priv->ring.size = init->ring_size;
1234 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1235
1236 dev_priv->ring.tail_mask =

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1457 radeon_do_cp_stop( dev_priv );
1458 radeon_do_engine_reset( dev );
1459 }
1460
1461 /* Disable *all* interrupts */
1462 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1463
1464 /* Free memory heap structures */
1468 radeon_mem_takedown( &(dev_priv->agp_heap) );
1465 radeon_mem_takedown( &(dev_priv->gart_heap) );
1469 radeon_mem_takedown( &(dev_priv->fb_heap) );
1470
1471 /* deallocate kernel resources */
1472 radeon_do_cleanup_cp( dev );
1473 }
1474}
1475
1476/* Just reset the CP ring. Called as part of an X Server engine reset.

--- 271 unchanged lines hidden --- 		1466 radeon_mem_takedown( &(dev_priv->fb_heap) );
1467
1468 /* deallocate kernel resources */
1469 radeon_do_cleanup_cp( dev );
1470 }
1471}
1472
1473/* Just reset the CP ring. Called as part of an X Server engine reset.

--- 271 unchanged lines hidden ---