1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 13 unchanged lines hidden (view full) --- 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * |
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119895 2003-09-09 00:24:31Z anholt $ |
31 */ 32 33#include "dev/drm/radeon.h" 34#include "dev/drm/drmP.h" 35#include "dev/drm/drm.h" 36#include "dev/drm/radeon_drm.h" 37#include "dev/drm/radeon_drv.h" 38 --- 813 unchanged lines hidden (view full) --- 852static void radeon_cp_init_ring_buffer( drm_device_t *dev, 853 drm_radeon_private_t *dev_priv ) 854{ 855 u32 ring_start, cur_read_ptr; 856 u32 tmp; 857 858 /* Initialize the memory controller */ 859 RADEON_WRITE( RADEON_MC_FB_LOCATION, |
860 (dev_priv->gart_vm_start - 1) & 0xffff0000 ); |
861 |
862#if __REALLY_HAVE_AGP |
863 if ( !dev_priv->is_pci ) { 864 RADEON_WRITE( RADEON_MC_AGP_LOCATION, |
865 (((dev_priv->gart_vm_start - 1 + 866 dev_priv->gart_size) & 0xffff0000) | 867 (dev_priv->gart_vm_start >> 16)) ); |
868 |
869 ring_start = (dev_priv->cp_ring->offset 870 - dev->agp->base |
871 + dev_priv->gart_vm_start); 872 } else |
873#endif 874 ring_start = (dev_priv->cp_ring->offset 875 - dev->sg->handle |
876 + dev_priv->gart_vm_start); |
877 878 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); 879 880 /* Set the write pointer delay */ 881 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); 882 883 /* Initialize the ring buffer's read and write pointers */ 884 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 885 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 886 SET_RING_HEAD( dev_priv, cur_read_ptr ); 887 dev_priv->ring.tail = cur_read_ptr; 888 889#if __REALLY_HAVE_AGP 890 if ( !dev_priv->is_pci ) { 891 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 892 dev_priv->ring_rptr->offset 893 - dev->agp->base |
894 + dev_priv->gart_vm_start); |
895 } else 896#endif 897 { 898 drm_sg_mem_t *entry = dev->sg; 899 unsigned long tmp_ofs, page_ofs; 900 901 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 902 page_ofs = tmp_ofs >> PAGE_SHIFT; --- 81 unchanged lines hidden (view full) --- 984 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); 985 986 /* set PCI GART page-table base address 987 */ 988 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); 989 990 /* set address range for PCI address translate 991 */ |
992 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); 993 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 994 + dev_priv->gart_size - 1); |
995 |
996 /* Turn off AGP aperture -- is this required for PCI GART? |
997 */ 998 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 999 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1000 } else { 1001 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); 1002 } 1003} 1004 --- 107 unchanged lines hidden (view full) --- 1112 1113 DRM_GETSAREA(); 1114 1115 dev_priv->fb_offset = init->fb_offset; 1116 dev_priv->mmio_offset = init->mmio_offset; 1117 dev_priv->ring_offset = init->ring_offset; 1118 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1119 dev_priv->buffers_offset = init->buffers_offset; |
1120 dev_priv->gart_textures_offset = init->gart_textures_offset; |
1121 1122 if(!dev_priv->sarea) { 1123 DRM_ERROR("could not find sarea!\n"); 1124 dev->dev_private = (void *)dev_priv; 1125 radeon_do_cleanup_cp(dev); 1126 return DRM_ERR(EINVAL); 1127 } 1128 --- 28 unchanged lines hidden (view full) --- 1157 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); 1158 if(!dev_priv->buffers) { 1159 DRM_ERROR("could not find dma buffer region!\n"); 1160 dev->dev_private = (void *)dev_priv; 1161 radeon_do_cleanup_cp(dev); 1162 return DRM_ERR(EINVAL); 1163 } 1164 |
1165 if ( init->gart_textures_offset ) { 1166 DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset ); 1167 if ( !dev_priv->gart_textures ) { 1168 DRM_ERROR("could not find GART texture region!\n"); |
1169 dev->dev_private = (void *)dev_priv; 1170 radeon_do_cleanup_cp(dev); 1171 return DRM_ERR(EINVAL); 1172 } 1173 } 1174 1175 dev_priv->sarea_priv = 1176 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + --- 25 unchanged lines hidden (view full) --- 1202 dev_priv->cp_ring->handle ); 1203 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", 1204 dev_priv->ring_rptr->handle ); 1205 DRM_DEBUG( "dev_priv->buffers->handle %p\n", 1206 dev_priv->buffers->handle ); 1207 } 1208 1209 |
1210 dev_priv->gart_size = init->gart_size; 1211 dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE ); |
1212#if __REALLY_HAVE_AGP 1213 if ( !dev_priv->is_pci ) |
1214 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset |
1215 - dev->agp->base |
1216 + dev_priv->gart_vm_start); |
1217 else 1218#endif |
1219 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset |
1220 - dev->sg->handle |
1221 + dev_priv->gart_vm_start); |
1222 |
1223 DRM_DEBUG( "dev_priv->gart_size %d\n", 1224 dev_priv->gart_size ); 1225 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", 1226 dev_priv->gart_vm_start ); 1227 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", 1228 dev_priv->gart_buffers_offset ); |
1229 1230 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; 1231 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle 1232 + init->ring_size / sizeof(u32)); 1233 dev_priv->ring.size = init->ring_size; 1234 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 1235 1236 dev_priv->ring.tail_mask = --- 220 unchanged lines hidden (view full) --- 1457 radeon_do_cp_stop( dev_priv ); 1458 radeon_do_engine_reset( dev ); 1459 } 1460 1461 /* Disable *all* interrupts */ 1462 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 1463 1464 /* Free memory heap structures */ |
1465 radeon_mem_takedown( &(dev_priv->gart_heap) ); |
1466 radeon_mem_takedown( &(dev_priv->fb_heap) ); 1467 1468 /* deallocate kernel resources */ 1469 radeon_do_cleanup_cp( dev ); 1470 } 1471} 1472 1473/* Just reset the CP ring. Called as part of an X Server engine reset. --- 271 unchanged lines hidden --- |