Deleted Added
sdiff udiff text old ( 119098 ) new ( 119895 )
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radeon_cp.c (119098) radeon_cp.c (119895)
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119098 2003-08-19 02:57:31Z anholt $
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119895 2003-09-09 00:24:31Z anholt $
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39#define RADEON_FIFO_DEBUG 0
40
41
42/* CP microcode (from ATI) */
43static u32 R200_cp_microcode[][2] = {
44 { 0x21007000, 0000000000 },
45 { 0x20007000, 0000000000 },
46 { 0x000000ab, 0x00000004 },
47 { 0x000000af, 0x00000004 },
48 { 0x66544a49, 0000000000 },
49 { 0x49494174, 0000000000 },
50 { 0x54517d83, 0000000000 },
51 { 0x498d8b64, 0000000000 },
52 { 0x49494949, 0000000000 },
53 { 0x49da493c, 0000000000 },
54 { 0x49989898, 0000000000 },
55 { 0xd34949d5, 0000000000 },
56 { 0x9dc90e11, 0000000000 },
57 { 0xce9b9b9b, 0000000000 },
58 { 0x000f0000, 0x00000016 },
59 { 0x352e232c, 0000000000 },
60 { 0x00000013, 0x00000004 },
61 { 0x000f0000, 0x00000016 },
62 { 0x352e272c, 0000000000 },
63 { 0x000f0001, 0x00000016 },
64 { 0x3239362f, 0000000000 },
65 { 0x000077ef, 0x00000002 },
66 { 0x00061000, 0x00000002 },
67 { 0x00000020, 0x0000001a },
68 { 0x00004000, 0x0000001e },
69 { 0x00061000, 0x00000002 },
70 { 0x00000020, 0x0000001a },
71 { 0x00004000, 0x0000001e },
72 { 0x00061000, 0x00000002 },
73 { 0x00000020, 0x0000001a },
74 { 0x00004000, 0x0000001e },
75 { 0x00000016, 0x00000004 },
76 { 0x0003802a, 0x00000002 },
77 { 0x040067e0, 0x00000002 },
78 { 0x00000016, 0x00000004 },
79 { 0x000077e0, 0x00000002 },
80 { 0x00065000, 0x00000002 },
81 { 0x000037e1, 0x00000002 },
82 { 0x040067e1, 0x00000006 },
83 { 0x000077e0, 0x00000002 },
84 { 0x000077e1, 0x00000002 },
85 { 0x000077e1, 0x00000006 },
86 { 0xffffffff, 0000000000 },
87 { 0x10000000, 0000000000 },
88 { 0x0003802a, 0x00000002 },
89 { 0x040067e0, 0x00000006 },
90 { 0x00007675, 0x00000002 },
91 { 0x00007676, 0x00000002 },
92 { 0x00007677, 0x00000002 },
93 { 0x00007678, 0x00000006 },
94 { 0x0003802b, 0x00000002 },
95 { 0x04002676, 0x00000002 },
96 { 0x00007677, 0x00000002 },
97 { 0x00007678, 0x00000006 },
98 { 0x0000002e, 0x00000018 },
99 { 0x0000002e, 0x00000018 },
100 { 0000000000, 0x00000006 },
101 { 0x0000002f, 0x00000018 },
102 { 0x0000002f, 0x00000018 },
103 { 0000000000, 0x00000006 },
104 { 0x01605000, 0x00000002 },
105 { 0x00065000, 0x00000002 },
106 { 0x00098000, 0x00000002 },
107 { 0x00061000, 0x00000002 },
108 { 0x64c0603d, 0x00000004 },
109 { 0x00080000, 0x00000016 },
110 { 0000000000, 0000000000 },
111 { 0x0400251d, 0x00000002 },
112 { 0x00007580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x04002580, 0x00000002 },
115 { 0x00067581, 0x00000002 },
116 { 0x00000046, 0x00000004 },
117 { 0x00005000, 0000000000 },
118 { 0x00061000, 0x00000002 },
119 { 0x0000750e, 0x00000002 },
120 { 0x00019000, 0x00000002 },
121 { 0x00011055, 0x00000014 },
122 { 0x00000055, 0x00000012 },
123 { 0x0400250f, 0x00000002 },
124 { 0x0000504a, 0x00000004 },
125 { 0x00007565, 0x00000002 },
126 { 0x00007566, 0x00000002 },
127 { 0x00000051, 0x00000004 },
128 { 0x01e655b4, 0x00000002 },
129 { 0x4401b0dc, 0x00000002 },
130 { 0x01c110dc, 0x00000002 },
131 { 0x2666705d, 0x00000018 },
132 { 0x040c2565, 0x00000002 },
133 { 0x0000005d, 0x00000018 },
134 { 0x04002564, 0x00000002 },
135 { 0x00007566, 0x00000002 },
136 { 0x00000054, 0x00000004 },
137 { 0x00401060, 0x00000008 },
138 { 0x00101000, 0x00000002 },
139 { 0x000d80ff, 0x00000002 },
140 { 0x00800063, 0x00000008 },
141 { 0x000f9000, 0x00000002 },
142 { 0x000e00ff, 0x00000002 },
143 { 0000000000, 0x00000006 },
144 { 0x00000080, 0x00000018 },
145 { 0x00000054, 0x00000004 },
146 { 0x00007576, 0x00000002 },
147 { 0x00065000, 0x00000002 },
148 { 0x00009000, 0x00000002 },
149 { 0x00041000, 0x00000002 },
150 { 0x0c00350e, 0x00000002 },
151 { 0x00049000, 0x00000002 },
152 { 0x00051000, 0x00000002 },
153 { 0x01e785f8, 0x00000002 },
154 { 0x00200000, 0x00000002 },
155 { 0x00600073, 0x0000000c },
156 { 0x00007563, 0x00000002 },
157 { 0x006075f0, 0x00000021 },
158 { 0x20007068, 0x00000004 },
159 { 0x00005068, 0x00000004 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600076, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000076, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x0020750f, 0x00000002 },
171 { 0x00600079, 0x00000004 },
172 { 0x00007570, 0x00000002 },
173 { 0x00007571, 0x00000002 },
174 { 0x00007572, 0x00000006 },
175 { 0x00005000, 0x00000002 },
176 { 0x00a05000, 0x00000002 },
177 { 0x00007568, 0x00000002 },
178 { 0x00061000, 0x00000002 },
179 { 0x00000084, 0x0000000c },
180 { 0x00058000, 0x00000002 },
181 { 0x0c607562, 0x00000002 },
182 { 0x00000086, 0x00000004 },
183 { 0x00600085, 0x00000004 },
184 { 0x400070dd, 0000000000 },
185 { 0x000380dd, 0x00000002 },
186 { 0x00000093, 0x0000001c },
187 { 0x00065095, 0x00000018 },
188 { 0x040025bb, 0x00000002 },
189 { 0x00061096, 0x00000018 },
190 { 0x040075bc, 0000000000 },
191 { 0x000075bb, 0x00000002 },
192 { 0x000075bc, 0000000000 },
193 { 0x00090000, 0x00000006 },
194 { 0x00090000, 0x00000002 },
195 { 0x000d8002, 0x00000006 },
196 { 0x00005000, 0x00000002 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x00007821, 0x00000002 },
200 { 0x00007800, 0000000000 },
201 { 0x01665000, 0x00000002 },
202 { 0x000a0000, 0x00000002 },
203 { 0x000671cc, 0x00000002 },
204 { 0x0286f1cd, 0x00000002 },
205 { 0x000000a3, 0x00000010 },
206 { 0x21007000, 0000000000 },
207 { 0x000000aa, 0x0000001c },
208 { 0x00065000, 0x00000002 },
209 { 0x000a0000, 0x00000002 },
210 { 0x00061000, 0x00000002 },
211 { 0x000b0000, 0x00000002 },
212 { 0x38067000, 0x00000002 },
213 { 0x000a00a6, 0x00000004 },
214 { 0x20007000, 0000000000 },
215 { 0x01200000, 0x00000002 },
216 { 0x20077000, 0x00000002 },
217 { 0x01200000, 0x00000002 },
218 { 0x20007000, 0000000000 },
219 { 0x00061000, 0x00000002 },
220 { 0x0120751b, 0x00000002 },
221 { 0x8040750a, 0x00000002 },
222 { 0x8040750b, 0x00000002 },
223 { 0x00110000, 0x00000002 },
224 { 0x000380dd, 0x00000002 },
225 { 0x000000bd, 0x0000001c },
226 { 0x00061096, 0x00000018 },
227 { 0x844075bd, 0x00000002 },
228 { 0x00061095, 0x00000018 },
229 { 0x840075bb, 0x00000002 },
230 { 0x00061096, 0x00000018 },
231 { 0x844075bc, 0x00000002 },
232 { 0x000000c0, 0x00000004 },
233 { 0x804075bd, 0x00000002 },
234 { 0x800075bb, 0x00000002 },
235 { 0x804075bc, 0x00000002 },
236 { 0x00108000, 0x00000002 },
237 { 0x01400000, 0x00000002 },
238 { 0x006000c4, 0x0000000c },
239 { 0x20c07000, 0x00000020 },
240 { 0x000000c6, 0x00000012 },
241 { 0x00800000, 0x00000006 },
242 { 0x0080751d, 0x00000006 },
243 { 0x000025bb, 0x00000002 },
244 { 0x000040c0, 0x00000004 },
245 { 0x0000775c, 0x00000002 },
246 { 0x00a05000, 0x00000002 },
247 { 0x00661000, 0x00000002 },
248 { 0x0460275d, 0x00000020 },
249 { 0x00004000, 0000000000 },
250 { 0x00007999, 0x00000002 },
251 { 0x00a05000, 0x00000002 },
252 { 0x00661000, 0x00000002 },
253 { 0x0460299b, 0x00000020 },
254 { 0x00004000, 0000000000 },
255 { 0x01e00830, 0x00000002 },
256 { 0x21007000, 0000000000 },
257 { 0x00005000, 0x00000002 },
258 { 0x00038042, 0x00000002 },
259 { 0x040025e0, 0x00000002 },
260 { 0x000075e1, 0000000000 },
261 { 0x00000001, 0000000000 },
262 { 0x000380d9, 0x00000002 },
263 { 0x04007394, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 { 0000000000, 0000000000 },
300};
301
302
303static u32 radeon_cp_microcode[][2] = {
304 { 0x21007000, 0000000000 },
305 { 0x20007000, 0000000000 },
306 { 0x000000b4, 0x00000004 },
307 { 0x000000b8, 0x00000004 },
308 { 0x6f5b4d4c, 0000000000 },
309 { 0x4c4c427f, 0000000000 },
310 { 0x5b568a92, 0000000000 },
311 { 0x4ca09c6d, 0000000000 },
312 { 0xad4c4c4c, 0000000000 },
313 { 0x4ce1af3d, 0000000000 },
314 { 0xd8afafaf, 0000000000 },
315 { 0xd64c4cdc, 0000000000 },
316 { 0x4cd10d10, 0000000000 },
317 { 0x000f0000, 0x00000016 },
318 { 0x362f242d, 0000000000 },
319 { 0x00000012, 0x00000004 },
320 { 0x000f0000, 0x00000016 },
321 { 0x362f282d, 0000000000 },
322 { 0x000380e7, 0x00000002 },
323 { 0x04002c97, 0x00000002 },
324 { 0x000f0001, 0x00000016 },
325 { 0x333a3730, 0000000000 },
326 { 0x000077ef, 0x00000002 },
327 { 0x00061000, 0x00000002 },
328 { 0x00000021, 0x0000001a },
329 { 0x00004000, 0x0000001e },
330 { 0x00061000, 0x00000002 },
331 { 0x00000021, 0x0000001a },
332 { 0x00004000, 0x0000001e },
333 { 0x00061000, 0x00000002 },
334 { 0x00000021, 0x0000001a },
335 { 0x00004000, 0x0000001e },
336 { 0x00000017, 0x00000004 },
337 { 0x0003802b, 0x00000002 },
338 { 0x040067e0, 0x00000002 },
339 { 0x00000017, 0x00000004 },
340 { 0x000077e0, 0x00000002 },
341 { 0x00065000, 0x00000002 },
342 { 0x000037e1, 0x00000002 },
343 { 0x040067e1, 0x00000006 },
344 { 0x000077e0, 0x00000002 },
345 { 0x000077e1, 0x00000002 },
346 { 0x000077e1, 0x00000006 },
347 { 0xffffffff, 0000000000 },
348 { 0x10000000, 0000000000 },
349 { 0x0003802b, 0x00000002 },
350 { 0x040067e0, 0x00000006 },
351 { 0x00007675, 0x00000002 },
352 { 0x00007676, 0x00000002 },
353 { 0x00007677, 0x00000002 },
354 { 0x00007678, 0x00000006 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002676, 0x00000002 },
357 { 0x00007677, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0000002f, 0x00000018 },
360 { 0x0000002f, 0x00000018 },
361 { 0000000000, 0x00000006 },
362 { 0x00000030, 0x00000018 },
363 { 0x00000030, 0x00000018 },
364 { 0000000000, 0x00000006 },
365 { 0x01605000, 0x00000002 },
366 { 0x00065000, 0x00000002 },
367 { 0x00098000, 0x00000002 },
368 { 0x00061000, 0x00000002 },
369 { 0x64c0603e, 0x00000004 },
370 { 0x000380e6, 0x00000002 },
371 { 0x040025c5, 0x00000002 },
372 { 0x00080000, 0x00000016 },
373 { 0000000000, 0000000000 },
374 { 0x0400251d, 0x00000002 },
375 { 0x00007580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x04002580, 0x00000002 },
378 { 0x00067581, 0x00000002 },
379 { 0x00000049, 0x00000004 },
380 { 0x00005000, 0000000000 },
381 { 0x000380e6, 0x00000002 },
382 { 0x040025c5, 0x00000002 },
383 { 0x00061000, 0x00000002 },
384 { 0x0000750e, 0x00000002 },
385 { 0x00019000, 0x00000002 },
386 { 0x00011055, 0x00000014 },
387 { 0x00000055, 0x00000012 },
388 { 0x0400250f, 0x00000002 },
389 { 0x0000504f, 0x00000004 },
390 { 0x000380e6, 0x00000002 },
391 { 0x040025c5, 0x00000002 },
392 { 0x00007565, 0x00000002 },
393 { 0x00007566, 0x00000002 },
394 { 0x00000058, 0x00000004 },
395 { 0x000380e6, 0x00000002 },
396 { 0x040025c5, 0x00000002 },
397 { 0x01e655b4, 0x00000002 },
398 { 0x4401b0e4, 0x00000002 },
399 { 0x01c110e4, 0x00000002 },
400 { 0x26667066, 0x00000018 },
401 { 0x040c2565, 0x00000002 },
402 { 0x00000066, 0x00000018 },
403 { 0x04002564, 0x00000002 },
404 { 0x00007566, 0x00000002 },
405 { 0x0000005d, 0x00000004 },
406 { 0x00401069, 0x00000008 },
407 { 0x00101000, 0x00000002 },
408 { 0x000d80ff, 0x00000002 },
409 { 0x0080006c, 0x00000008 },
410 { 0x000f9000, 0x00000002 },
411 { 0x000e00ff, 0x00000002 },
412 { 0000000000, 0x00000006 },
413 { 0x0000008f, 0x00000018 },
414 { 0x0000005b, 0x00000004 },
415 { 0x000380e6, 0x00000002 },
416 { 0x040025c5, 0x00000002 },
417 { 0x00007576, 0x00000002 },
418 { 0x00065000, 0x00000002 },
419 { 0x00009000, 0x00000002 },
420 { 0x00041000, 0x00000002 },
421 { 0x0c00350e, 0x00000002 },
422 { 0x00049000, 0x00000002 },
423 { 0x00051000, 0x00000002 },
424 { 0x01e785f8, 0x00000002 },
425 { 0x00200000, 0x00000002 },
426 { 0x0060007e, 0x0000000c },
427 { 0x00007563, 0x00000002 },
428 { 0x006075f0, 0x00000021 },
429 { 0x20007073, 0x00000004 },
430 { 0x00005073, 0x00000004 },
431 { 0x000380e6, 0x00000002 },
432 { 0x040025c5, 0x00000002 },
433 { 0x00007576, 0x00000002 },
434 { 0x00007577, 0x00000002 },
435 { 0x0000750e, 0x00000002 },
436 { 0x0000750f, 0x00000002 },
437 { 0x00a05000, 0x00000002 },
438 { 0x00600083, 0x0000000c },
439 { 0x006075f0, 0x00000021 },
440 { 0x000075f8, 0x00000002 },
441 { 0x00000083, 0x00000004 },
442 { 0x000a750e, 0x00000002 },
443 { 0x000380e6, 0x00000002 },
444 { 0x040025c5, 0x00000002 },
445 { 0x0020750f, 0x00000002 },
446 { 0x00600086, 0x00000004 },
447 { 0x00007570, 0x00000002 },
448 { 0x00007571, 0x00000002 },
449 { 0x00007572, 0x00000006 },
450 { 0x000380e6, 0x00000002 },
451 { 0x040025c5, 0x00000002 },
452 { 0x00005000, 0x00000002 },
453 { 0x00a05000, 0x00000002 },
454 { 0x00007568, 0x00000002 },
455 { 0x00061000, 0x00000002 },
456 { 0x00000095, 0x0000000c },
457 { 0x00058000, 0x00000002 },
458 { 0x0c607562, 0x00000002 },
459 { 0x00000097, 0x00000004 },
460 { 0x000380e6, 0x00000002 },
461 { 0x040025c5, 0x00000002 },
462 { 0x00600096, 0x00000004 },
463 { 0x400070e5, 0000000000 },
464 { 0x000380e6, 0x00000002 },
465 { 0x040025c5, 0x00000002 },
466 { 0x000380e5, 0x00000002 },
467 { 0x000000a8, 0x0000001c },
468 { 0x000650aa, 0x00000018 },
469 { 0x040025bb, 0x00000002 },
470 { 0x000610ab, 0x00000018 },
471 { 0x040075bc, 0000000000 },
472 { 0x000075bb, 0x00000002 },
473 { 0x000075bc, 0000000000 },
474 { 0x00090000, 0x00000006 },
475 { 0x00090000, 0x00000002 },
476 { 0x000d8002, 0x00000006 },
477 { 0x00007832, 0x00000002 },
478 { 0x00005000, 0x00000002 },
479 { 0x000380e7, 0x00000002 },
480 { 0x04002c97, 0x00000002 },
481 { 0x00007820, 0x00000002 },
482 { 0x00007821, 0x00000002 },
483 { 0x00007800, 0000000000 },
484 { 0x01200000, 0x00000002 },
485 { 0x20077000, 0x00000002 },
486 { 0x01200000, 0x00000002 },
487 { 0x20007000, 0x00000002 },
488 { 0x00061000, 0x00000002 },
489 { 0x0120751b, 0x00000002 },
490 { 0x8040750a, 0x00000002 },
491 { 0x8040750b, 0x00000002 },
492 { 0x00110000, 0x00000002 },
493 { 0x000380e5, 0x00000002 },
494 { 0x000000c6, 0x0000001c },
495 { 0x000610ab, 0x00000018 },
496 { 0x844075bd, 0x00000002 },
497 { 0x000610aa, 0x00000018 },
498 { 0x840075bb, 0x00000002 },
499 { 0x000610ab, 0x00000018 },
500 { 0x844075bc, 0x00000002 },
501 { 0x000000c9, 0x00000004 },
502 { 0x804075bd, 0x00000002 },
503 { 0x800075bb, 0x00000002 },
504 { 0x804075bc, 0x00000002 },
505 { 0x00108000, 0x00000002 },
506 { 0x01400000, 0x00000002 },
507 { 0x006000cd, 0x0000000c },
508 { 0x20c07000, 0x00000020 },
509 { 0x000000cf, 0x00000012 },
510 { 0x00800000, 0x00000006 },
511 { 0x0080751d, 0x00000006 },
512 { 0000000000, 0000000000 },
513 { 0x0000775c, 0x00000002 },
514 { 0x00a05000, 0x00000002 },
515 { 0x00661000, 0x00000002 },
516 { 0x0460275d, 0x00000020 },
517 { 0x00004000, 0000000000 },
518 { 0x01e00830, 0x00000002 },
519 { 0x21007000, 0000000000 },
520 { 0x6464614d, 0000000000 },
521 { 0x69687420, 0000000000 },
522 { 0x00000073, 0000000000 },
523 { 0000000000, 0000000000 },
524 { 0x00005000, 0x00000002 },
525 { 0x000380d0, 0x00000002 },
526 { 0x040025e0, 0x00000002 },
527 { 0x000075e1, 0000000000 },
528 { 0x00000001, 0000000000 },
529 { 0x000380e0, 0x00000002 },
530 { 0x04002394, 0x00000002 },
531 { 0x00005000, 0000000000 },
532 { 0000000000, 0000000000 },
533 { 0000000000, 0000000000 },
534 { 0x00000008, 0000000000 },
535 { 0x00000004, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 { 0000000000, 0000000000 },
560};
561
562
563int RADEON_READ_PLL(drm_device_t *dev, int addr)
564{
565 drm_radeon_private_t *dev_priv = dev->dev_private;
566
567 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
568 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
569}
570
571#if RADEON_FIFO_DEBUG
572static void radeon_status( drm_radeon_private_t *dev_priv )
573{
574 printk( "%s:\n", __FUNCTION__ );
575 printk( "RBBM_STATUS = 0x%08x\n",
576 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
577 printk( "CP_RB_RTPR = 0x%08x\n",
578 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
579 printk( "CP_RB_WTPR = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
581 printk( "AIC_CNTL = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
583 printk( "AIC_STAT = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
585 printk( "AIC_PT_BASE = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
587 printk( "TLB_ADDR = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
589 printk( "TLB_DATA = 0x%08x\n",
590 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
591}
592#endif
593
594
595/* ================================================================
596 * Engine, FIFO control
597 */
598
599static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
600{
601 u32 tmp;
602 int i;
603
604 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
605
606 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
607 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
608 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
609
610 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
611 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
612 & RADEON_RB2D_DC_BUSY) ) {
613 return 0;
614 }
615 DRM_UDELAY( 1 );
616 }
617
618#if RADEON_FIFO_DEBUG
619 DRM_ERROR( "failed!\n" );
620 radeon_status( dev_priv );
621#endif
622 return DRM_ERR(EBUSY);
623}
624
625static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
626 int entries )
627{
628 int i;
629
630 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
631
632 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
633 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
634 & RADEON_RBBM_FIFOCNT_MASK );
635 if ( slots >= entries ) return 0;
636 DRM_UDELAY( 1 );
637 }
638
639#if RADEON_FIFO_DEBUG
640 DRM_ERROR( "failed!\n" );
641 radeon_status( dev_priv );
642#endif
643 return DRM_ERR(EBUSY);
644}
645
646static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
647{
648 int i, ret;
649
650 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
651
652 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
653 if ( ret ) return ret;
654
655 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
656 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
657 & RADEON_RBBM_ACTIVE) ) {
658 radeon_do_pixcache_flush( dev_priv );
659 return 0;
660 }
661 DRM_UDELAY( 1 );
662 }
663
664#if RADEON_FIFO_DEBUG
665 DRM_ERROR( "failed!\n" );
666 radeon_status( dev_priv );
667#endif
668 return DRM_ERR(EBUSY);
669}
670
671
672/* ================================================================
673 * CP control, initialization
674 */
675
676/* Load the microcode for the CP */
677static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
678{
679 int i;
680 DRM_DEBUG( "\n" );
681
682 radeon_do_wait_for_idle( dev_priv );
683
684 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
685
686 if (dev_priv->is_r200)
687 {
688 DRM_INFO("Loading R200 Microcode\n");
689 for ( i = 0 ; i < 256 ; i++ )
690 {
691 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
692 R200_cp_microcode[i][1] );
693 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
694 R200_cp_microcode[i][0] );
695 }
696 }
697 else
698 {
699 for ( i = 0 ; i < 256 ; i++ ) {
700 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
701 radeon_cp_microcode[i][1] );
702 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
703 radeon_cp_microcode[i][0] );
704 }
705 }
706}
707
708/* Flush any pending commands to the CP. This should only be used just
709 * prior to a wait for idle, as it informs the engine that the command
710 * stream is ending.
711 */
712static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
713{
714 DRM_DEBUG( "\n" );
715#if 0
716 u32 tmp;
717
718 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
719 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
720#endif
721}
722
723/* Wait for the CP to go idle.
724 */
725int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
726{
727 RING_LOCALS;
728 DRM_DEBUG( "\n" );
729
730 BEGIN_RING( 6 );
731
732 RADEON_PURGE_CACHE();
733 RADEON_PURGE_ZCACHE();
734 RADEON_WAIT_UNTIL_IDLE();
735
736 ADVANCE_RING();
737 COMMIT_RING();
738
739 return radeon_do_wait_for_idle( dev_priv );
740}
741
742/* Start the Command Processor.
743 */
744static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
745{
746 RING_LOCALS;
747 DRM_DEBUG( "\n" );
748
749 radeon_do_wait_for_idle( dev_priv );
750
751 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
752
753 dev_priv->cp_running = 1;
754
755 BEGIN_RING( 6 );
756
757 RADEON_PURGE_CACHE();
758 RADEON_PURGE_ZCACHE();
759 RADEON_WAIT_UNTIL_IDLE();
760
761 ADVANCE_RING();
762 COMMIT_RING();
763}
764
765/* Reset the Command Processor. This will not flush any pending
766 * commands, so you must wait for the CP command stream to complete
767 * before calling this routine.
768 */
769static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
770{
771 u32 cur_read_ptr;
772 DRM_DEBUG( "\n" );
773
774 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
775 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
776 SET_RING_HEAD( dev_priv, cur_read_ptr );
777 dev_priv->ring.tail = cur_read_ptr;
778}
779
780/* Stop the Command Processor. This will not flush any pending
781 * commands, so you must flush the command stream and wait for the CP
782 * to go idle before calling this routine.
783 */
784static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
785{
786 DRM_DEBUG( "\n" );
787
788 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
789
790 dev_priv->cp_running = 0;
791}
792
793/* Reset the engine. This will stop the CP if it is running.
794 */
795static int radeon_do_engine_reset( drm_device_t *dev )
796{
797 drm_radeon_private_t *dev_priv = dev->dev_private;
798 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
799 DRM_DEBUG( "\n" );
800
801 radeon_do_pixcache_flush( dev_priv );
802
803 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
804 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
805
806 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
807 RADEON_FORCEON_MCLKA |
808 RADEON_FORCEON_MCLKB |
809 RADEON_FORCEON_YCLKA |
810 RADEON_FORCEON_YCLKB |
811 RADEON_FORCEON_MC |
812 RADEON_FORCEON_AIC ) );
813
814 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
815
816 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
817 RADEON_SOFT_RESET_CP |
818 RADEON_SOFT_RESET_HI |
819 RADEON_SOFT_RESET_SE |
820 RADEON_SOFT_RESET_RE |
821 RADEON_SOFT_RESET_PP |
822 RADEON_SOFT_RESET_E2 |
823 RADEON_SOFT_RESET_RB ) );
824 RADEON_READ( RADEON_RBBM_SOFT_RESET );
825 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
826 ~( RADEON_SOFT_RESET_CP |
827 RADEON_SOFT_RESET_HI |
828 RADEON_SOFT_RESET_SE |
829 RADEON_SOFT_RESET_RE |
830 RADEON_SOFT_RESET_PP |
831 RADEON_SOFT_RESET_E2 |
832 RADEON_SOFT_RESET_RB ) ) );
833 RADEON_READ( RADEON_RBBM_SOFT_RESET );
834
835
836 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
837 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
838 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
839
840 /* Reset the CP ring */
841 radeon_do_cp_reset( dev_priv );
842
843 /* The CP is no longer running after an engine reset */
844 dev_priv->cp_running = 0;
845
846 /* Reset any pending vertex, indirect buffers */
847 radeon_freelist_reset( dev );
848
849 return 0;
850}
851
852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39#define RADEON_FIFO_DEBUG 0
40
41
42/* CP microcode (from ATI) */
43static u32 R200_cp_microcode[][2] = {
44 { 0x21007000, 0000000000 },
45 { 0x20007000, 0000000000 },
46 { 0x000000ab, 0x00000004 },
47 { 0x000000af, 0x00000004 },
48 { 0x66544a49, 0000000000 },
49 { 0x49494174, 0000000000 },
50 { 0x54517d83, 0000000000 },
51 { 0x498d8b64, 0000000000 },
52 { 0x49494949, 0000000000 },
53 { 0x49da493c, 0000000000 },
54 { 0x49989898, 0000000000 },
55 { 0xd34949d5, 0000000000 },
56 { 0x9dc90e11, 0000000000 },
57 { 0xce9b9b9b, 0000000000 },
58 { 0x000f0000, 0x00000016 },
59 { 0x352e232c, 0000000000 },
60 { 0x00000013, 0x00000004 },
61 { 0x000f0000, 0x00000016 },
62 { 0x352e272c, 0000000000 },
63 { 0x000f0001, 0x00000016 },
64 { 0x3239362f, 0000000000 },
65 { 0x000077ef, 0x00000002 },
66 { 0x00061000, 0x00000002 },
67 { 0x00000020, 0x0000001a },
68 { 0x00004000, 0x0000001e },
69 { 0x00061000, 0x00000002 },
70 { 0x00000020, 0x0000001a },
71 { 0x00004000, 0x0000001e },
72 { 0x00061000, 0x00000002 },
73 { 0x00000020, 0x0000001a },
74 { 0x00004000, 0x0000001e },
75 { 0x00000016, 0x00000004 },
76 { 0x0003802a, 0x00000002 },
77 { 0x040067e0, 0x00000002 },
78 { 0x00000016, 0x00000004 },
79 { 0x000077e0, 0x00000002 },
80 { 0x00065000, 0x00000002 },
81 { 0x000037e1, 0x00000002 },
82 { 0x040067e1, 0x00000006 },
83 { 0x000077e0, 0x00000002 },
84 { 0x000077e1, 0x00000002 },
85 { 0x000077e1, 0x00000006 },
86 { 0xffffffff, 0000000000 },
87 { 0x10000000, 0000000000 },
88 { 0x0003802a, 0x00000002 },
89 { 0x040067e0, 0x00000006 },
90 { 0x00007675, 0x00000002 },
91 { 0x00007676, 0x00000002 },
92 { 0x00007677, 0x00000002 },
93 { 0x00007678, 0x00000006 },
94 { 0x0003802b, 0x00000002 },
95 { 0x04002676, 0x00000002 },
96 { 0x00007677, 0x00000002 },
97 { 0x00007678, 0x00000006 },
98 { 0x0000002e, 0x00000018 },
99 { 0x0000002e, 0x00000018 },
100 { 0000000000, 0x00000006 },
101 { 0x0000002f, 0x00000018 },
102 { 0x0000002f, 0x00000018 },
103 { 0000000000, 0x00000006 },
104 { 0x01605000, 0x00000002 },
105 { 0x00065000, 0x00000002 },
106 { 0x00098000, 0x00000002 },
107 { 0x00061000, 0x00000002 },
108 { 0x64c0603d, 0x00000004 },
109 { 0x00080000, 0x00000016 },
110 { 0000000000, 0000000000 },
111 { 0x0400251d, 0x00000002 },
112 { 0x00007580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x04002580, 0x00000002 },
115 { 0x00067581, 0x00000002 },
116 { 0x00000046, 0x00000004 },
117 { 0x00005000, 0000000000 },
118 { 0x00061000, 0x00000002 },
119 { 0x0000750e, 0x00000002 },
120 { 0x00019000, 0x00000002 },
121 { 0x00011055, 0x00000014 },
122 { 0x00000055, 0x00000012 },
123 { 0x0400250f, 0x00000002 },
124 { 0x0000504a, 0x00000004 },
125 { 0x00007565, 0x00000002 },
126 { 0x00007566, 0x00000002 },
127 { 0x00000051, 0x00000004 },
128 { 0x01e655b4, 0x00000002 },
129 { 0x4401b0dc, 0x00000002 },
130 { 0x01c110dc, 0x00000002 },
131 { 0x2666705d, 0x00000018 },
132 { 0x040c2565, 0x00000002 },
133 { 0x0000005d, 0x00000018 },
134 { 0x04002564, 0x00000002 },
135 { 0x00007566, 0x00000002 },
136 { 0x00000054, 0x00000004 },
137 { 0x00401060, 0x00000008 },
138 { 0x00101000, 0x00000002 },
139 { 0x000d80ff, 0x00000002 },
140 { 0x00800063, 0x00000008 },
141 { 0x000f9000, 0x00000002 },
142 { 0x000e00ff, 0x00000002 },
143 { 0000000000, 0x00000006 },
144 { 0x00000080, 0x00000018 },
145 { 0x00000054, 0x00000004 },
146 { 0x00007576, 0x00000002 },
147 { 0x00065000, 0x00000002 },
148 { 0x00009000, 0x00000002 },
149 { 0x00041000, 0x00000002 },
150 { 0x0c00350e, 0x00000002 },
151 { 0x00049000, 0x00000002 },
152 { 0x00051000, 0x00000002 },
153 { 0x01e785f8, 0x00000002 },
154 { 0x00200000, 0x00000002 },
155 { 0x00600073, 0x0000000c },
156 { 0x00007563, 0x00000002 },
157 { 0x006075f0, 0x00000021 },
158 { 0x20007068, 0x00000004 },
159 { 0x00005068, 0x00000004 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600076, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000076, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x0020750f, 0x00000002 },
171 { 0x00600079, 0x00000004 },
172 { 0x00007570, 0x00000002 },
173 { 0x00007571, 0x00000002 },
174 { 0x00007572, 0x00000006 },
175 { 0x00005000, 0x00000002 },
176 { 0x00a05000, 0x00000002 },
177 { 0x00007568, 0x00000002 },
178 { 0x00061000, 0x00000002 },
179 { 0x00000084, 0x0000000c },
180 { 0x00058000, 0x00000002 },
181 { 0x0c607562, 0x00000002 },
182 { 0x00000086, 0x00000004 },
183 { 0x00600085, 0x00000004 },
184 { 0x400070dd, 0000000000 },
185 { 0x000380dd, 0x00000002 },
186 { 0x00000093, 0x0000001c },
187 { 0x00065095, 0x00000018 },
188 { 0x040025bb, 0x00000002 },
189 { 0x00061096, 0x00000018 },
190 { 0x040075bc, 0000000000 },
191 { 0x000075bb, 0x00000002 },
192 { 0x000075bc, 0000000000 },
193 { 0x00090000, 0x00000006 },
194 { 0x00090000, 0x00000002 },
195 { 0x000d8002, 0x00000006 },
196 { 0x00005000, 0x00000002 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x00007821, 0x00000002 },
200 { 0x00007800, 0000000000 },
201 { 0x01665000, 0x00000002 },
202 { 0x000a0000, 0x00000002 },
203 { 0x000671cc, 0x00000002 },
204 { 0x0286f1cd, 0x00000002 },
205 { 0x000000a3, 0x00000010 },
206 { 0x21007000, 0000000000 },
207 { 0x000000aa, 0x0000001c },
208 { 0x00065000, 0x00000002 },
209 { 0x000a0000, 0x00000002 },
210 { 0x00061000, 0x00000002 },
211 { 0x000b0000, 0x00000002 },
212 { 0x38067000, 0x00000002 },
213 { 0x000a00a6, 0x00000004 },
214 { 0x20007000, 0000000000 },
215 { 0x01200000, 0x00000002 },
216 { 0x20077000, 0x00000002 },
217 { 0x01200000, 0x00000002 },
218 { 0x20007000, 0000000000 },
219 { 0x00061000, 0x00000002 },
220 { 0x0120751b, 0x00000002 },
221 { 0x8040750a, 0x00000002 },
222 { 0x8040750b, 0x00000002 },
223 { 0x00110000, 0x00000002 },
224 { 0x000380dd, 0x00000002 },
225 { 0x000000bd, 0x0000001c },
226 { 0x00061096, 0x00000018 },
227 { 0x844075bd, 0x00000002 },
228 { 0x00061095, 0x00000018 },
229 { 0x840075bb, 0x00000002 },
230 { 0x00061096, 0x00000018 },
231 { 0x844075bc, 0x00000002 },
232 { 0x000000c0, 0x00000004 },
233 { 0x804075bd, 0x00000002 },
234 { 0x800075bb, 0x00000002 },
235 { 0x804075bc, 0x00000002 },
236 { 0x00108000, 0x00000002 },
237 { 0x01400000, 0x00000002 },
238 { 0x006000c4, 0x0000000c },
239 { 0x20c07000, 0x00000020 },
240 { 0x000000c6, 0x00000012 },
241 { 0x00800000, 0x00000006 },
242 { 0x0080751d, 0x00000006 },
243 { 0x000025bb, 0x00000002 },
244 { 0x000040c0, 0x00000004 },
245 { 0x0000775c, 0x00000002 },
246 { 0x00a05000, 0x00000002 },
247 { 0x00661000, 0x00000002 },
248 { 0x0460275d, 0x00000020 },
249 { 0x00004000, 0000000000 },
250 { 0x00007999, 0x00000002 },
251 { 0x00a05000, 0x00000002 },
252 { 0x00661000, 0x00000002 },
253 { 0x0460299b, 0x00000020 },
254 { 0x00004000, 0000000000 },
255 { 0x01e00830, 0x00000002 },
256 { 0x21007000, 0000000000 },
257 { 0x00005000, 0x00000002 },
258 { 0x00038042, 0x00000002 },
259 { 0x040025e0, 0x00000002 },
260 { 0x000075e1, 0000000000 },
261 { 0x00000001, 0000000000 },
262 { 0x000380d9, 0x00000002 },
263 { 0x04007394, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 { 0000000000, 0000000000 },
300};
301
302
303static u32 radeon_cp_microcode[][2] = {
304 { 0x21007000, 0000000000 },
305 { 0x20007000, 0000000000 },
306 { 0x000000b4, 0x00000004 },
307 { 0x000000b8, 0x00000004 },
308 { 0x6f5b4d4c, 0000000000 },
309 { 0x4c4c427f, 0000000000 },
310 { 0x5b568a92, 0000000000 },
311 { 0x4ca09c6d, 0000000000 },
312 { 0xad4c4c4c, 0000000000 },
313 { 0x4ce1af3d, 0000000000 },
314 { 0xd8afafaf, 0000000000 },
315 { 0xd64c4cdc, 0000000000 },
316 { 0x4cd10d10, 0000000000 },
317 { 0x000f0000, 0x00000016 },
318 { 0x362f242d, 0000000000 },
319 { 0x00000012, 0x00000004 },
320 { 0x000f0000, 0x00000016 },
321 { 0x362f282d, 0000000000 },
322 { 0x000380e7, 0x00000002 },
323 { 0x04002c97, 0x00000002 },
324 { 0x000f0001, 0x00000016 },
325 { 0x333a3730, 0000000000 },
326 { 0x000077ef, 0x00000002 },
327 { 0x00061000, 0x00000002 },
328 { 0x00000021, 0x0000001a },
329 { 0x00004000, 0x0000001e },
330 { 0x00061000, 0x00000002 },
331 { 0x00000021, 0x0000001a },
332 { 0x00004000, 0x0000001e },
333 { 0x00061000, 0x00000002 },
334 { 0x00000021, 0x0000001a },
335 { 0x00004000, 0x0000001e },
336 { 0x00000017, 0x00000004 },
337 { 0x0003802b, 0x00000002 },
338 { 0x040067e0, 0x00000002 },
339 { 0x00000017, 0x00000004 },
340 { 0x000077e0, 0x00000002 },
341 { 0x00065000, 0x00000002 },
342 { 0x000037e1, 0x00000002 },
343 { 0x040067e1, 0x00000006 },
344 { 0x000077e0, 0x00000002 },
345 { 0x000077e1, 0x00000002 },
346 { 0x000077e1, 0x00000006 },
347 { 0xffffffff, 0000000000 },
348 { 0x10000000, 0000000000 },
349 { 0x0003802b, 0x00000002 },
350 { 0x040067e0, 0x00000006 },
351 { 0x00007675, 0x00000002 },
352 { 0x00007676, 0x00000002 },
353 { 0x00007677, 0x00000002 },
354 { 0x00007678, 0x00000006 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002676, 0x00000002 },
357 { 0x00007677, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0000002f, 0x00000018 },
360 { 0x0000002f, 0x00000018 },
361 { 0000000000, 0x00000006 },
362 { 0x00000030, 0x00000018 },
363 { 0x00000030, 0x00000018 },
364 { 0000000000, 0x00000006 },
365 { 0x01605000, 0x00000002 },
366 { 0x00065000, 0x00000002 },
367 { 0x00098000, 0x00000002 },
368 { 0x00061000, 0x00000002 },
369 { 0x64c0603e, 0x00000004 },
370 { 0x000380e6, 0x00000002 },
371 { 0x040025c5, 0x00000002 },
372 { 0x00080000, 0x00000016 },
373 { 0000000000, 0000000000 },
374 { 0x0400251d, 0x00000002 },
375 { 0x00007580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x04002580, 0x00000002 },
378 { 0x00067581, 0x00000002 },
379 { 0x00000049, 0x00000004 },
380 { 0x00005000, 0000000000 },
381 { 0x000380e6, 0x00000002 },
382 { 0x040025c5, 0x00000002 },
383 { 0x00061000, 0x00000002 },
384 { 0x0000750e, 0x00000002 },
385 { 0x00019000, 0x00000002 },
386 { 0x00011055, 0x00000014 },
387 { 0x00000055, 0x00000012 },
388 { 0x0400250f, 0x00000002 },
389 { 0x0000504f, 0x00000004 },
390 { 0x000380e6, 0x00000002 },
391 { 0x040025c5, 0x00000002 },
392 { 0x00007565, 0x00000002 },
393 { 0x00007566, 0x00000002 },
394 { 0x00000058, 0x00000004 },
395 { 0x000380e6, 0x00000002 },
396 { 0x040025c5, 0x00000002 },
397 { 0x01e655b4, 0x00000002 },
398 { 0x4401b0e4, 0x00000002 },
399 { 0x01c110e4, 0x00000002 },
400 { 0x26667066, 0x00000018 },
401 { 0x040c2565, 0x00000002 },
402 { 0x00000066, 0x00000018 },
403 { 0x04002564, 0x00000002 },
404 { 0x00007566, 0x00000002 },
405 { 0x0000005d, 0x00000004 },
406 { 0x00401069, 0x00000008 },
407 { 0x00101000, 0x00000002 },
408 { 0x000d80ff, 0x00000002 },
409 { 0x0080006c, 0x00000008 },
410 { 0x000f9000, 0x00000002 },
411 { 0x000e00ff, 0x00000002 },
412 { 0000000000, 0x00000006 },
413 { 0x0000008f, 0x00000018 },
414 { 0x0000005b, 0x00000004 },
415 { 0x000380e6, 0x00000002 },
416 { 0x040025c5, 0x00000002 },
417 { 0x00007576, 0x00000002 },
418 { 0x00065000, 0x00000002 },
419 { 0x00009000, 0x00000002 },
420 { 0x00041000, 0x00000002 },
421 { 0x0c00350e, 0x00000002 },
422 { 0x00049000, 0x00000002 },
423 { 0x00051000, 0x00000002 },
424 { 0x01e785f8, 0x00000002 },
425 { 0x00200000, 0x00000002 },
426 { 0x0060007e, 0x0000000c },
427 { 0x00007563, 0x00000002 },
428 { 0x006075f0, 0x00000021 },
429 { 0x20007073, 0x00000004 },
430 { 0x00005073, 0x00000004 },
431 { 0x000380e6, 0x00000002 },
432 { 0x040025c5, 0x00000002 },
433 { 0x00007576, 0x00000002 },
434 { 0x00007577, 0x00000002 },
435 { 0x0000750e, 0x00000002 },
436 { 0x0000750f, 0x00000002 },
437 { 0x00a05000, 0x00000002 },
438 { 0x00600083, 0x0000000c },
439 { 0x006075f0, 0x00000021 },
440 { 0x000075f8, 0x00000002 },
441 { 0x00000083, 0x00000004 },
442 { 0x000a750e, 0x00000002 },
443 { 0x000380e6, 0x00000002 },
444 { 0x040025c5, 0x00000002 },
445 { 0x0020750f, 0x00000002 },
446 { 0x00600086, 0x00000004 },
447 { 0x00007570, 0x00000002 },
448 { 0x00007571, 0x00000002 },
449 { 0x00007572, 0x00000006 },
450 { 0x000380e6, 0x00000002 },
451 { 0x040025c5, 0x00000002 },
452 { 0x00005000, 0x00000002 },
453 { 0x00a05000, 0x00000002 },
454 { 0x00007568, 0x00000002 },
455 { 0x00061000, 0x00000002 },
456 { 0x00000095, 0x0000000c },
457 { 0x00058000, 0x00000002 },
458 { 0x0c607562, 0x00000002 },
459 { 0x00000097, 0x00000004 },
460 { 0x000380e6, 0x00000002 },
461 { 0x040025c5, 0x00000002 },
462 { 0x00600096, 0x00000004 },
463 { 0x400070e5, 0000000000 },
464 { 0x000380e6, 0x00000002 },
465 { 0x040025c5, 0x00000002 },
466 { 0x000380e5, 0x00000002 },
467 { 0x000000a8, 0x0000001c },
468 { 0x000650aa, 0x00000018 },
469 { 0x040025bb, 0x00000002 },
470 { 0x000610ab, 0x00000018 },
471 { 0x040075bc, 0000000000 },
472 { 0x000075bb, 0x00000002 },
473 { 0x000075bc, 0000000000 },
474 { 0x00090000, 0x00000006 },
475 { 0x00090000, 0x00000002 },
476 { 0x000d8002, 0x00000006 },
477 { 0x00007832, 0x00000002 },
478 { 0x00005000, 0x00000002 },
479 { 0x000380e7, 0x00000002 },
480 { 0x04002c97, 0x00000002 },
481 { 0x00007820, 0x00000002 },
482 { 0x00007821, 0x00000002 },
483 { 0x00007800, 0000000000 },
484 { 0x01200000, 0x00000002 },
485 { 0x20077000, 0x00000002 },
486 { 0x01200000, 0x00000002 },
487 { 0x20007000, 0x00000002 },
488 { 0x00061000, 0x00000002 },
489 { 0x0120751b, 0x00000002 },
490 { 0x8040750a, 0x00000002 },
491 { 0x8040750b, 0x00000002 },
492 { 0x00110000, 0x00000002 },
493 { 0x000380e5, 0x00000002 },
494 { 0x000000c6, 0x0000001c },
495 { 0x000610ab, 0x00000018 },
496 { 0x844075bd, 0x00000002 },
497 { 0x000610aa, 0x00000018 },
498 { 0x840075bb, 0x00000002 },
499 { 0x000610ab, 0x00000018 },
500 { 0x844075bc, 0x00000002 },
501 { 0x000000c9, 0x00000004 },
502 { 0x804075bd, 0x00000002 },
503 { 0x800075bb, 0x00000002 },
504 { 0x804075bc, 0x00000002 },
505 { 0x00108000, 0x00000002 },
506 { 0x01400000, 0x00000002 },
507 { 0x006000cd, 0x0000000c },
508 { 0x20c07000, 0x00000020 },
509 { 0x000000cf, 0x00000012 },
510 { 0x00800000, 0x00000006 },
511 { 0x0080751d, 0x00000006 },
512 { 0000000000, 0000000000 },
513 { 0x0000775c, 0x00000002 },
514 { 0x00a05000, 0x00000002 },
515 { 0x00661000, 0x00000002 },
516 { 0x0460275d, 0x00000020 },
517 { 0x00004000, 0000000000 },
518 { 0x01e00830, 0x00000002 },
519 { 0x21007000, 0000000000 },
520 { 0x6464614d, 0000000000 },
521 { 0x69687420, 0000000000 },
522 { 0x00000073, 0000000000 },
523 { 0000000000, 0000000000 },
524 { 0x00005000, 0x00000002 },
525 { 0x000380d0, 0x00000002 },
526 { 0x040025e0, 0x00000002 },
527 { 0x000075e1, 0000000000 },
528 { 0x00000001, 0000000000 },
529 { 0x000380e0, 0x00000002 },
530 { 0x04002394, 0x00000002 },
531 { 0x00005000, 0000000000 },
532 { 0000000000, 0000000000 },
533 { 0000000000, 0000000000 },
534 { 0x00000008, 0000000000 },
535 { 0x00000004, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 { 0000000000, 0000000000 },
560};
561
562
563int RADEON_READ_PLL(drm_device_t *dev, int addr)
564{
565 drm_radeon_private_t *dev_priv = dev->dev_private;
566
567 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
568 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
569}
570
571#if RADEON_FIFO_DEBUG
572static void radeon_status( drm_radeon_private_t *dev_priv )
573{
574 printk( "%s:\n", __FUNCTION__ );
575 printk( "RBBM_STATUS = 0x%08x\n",
576 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
577 printk( "CP_RB_RTPR = 0x%08x\n",
578 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
579 printk( "CP_RB_WTPR = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
581 printk( "AIC_CNTL = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
583 printk( "AIC_STAT = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
585 printk( "AIC_PT_BASE = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
587 printk( "TLB_ADDR = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
589 printk( "TLB_DATA = 0x%08x\n",
590 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
591}
592#endif
593
594
595/* ================================================================
596 * Engine, FIFO control
597 */
598
599static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
600{
601 u32 tmp;
602 int i;
603
604 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
605
606 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
607 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
608 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
609
610 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
611 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
612 & RADEON_RB2D_DC_BUSY) ) {
613 return 0;
614 }
615 DRM_UDELAY( 1 );
616 }
617
618#if RADEON_FIFO_DEBUG
619 DRM_ERROR( "failed!\n" );
620 radeon_status( dev_priv );
621#endif
622 return DRM_ERR(EBUSY);
623}
624
625static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
626 int entries )
627{
628 int i;
629
630 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
631
632 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
633 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
634 & RADEON_RBBM_FIFOCNT_MASK );
635 if ( slots >= entries ) return 0;
636 DRM_UDELAY( 1 );
637 }
638
639#if RADEON_FIFO_DEBUG
640 DRM_ERROR( "failed!\n" );
641 radeon_status( dev_priv );
642#endif
643 return DRM_ERR(EBUSY);
644}
645
646static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
647{
648 int i, ret;
649
650 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
651
652 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
653 if ( ret ) return ret;
654
655 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
656 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
657 & RADEON_RBBM_ACTIVE) ) {
658 radeon_do_pixcache_flush( dev_priv );
659 return 0;
660 }
661 DRM_UDELAY( 1 );
662 }
663
664#if RADEON_FIFO_DEBUG
665 DRM_ERROR( "failed!\n" );
666 radeon_status( dev_priv );
667#endif
668 return DRM_ERR(EBUSY);
669}
670
671
672/* ================================================================
673 * CP control, initialization
674 */
675
676/* Load the microcode for the CP */
677static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
678{
679 int i;
680 DRM_DEBUG( "\n" );
681
682 radeon_do_wait_for_idle( dev_priv );
683
684 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
685
686 if (dev_priv->is_r200)
687 {
688 DRM_INFO("Loading R200 Microcode\n");
689 for ( i = 0 ; i < 256 ; i++ )
690 {
691 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
692 R200_cp_microcode[i][1] );
693 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
694 R200_cp_microcode[i][0] );
695 }
696 }
697 else
698 {
699 for ( i = 0 ; i < 256 ; i++ ) {
700 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
701 radeon_cp_microcode[i][1] );
702 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
703 radeon_cp_microcode[i][0] );
704 }
705 }
706}
707
708/* Flush any pending commands to the CP. This should only be used just
709 * prior to a wait for idle, as it informs the engine that the command
710 * stream is ending.
711 */
712static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
713{
714 DRM_DEBUG( "\n" );
715#if 0
716 u32 tmp;
717
718 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
719 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
720#endif
721}
722
723/* Wait for the CP to go idle.
724 */
725int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
726{
727 RING_LOCALS;
728 DRM_DEBUG( "\n" );
729
730 BEGIN_RING( 6 );
731
732 RADEON_PURGE_CACHE();
733 RADEON_PURGE_ZCACHE();
734 RADEON_WAIT_UNTIL_IDLE();
735
736 ADVANCE_RING();
737 COMMIT_RING();
738
739 return radeon_do_wait_for_idle( dev_priv );
740}
741
742/* Start the Command Processor.
743 */
744static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
745{
746 RING_LOCALS;
747 DRM_DEBUG( "\n" );
748
749 radeon_do_wait_for_idle( dev_priv );
750
751 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
752
753 dev_priv->cp_running = 1;
754
755 BEGIN_RING( 6 );
756
757 RADEON_PURGE_CACHE();
758 RADEON_PURGE_ZCACHE();
759 RADEON_WAIT_UNTIL_IDLE();
760
761 ADVANCE_RING();
762 COMMIT_RING();
763}
764
765/* Reset the Command Processor. This will not flush any pending
766 * commands, so you must wait for the CP command stream to complete
767 * before calling this routine.
768 */
769static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
770{
771 u32 cur_read_ptr;
772 DRM_DEBUG( "\n" );
773
774 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
775 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
776 SET_RING_HEAD( dev_priv, cur_read_ptr );
777 dev_priv->ring.tail = cur_read_ptr;
778}
779
780/* Stop the Command Processor. This will not flush any pending
781 * commands, so you must flush the command stream and wait for the CP
782 * to go idle before calling this routine.
783 */
784static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
785{
786 DRM_DEBUG( "\n" );
787
788 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
789
790 dev_priv->cp_running = 0;
791}
792
793/* Reset the engine. This will stop the CP if it is running.
794 */
795static int radeon_do_engine_reset( drm_device_t *dev )
796{
797 drm_radeon_private_t *dev_priv = dev->dev_private;
798 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
799 DRM_DEBUG( "\n" );
800
801 radeon_do_pixcache_flush( dev_priv );
802
803 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
804 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
805
806 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
807 RADEON_FORCEON_MCLKA |
808 RADEON_FORCEON_MCLKB |
809 RADEON_FORCEON_YCLKA |
810 RADEON_FORCEON_YCLKB |
811 RADEON_FORCEON_MC |
812 RADEON_FORCEON_AIC ) );
813
814 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
815
816 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
817 RADEON_SOFT_RESET_CP |
818 RADEON_SOFT_RESET_HI |
819 RADEON_SOFT_RESET_SE |
820 RADEON_SOFT_RESET_RE |
821 RADEON_SOFT_RESET_PP |
822 RADEON_SOFT_RESET_E2 |
823 RADEON_SOFT_RESET_RB ) );
824 RADEON_READ( RADEON_RBBM_SOFT_RESET );
825 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
826 ~( RADEON_SOFT_RESET_CP |
827 RADEON_SOFT_RESET_HI |
828 RADEON_SOFT_RESET_SE |
829 RADEON_SOFT_RESET_RE |
830 RADEON_SOFT_RESET_PP |
831 RADEON_SOFT_RESET_E2 |
832 RADEON_SOFT_RESET_RB ) ) );
833 RADEON_READ( RADEON_RBBM_SOFT_RESET );
834
835
836 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
837 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
838 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
839
840 /* Reset the CP ring */
841 radeon_do_cp_reset( dev_priv );
842
843 /* The CP is no longer running after an engine reset */
844 dev_priv->cp_running = 0;
845
846 /* Reset any pending vertex, indirect buffers */
847 radeon_freelist_reset( dev );
848
849 return 0;
850}
851
852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
860 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
860 (dev_priv->gart_vm_start - 1) & 0xffff0000 );
861
861
862#if __REALLY_HAVE_AGP
862 if ( !dev_priv->is_pci ) {
863 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
863 if ( !dev_priv->is_pci ) {
864 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
864 (((dev_priv->agp_vm_start - 1 +
865 dev_priv->agp_size) & 0xffff0000) |
866 (dev_priv->agp_vm_start >> 16)) );
867 }
865 (((dev_priv->gart_vm_start - 1 +
866 dev_priv->gart_size) & 0xffff0000) |
867 (dev_priv->gart_vm_start >> 16)) );
868
868
869#if __REALLY_HAVE_AGP
870 if ( !dev_priv->is_pci )
871 ring_start = (dev_priv->cp_ring->offset
872 - dev->agp->base
869 ring_start = (dev_priv->cp_ring->offset
870 - dev->agp->base
873 + dev_priv->agp_vm_start);
874 else
871 + dev_priv->gart_vm_start);
872 } else
875#endif
876 ring_start = (dev_priv->cp_ring->offset
877 - dev->sg->handle
873#endif
874 ring_start = (dev_priv->cp_ring->offset
875 - dev->sg->handle
878 + dev_priv->agp_vm_start);
876 + dev_priv->gart_vm_start);
879
880 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
881
882 /* Set the write pointer delay */
883 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
884
885 /* Initialize the ring buffer's read and write pointers */
886 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
887 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
888 SET_RING_HEAD( dev_priv, cur_read_ptr );
889 dev_priv->ring.tail = cur_read_ptr;
890
891#if __REALLY_HAVE_AGP
892 if ( !dev_priv->is_pci ) {
893 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
894 dev_priv->ring_rptr->offset
895 - dev->agp->base
877
878 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
879
880 /* Set the write pointer delay */
881 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
882
883 /* Initialize the ring buffer's read and write pointers */
884 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
885 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
886 SET_RING_HEAD( dev_priv, cur_read_ptr );
887 dev_priv->ring.tail = cur_read_ptr;
888
889#if __REALLY_HAVE_AGP
890 if ( !dev_priv->is_pci ) {
891 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
892 dev_priv->ring_rptr->offset
893 - dev->agp->base
896 + dev_priv->agp_vm_start);
894 + dev_priv->gart_vm_start);
897 } else
898#endif
899 {
900 drm_sg_mem_t *entry = dev->sg;
901 unsigned long tmp_ofs, page_ofs;
902
903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
904 page_ofs = tmp_ofs >> PAGE_SHIFT;
905
906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
907 entry->busaddr[page_ofs]);
908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
909 (unsigned long) entry->busaddr[page_ofs],
910 entry->handle + tmp_ofs );
911 }
912
913 /* Initialize the scratch register pointer. This will cause
914 * the scratch register values to be written out to memory
915 * whenever they are updated.
916 *
917 * We simply put this behind the ring read pointer, this works
918 * with PCI GART as well as (whatever kind of) AGP GART
919 */
920 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
921 + RADEON_SCRATCH_REG_OFFSET );
922
923 dev_priv->scratch = ((__volatile__ u32 *)
924 dev_priv->ring_rptr->handle +
925 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
926
927 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
928
929 /* Writeback doesn't seem to work everywhere, test it first */
930 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
931 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
932
933 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
934 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
935 break;
936 DRM_UDELAY( 1 );
937 }
938
939 if ( tmp < dev_priv->usec_timeout ) {
940 dev_priv->writeback_works = 1;
941 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
942 } else {
943 dev_priv->writeback_works = 0;
944 DRM_DEBUG( "writeback test failed\n" );
945 }
946
947 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
948 RADEON_WRITE( RADEON_LAST_FRAME_REG,
949 dev_priv->sarea_priv->last_frame );
950
951 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
952 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
953 dev_priv->sarea_priv->last_dispatch );
954
955 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
956 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
957 dev_priv->sarea_priv->last_clear );
958
959 /* Set ring buffer size */
960#ifdef __BIG_ENDIAN
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
962#else
963 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
964#endif
965
966 radeon_do_wait_for_idle( dev_priv );
967
968 /* Turn on bus mastering */
969 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
970 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
971
972 /* Sync everything up */
973 RADEON_WRITE( RADEON_ISYNC_CNTL,
974 (RADEON_ISYNC_ANY2D_IDLE3D |
975 RADEON_ISYNC_ANY3D_IDLE2D |
976 RADEON_ISYNC_WAIT_IDLEGUI |
977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978}
979
980/* Enable or disable PCI GART on the chip */
981static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
982{
983 u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
984
985 if ( on ) {
986 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
987
988 /* set PCI GART page-table base address
989 */
990 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
991
992 /* set address range for PCI address translate
993 */
895 } else
896#endif
897 {
898 drm_sg_mem_t *entry = dev->sg;
899 unsigned long tmp_ofs, page_ofs;
900
901 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
902 page_ofs = tmp_ofs >> PAGE_SHIFT;
903
904 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
905 entry->busaddr[page_ofs]);
906 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
907 (unsigned long) entry->busaddr[page_ofs],
908 entry->handle + tmp_ofs );
909 }
910
911 /* Initialize the scratch register pointer. This will cause
912 * the scratch register values to be written out to memory
913 * whenever they are updated.
914 *
915 * We simply put this behind the ring read pointer, this works
916 * with PCI GART as well as (whatever kind of) AGP GART
917 */
918 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
919 + RADEON_SCRATCH_REG_OFFSET );
920
921 dev_priv->scratch = ((__volatile__ u32 *)
922 dev_priv->ring_rptr->handle +
923 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
924
925 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
926
927 /* Writeback doesn't seem to work everywhere, test it first */
928 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
929 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
930
931 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
932 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
933 break;
934 DRM_UDELAY( 1 );
935 }
936
937 if ( tmp < dev_priv->usec_timeout ) {
938 dev_priv->writeback_works = 1;
939 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
940 } else {
941 dev_priv->writeback_works = 0;
942 DRM_DEBUG( "writeback test failed\n" );
943 }
944
945 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
946 RADEON_WRITE( RADEON_LAST_FRAME_REG,
947 dev_priv->sarea_priv->last_frame );
948
949 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
950 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
951 dev_priv->sarea_priv->last_dispatch );
952
953 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
954 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
955 dev_priv->sarea_priv->last_clear );
956
957 /* Set ring buffer size */
958#ifdef __BIG_ENDIAN
959 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
960#else
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
962#endif
963
964 radeon_do_wait_for_idle( dev_priv );
965
966 /* Turn on bus mastering */
967 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
968 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
969
970 /* Sync everything up */
971 RADEON_WRITE( RADEON_ISYNC_CNTL,
972 (RADEON_ISYNC_ANY2D_IDLE3D |
973 RADEON_ISYNC_ANY3D_IDLE2D |
974 RADEON_ISYNC_WAIT_IDLEGUI |
975 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
976}
977
978/* Enable or disable PCI GART on the chip */
979static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
980{
981 u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
982
983 if ( on ) {
984 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
985
986 /* set PCI GART page-table base address
987 */
988 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
989
990 /* set address range for PCI address translate
991 */
994 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
995 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
996 + dev_priv->agp_size - 1);
992 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
993 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
994 + dev_priv->gart_size - 1);
997
995
998 /* Turn off AGP aperture -- is this required for PCIGART?
996 /* Turn off AGP aperture -- is this required for PCI GART?
999 */
1000 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1001 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1002 } else {
1003 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1004 }
1005}
1006
1007static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1008{
1009 drm_radeon_private_t *dev_priv;
1010 DRM_DEBUG( "\n" );
1011
1012 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
1013 if ( dev_priv == NULL )
1014 return DRM_ERR(ENOMEM);
1015
1016 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
1017
1018 dev_priv->is_pci = init->is_pci;
1019
1020 if ( dev_priv->is_pci && !dev->sg ) {
1021 DRM_ERROR( "PCI GART memory not allocated!\n" );
1022 dev->dev_private = (void *)dev_priv;
1023 radeon_do_cleanup_cp(dev);
1024 return DRM_ERR(EINVAL);
1025 }
1026
1027 dev_priv->usec_timeout = init->usec_timeout;
1028 if ( dev_priv->usec_timeout < 1 ||
1029 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1030 DRM_DEBUG( "TIMEOUT problem!\n" );
1031 dev->dev_private = (void *)dev_priv;
1032 radeon_do_cleanup_cp(dev);
1033 return DRM_ERR(EINVAL);
1034 }
1035
1036 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1037 dev_priv->do_boxes = 0;
1038 dev_priv->cp_mode = init->cp_mode;
1039
1040 /* We don't support anything other than bus-mastering ring mode,
1041 * but the ring can be in either AGP or PCI space for the ring
1042 * read pointer.
1043 */
1044 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1045 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1046 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1047 dev->dev_private = (void *)dev_priv;
1048 radeon_do_cleanup_cp(dev);
1049 return DRM_ERR(EINVAL);
1050 }
1051
1052 switch ( init->fb_bpp ) {
1053 case 16:
1054 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1055 break;
1056 case 32:
1057 default:
1058 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1059 break;
1060 }
1061 dev_priv->front_offset = init->front_offset;
1062 dev_priv->front_pitch = init->front_pitch;
1063 dev_priv->back_offset = init->back_offset;
1064 dev_priv->back_pitch = init->back_pitch;
1065
1066 switch ( init->depth_bpp ) {
1067 case 16:
1068 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1069 break;
1070 case 32:
1071 default:
1072 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1073 break;
1074 }
1075 dev_priv->depth_offset = init->depth_offset;
1076 dev_priv->depth_pitch = init->depth_pitch;
1077
1078 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1079 (dev_priv->front_offset >> 10));
1080 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1081 (dev_priv->back_offset >> 10));
1082 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1083 (dev_priv->depth_offset >> 10));
1084
1085 /* Hardware state for depth clears. Remove this if/when we no
1086 * longer clear the depth buffer with a 3D rectangle. Hard-code
1087 * all values to prevent unwanted 3D state from slipping through
1088 * and screwing with the clear operation.
1089 */
1090 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1091 (dev_priv->color_fmt << 10) |
1092 (1<<15));
1093
1094 dev_priv->depth_clear.rb3d_zstencilcntl =
1095 (dev_priv->depth_fmt |
1096 RADEON_Z_TEST_ALWAYS |
1097 RADEON_STENCIL_TEST_ALWAYS |
1098 RADEON_STENCIL_S_FAIL_REPLACE |
1099 RADEON_STENCIL_ZPASS_REPLACE |
1100 RADEON_STENCIL_ZFAIL_REPLACE |
1101 RADEON_Z_WRITE_ENABLE);
1102
1103 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1104 RADEON_BFACE_SOLID |
1105 RADEON_FFACE_SOLID |
1106 RADEON_FLAT_SHADE_VTX_LAST |
1107 RADEON_DIFFUSE_SHADE_FLAT |
1108 RADEON_ALPHA_SHADE_FLAT |
1109 RADEON_SPECULAR_SHADE_FLAT |
1110 RADEON_FOG_SHADE_FLAT |
1111 RADEON_VTX_PIX_CENTER_OGL |
1112 RADEON_ROUND_MODE_TRUNC |
1113 RADEON_ROUND_PREC_8TH_PIX);
1114
1115 DRM_GETSAREA();
1116
1117 dev_priv->fb_offset = init->fb_offset;
1118 dev_priv->mmio_offset = init->mmio_offset;
1119 dev_priv->ring_offset = init->ring_offset;
1120 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1121 dev_priv->buffers_offset = init->buffers_offset;
997 */
998 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
999 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1000 } else {
1001 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1002 }
1003}
1004
1005static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1006{
1007 drm_radeon_private_t *dev_priv;
1008 DRM_DEBUG( "\n" );
1009
1010 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
1011 if ( dev_priv == NULL )
1012 return DRM_ERR(ENOMEM);
1013
1014 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
1015
1016 dev_priv->is_pci = init->is_pci;
1017
1018 if ( dev_priv->is_pci && !dev->sg ) {
1019 DRM_ERROR( "PCI GART memory not allocated!\n" );
1020 dev->dev_private = (void *)dev_priv;
1021 radeon_do_cleanup_cp(dev);
1022 return DRM_ERR(EINVAL);
1023 }
1024
1025 dev_priv->usec_timeout = init->usec_timeout;
1026 if ( dev_priv->usec_timeout < 1 ||
1027 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1028 DRM_DEBUG( "TIMEOUT problem!\n" );
1029 dev->dev_private = (void *)dev_priv;
1030 radeon_do_cleanup_cp(dev);
1031 return DRM_ERR(EINVAL);
1032 }
1033
1034 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1035 dev_priv->do_boxes = 0;
1036 dev_priv->cp_mode = init->cp_mode;
1037
1038 /* We don't support anything other than bus-mastering ring mode,
1039 * but the ring can be in either AGP or PCI space for the ring
1040 * read pointer.
1041 */
1042 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1043 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1044 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1045 dev->dev_private = (void *)dev_priv;
1046 radeon_do_cleanup_cp(dev);
1047 return DRM_ERR(EINVAL);
1048 }
1049
1050 switch ( init->fb_bpp ) {
1051 case 16:
1052 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1053 break;
1054 case 32:
1055 default:
1056 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1057 break;
1058 }
1059 dev_priv->front_offset = init->front_offset;
1060 dev_priv->front_pitch = init->front_pitch;
1061 dev_priv->back_offset = init->back_offset;
1062 dev_priv->back_pitch = init->back_pitch;
1063
1064 switch ( init->depth_bpp ) {
1065 case 16:
1066 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1067 break;
1068 case 32:
1069 default:
1070 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1071 break;
1072 }
1073 dev_priv->depth_offset = init->depth_offset;
1074 dev_priv->depth_pitch = init->depth_pitch;
1075
1076 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1077 (dev_priv->front_offset >> 10));
1078 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1079 (dev_priv->back_offset >> 10));
1080 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1081 (dev_priv->depth_offset >> 10));
1082
1083 /* Hardware state for depth clears. Remove this if/when we no
1084 * longer clear the depth buffer with a 3D rectangle. Hard-code
1085 * all values to prevent unwanted 3D state from slipping through
1086 * and screwing with the clear operation.
1087 */
1088 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1089 (dev_priv->color_fmt << 10) |
1090 (1<<15));
1091
1092 dev_priv->depth_clear.rb3d_zstencilcntl =
1093 (dev_priv->depth_fmt |
1094 RADEON_Z_TEST_ALWAYS |
1095 RADEON_STENCIL_TEST_ALWAYS |
1096 RADEON_STENCIL_S_FAIL_REPLACE |
1097 RADEON_STENCIL_ZPASS_REPLACE |
1098 RADEON_STENCIL_ZFAIL_REPLACE |
1099 RADEON_Z_WRITE_ENABLE);
1100
1101 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1102 RADEON_BFACE_SOLID |
1103 RADEON_FFACE_SOLID |
1104 RADEON_FLAT_SHADE_VTX_LAST |
1105 RADEON_DIFFUSE_SHADE_FLAT |
1106 RADEON_ALPHA_SHADE_FLAT |
1107 RADEON_SPECULAR_SHADE_FLAT |
1108 RADEON_FOG_SHADE_FLAT |
1109 RADEON_VTX_PIX_CENTER_OGL |
1110 RADEON_ROUND_MODE_TRUNC |
1111 RADEON_ROUND_PREC_8TH_PIX);
1112
1113 DRM_GETSAREA();
1114
1115 dev_priv->fb_offset = init->fb_offset;
1116 dev_priv->mmio_offset = init->mmio_offset;
1117 dev_priv->ring_offset = init->ring_offset;
1118 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1119 dev_priv->buffers_offset = init->buffers_offset;
1122 dev_priv->agp_textures_offset = init->agp_textures_offset;
1120 dev_priv->gart_textures_offset = init->gart_textures_offset;
1123
1124 if(!dev_priv->sarea) {
1125 DRM_ERROR("could not find sarea!\n");
1126 dev->dev_private = (void *)dev_priv;
1127 radeon_do_cleanup_cp(dev);
1128 return DRM_ERR(EINVAL);
1129 }
1130
1131 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1132 if(!dev_priv->fb) {
1133 DRM_ERROR("could not find framebuffer!\n");
1134 dev->dev_private = (void *)dev_priv;
1135 radeon_do_cleanup_cp(dev);
1136 return DRM_ERR(EINVAL);
1137 }
1138 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1139 if(!dev_priv->mmio) {
1140 DRM_ERROR("could not find mmio region!\n");
1141 dev->dev_private = (void *)dev_priv;
1142 radeon_do_cleanup_cp(dev);
1143 return DRM_ERR(EINVAL);
1144 }
1145 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1146 if(!dev_priv->cp_ring) {
1147 DRM_ERROR("could not find cp ring region!\n");
1148 dev->dev_private = (void *)dev_priv;
1149 radeon_do_cleanup_cp(dev);
1150 return DRM_ERR(EINVAL);
1151 }
1152 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1153 if(!dev_priv->ring_rptr) {
1154 DRM_ERROR("could not find ring read pointer!\n");
1155 dev->dev_private = (void *)dev_priv;
1156 radeon_do_cleanup_cp(dev);
1157 return DRM_ERR(EINVAL);
1158 }
1159 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1160 if(!dev_priv->buffers) {
1161 DRM_ERROR("could not find dma buffer region!\n");
1162 dev->dev_private = (void *)dev_priv;
1163 radeon_do_cleanup_cp(dev);
1164 return DRM_ERR(EINVAL);
1165 }
1166
1121
1122 if(!dev_priv->sarea) {
1123 DRM_ERROR("could not find sarea!\n");
1124 dev->dev_private = (void *)dev_priv;
1125 radeon_do_cleanup_cp(dev);
1126 return DRM_ERR(EINVAL);
1127 }
1128
1129 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1130 if(!dev_priv->fb) {
1131 DRM_ERROR("could not find framebuffer!\n");
1132 dev->dev_private = (void *)dev_priv;
1133 radeon_do_cleanup_cp(dev);
1134 return DRM_ERR(EINVAL);
1135 }
1136 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1137 if(!dev_priv->mmio) {
1138 DRM_ERROR("could not find mmio region!\n");
1139 dev->dev_private = (void *)dev_priv;
1140 radeon_do_cleanup_cp(dev);
1141 return DRM_ERR(EINVAL);
1142 }
1143 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1144 if(!dev_priv->cp_ring) {
1145 DRM_ERROR("could not find cp ring region!\n");
1146 dev->dev_private = (void *)dev_priv;
1147 radeon_do_cleanup_cp(dev);
1148 return DRM_ERR(EINVAL);
1149 }
1150 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1151 if(!dev_priv->ring_rptr) {
1152 DRM_ERROR("could not find ring read pointer!\n");
1153 dev->dev_private = (void *)dev_priv;
1154 radeon_do_cleanup_cp(dev);
1155 return DRM_ERR(EINVAL);
1156 }
1157 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1158 if(!dev_priv->buffers) {
1159 DRM_ERROR("could not find dma buffer region!\n");
1160 dev->dev_private = (void *)dev_priv;
1161 radeon_do_cleanup_cp(dev);
1162 return DRM_ERR(EINVAL);
1163 }
1164
1167 if ( !dev_priv->is_pci ) {
1168 DRM_FIND_MAP( dev_priv->agp_textures,
1169 init->agp_textures_offset );
1170 if(!dev_priv->agp_textures) {
1171 DRM_ERROR("could not find agp texture region!\n");
1165 if ( init->gart_textures_offset ) {
1166 DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
1167 if ( !dev_priv->gart_textures ) {
1168 DRM_ERROR("could not find GART texture region!\n");
1172 dev->dev_private = (void *)dev_priv;
1173 radeon_do_cleanup_cp(dev);
1174 return DRM_ERR(EINVAL);
1175 }
1176 }
1177
1178 dev_priv->sarea_priv =
1179 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1180 init->sarea_priv_offset);
1181
1182#if __REALLY_HAVE_AGP
1183 if ( !dev_priv->is_pci ) {
1184 DRM_IOREMAP( dev_priv->cp_ring, dev );
1185 DRM_IOREMAP( dev_priv->ring_rptr, dev );
1186 DRM_IOREMAP( dev_priv->buffers, dev );
1187 if(!dev_priv->cp_ring->handle ||
1188 !dev_priv->ring_rptr->handle ||
1189 !dev_priv->buffers->handle) {
1190 DRM_ERROR("could not find ioremap agp regions!\n");
1191 dev->dev_private = (void *)dev_priv;
1192 radeon_do_cleanup_cp(dev);
1193 return DRM_ERR(EINVAL);
1194 }
1195 } else
1196#endif
1197 {
1198 dev_priv->cp_ring->handle =
1199 (void *)dev_priv->cp_ring->offset;
1200 dev_priv->ring_rptr->handle =
1201 (void *)dev_priv->ring_rptr->offset;
1202 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1203
1204 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1205 dev_priv->cp_ring->handle );
1206 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1207 dev_priv->ring_rptr->handle );
1208 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1209 dev_priv->buffers->handle );
1210 }
1211
1212
1169 dev->dev_private = (void *)dev_priv;
1170 radeon_do_cleanup_cp(dev);
1171 return DRM_ERR(EINVAL);
1172 }
1173 }
1174
1175 dev_priv->sarea_priv =
1176 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1177 init->sarea_priv_offset);
1178
1179#if __REALLY_HAVE_AGP
1180 if ( !dev_priv->is_pci ) {
1181 DRM_IOREMAP( dev_priv->cp_ring, dev );
1182 DRM_IOREMAP( dev_priv->ring_rptr, dev );
1183 DRM_IOREMAP( dev_priv->buffers, dev );
1184 if(!dev_priv->cp_ring->handle ||
1185 !dev_priv->ring_rptr->handle ||
1186 !dev_priv->buffers->handle) {
1187 DRM_ERROR("could not find ioremap agp regions!\n");
1188 dev->dev_private = (void *)dev_priv;
1189 radeon_do_cleanup_cp(dev);
1190 return DRM_ERR(EINVAL);
1191 }
1192 } else
1193#endif
1194 {
1195 dev_priv->cp_ring->handle =
1196 (void *)dev_priv->cp_ring->offset;
1197 dev_priv->ring_rptr->handle =
1198 (void *)dev_priv->ring_rptr->offset;
1199 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1200
1201 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1202 dev_priv->cp_ring->handle );
1203 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1204 dev_priv->ring_rptr->handle );
1205 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1206 dev_priv->buffers->handle );
1207 }
1208
1209
1213 dev_priv->agp_size = init->agp_size;
1214 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1210 dev_priv->gart_size = init->gart_size;
1211 dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1215#if __REALLY_HAVE_AGP
1216 if ( !dev_priv->is_pci )
1212#if __REALLY_HAVE_AGP
1213 if ( !dev_priv->is_pci )
1217 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1214 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1218 - dev->agp->base
1215 - dev->agp->base
1219 + dev_priv->agp_vm_start);
1216 + dev_priv->gart_vm_start);
1220 else
1221#endif
1217 else
1218#endif
1222 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1219 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1223 - dev->sg->handle
1220 - dev->sg->handle
1224 + dev_priv->agp_vm_start);
1221 + dev_priv->gart_vm_start);
1225
1222
1226 DRM_DEBUG( "dev_priv->agp_size %d\n",
1227 dev_priv->agp_size );
1228 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1229 dev_priv->agp_vm_start );
1230 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1231 dev_priv->agp_buffers_offset );
1223 DRM_DEBUG( "dev_priv->gart_size %d\n",
1224 dev_priv->gart_size );
1225 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1226 dev_priv->gart_vm_start );
1227 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1228 dev_priv->gart_buffers_offset );
1232
1233 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1234 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1235 + init->ring_size / sizeof(u32));
1236 dev_priv->ring.size = init->ring_size;
1237 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1238
1239 dev_priv->ring.tail_mask =
1240 (dev_priv->ring.size / sizeof(u32)) - 1;
1241
1242 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1243
1244#if __REALLY_HAVE_AGP
1245 if ( !dev_priv->is_pci ) {
1246 /* Turn off PCI GART */
1247 radeon_set_pcigart( dev_priv, 0 );
1248 } else
1249#endif
1250 {
1251 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1252 &dev_priv->bus_pci_gart)) {
1253 DRM_ERROR( "failed to init PCI GART!\n" );
1254 dev->dev_private = (void *)dev_priv;
1255 radeon_do_cleanup_cp(dev);
1256 return DRM_ERR(ENOMEM);
1257 }
1258
1259 /* Turn on PCI GART */
1260 radeon_set_pcigart( dev_priv, 1 );
1261 }
1262
1263 radeon_cp_load_microcode( dev_priv );
1264 radeon_cp_init_ring_buffer( dev, dev_priv );
1265
1266 dev_priv->last_buf = 0;
1267
1268 dev->dev_private = (void *)dev_priv;
1269
1270 radeon_do_engine_reset( dev );
1271
1272 return 0;
1273}
1274
1275int radeon_do_cleanup_cp( drm_device_t *dev )
1276{
1277 DRM_DEBUG( "\n" );
1278
1279#if _HAVE_DMA_IRQ
1280 /* Make sure interrupts are disabled here because the uninstall ioctl
1281 * may not have been called from userspace and after dev_private
1282 * is freed, it's too late.
1283 */
1284 if ( dev->irq ) DRM(irq_uninstall)(dev);
1285#endif
1286
1287 if ( dev->dev_private ) {
1288 drm_radeon_private_t *dev_priv = dev->dev_private;
1289
1290#if __REALLY_HAVE_AGP
1291 if ( !dev_priv->is_pci ) {
1292 if ( dev_priv->cp_ring != NULL )
1293 DRM_IOREMAPFREE( dev_priv->cp_ring, dev );
1294 if ( dev_priv->ring_rptr != NULL )
1295 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
1296 if ( dev_priv->buffers != NULL )
1297 DRM_IOREMAPFREE( dev_priv->buffers, dev );
1298 } else
1299#endif
1300 {
1301 if (!DRM(ati_pcigart_cleanup)( dev,
1302 dev_priv->phys_pci_gart,
1303 dev_priv->bus_pci_gart ))
1304 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1305 }
1306
1307 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1308 DRM_MEM_DRIVER );
1309 dev->dev_private = NULL;
1310 }
1311
1312 return 0;
1313}
1314
1315/* This code will reinit the Radeon CP hardware after a resume from disc.
1316 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1317 * here we make sure that all Radeon hardware initialisation is re-done without
1318 * affecting running applications.
1319 *
1320 * Charl P. Botha <http://cpbotha.net>
1321 */
1322static int radeon_do_resume_cp( drm_device_t *dev )
1323{
1324 drm_radeon_private_t *dev_priv = dev->dev_private;
1325
1326 if ( !dev_priv ) {
1327 DRM_ERROR( "Called with no initialization\n" );
1328 return DRM_ERR( EINVAL );
1329 }
1330
1331 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1332
1333#if __REALLY_HAVE_AGP
1334 if ( !dev_priv->is_pci ) {
1335 /* Turn off PCI GART */
1336 radeon_set_pcigart( dev_priv, 0 );
1337 } else
1338#endif
1339 {
1340 /* Turn on PCI GART */
1341 radeon_set_pcigart( dev_priv, 1 );
1342 }
1343
1344 radeon_cp_load_microcode( dev_priv );
1345 radeon_cp_init_ring_buffer( dev, dev_priv );
1346
1347 radeon_do_engine_reset( dev );
1348
1349 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1350
1351 return 0;
1352}
1353
1354
1355int radeon_cp_init( DRM_IOCTL_ARGS )
1356{
1357 DRM_DEVICE;
1358 drm_radeon_init_t init;
1359
1360 LOCK_TEST_WITH_RETURN( dev, filp );
1361
1362 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1363
1364 switch ( init.func ) {
1365 case RADEON_INIT_CP:
1366 case RADEON_INIT_R200_CP:
1367 return radeon_do_init_cp( dev, &init );
1368 case RADEON_CLEANUP_CP:
1369 return radeon_do_cleanup_cp( dev );
1370 }
1371
1372 return DRM_ERR(EINVAL);
1373}
1374
1375int radeon_cp_start( DRM_IOCTL_ARGS )
1376{
1377 DRM_DEVICE;
1378 drm_radeon_private_t *dev_priv = dev->dev_private;
1379 DRM_DEBUG( "\n" );
1380
1381 LOCK_TEST_WITH_RETURN( dev, filp );
1382
1383 if ( dev_priv->cp_running ) {
1384 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1385 return 0;
1386 }
1387 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1388 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1389 __FUNCTION__, dev_priv->cp_mode );
1390 return 0;
1391 }
1392
1393 radeon_do_cp_start( dev_priv );
1394
1395 return 0;
1396}
1397
1398/* Stop the CP. The engine must have been idled before calling this
1399 * routine.
1400 */
1401int radeon_cp_stop( DRM_IOCTL_ARGS )
1402{
1403 DRM_DEVICE;
1404 drm_radeon_private_t *dev_priv = dev->dev_private;
1405 drm_radeon_cp_stop_t stop;
1406 int ret;
1407 DRM_DEBUG( "\n" );
1408
1409 LOCK_TEST_WITH_RETURN( dev, filp );
1410
1411 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1412
1413 if (!dev_priv->cp_running)
1414 return 0;
1415
1416 /* Flush any pending CP commands. This ensures any outstanding
1417 * commands are exectuted by the engine before we turn it off.
1418 */
1419 if ( stop.flush ) {
1420 radeon_do_cp_flush( dev_priv );
1421 }
1422
1423 /* If we fail to make the engine go idle, we return an error
1424 * code so that the DRM ioctl wrapper can try again.
1425 */
1426 if ( stop.idle ) {
1427 ret = radeon_do_cp_idle( dev_priv );
1428 if ( ret ) return ret;
1429 }
1430
1431 /* Finally, we can turn off the CP. If the engine isn't idle,
1432 * we will get some dropped triangles as they won't be fully
1433 * rendered before the CP is shut down.
1434 */
1435 radeon_do_cp_stop( dev_priv );
1436
1437 /* Reset the engine */
1438 radeon_do_engine_reset( dev );
1439
1440 return 0;
1441}
1442
1443
1444void radeon_do_release( drm_device_t *dev )
1445{
1446 drm_radeon_private_t *dev_priv = dev->dev_private;
1447 int ret;
1448
1449 if (dev_priv) {
1450 if (dev_priv->cp_running) {
1451 /* Stop the cp */
1452 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1453 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1454#ifdef __linux__
1455 schedule();
1456#else
1457 tsleep(&ret, PZERO, "rdnrel", 1);
1458#endif
1459 }
1460 radeon_do_cp_stop( dev_priv );
1461 radeon_do_engine_reset( dev );
1462 }
1463
1464 /* Disable *all* interrupts */
1465 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1466
1467 /* Free memory heap structures */
1229
1230 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1231 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1232 + init->ring_size / sizeof(u32));
1233 dev_priv->ring.size = init->ring_size;
1234 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1235
1236 dev_priv->ring.tail_mask =
1237 (dev_priv->ring.size / sizeof(u32)) - 1;
1238
1239 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1240
1241#if __REALLY_HAVE_AGP
1242 if ( !dev_priv->is_pci ) {
1243 /* Turn off PCI GART */
1244 radeon_set_pcigart( dev_priv, 0 );
1245 } else
1246#endif
1247 {
1248 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1249 &dev_priv->bus_pci_gart)) {
1250 DRM_ERROR( "failed to init PCI GART!\n" );
1251 dev->dev_private = (void *)dev_priv;
1252 radeon_do_cleanup_cp(dev);
1253 return DRM_ERR(ENOMEM);
1254 }
1255
1256 /* Turn on PCI GART */
1257 radeon_set_pcigart( dev_priv, 1 );
1258 }
1259
1260 radeon_cp_load_microcode( dev_priv );
1261 radeon_cp_init_ring_buffer( dev, dev_priv );
1262
1263 dev_priv->last_buf = 0;
1264
1265 dev->dev_private = (void *)dev_priv;
1266
1267 radeon_do_engine_reset( dev );
1268
1269 return 0;
1270}
1271
1272int radeon_do_cleanup_cp( drm_device_t *dev )
1273{
1274 DRM_DEBUG( "\n" );
1275
1276#if _HAVE_DMA_IRQ
1277 /* Make sure interrupts are disabled here because the uninstall ioctl
1278 * may not have been called from userspace and after dev_private
1279 * is freed, it's too late.
1280 */
1281 if ( dev->irq ) DRM(irq_uninstall)(dev);
1282#endif
1283
1284 if ( dev->dev_private ) {
1285 drm_radeon_private_t *dev_priv = dev->dev_private;
1286
1287#if __REALLY_HAVE_AGP
1288 if ( !dev_priv->is_pci ) {
1289 if ( dev_priv->cp_ring != NULL )
1290 DRM_IOREMAPFREE( dev_priv->cp_ring, dev );
1291 if ( dev_priv->ring_rptr != NULL )
1292 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
1293 if ( dev_priv->buffers != NULL )
1294 DRM_IOREMAPFREE( dev_priv->buffers, dev );
1295 } else
1296#endif
1297 {
1298 if (!DRM(ati_pcigart_cleanup)( dev,
1299 dev_priv->phys_pci_gart,
1300 dev_priv->bus_pci_gart ))
1301 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1302 }
1303
1304 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1305 DRM_MEM_DRIVER );
1306 dev->dev_private = NULL;
1307 }
1308
1309 return 0;
1310}
1311
1312/* This code will reinit the Radeon CP hardware after a resume from disc.
1313 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1314 * here we make sure that all Radeon hardware initialisation is re-done without
1315 * affecting running applications.
1316 *
1317 * Charl P. Botha <http://cpbotha.net>
1318 */
1319static int radeon_do_resume_cp( drm_device_t *dev )
1320{
1321 drm_radeon_private_t *dev_priv = dev->dev_private;
1322
1323 if ( !dev_priv ) {
1324 DRM_ERROR( "Called with no initialization\n" );
1325 return DRM_ERR( EINVAL );
1326 }
1327
1328 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1329
1330#if __REALLY_HAVE_AGP
1331 if ( !dev_priv->is_pci ) {
1332 /* Turn off PCI GART */
1333 radeon_set_pcigart( dev_priv, 0 );
1334 } else
1335#endif
1336 {
1337 /* Turn on PCI GART */
1338 radeon_set_pcigart( dev_priv, 1 );
1339 }
1340
1341 radeon_cp_load_microcode( dev_priv );
1342 radeon_cp_init_ring_buffer( dev, dev_priv );
1343
1344 radeon_do_engine_reset( dev );
1345
1346 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1347
1348 return 0;
1349}
1350
1351
1352int radeon_cp_init( DRM_IOCTL_ARGS )
1353{
1354 DRM_DEVICE;
1355 drm_radeon_init_t init;
1356
1357 LOCK_TEST_WITH_RETURN( dev, filp );
1358
1359 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1360
1361 switch ( init.func ) {
1362 case RADEON_INIT_CP:
1363 case RADEON_INIT_R200_CP:
1364 return radeon_do_init_cp( dev, &init );
1365 case RADEON_CLEANUP_CP:
1366 return radeon_do_cleanup_cp( dev );
1367 }
1368
1369 return DRM_ERR(EINVAL);
1370}
1371
1372int radeon_cp_start( DRM_IOCTL_ARGS )
1373{
1374 DRM_DEVICE;
1375 drm_radeon_private_t *dev_priv = dev->dev_private;
1376 DRM_DEBUG( "\n" );
1377
1378 LOCK_TEST_WITH_RETURN( dev, filp );
1379
1380 if ( dev_priv->cp_running ) {
1381 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1382 return 0;
1383 }
1384 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1385 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1386 __FUNCTION__, dev_priv->cp_mode );
1387 return 0;
1388 }
1389
1390 radeon_do_cp_start( dev_priv );
1391
1392 return 0;
1393}
1394
1395/* Stop the CP. The engine must have been idled before calling this
1396 * routine.
1397 */
1398int radeon_cp_stop( DRM_IOCTL_ARGS )
1399{
1400 DRM_DEVICE;
1401 drm_radeon_private_t *dev_priv = dev->dev_private;
1402 drm_radeon_cp_stop_t stop;
1403 int ret;
1404 DRM_DEBUG( "\n" );
1405
1406 LOCK_TEST_WITH_RETURN( dev, filp );
1407
1408 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1409
1410 if (!dev_priv->cp_running)
1411 return 0;
1412
1413 /* Flush any pending CP commands. This ensures any outstanding
1414 * commands are exectuted by the engine before we turn it off.
1415 */
1416 if ( stop.flush ) {
1417 radeon_do_cp_flush( dev_priv );
1418 }
1419
1420 /* If we fail to make the engine go idle, we return an error
1421 * code so that the DRM ioctl wrapper can try again.
1422 */
1423 if ( stop.idle ) {
1424 ret = radeon_do_cp_idle( dev_priv );
1425 if ( ret ) return ret;
1426 }
1427
1428 /* Finally, we can turn off the CP. If the engine isn't idle,
1429 * we will get some dropped triangles as they won't be fully
1430 * rendered before the CP is shut down.
1431 */
1432 radeon_do_cp_stop( dev_priv );
1433
1434 /* Reset the engine */
1435 radeon_do_engine_reset( dev );
1436
1437 return 0;
1438}
1439
1440
1441void radeon_do_release( drm_device_t *dev )
1442{
1443 drm_radeon_private_t *dev_priv = dev->dev_private;
1444 int ret;
1445
1446 if (dev_priv) {
1447 if (dev_priv->cp_running) {
1448 /* Stop the cp */
1449 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1450 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1451#ifdef __linux__
1452 schedule();
1453#else
1454 tsleep(&ret, PZERO, "rdnrel", 1);
1455#endif
1456 }
1457 radeon_do_cp_stop( dev_priv );
1458 radeon_do_engine_reset( dev );
1459 }
1460
1461 /* Disable *all* interrupts */
1462 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1463
1464 /* Free memory heap structures */
1468 radeon_mem_takedown( &(dev_priv->agp_heap) );
1465 radeon_mem_takedown( &(dev_priv->gart_heap) );
1469 radeon_mem_takedown( &(dev_priv->fb_heap) );
1470
1471 /* deallocate kernel resources */
1472 radeon_do_cleanup_cp( dev );
1473 }
1474}
1475
1476/* Just reset the CP ring. Called as part of an X Server engine reset.
1477 */
1478int radeon_cp_reset( DRM_IOCTL_ARGS )
1479{
1480 DRM_DEVICE;
1481 drm_radeon_private_t *dev_priv = dev->dev_private;
1482 DRM_DEBUG( "\n" );
1483
1484 LOCK_TEST_WITH_RETURN( dev, filp );
1485
1486 if ( !dev_priv ) {
1487 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1488 return DRM_ERR(EINVAL);
1489 }
1490
1491 radeon_do_cp_reset( dev_priv );
1492
1493 /* The CP is no longer running after an engine reset */
1494 dev_priv->cp_running = 0;
1495
1496 return 0;
1497}
1498
1499int radeon_cp_idle( DRM_IOCTL_ARGS )
1500{
1501 DRM_DEVICE;
1502 drm_radeon_private_t *dev_priv = dev->dev_private;
1503 DRM_DEBUG( "\n" );
1504
1505 LOCK_TEST_WITH_RETURN( dev, filp );
1506
1507 return radeon_do_cp_idle( dev_priv );
1508}
1509
1510/* Added by Charl P. Botha to call radeon_do_resume_cp().
1511 */
1512int radeon_cp_resume( DRM_IOCTL_ARGS )
1513{
1514 DRM_DEVICE;
1515
1516 return radeon_do_resume_cp(dev);
1517}
1518
1519
1520int radeon_engine_reset( DRM_IOCTL_ARGS )
1521{
1522 DRM_DEVICE;
1523 DRM_DEBUG( "\n" );
1524
1525 LOCK_TEST_WITH_RETURN( dev, filp );
1526
1527 return radeon_do_engine_reset( dev );
1528}
1529
1530
1531/* ================================================================
1532 * Fullscreen mode
1533 */
1534
1535/* KW: Deprecated to say the least:
1536 */
1537int radeon_fullscreen( DRM_IOCTL_ARGS )
1538{
1539 return 0;
1540}
1541
1542
1543/* ================================================================
1544 * Freelist management
1545 */
1546
1547/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1548 * bufs until freelist code is used. Note this hides a problem with
1549 * the scratch register * (used to keep track of last buffer
1550 * completed) being written to before * the last buffer has actually
1551 * completed rendering.
1552 *
1553 * KW: It's also a good way to find free buffers quickly.
1554 *
1555 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1556 * sleep. However, bugs in older versions of radeon_accel.c mean that
1557 * we essentially have to do this, else old clients will break.
1558 *
1559 * However, it does leave open a potential deadlock where all the
1560 * buffers are held by other clients, which can't release them because
1561 * they can't get the lock.
1562 */
1563
1564drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1565{
1566 drm_device_dma_t *dma = dev->dma;
1567 drm_radeon_private_t *dev_priv = dev->dev_private;
1568 drm_radeon_buf_priv_t *buf_priv;
1569 drm_buf_t *buf;
1570 int i, t;
1571 int start;
1572
1573 if ( ++dev_priv->last_buf >= dma->buf_count )
1574 dev_priv->last_buf = 0;
1575
1576 start = dev_priv->last_buf;
1577
1578 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1579 u32 done_age = GET_SCRATCH( 1 );
1580 DRM_DEBUG("done_age = %d\n",done_age);
1581 for ( i = start ; i < dma->buf_count ; i++ ) {
1582 buf = dma->buflist[i];
1583 buf_priv = buf->dev_private;
1584 if ( buf->filp == 0 || (buf->pending &&
1585 buf_priv->age <= done_age) ) {
1586 dev_priv->stats.requested_bufs++;
1587 buf->pending = 0;
1588 return buf;
1589 }
1590 start = 0;
1591 }
1592
1593 if (t) {
1594 DRM_UDELAY( 1 );
1595 dev_priv->stats.freelist_loops++;
1596 }
1597 }
1598
1599 DRM_DEBUG( "returning NULL!\n" );
1600 return NULL;
1601}
1602#if 0
1603drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1604{
1605 drm_device_dma_t *dma = dev->dma;
1606 drm_radeon_private_t *dev_priv = dev->dev_private;
1607 drm_radeon_buf_priv_t *buf_priv;
1608 drm_buf_t *buf;
1609 int i, t;
1610 int start;
1611 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1612
1613 if ( ++dev_priv->last_buf >= dma->buf_count )
1614 dev_priv->last_buf = 0;
1615
1616 start = dev_priv->last_buf;
1617 dev_priv->stats.freelist_loops++;
1618
1619 for ( t = 0 ; t < 2 ; t++ ) {
1620 for ( i = start ; i < dma->buf_count ; i++ ) {
1621 buf = dma->buflist[i];
1622 buf_priv = buf->dev_private;
1623 if ( buf->filp == 0 || (buf->pending &&
1624 buf_priv->age <= done_age) ) {
1625 dev_priv->stats.requested_bufs++;
1626 buf->pending = 0;
1627 return buf;
1628 }
1629 }
1630 start = 0;
1631 }
1632
1633 return NULL;
1634}
1635#endif
1636
1637void radeon_freelist_reset( drm_device_t *dev )
1638{
1639 drm_device_dma_t *dma = dev->dma;
1640 drm_radeon_private_t *dev_priv = dev->dev_private;
1641 int i;
1642
1643 dev_priv->last_buf = 0;
1644 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1645 drm_buf_t *buf = dma->buflist[i];
1646 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1647 buf_priv->age = 0;
1648 }
1649}
1650
1651
1652/* ================================================================
1653 * CP command submission
1654 */
1655
1656int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1657{
1658 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1659 int i;
1660 u32 last_head = GET_RING_HEAD( dev_priv );
1661
1662 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1663 u32 head = GET_RING_HEAD( dev_priv );
1664
1665 ring->space = (head - ring->tail) * sizeof(u32);
1666 if ( ring->space <= 0 )
1667 ring->space += ring->size;
1668 if ( ring->space > n )
1669 return 0;
1670
1671 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1672
1673 if (head != last_head)
1674 i = 0;
1675 last_head = head;
1676
1677 DRM_UDELAY( 1 );
1678 }
1679
1680 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1681#if RADEON_FIFO_DEBUG
1682 radeon_status( dev_priv );
1683 DRM_ERROR( "failed!\n" );
1684#endif
1685 return DRM_ERR(EBUSY);
1686}
1687
1688static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1689{
1690 int i;
1691 drm_buf_t *buf;
1692
1693 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1694 buf = radeon_freelist_get( dev );
1695 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1696
1697 buf->filp = filp;
1698
1699 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1700 sizeof(buf->idx) ) )
1701 return DRM_ERR(EFAULT);
1702 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1703 sizeof(buf->total) ) )
1704 return DRM_ERR(EFAULT);
1705
1706 d->granted_count++;
1707 }
1708 return 0;
1709}
1710
1711int radeon_cp_buffers( DRM_IOCTL_ARGS )
1712{
1713 DRM_DEVICE;
1714 drm_device_dma_t *dma = dev->dma;
1715 int ret = 0;
1716 drm_dma_t d;
1717
1718 LOCK_TEST_WITH_RETURN( dev, filp );
1719
1720 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1721
1722 /* Please don't send us buffers.
1723 */
1724 if ( d.send_count != 0 ) {
1725 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1726 DRM_CURRENTPID, d.send_count );
1727 return DRM_ERR(EINVAL);
1728 }
1729
1730 /* We'll send you buffers.
1731 */
1732 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1733 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1734 DRM_CURRENTPID, d.request_count, dma->buf_count );
1735 return DRM_ERR(EINVAL);
1736 }
1737
1738 d.granted_count = 0;
1739
1740 if ( d.request_count ) {
1741 ret = radeon_cp_get_buffers( filp, dev, &d );
1742 }
1743
1744 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1745
1746 return ret;
1747}
1466 radeon_mem_takedown( &(dev_priv->fb_heap) );
1467
1468 /* deallocate kernel resources */
1469 radeon_do_cleanup_cp( dev );
1470 }
1471}
1472
1473/* Just reset the CP ring. Called as part of an X Server engine reset.
1474 */
1475int radeon_cp_reset( DRM_IOCTL_ARGS )
1476{
1477 DRM_DEVICE;
1478 drm_radeon_private_t *dev_priv = dev->dev_private;
1479 DRM_DEBUG( "\n" );
1480
1481 LOCK_TEST_WITH_RETURN( dev, filp );
1482
1483 if ( !dev_priv ) {
1484 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1485 return DRM_ERR(EINVAL);
1486 }
1487
1488 radeon_do_cp_reset( dev_priv );
1489
1490 /* The CP is no longer running after an engine reset */
1491 dev_priv->cp_running = 0;
1492
1493 return 0;
1494}
1495
1496int radeon_cp_idle( DRM_IOCTL_ARGS )
1497{
1498 DRM_DEVICE;
1499 drm_radeon_private_t *dev_priv = dev->dev_private;
1500 DRM_DEBUG( "\n" );
1501
1502 LOCK_TEST_WITH_RETURN( dev, filp );
1503
1504 return radeon_do_cp_idle( dev_priv );
1505}
1506
1507/* Added by Charl P. Botha to call radeon_do_resume_cp().
1508 */
1509int radeon_cp_resume( DRM_IOCTL_ARGS )
1510{
1511 DRM_DEVICE;
1512
1513 return radeon_do_resume_cp(dev);
1514}
1515
1516
1517int radeon_engine_reset( DRM_IOCTL_ARGS )
1518{
1519 DRM_DEVICE;
1520 DRM_DEBUG( "\n" );
1521
1522 LOCK_TEST_WITH_RETURN( dev, filp );
1523
1524 return radeon_do_engine_reset( dev );
1525}
1526
1527
1528/* ================================================================
1529 * Fullscreen mode
1530 */
1531
1532/* KW: Deprecated to say the least:
1533 */
1534int radeon_fullscreen( DRM_IOCTL_ARGS )
1535{
1536 return 0;
1537}
1538
1539
1540/* ================================================================
1541 * Freelist management
1542 */
1543
1544/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1545 * bufs until freelist code is used. Note this hides a problem with
1546 * the scratch register * (used to keep track of last buffer
1547 * completed) being written to before * the last buffer has actually
1548 * completed rendering.
1549 *
1550 * KW: It's also a good way to find free buffers quickly.
1551 *
1552 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1553 * sleep. However, bugs in older versions of radeon_accel.c mean that
1554 * we essentially have to do this, else old clients will break.
1555 *
1556 * However, it does leave open a potential deadlock where all the
1557 * buffers are held by other clients, which can't release them because
1558 * they can't get the lock.
1559 */
1560
1561drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1562{
1563 drm_device_dma_t *dma = dev->dma;
1564 drm_radeon_private_t *dev_priv = dev->dev_private;
1565 drm_radeon_buf_priv_t *buf_priv;
1566 drm_buf_t *buf;
1567 int i, t;
1568 int start;
1569
1570 if ( ++dev_priv->last_buf >= dma->buf_count )
1571 dev_priv->last_buf = 0;
1572
1573 start = dev_priv->last_buf;
1574
1575 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1576 u32 done_age = GET_SCRATCH( 1 );
1577 DRM_DEBUG("done_age = %d\n",done_age);
1578 for ( i = start ; i < dma->buf_count ; i++ ) {
1579 buf = dma->buflist[i];
1580 buf_priv = buf->dev_private;
1581 if ( buf->filp == 0 || (buf->pending &&
1582 buf_priv->age <= done_age) ) {
1583 dev_priv->stats.requested_bufs++;
1584 buf->pending = 0;
1585 return buf;
1586 }
1587 start = 0;
1588 }
1589
1590 if (t) {
1591 DRM_UDELAY( 1 );
1592 dev_priv->stats.freelist_loops++;
1593 }
1594 }
1595
1596 DRM_DEBUG( "returning NULL!\n" );
1597 return NULL;
1598}
1599#if 0
1600drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1601{
1602 drm_device_dma_t *dma = dev->dma;
1603 drm_radeon_private_t *dev_priv = dev->dev_private;
1604 drm_radeon_buf_priv_t *buf_priv;
1605 drm_buf_t *buf;
1606 int i, t;
1607 int start;
1608 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1609
1610 if ( ++dev_priv->last_buf >= dma->buf_count )
1611 dev_priv->last_buf = 0;
1612
1613 start = dev_priv->last_buf;
1614 dev_priv->stats.freelist_loops++;
1615
1616 for ( t = 0 ; t < 2 ; t++ ) {
1617 for ( i = start ; i < dma->buf_count ; i++ ) {
1618 buf = dma->buflist[i];
1619 buf_priv = buf->dev_private;
1620 if ( buf->filp == 0 || (buf->pending &&
1621 buf_priv->age <= done_age) ) {
1622 dev_priv->stats.requested_bufs++;
1623 buf->pending = 0;
1624 return buf;
1625 }
1626 }
1627 start = 0;
1628 }
1629
1630 return NULL;
1631}
1632#endif
1633
1634void radeon_freelist_reset( drm_device_t *dev )
1635{
1636 drm_device_dma_t *dma = dev->dma;
1637 drm_radeon_private_t *dev_priv = dev->dev_private;
1638 int i;
1639
1640 dev_priv->last_buf = 0;
1641 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1642 drm_buf_t *buf = dma->buflist[i];
1643 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1644 buf_priv->age = 0;
1645 }
1646}
1647
1648
1649/* ================================================================
1650 * CP command submission
1651 */
1652
1653int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1654{
1655 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1656 int i;
1657 u32 last_head = GET_RING_HEAD( dev_priv );
1658
1659 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1660 u32 head = GET_RING_HEAD( dev_priv );
1661
1662 ring->space = (head - ring->tail) * sizeof(u32);
1663 if ( ring->space <= 0 )
1664 ring->space += ring->size;
1665 if ( ring->space > n )
1666 return 0;
1667
1668 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1669
1670 if (head != last_head)
1671 i = 0;
1672 last_head = head;
1673
1674 DRM_UDELAY( 1 );
1675 }
1676
1677 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1678#if RADEON_FIFO_DEBUG
1679 radeon_status( dev_priv );
1680 DRM_ERROR( "failed!\n" );
1681#endif
1682 return DRM_ERR(EBUSY);
1683}
1684
1685static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1686{
1687 int i;
1688 drm_buf_t *buf;
1689
1690 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1691 buf = radeon_freelist_get( dev );
1692 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1693
1694 buf->filp = filp;
1695
1696 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1697 sizeof(buf->idx) ) )
1698 return DRM_ERR(EFAULT);
1699 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1700 sizeof(buf->total) ) )
1701 return DRM_ERR(EFAULT);
1702
1703 d->granted_count++;
1704 }
1705 return 0;
1706}
1707
1708int radeon_cp_buffers( DRM_IOCTL_ARGS )
1709{
1710 DRM_DEVICE;
1711 drm_device_dma_t *dma = dev->dma;
1712 int ret = 0;
1713 drm_dma_t d;
1714
1715 LOCK_TEST_WITH_RETURN( dev, filp );
1716
1717 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1718
1719 /* Please don't send us buffers.
1720 */
1721 if ( d.send_count != 0 ) {
1722 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1723 DRM_CURRENTPID, d.send_count );
1724 return DRM_ERR(EINVAL);
1725 }
1726
1727 /* We'll send you buffers.
1728 */
1729 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1730 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1731 DRM_CURRENTPID, d.request_count, dma->buf_count );
1732 return DRM_ERR(EINVAL);
1733 }
1734
1735 d.granted_count = 0;
1736
1737 if ( d.request_count ) {
1738 ret = radeon_cp_get_buffers( filp, dev, &d );
1739 }
1740
1741 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1742
1743 return ret;
1744}