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r128_cce.c (145132) r128_cce.c (148211)
1/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com */
3/*-
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
1/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com */
3/*-
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/r128_cce.c 145132 2005-04-16 03:44:47Z anholt $
30 * $FreeBSD: head/sys/dev/drm/r128_cce.c 148211 2005-07-20 21:10:57Z anholt $
31 */
32
33#include "dev/drm/drmP.h"
34#include "dev/drm/drm.h"
35#include "dev/drm/r128_drm.h"
36#include "dev/drm/r128_drv.h"
37
38#define R128_FIFO_DEBUG 0
39
40/* CCE microcode (from ATI) */
41static u32 r128_cce_microcode[] = {
42 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
43 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
44 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
45 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
46 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
47 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
48 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
49 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
50 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
51 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
52 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
53 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
54 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
55 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
56 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
57 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
58 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
59 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
60 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
61 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
62 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
63 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
64 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
65 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
66 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
67 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
68 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
69 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
70 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
71 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
72 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
73 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
74 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
75 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
76 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
83};
84
85static int R128_READ_PLL(drm_device_t * dev, int addr)
86{
87 drm_r128_private_t *dev_priv = dev->dev_private;
88
89 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
90 return R128_READ(R128_CLOCK_CNTL_DATA);
91}
92
93#if R128_FIFO_DEBUG
94static void r128_status(drm_r128_private_t * dev_priv)
95{
96 printk("GUI_STAT = 0x%08x\n",
97 (unsigned int)R128_READ(R128_GUI_STAT));
98 printk("PM4_STAT = 0x%08x\n",
99 (unsigned int)R128_READ(R128_PM4_STAT));
100 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
101 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
102 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
103 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
104 printk("PM4_MICRO_CNTL = 0x%08x\n",
105 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
106 printk("PM4_BUFFER_CNTL = 0x%08x\n",
107 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
108}
109#endif
110
111/* ================================================================
112 * Engine, FIFO control
113 */
114
115static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
116{
117 u32 tmp;
118 int i;
119
120 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
121 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
122
123 for (i = 0; i < dev_priv->usec_timeout; i++) {
124 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
125 return 0;
126 }
127 DRM_UDELAY(1);
128 }
129
130#if R128_FIFO_DEBUG
131 DRM_ERROR("failed!\n");
132#endif
133 return DRM_ERR(EBUSY);
134}
135
136static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
137{
138 int i;
139
140 for (i = 0; i < dev_priv->usec_timeout; i++) {
141 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
142 if (slots >= entries)
143 return 0;
144 DRM_UDELAY(1);
145 }
146
147#if R128_FIFO_DEBUG
148 DRM_ERROR("failed!\n");
149#endif
150 return DRM_ERR(EBUSY);
151}
152
153static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
154{
155 int i, ret;
156
157 ret = r128_do_wait_for_fifo(dev_priv, 64);
158 if (ret)
159 return ret;
160
161 for (i = 0; i < dev_priv->usec_timeout; i++) {
162 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
163 r128_do_pixcache_flush(dev_priv);
164 return 0;
165 }
166 DRM_UDELAY(1);
167 }
168
169#if R128_FIFO_DEBUG
170 DRM_ERROR("failed!\n");
171#endif
172 return DRM_ERR(EBUSY);
173}
174
175/* ================================================================
176 * CCE control, initialization
177 */
178
179/* Load the microcode for the CCE */
180static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
181{
182 int i;
183
184 DRM_DEBUG("\n");
185
186 r128_do_wait_for_idle(dev_priv);
187
188 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
189 for (i = 0; i < 256; i++) {
190 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
191 R128_WRITE(R128_PM4_MICROCODE_DATAL,
192 r128_cce_microcode[i * 2 + 1]);
193 }
194}
195
196/* Flush any pending commands to the CCE. This should only be used just
197 * prior to a wait for idle, as it informs the engine that the command
198 * stream is ending.
199 */
200static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
201{
202 u32 tmp;
203
204 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
205 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
206}
207
208/* Wait for the CCE to go idle.
209 */
210int r128_do_cce_idle(drm_r128_private_t * dev_priv)
211{
212 int i;
213
214 for (i = 0; i < dev_priv->usec_timeout; i++) {
215 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
216 int pm4stat = R128_READ(R128_PM4_STAT);
217 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
218 dev_priv->cce_fifo_size) &&
219 !(pm4stat & (R128_PM4_BUSY |
220 R128_PM4_GUI_ACTIVE))) {
221 return r128_do_pixcache_flush(dev_priv);
222 }
223 }
224 DRM_UDELAY(1);
225 }
226
227#if R128_FIFO_DEBUG
228 DRM_ERROR("failed!\n");
229 r128_status(dev_priv);
230#endif
231 return DRM_ERR(EBUSY);
232}
233
234/* Start the Concurrent Command Engine.
235 */
236static void r128_do_cce_start(drm_r128_private_t * dev_priv)
237{
238 r128_do_wait_for_idle(dev_priv);
239
240 R128_WRITE(R128_PM4_BUFFER_CNTL,
241 dev_priv->cce_mode | dev_priv->ring.size_l2qw
242 | R128_PM4_BUFFER_CNTL_NOUPDATE);
243 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
244 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
245
246 dev_priv->cce_running = 1;
247}
248
249/* Reset the Concurrent Command Engine. This will not flush any pending
250 * commands, so you must wait for the CCE command stream to complete
251 * before calling this routine.
252 */
253static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
254{
255 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
256 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
257 dev_priv->ring.tail = 0;
258}
259
260/* Stop the Concurrent Command Engine. This will not flush any pending
261 * commands, so you must flush the command stream and wait for the CCE
262 * to go idle before calling this routine.
263 */
264static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
265{
266 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
267 R128_WRITE(R128_PM4_BUFFER_CNTL,
268 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
269
270 dev_priv->cce_running = 0;
271}
272
273/* Reset the engine. This will stop the CCE if it is running.
274 */
275static int r128_do_engine_reset(drm_device_t * dev)
276{
277 drm_r128_private_t *dev_priv = dev->dev_private;
278 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
279
280 r128_do_pixcache_flush(dev_priv);
281
282 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
283 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
284
285 R128_WRITE_PLL(R128_MCLK_CNTL,
286 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
287
288 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
289
290 /* Taken from the sample code - do not change */
291 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
292 R128_READ(R128_GEN_RESET_CNTL);
293 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
294 R128_READ(R128_GEN_RESET_CNTL);
295
296 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
297 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
298 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
299
300 /* Reset the CCE ring */
301 r128_do_cce_reset(dev_priv);
302
303 /* The CCE is no longer running after an engine reset */
304 dev_priv->cce_running = 0;
305
306 /* Reset any pending vertex, indirect buffers */
307 r128_freelist_reset(dev);
308
309 return 0;
310}
311
312static void r128_cce_init_ring_buffer(drm_device_t * dev,
313 drm_r128_private_t * dev_priv)
314{
315 u32 ring_start;
316 u32 tmp;
317
318 DRM_DEBUG("\n");
319
320 /* The manual (p. 2) says this address is in "VM space". This
321 * means it's an offset from the start of AGP space.
322 */
323#if __OS_HAS_AGP
324 if (!dev_priv->is_pci)
325 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
326 else
327#endif
328 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
329
330 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
331
332 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
333 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
334
335 /* Set watermark control */
336 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
337 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
338 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
339 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
340 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
341
342 /* Force read. Why? Because it's in the examples... */
343 R128_READ(R128_PM4_BUFFER_ADDR);
344
345 /* Turn on bus mastering */
346 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
347 R128_WRITE(R128_BUS_CNTL, tmp);
348}
349
350static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
351{
352 drm_r128_private_t *dev_priv;
353
354 DRM_DEBUG("\n");
355
356 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
357 if (dev_priv == NULL)
358 return DRM_ERR(ENOMEM);
359
360 memset(dev_priv, 0, sizeof(drm_r128_private_t));
361
362 dev_priv->is_pci = init->is_pci;
363
364 if (dev_priv->is_pci && !dev->sg) {
365 DRM_ERROR("PCI GART memory not allocated!\n");
366 dev->dev_private = (void *)dev_priv;
367 r128_do_cleanup_cce(dev);
368 return DRM_ERR(EINVAL);
369 }
370
371 dev_priv->usec_timeout = init->usec_timeout;
372 if (dev_priv->usec_timeout < 1 ||
373 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
374 DRM_DEBUG("TIMEOUT problem!\n");
375 dev->dev_private = (void *)dev_priv;
376 r128_do_cleanup_cce(dev);
377 return DRM_ERR(EINVAL);
378 }
379
380 dev_priv->cce_mode = init->cce_mode;
381
382 /* GH: Simple idle check.
383 */
384 atomic_set(&dev_priv->idle_count, 0);
385
386 /* We don't support anything other than bus-mastering ring mode,
387 * but the ring can be in either AGP or PCI space for the ring
388 * read pointer.
389 */
390 if ((init->cce_mode != R128_PM4_192BM) &&
391 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
392 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
393 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
394 DRM_DEBUG("Bad cce_mode!\n");
395 dev->dev_private = (void *)dev_priv;
396 r128_do_cleanup_cce(dev);
397 return DRM_ERR(EINVAL);
398 }
399
400 switch (init->cce_mode) {
401 case R128_PM4_NONPM4:
402 dev_priv->cce_fifo_size = 0;
403 break;
404 case R128_PM4_192PIO:
405 case R128_PM4_192BM:
406 dev_priv->cce_fifo_size = 192;
407 break;
408 case R128_PM4_128PIO_64INDBM:
409 case R128_PM4_128BM_64INDBM:
410 dev_priv->cce_fifo_size = 128;
411 break;
412 case R128_PM4_64PIO_128INDBM:
413 case R128_PM4_64BM_128INDBM:
414 case R128_PM4_64PIO_64VCBM_64INDBM:
415 case R128_PM4_64BM_64VCBM_64INDBM:
416 case R128_PM4_64PIO_64VCPIO_64INDPIO:
417 dev_priv->cce_fifo_size = 64;
418 break;
419 }
420
421 switch (init->fb_bpp) {
422 case 16:
423 dev_priv->color_fmt = R128_DATATYPE_RGB565;
424 break;
425 case 32:
426 default:
427 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
428 break;
429 }
430 dev_priv->front_offset = init->front_offset;
431 dev_priv->front_pitch = init->front_pitch;
432 dev_priv->back_offset = init->back_offset;
433 dev_priv->back_pitch = init->back_pitch;
434
435 switch (init->depth_bpp) {
436 case 16:
437 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
438 break;
439 case 24:
440 case 32:
441 default:
442 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
443 break;
444 }
445 dev_priv->depth_offset = init->depth_offset;
446 dev_priv->depth_pitch = init->depth_pitch;
447 dev_priv->span_offset = init->span_offset;
448
449 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
450 (dev_priv->front_offset >> 5));
451 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
452 (dev_priv->back_offset >> 5));
453 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
454 (dev_priv->depth_offset >> 5) |
455 R128_DST_TILE);
456 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->span_offset >> 5));
458
459 DRM_GETSAREA();
460
461 if (!dev_priv->sarea) {
462 DRM_ERROR("could not find sarea!\n");
463 dev->dev_private = (void *)dev_priv;
464 r128_do_cleanup_cce(dev);
465 return DRM_ERR(EINVAL);
466 }
467
468 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
469 if (!dev_priv->mmio) {
470 DRM_ERROR("could not find mmio region!\n");
471 dev->dev_private = (void *)dev_priv;
472 r128_do_cleanup_cce(dev);
473 return DRM_ERR(EINVAL);
474 }
475 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
476 if (!dev_priv->cce_ring) {
477 DRM_ERROR("could not find cce ring region!\n");
478 dev->dev_private = (void *)dev_priv;
479 r128_do_cleanup_cce(dev);
480 return DRM_ERR(EINVAL);
481 }
482 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
483 if (!dev_priv->ring_rptr) {
484 DRM_ERROR("could not find ring read pointer!\n");
485 dev->dev_private = (void *)dev_priv;
486 r128_do_cleanup_cce(dev);
487 return DRM_ERR(EINVAL);
488 }
489 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
490 if (!dev->agp_buffer_map) {
491 DRM_ERROR("could not find dma buffer region!\n");
492 dev->dev_private = (void *)dev_priv;
493 r128_do_cleanup_cce(dev);
494 return DRM_ERR(EINVAL);
495 }
496
497 if (!dev_priv->is_pci) {
498 dev_priv->agp_textures =
499 drm_core_findmap(dev, init->agp_textures_offset);
500 if (!dev_priv->agp_textures) {
501 DRM_ERROR("could not find agp texture region!\n");
502 dev->dev_private = (void *)dev_priv;
503 r128_do_cleanup_cce(dev);
504 return DRM_ERR(EINVAL);
505 }
506 }
507
508 dev_priv->sarea_priv =
509 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
510 init->sarea_priv_offset);
511
512#if __OS_HAS_AGP
513 if (!dev_priv->is_pci) {
514 drm_core_ioremap(dev_priv->cce_ring, dev);
515 drm_core_ioremap(dev_priv->ring_rptr, dev);
516 drm_core_ioremap(dev->agp_buffer_map, dev);
517 if (!dev_priv->cce_ring->handle ||
518 !dev_priv->ring_rptr->handle ||
519 !dev->agp_buffer_map->handle) {
520 DRM_ERROR("Could not ioremap agp regions!\n");
521 dev->dev_private = (void *)dev_priv;
522 r128_do_cleanup_cce(dev);
523 return DRM_ERR(ENOMEM);
524 }
525 } else
526#endif
527 {
528 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
529 dev_priv->ring_rptr->handle =
530 (void *)dev_priv->ring_rptr->offset;
531 dev->agp_buffer_map->handle =
532 (void *)dev->agp_buffer_map->offset;
533 }
534
535#if __OS_HAS_AGP
536 if (!dev_priv->is_pci)
537 dev_priv->cce_buffers_offset = dev->agp->base;
538 else
539#endif
540 dev_priv->cce_buffers_offset = dev->sg->handle;
541
542 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
543 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
544 + init->ring_size / sizeof(u32));
545 dev_priv->ring.size = init->ring_size;
546 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
547
548 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
549
550 dev_priv->ring.high_mark = 128;
551
552 dev_priv->sarea_priv->last_frame = 0;
553 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
554
555 dev_priv->sarea_priv->last_dispatch = 0;
556 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
557
558#if __OS_HAS_AGP
559 if (dev_priv->is_pci) {
560#endif
561 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
31 */
32
33#include "dev/drm/drmP.h"
34#include "dev/drm/drm.h"
35#include "dev/drm/r128_drm.h"
36#include "dev/drm/r128_drv.h"
37
38#define R128_FIFO_DEBUG 0
39
40/* CCE microcode (from ATI) */
41static u32 r128_cce_microcode[] = {
42 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
43 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
44 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
45 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
46 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
47 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
48 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
49 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
50 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
51 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
52 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
53 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
54 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
55 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
56 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
57 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
58 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
59 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
60 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
61 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
62 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
63 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
64 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
65 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
66 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
67 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
68 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
69 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
70 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
71 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
72 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
73 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
74 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
75 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
76 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
83};
84
85static int R128_READ_PLL(drm_device_t * dev, int addr)
86{
87 drm_r128_private_t *dev_priv = dev->dev_private;
88
89 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
90 return R128_READ(R128_CLOCK_CNTL_DATA);
91}
92
93#if R128_FIFO_DEBUG
94static void r128_status(drm_r128_private_t * dev_priv)
95{
96 printk("GUI_STAT = 0x%08x\n",
97 (unsigned int)R128_READ(R128_GUI_STAT));
98 printk("PM4_STAT = 0x%08x\n",
99 (unsigned int)R128_READ(R128_PM4_STAT));
100 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
101 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
102 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
103 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
104 printk("PM4_MICRO_CNTL = 0x%08x\n",
105 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
106 printk("PM4_BUFFER_CNTL = 0x%08x\n",
107 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
108}
109#endif
110
111/* ================================================================
112 * Engine, FIFO control
113 */
114
115static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
116{
117 u32 tmp;
118 int i;
119
120 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
121 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
122
123 for (i = 0; i < dev_priv->usec_timeout; i++) {
124 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
125 return 0;
126 }
127 DRM_UDELAY(1);
128 }
129
130#if R128_FIFO_DEBUG
131 DRM_ERROR("failed!\n");
132#endif
133 return DRM_ERR(EBUSY);
134}
135
136static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
137{
138 int i;
139
140 for (i = 0; i < dev_priv->usec_timeout; i++) {
141 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
142 if (slots >= entries)
143 return 0;
144 DRM_UDELAY(1);
145 }
146
147#if R128_FIFO_DEBUG
148 DRM_ERROR("failed!\n");
149#endif
150 return DRM_ERR(EBUSY);
151}
152
153static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
154{
155 int i, ret;
156
157 ret = r128_do_wait_for_fifo(dev_priv, 64);
158 if (ret)
159 return ret;
160
161 for (i = 0; i < dev_priv->usec_timeout; i++) {
162 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
163 r128_do_pixcache_flush(dev_priv);
164 return 0;
165 }
166 DRM_UDELAY(1);
167 }
168
169#if R128_FIFO_DEBUG
170 DRM_ERROR("failed!\n");
171#endif
172 return DRM_ERR(EBUSY);
173}
174
175/* ================================================================
176 * CCE control, initialization
177 */
178
179/* Load the microcode for the CCE */
180static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
181{
182 int i;
183
184 DRM_DEBUG("\n");
185
186 r128_do_wait_for_idle(dev_priv);
187
188 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
189 for (i = 0; i < 256; i++) {
190 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
191 R128_WRITE(R128_PM4_MICROCODE_DATAL,
192 r128_cce_microcode[i * 2 + 1]);
193 }
194}
195
196/* Flush any pending commands to the CCE. This should only be used just
197 * prior to a wait for idle, as it informs the engine that the command
198 * stream is ending.
199 */
200static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
201{
202 u32 tmp;
203
204 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
205 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
206}
207
208/* Wait for the CCE to go idle.
209 */
210int r128_do_cce_idle(drm_r128_private_t * dev_priv)
211{
212 int i;
213
214 for (i = 0; i < dev_priv->usec_timeout; i++) {
215 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
216 int pm4stat = R128_READ(R128_PM4_STAT);
217 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
218 dev_priv->cce_fifo_size) &&
219 !(pm4stat & (R128_PM4_BUSY |
220 R128_PM4_GUI_ACTIVE))) {
221 return r128_do_pixcache_flush(dev_priv);
222 }
223 }
224 DRM_UDELAY(1);
225 }
226
227#if R128_FIFO_DEBUG
228 DRM_ERROR("failed!\n");
229 r128_status(dev_priv);
230#endif
231 return DRM_ERR(EBUSY);
232}
233
234/* Start the Concurrent Command Engine.
235 */
236static void r128_do_cce_start(drm_r128_private_t * dev_priv)
237{
238 r128_do_wait_for_idle(dev_priv);
239
240 R128_WRITE(R128_PM4_BUFFER_CNTL,
241 dev_priv->cce_mode | dev_priv->ring.size_l2qw
242 | R128_PM4_BUFFER_CNTL_NOUPDATE);
243 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
244 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
245
246 dev_priv->cce_running = 1;
247}
248
249/* Reset the Concurrent Command Engine. This will not flush any pending
250 * commands, so you must wait for the CCE command stream to complete
251 * before calling this routine.
252 */
253static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
254{
255 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
256 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
257 dev_priv->ring.tail = 0;
258}
259
260/* Stop the Concurrent Command Engine. This will not flush any pending
261 * commands, so you must flush the command stream and wait for the CCE
262 * to go idle before calling this routine.
263 */
264static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
265{
266 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
267 R128_WRITE(R128_PM4_BUFFER_CNTL,
268 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
269
270 dev_priv->cce_running = 0;
271}
272
273/* Reset the engine. This will stop the CCE if it is running.
274 */
275static int r128_do_engine_reset(drm_device_t * dev)
276{
277 drm_r128_private_t *dev_priv = dev->dev_private;
278 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
279
280 r128_do_pixcache_flush(dev_priv);
281
282 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
283 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
284
285 R128_WRITE_PLL(R128_MCLK_CNTL,
286 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
287
288 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
289
290 /* Taken from the sample code - do not change */
291 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
292 R128_READ(R128_GEN_RESET_CNTL);
293 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
294 R128_READ(R128_GEN_RESET_CNTL);
295
296 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
297 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
298 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
299
300 /* Reset the CCE ring */
301 r128_do_cce_reset(dev_priv);
302
303 /* The CCE is no longer running after an engine reset */
304 dev_priv->cce_running = 0;
305
306 /* Reset any pending vertex, indirect buffers */
307 r128_freelist_reset(dev);
308
309 return 0;
310}
311
312static void r128_cce_init_ring_buffer(drm_device_t * dev,
313 drm_r128_private_t * dev_priv)
314{
315 u32 ring_start;
316 u32 tmp;
317
318 DRM_DEBUG("\n");
319
320 /* The manual (p. 2) says this address is in "VM space". This
321 * means it's an offset from the start of AGP space.
322 */
323#if __OS_HAS_AGP
324 if (!dev_priv->is_pci)
325 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
326 else
327#endif
328 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
329
330 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
331
332 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
333 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
334
335 /* Set watermark control */
336 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
337 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
338 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
339 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
340 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
341
342 /* Force read. Why? Because it's in the examples... */
343 R128_READ(R128_PM4_BUFFER_ADDR);
344
345 /* Turn on bus mastering */
346 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
347 R128_WRITE(R128_BUS_CNTL, tmp);
348}
349
350static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
351{
352 drm_r128_private_t *dev_priv;
353
354 DRM_DEBUG("\n");
355
356 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
357 if (dev_priv == NULL)
358 return DRM_ERR(ENOMEM);
359
360 memset(dev_priv, 0, sizeof(drm_r128_private_t));
361
362 dev_priv->is_pci = init->is_pci;
363
364 if (dev_priv->is_pci && !dev->sg) {
365 DRM_ERROR("PCI GART memory not allocated!\n");
366 dev->dev_private = (void *)dev_priv;
367 r128_do_cleanup_cce(dev);
368 return DRM_ERR(EINVAL);
369 }
370
371 dev_priv->usec_timeout = init->usec_timeout;
372 if (dev_priv->usec_timeout < 1 ||
373 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
374 DRM_DEBUG("TIMEOUT problem!\n");
375 dev->dev_private = (void *)dev_priv;
376 r128_do_cleanup_cce(dev);
377 return DRM_ERR(EINVAL);
378 }
379
380 dev_priv->cce_mode = init->cce_mode;
381
382 /* GH: Simple idle check.
383 */
384 atomic_set(&dev_priv->idle_count, 0);
385
386 /* We don't support anything other than bus-mastering ring mode,
387 * but the ring can be in either AGP or PCI space for the ring
388 * read pointer.
389 */
390 if ((init->cce_mode != R128_PM4_192BM) &&
391 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
392 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
393 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
394 DRM_DEBUG("Bad cce_mode!\n");
395 dev->dev_private = (void *)dev_priv;
396 r128_do_cleanup_cce(dev);
397 return DRM_ERR(EINVAL);
398 }
399
400 switch (init->cce_mode) {
401 case R128_PM4_NONPM4:
402 dev_priv->cce_fifo_size = 0;
403 break;
404 case R128_PM4_192PIO:
405 case R128_PM4_192BM:
406 dev_priv->cce_fifo_size = 192;
407 break;
408 case R128_PM4_128PIO_64INDBM:
409 case R128_PM4_128BM_64INDBM:
410 dev_priv->cce_fifo_size = 128;
411 break;
412 case R128_PM4_64PIO_128INDBM:
413 case R128_PM4_64BM_128INDBM:
414 case R128_PM4_64PIO_64VCBM_64INDBM:
415 case R128_PM4_64BM_64VCBM_64INDBM:
416 case R128_PM4_64PIO_64VCPIO_64INDPIO:
417 dev_priv->cce_fifo_size = 64;
418 break;
419 }
420
421 switch (init->fb_bpp) {
422 case 16:
423 dev_priv->color_fmt = R128_DATATYPE_RGB565;
424 break;
425 case 32:
426 default:
427 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
428 break;
429 }
430 dev_priv->front_offset = init->front_offset;
431 dev_priv->front_pitch = init->front_pitch;
432 dev_priv->back_offset = init->back_offset;
433 dev_priv->back_pitch = init->back_pitch;
434
435 switch (init->depth_bpp) {
436 case 16:
437 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
438 break;
439 case 24:
440 case 32:
441 default:
442 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
443 break;
444 }
445 dev_priv->depth_offset = init->depth_offset;
446 dev_priv->depth_pitch = init->depth_pitch;
447 dev_priv->span_offset = init->span_offset;
448
449 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
450 (dev_priv->front_offset >> 5));
451 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
452 (dev_priv->back_offset >> 5));
453 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
454 (dev_priv->depth_offset >> 5) |
455 R128_DST_TILE);
456 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->span_offset >> 5));
458
459 DRM_GETSAREA();
460
461 if (!dev_priv->sarea) {
462 DRM_ERROR("could not find sarea!\n");
463 dev->dev_private = (void *)dev_priv;
464 r128_do_cleanup_cce(dev);
465 return DRM_ERR(EINVAL);
466 }
467
468 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
469 if (!dev_priv->mmio) {
470 DRM_ERROR("could not find mmio region!\n");
471 dev->dev_private = (void *)dev_priv;
472 r128_do_cleanup_cce(dev);
473 return DRM_ERR(EINVAL);
474 }
475 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
476 if (!dev_priv->cce_ring) {
477 DRM_ERROR("could not find cce ring region!\n");
478 dev->dev_private = (void *)dev_priv;
479 r128_do_cleanup_cce(dev);
480 return DRM_ERR(EINVAL);
481 }
482 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
483 if (!dev_priv->ring_rptr) {
484 DRM_ERROR("could not find ring read pointer!\n");
485 dev->dev_private = (void *)dev_priv;
486 r128_do_cleanup_cce(dev);
487 return DRM_ERR(EINVAL);
488 }
489 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
490 if (!dev->agp_buffer_map) {
491 DRM_ERROR("could not find dma buffer region!\n");
492 dev->dev_private = (void *)dev_priv;
493 r128_do_cleanup_cce(dev);
494 return DRM_ERR(EINVAL);
495 }
496
497 if (!dev_priv->is_pci) {
498 dev_priv->agp_textures =
499 drm_core_findmap(dev, init->agp_textures_offset);
500 if (!dev_priv->agp_textures) {
501 DRM_ERROR("could not find agp texture region!\n");
502 dev->dev_private = (void *)dev_priv;
503 r128_do_cleanup_cce(dev);
504 return DRM_ERR(EINVAL);
505 }
506 }
507
508 dev_priv->sarea_priv =
509 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
510 init->sarea_priv_offset);
511
512#if __OS_HAS_AGP
513 if (!dev_priv->is_pci) {
514 drm_core_ioremap(dev_priv->cce_ring, dev);
515 drm_core_ioremap(dev_priv->ring_rptr, dev);
516 drm_core_ioremap(dev->agp_buffer_map, dev);
517 if (!dev_priv->cce_ring->handle ||
518 !dev_priv->ring_rptr->handle ||
519 !dev->agp_buffer_map->handle) {
520 DRM_ERROR("Could not ioremap agp regions!\n");
521 dev->dev_private = (void *)dev_priv;
522 r128_do_cleanup_cce(dev);
523 return DRM_ERR(ENOMEM);
524 }
525 } else
526#endif
527 {
528 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
529 dev_priv->ring_rptr->handle =
530 (void *)dev_priv->ring_rptr->offset;
531 dev->agp_buffer_map->handle =
532 (void *)dev->agp_buffer_map->offset;
533 }
534
535#if __OS_HAS_AGP
536 if (!dev_priv->is_pci)
537 dev_priv->cce_buffers_offset = dev->agp->base;
538 else
539#endif
540 dev_priv->cce_buffers_offset = dev->sg->handle;
541
542 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
543 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
544 + init->ring_size / sizeof(u32));
545 dev_priv->ring.size = init->ring_size;
546 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
547
548 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
549
550 dev_priv->ring.high_mark = 128;
551
552 dev_priv->sarea_priv->last_frame = 0;
553 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
554
555 dev_priv->sarea_priv->last_dispatch = 0;
556 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
557
558#if __OS_HAS_AGP
559 if (dev_priv->is_pci) {
560#endif
561 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
562 &dev_priv->bus_pci_gart)) {
562 &dev_priv->bus_pci_gart, 0)) {
563 DRM_ERROR("failed to init PCI GART!\n");
564 dev->dev_private = (void *)dev_priv;
565 r128_do_cleanup_cce(dev);
566 return DRM_ERR(ENOMEM);
567 }
568 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->bus_pci_gart);
569#if __OS_HAS_AGP
570 }
571#endif
572
573 r128_cce_init_ring_buffer(dev, dev_priv);
574 r128_cce_load_microcode(dev_priv);
575
576 dev->dev_private = (void *)dev_priv;
577
578 r128_do_engine_reset(dev);
579
580 return 0;
581}
582
583int r128_do_cleanup_cce(drm_device_t * dev)
584{
585
586 /* Make sure interrupts are disabled here because the uninstall ioctl
587 * may not have been called from userspace and after dev_private
588 * is freed, it's too late.
589 */
590 if (dev->irq_enabled)
591 drm_irq_uninstall(dev);
592
593 if (dev->dev_private) {
594 drm_r128_private_t *dev_priv = dev->dev_private;
595
596#if __OS_HAS_AGP
597 if (!dev_priv->is_pci) {
598 if (dev_priv->cce_ring != NULL)
599 drm_core_ioremapfree(dev_priv->cce_ring, dev);
600 if (dev_priv->ring_rptr != NULL)
601 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
602 if (dev->agp_buffer_map != NULL) {
603 drm_core_ioremapfree(dev->agp_buffer_map, dev);
604 dev->agp_buffer_map = NULL;
605 }
606 } else
607#endif
608 {
609 if (!drm_ati_pcigart_cleanup(dev,
610 dev_priv->phys_pci_gart,
611 dev_priv->bus_pci_gart))
612 DRM_ERROR("failed to cleanup PCI GART!\n");
613 }
614
615 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
616 DRM_MEM_DRIVER);
617 dev->dev_private = NULL;
618 }
619
620 return 0;
621}
622
623int r128_cce_init(DRM_IOCTL_ARGS)
624{
625 DRM_DEVICE;
626 drm_r128_init_t init;
627
628 DRM_DEBUG("\n");
629
630 LOCK_TEST_WITH_RETURN(dev, filp);
631
632 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
633 sizeof(init));
634
635 switch (init.func) {
636 case R128_INIT_CCE:
637 return r128_do_init_cce(dev, &init);
638 case R128_CLEANUP_CCE:
639 return r128_do_cleanup_cce(dev);
640 }
641
642 return DRM_ERR(EINVAL);
643}
644
645int r128_cce_start(DRM_IOCTL_ARGS)
646{
647 DRM_DEVICE;
648 drm_r128_private_t *dev_priv = dev->dev_private;
649 DRM_DEBUG("\n");
650
651 LOCK_TEST_WITH_RETURN(dev, filp);
652
653 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
654 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
655 return 0;
656 }
657
658 r128_do_cce_start(dev_priv);
659
660 return 0;
661}
662
663/* Stop the CCE. The engine must have been idled before calling this
664 * routine.
665 */
666int r128_cce_stop(DRM_IOCTL_ARGS)
667{
668 DRM_DEVICE;
669 drm_r128_private_t *dev_priv = dev->dev_private;
670 drm_r128_cce_stop_t stop;
671 int ret;
672 DRM_DEBUG("\n");
673
674 LOCK_TEST_WITH_RETURN(dev, filp);
675
676 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
677 sizeof(stop));
678
679 /* Flush any pending CCE commands. This ensures any outstanding
680 * commands are exectuted by the engine before we turn it off.
681 */
682 if (stop.flush) {
683 r128_do_cce_flush(dev_priv);
684 }
685
686 /* If we fail to make the engine go idle, we return an error
687 * code so that the DRM ioctl wrapper can try again.
688 */
689 if (stop.idle) {
690 ret = r128_do_cce_idle(dev_priv);
691 if (ret)
692 return ret;
693 }
694
695 /* Finally, we can turn off the CCE. If the engine isn't idle,
696 * we will get some dropped triangles as they won't be fully
697 * rendered before the CCE is shut down.
698 */
699 r128_do_cce_stop(dev_priv);
700
701 /* Reset the engine */
702 r128_do_engine_reset(dev);
703
704 return 0;
705}
706
707/* Just reset the CCE ring. Called as part of an X Server engine reset.
708 */
709int r128_cce_reset(DRM_IOCTL_ARGS)
710{
711 DRM_DEVICE;
712 drm_r128_private_t *dev_priv = dev->dev_private;
713 DRM_DEBUG("\n");
714
715 LOCK_TEST_WITH_RETURN(dev, filp);
716
717 if (!dev_priv) {
718 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
719 return DRM_ERR(EINVAL);
720 }
721
722 r128_do_cce_reset(dev_priv);
723
724 /* The CCE is no longer running after an engine reset */
725 dev_priv->cce_running = 0;
726
727 return 0;
728}
729
730int r128_cce_idle(DRM_IOCTL_ARGS)
731{
732 DRM_DEVICE;
733 drm_r128_private_t *dev_priv = dev->dev_private;
734 DRM_DEBUG("\n");
735
736 LOCK_TEST_WITH_RETURN(dev, filp);
737
738 if (dev_priv->cce_running) {
739 r128_do_cce_flush(dev_priv);
740 }
741
742 return r128_do_cce_idle(dev_priv);
743}
744
745int r128_engine_reset(DRM_IOCTL_ARGS)
746{
747 DRM_DEVICE;
748 DRM_DEBUG("\n");
749
750 LOCK_TEST_WITH_RETURN(dev, filp);
751
752 return r128_do_engine_reset(dev);
753}
754
755int r128_fullscreen(DRM_IOCTL_ARGS)
756{
757 return DRM_ERR(EINVAL);
758}
759
760/* ================================================================
761 * Freelist management
762 */
763#define R128_BUFFER_USED 0xffffffff
764#define R128_BUFFER_FREE 0
765
766#if 0
767static int r128_freelist_init(drm_device_t * dev)
768{
769 drm_device_dma_t *dma = dev->dma;
770 drm_r128_private_t *dev_priv = dev->dev_private;
771 drm_buf_t *buf;
772 drm_r128_buf_priv_t *buf_priv;
773 drm_r128_freelist_t *entry;
774 int i;
775
776 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
777 if (dev_priv->head == NULL)
778 return DRM_ERR(ENOMEM);
779
780 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
781 dev_priv->head->age = R128_BUFFER_USED;
782
783 for (i = 0; i < dma->buf_count; i++) {
784 buf = dma->buflist[i];
785 buf_priv = buf->dev_private;
786
787 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
788 if (!entry)
789 return DRM_ERR(ENOMEM);
790
791 entry->age = R128_BUFFER_FREE;
792 entry->buf = buf;
793 entry->prev = dev_priv->head;
794 entry->next = dev_priv->head->next;
795 if (!entry->next)
796 dev_priv->tail = entry;
797
798 buf_priv->discard = 0;
799 buf_priv->dispatched = 0;
800 buf_priv->list_entry = entry;
801
802 dev_priv->head->next = entry;
803
804 if (dev_priv->head->next)
805 dev_priv->head->next->prev = entry;
806 }
807
808 return 0;
809
810}
811#endif
812
813static drm_buf_t *r128_freelist_get(drm_device_t * dev)
814{
815 drm_device_dma_t *dma = dev->dma;
816 drm_r128_private_t *dev_priv = dev->dev_private;
817 drm_r128_buf_priv_t *buf_priv;
818 drm_buf_t *buf;
819 int i, t;
820
821 /* FIXME: Optimize -- use freelist code */
822
823 for (i = 0; i < dma->buf_count; i++) {
824 buf = dma->buflist[i];
825 buf_priv = buf->dev_private;
826 if (buf->filp == 0)
827 return buf;
828 }
829
830 for (t = 0; t < dev_priv->usec_timeout; t++) {
831 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
832
833 for (i = 0; i < dma->buf_count; i++) {
834 buf = dma->buflist[i];
835 buf_priv = buf->dev_private;
836 if (buf->pending && buf_priv->age <= done_age) {
837 /* The buffer has been processed, so it
838 * can now be used.
839 */
840 buf->pending = 0;
841 return buf;
842 }
843 }
844 DRM_UDELAY(1);
845 }
846
847 DRM_DEBUG("returning NULL!\n");
848 return NULL;
849}
850
851void r128_freelist_reset(drm_device_t * dev)
852{
853 drm_device_dma_t *dma = dev->dma;
854 int i;
855
856 for (i = 0; i < dma->buf_count; i++) {
857 drm_buf_t *buf = dma->buflist[i];
858 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
859 buf_priv->age = 0;
860 }
861}
862
863/* ================================================================
864 * CCE command submission
865 */
866
867int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
868{
869 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
870 int i;
871
872 for (i = 0; i < dev_priv->usec_timeout; i++) {
873 r128_update_ring_snapshot(dev_priv);
874 if (ring->space >= n)
875 return 0;
876 DRM_UDELAY(1);
877 }
878
879 /* FIXME: This is being ignored... */
880 DRM_ERROR("failed!\n");
881 return DRM_ERR(EBUSY);
882}
883
884static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
885{
886 int i;
887 drm_buf_t *buf;
888
889 for (i = d->granted_count; i < d->request_count; i++) {
890 buf = r128_freelist_get(dev);
891 if (!buf)
892 return DRM_ERR(EAGAIN);
893
894 buf->filp = filp;
895
896 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
897 sizeof(buf->idx)))
898 return DRM_ERR(EFAULT);
899 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
900 sizeof(buf->total)))
901 return DRM_ERR(EFAULT);
902
903 d->granted_count++;
904 }
905 return 0;
906}
907
908int r128_cce_buffers(DRM_IOCTL_ARGS)
909{
910 DRM_DEVICE;
911 drm_device_dma_t *dma = dev->dma;
912 int ret = 0;
913 drm_dma_t __user *argp = (void __user *)data;
914 drm_dma_t d;
915
916 LOCK_TEST_WITH_RETURN(dev, filp);
917
918 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
919
920 /* Please don't send us buffers.
921 */
922 if (d.send_count != 0) {
923 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
924 DRM_CURRENTPID, d.send_count);
925 return DRM_ERR(EINVAL);
926 }
927
928 /* We'll send you buffers.
929 */
930 if (d.request_count < 0 || d.request_count > dma->buf_count) {
931 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
932 DRM_CURRENTPID, d.request_count, dma->buf_count);
933 return DRM_ERR(EINVAL);
934 }
935
936 d.granted_count = 0;
937
938 if (d.request_count) {
939 ret = r128_cce_get_buffers(filp, dev, &d);
940 }
941
942 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
943
944 return ret;
945}
563 DRM_ERROR("failed to init PCI GART!\n");
564 dev->dev_private = (void *)dev_priv;
565 r128_do_cleanup_cce(dev);
566 return DRM_ERR(ENOMEM);
567 }
568 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->bus_pci_gart);
569#if __OS_HAS_AGP
570 }
571#endif
572
573 r128_cce_init_ring_buffer(dev, dev_priv);
574 r128_cce_load_microcode(dev_priv);
575
576 dev->dev_private = (void *)dev_priv;
577
578 r128_do_engine_reset(dev);
579
580 return 0;
581}
582
583int r128_do_cleanup_cce(drm_device_t * dev)
584{
585
586 /* Make sure interrupts are disabled here because the uninstall ioctl
587 * may not have been called from userspace and after dev_private
588 * is freed, it's too late.
589 */
590 if (dev->irq_enabled)
591 drm_irq_uninstall(dev);
592
593 if (dev->dev_private) {
594 drm_r128_private_t *dev_priv = dev->dev_private;
595
596#if __OS_HAS_AGP
597 if (!dev_priv->is_pci) {
598 if (dev_priv->cce_ring != NULL)
599 drm_core_ioremapfree(dev_priv->cce_ring, dev);
600 if (dev_priv->ring_rptr != NULL)
601 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
602 if (dev->agp_buffer_map != NULL) {
603 drm_core_ioremapfree(dev->agp_buffer_map, dev);
604 dev->agp_buffer_map = NULL;
605 }
606 } else
607#endif
608 {
609 if (!drm_ati_pcigart_cleanup(dev,
610 dev_priv->phys_pci_gart,
611 dev_priv->bus_pci_gart))
612 DRM_ERROR("failed to cleanup PCI GART!\n");
613 }
614
615 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
616 DRM_MEM_DRIVER);
617 dev->dev_private = NULL;
618 }
619
620 return 0;
621}
622
623int r128_cce_init(DRM_IOCTL_ARGS)
624{
625 DRM_DEVICE;
626 drm_r128_init_t init;
627
628 DRM_DEBUG("\n");
629
630 LOCK_TEST_WITH_RETURN(dev, filp);
631
632 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
633 sizeof(init));
634
635 switch (init.func) {
636 case R128_INIT_CCE:
637 return r128_do_init_cce(dev, &init);
638 case R128_CLEANUP_CCE:
639 return r128_do_cleanup_cce(dev);
640 }
641
642 return DRM_ERR(EINVAL);
643}
644
645int r128_cce_start(DRM_IOCTL_ARGS)
646{
647 DRM_DEVICE;
648 drm_r128_private_t *dev_priv = dev->dev_private;
649 DRM_DEBUG("\n");
650
651 LOCK_TEST_WITH_RETURN(dev, filp);
652
653 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
654 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
655 return 0;
656 }
657
658 r128_do_cce_start(dev_priv);
659
660 return 0;
661}
662
663/* Stop the CCE. The engine must have been idled before calling this
664 * routine.
665 */
666int r128_cce_stop(DRM_IOCTL_ARGS)
667{
668 DRM_DEVICE;
669 drm_r128_private_t *dev_priv = dev->dev_private;
670 drm_r128_cce_stop_t stop;
671 int ret;
672 DRM_DEBUG("\n");
673
674 LOCK_TEST_WITH_RETURN(dev, filp);
675
676 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
677 sizeof(stop));
678
679 /* Flush any pending CCE commands. This ensures any outstanding
680 * commands are exectuted by the engine before we turn it off.
681 */
682 if (stop.flush) {
683 r128_do_cce_flush(dev_priv);
684 }
685
686 /* If we fail to make the engine go idle, we return an error
687 * code so that the DRM ioctl wrapper can try again.
688 */
689 if (stop.idle) {
690 ret = r128_do_cce_idle(dev_priv);
691 if (ret)
692 return ret;
693 }
694
695 /* Finally, we can turn off the CCE. If the engine isn't idle,
696 * we will get some dropped triangles as they won't be fully
697 * rendered before the CCE is shut down.
698 */
699 r128_do_cce_stop(dev_priv);
700
701 /* Reset the engine */
702 r128_do_engine_reset(dev);
703
704 return 0;
705}
706
707/* Just reset the CCE ring. Called as part of an X Server engine reset.
708 */
709int r128_cce_reset(DRM_IOCTL_ARGS)
710{
711 DRM_DEVICE;
712 drm_r128_private_t *dev_priv = dev->dev_private;
713 DRM_DEBUG("\n");
714
715 LOCK_TEST_WITH_RETURN(dev, filp);
716
717 if (!dev_priv) {
718 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
719 return DRM_ERR(EINVAL);
720 }
721
722 r128_do_cce_reset(dev_priv);
723
724 /* The CCE is no longer running after an engine reset */
725 dev_priv->cce_running = 0;
726
727 return 0;
728}
729
730int r128_cce_idle(DRM_IOCTL_ARGS)
731{
732 DRM_DEVICE;
733 drm_r128_private_t *dev_priv = dev->dev_private;
734 DRM_DEBUG("\n");
735
736 LOCK_TEST_WITH_RETURN(dev, filp);
737
738 if (dev_priv->cce_running) {
739 r128_do_cce_flush(dev_priv);
740 }
741
742 return r128_do_cce_idle(dev_priv);
743}
744
745int r128_engine_reset(DRM_IOCTL_ARGS)
746{
747 DRM_DEVICE;
748 DRM_DEBUG("\n");
749
750 LOCK_TEST_WITH_RETURN(dev, filp);
751
752 return r128_do_engine_reset(dev);
753}
754
755int r128_fullscreen(DRM_IOCTL_ARGS)
756{
757 return DRM_ERR(EINVAL);
758}
759
760/* ================================================================
761 * Freelist management
762 */
763#define R128_BUFFER_USED 0xffffffff
764#define R128_BUFFER_FREE 0
765
766#if 0
767static int r128_freelist_init(drm_device_t * dev)
768{
769 drm_device_dma_t *dma = dev->dma;
770 drm_r128_private_t *dev_priv = dev->dev_private;
771 drm_buf_t *buf;
772 drm_r128_buf_priv_t *buf_priv;
773 drm_r128_freelist_t *entry;
774 int i;
775
776 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
777 if (dev_priv->head == NULL)
778 return DRM_ERR(ENOMEM);
779
780 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
781 dev_priv->head->age = R128_BUFFER_USED;
782
783 for (i = 0; i < dma->buf_count; i++) {
784 buf = dma->buflist[i];
785 buf_priv = buf->dev_private;
786
787 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
788 if (!entry)
789 return DRM_ERR(ENOMEM);
790
791 entry->age = R128_BUFFER_FREE;
792 entry->buf = buf;
793 entry->prev = dev_priv->head;
794 entry->next = dev_priv->head->next;
795 if (!entry->next)
796 dev_priv->tail = entry;
797
798 buf_priv->discard = 0;
799 buf_priv->dispatched = 0;
800 buf_priv->list_entry = entry;
801
802 dev_priv->head->next = entry;
803
804 if (dev_priv->head->next)
805 dev_priv->head->next->prev = entry;
806 }
807
808 return 0;
809
810}
811#endif
812
813static drm_buf_t *r128_freelist_get(drm_device_t * dev)
814{
815 drm_device_dma_t *dma = dev->dma;
816 drm_r128_private_t *dev_priv = dev->dev_private;
817 drm_r128_buf_priv_t *buf_priv;
818 drm_buf_t *buf;
819 int i, t;
820
821 /* FIXME: Optimize -- use freelist code */
822
823 for (i = 0; i < dma->buf_count; i++) {
824 buf = dma->buflist[i];
825 buf_priv = buf->dev_private;
826 if (buf->filp == 0)
827 return buf;
828 }
829
830 for (t = 0; t < dev_priv->usec_timeout; t++) {
831 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
832
833 for (i = 0; i < dma->buf_count; i++) {
834 buf = dma->buflist[i];
835 buf_priv = buf->dev_private;
836 if (buf->pending && buf_priv->age <= done_age) {
837 /* The buffer has been processed, so it
838 * can now be used.
839 */
840 buf->pending = 0;
841 return buf;
842 }
843 }
844 DRM_UDELAY(1);
845 }
846
847 DRM_DEBUG("returning NULL!\n");
848 return NULL;
849}
850
851void r128_freelist_reset(drm_device_t * dev)
852{
853 drm_device_dma_t *dma = dev->dma;
854 int i;
855
856 for (i = 0; i < dma->buf_count; i++) {
857 drm_buf_t *buf = dma->buflist[i];
858 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
859 buf_priv->age = 0;
860 }
861}
862
863/* ================================================================
864 * CCE command submission
865 */
866
867int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
868{
869 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
870 int i;
871
872 for (i = 0; i < dev_priv->usec_timeout; i++) {
873 r128_update_ring_snapshot(dev_priv);
874 if (ring->space >= n)
875 return 0;
876 DRM_UDELAY(1);
877 }
878
879 /* FIXME: This is being ignored... */
880 DRM_ERROR("failed!\n");
881 return DRM_ERR(EBUSY);
882}
883
884static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
885{
886 int i;
887 drm_buf_t *buf;
888
889 for (i = d->granted_count; i < d->request_count; i++) {
890 buf = r128_freelist_get(dev);
891 if (!buf)
892 return DRM_ERR(EAGAIN);
893
894 buf->filp = filp;
895
896 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
897 sizeof(buf->idx)))
898 return DRM_ERR(EFAULT);
899 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
900 sizeof(buf->total)))
901 return DRM_ERR(EFAULT);
902
903 d->granted_count++;
904 }
905 return 0;
906}
907
908int r128_cce_buffers(DRM_IOCTL_ARGS)
909{
910 DRM_DEVICE;
911 drm_device_dma_t *dma = dev->dma;
912 int ret = 0;
913 drm_dma_t __user *argp = (void __user *)data;
914 drm_dma_t d;
915
916 LOCK_TEST_WITH_RETURN(dev, filp);
917
918 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
919
920 /* Please don't send us buffers.
921 */
922 if (d.send_count != 0) {
923 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
924 DRM_CURRENTPID, d.send_count);
925 return DRM_ERR(EINVAL);
926 }
927
928 /* We'll send you buffers.
929 */
930 if (d.request_count < 0 || d.request_count > dma->buf_count) {
931 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
932 DRM_CURRENTPID, d.request_count, dma->buf_count);
933 return DRM_ERR(EINVAL);
934 }
935
936 d.granted_count = 0;
937
938 if (d.request_count) {
939 ret = r128_cce_get_buffers(filp, dev, &d);
940 }
941
942 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
943
944 return ret;
945}