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dcphy.c (59391) dcphy.c (61110)
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/dc/dcphy.c 59391 2000-04-19 14:58:28Z phk $
32 * $FreeBSD: head/sys/dev/dc/dcphy.c 61110 2000-05-31 05:40:53Z wpaul $
33 */
34
35/*
36 * Pseudo-driver for internal NWAY support on DEC 21143 and workalike
37 * controllers. Technically we're abusing the miibus code to handle
38 * media selection and NWAY support here since there is no MII
39 * interface. However the logical operations are roughly the same,
40 * and the alternative is to create a fake MII interface in the driver,

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67#include <pci/pcivar.h>
68
69#include <pci/if_dcreg.h>
70
71#include "miibus_if.h"
72
73#if !defined(lint)
74static const char rcsid[] =
33 */
34
35/*
36 * Pseudo-driver for internal NWAY support on DEC 21143 and workalike
37 * controllers. Technically we're abusing the miibus code to handle
38 * media selection and NWAY support here since there is no MII
39 * interface. However the logical operations are roughly the same,
40 * and the alternative is to create a fake MII interface in the driver,

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67#include <pci/pcivar.h>
68
69#include <pci/if_dcreg.h>
70
71#include "miibus_if.h"
72
73#if !defined(lint)
74static const char rcsid[] =
75 "$FreeBSD: head/sys/dev/dc/dcphy.c 59391 2000-04-19 14:58:28Z phk $";
75 "$FreeBSD: head/sys/dev/dc/dcphy.c 61110 2000-05-31 05:40:53Z wpaul $";
76#endif
77
78#define DC_SETBIT(sc, reg, x) \
79 CSR_WRITE_4(sc, reg, \
80 CSR_READ_4(sc, reg) | x)
81
82#define DC_CLRBIT(sc, reg, x) \
83 CSR_WRITE_4(sc, reg, \

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257 mii->mii_media_active = IFM_NONE;
258 mode = CSR_READ_4(dc_sc, DC_NETCFG);
259 mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL|
260 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL);
261
262 switch (IFM_SUBTYPE(ife->ifm_media)) {
263 case IFM_AUTO:
264 /*dcphy_reset(sc);*/
76#endif
77
78#define DC_SETBIT(sc, reg, x) \
79 CSR_WRITE_4(sc, reg, \
80 CSR_READ_4(sc, reg) | x)
81
82#define DC_CLRBIT(sc, reg, x) \
83 CSR_WRITE_4(sc, reg, \

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257 mii->mii_media_active = IFM_NONE;
258 mode = CSR_READ_4(dc_sc, DC_NETCFG);
259 mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL|
260 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL);
261
262 switch (IFM_SUBTYPE(ife->ifm_media)) {
263 case IFM_AUTO:
264 /*dcphy_reset(sc);*/
265 sc->mii_flags &= ~MIIF_DOINGAUTO;
265 (void) dcphy_auto(sc, 0);
266 break;
267 case IFM_100_T4:
268 /*
269 * XXX Not supported as a manual setting right now.
270 */
271 return (EINVAL);
272 case IFM_100_TX:

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317 return (0);
318
319 /*
320 * Is the interface even up?
321 */
322 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
323 return (0);
324
266 (void) dcphy_auto(sc, 0);
267 break;
268 case IFM_100_T4:
269 /*
270 * XXX Not supported as a manual setting right now.
271 */
272 return (EINVAL);
273 case IFM_100_TX:

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318 return (0);
319
320 /*
321 * Is the interface even up?
322 */
323 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
324 return (0);
325
325 if (sc->mii_flags & MIIF_DOINGAUTO) {
326 if (++sc->mii_ticks != 5)
327 return(0);
328 else {
329 sc->mii_ticks = 0;
330 sc->mii_flags &= ~MIIF_DOINGAUTO;
331 sc->mii_flags |= MIIF_AUTOTIMEOUT;
332 }
333 }
334
335 sc->mii_flags &= ~MIIF_DOINGAUTO;
336
337 /*
338 * Check to see if we have link. If we do, we don't
339 * need to restart the autonegotiation process. Read
340 * the BMSR twice in case it's latched.
341 */
342 reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
343 (DC_TSTAT_LS10|DC_TSTAT_LS100);
344
326 reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
327 (DC_TSTAT_LS10|DC_TSTAT_LS100);
328
345 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX &&
346 !(reg & DC_TSTAT_LS100)) {
347 if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
348 sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
349 break;
350 } else
351 return(0);
352 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
353 !(reg & DC_TSTAT_LS10)) {
354 if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
355 sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
356 break;
357 } else
358 return(0);
359 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE &&
360 (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))) {
361 if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
362 sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
363 break;
364 } else
365 return(0);
366 } else if (CSR_READ_4(dc_sc, DC_ISR) & DC_ISR_LINKGOOD) {
367 if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
368 sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
369 break;
370 } else
371 return(0);
372 }
329 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
330 return(0);
373
331
332 /*
333 * Only retry autonegotiation every 5 seconds.
334 */
335 if (++sc->mii_ticks != 50)
336 return (0);
337
374 sc->mii_ticks = 0;
338 sc->mii_ticks = 0;
375 /*dcphy_reset(sc);*/
339 /*if (DC_IS_INTEL(dc_sc))*/
340 sc->mii_flags &= ~MIIF_DOINGAUTO;
376 dcphy_auto(sc, 0);
377
378 break;
379 }
380
381 /* Update the media status. */
382 dcphy_status(sc);
383

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389 return (0);
390}
391
392void
393dcphy_status(sc)
394 struct mii_softc *sc;
395{
396 struct mii_data *mii = sc->mii_pdata;
341 dcphy_auto(sc, 0);
342
343 break;
344 }
345
346 /* Update the media status. */
347 dcphy_status(sc);
348

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354 return (0);
355}
356
357void
358dcphy_status(sc)
359 struct mii_softc *sc;
360{
361 struct mii_data *mii = sc->mii_pdata;
397 int reg, anlpar;
362 int reg, anlpar, tstat = 0;
398 struct dc_softc *dc_sc;
399
400 dc_sc = mii->mii_ifp->if_softc;
401
402 mii->mii_media_status = IFM_AVALID;
403 mii->mii_media_active = IFM_ETHER;
404
405 reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
363 struct dc_softc *dc_sc;
364
365 dc_sc = mii->mii_ifp->if_softc;
366
367 mii->mii_media_status = IFM_AVALID;
368 mii->mii_media_active = IFM_ETHER;
369
370 reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
406 (DC_TSTAT_LS10|DC_TSTAT_LS100);
371 (DC_TSTAT_LS10|DC_TSTAT_LS100);
407
408 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
409 mii->mii_media_status |= IFM_ACTIVE;
410
372
373 if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
374 mii->mii_media_status |= IFM_ACTIVE;
375
411 if (sc->mii_flags & MIIF_DOINGAUTO) {
412 mii->mii_media_active |= IFM_NONE;
413 return;
414 }
415
416 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL &&
417 CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT) {
376 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
418 /* Erg, still trying, I guess... */
377 /* Erg, still trying, I guess... */
419 if ((CSR_READ_4(dc_sc, DC_10BTSTAT) &
420 DC_ASTAT_AUTONEGCMP) != DC_ASTAT_AUTONEGCMP) {
378 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
379 if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {
380 if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&
381 (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)
382 goto skip;
421 mii->mii_media_active |= IFM_NONE;
422 return;
423 }
424
383 mii->mii_media_active |= IFM_NONE;
384 return;
385 }
386
425 if (CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_LP_CAN_NWAY) {
426 anlpar = CSR_READ_4(dc_sc, DC_10BTSTAT) >> 16;
387 if (tstat & DC_TSTAT_LP_CAN_NWAY) {
388 anlpar = tstat >> 16;
427 if (anlpar & ANLPAR_T4 &&
428 sc->mii_capabilities & BMSR_100TXHDX)
429 mii->mii_media_active |= IFM_100_T4;
430 else if (anlpar & ANLPAR_TX_FD &&
389 if (anlpar & ANLPAR_T4 &&
390 sc->mii_capabilities & BMSR_100TXHDX)
391 mii->mii_media_active |= IFM_100_T4;
392 else if (anlpar & ANLPAR_TX_FD &&
431 sc->mii_capabilities & BMSR_100TXHDX)
393 sc->mii_capabilities & BMSR_100TXFDX)
432 mii->mii_media_active |= IFM_100_TX|IFM_FDX;
433 else if (anlpar & ANLPAR_TX &&
434 sc->mii_capabilities & BMSR_100TXHDX)
435 mii->mii_media_active |= IFM_100_TX;
436 else if (anlpar & ANLPAR_10_FD)
437 mii->mii_media_active |= IFM_10_T|IFM_FDX;
438 else if (anlpar & ANLPAR_10)
439 mii->mii_media_active |= IFM_10_T;

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458 mii->mii_media_active |= IFM_10_T;
459 else
460 mii->mii_media_active |= IFM_NONE;
461 if (DC_IS_INTEL(dc_sc))
462 DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
463 return;
464 }
465
394 mii->mii_media_active |= IFM_100_TX|IFM_FDX;
395 else if (anlpar & ANLPAR_TX &&
396 sc->mii_capabilities & BMSR_100TXHDX)
397 mii->mii_media_active |= IFM_100_TX;
398 else if (anlpar & ANLPAR_10_FD)
399 mii->mii_media_active |= IFM_10_T|IFM_FDX;
400 else if (anlpar & ANLPAR_10)
401 mii->mii_media_active |= IFM_10_T;

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420 mii->mii_media_active |= IFM_10_T;
421 else
422 mii->mii_media_active |= IFM_NONE;
423 if (DC_IS_INTEL(dc_sc))
424 DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
425 return;
426 }
427
428skip:
466 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SCRAMBLER)
467 mii->mii_media_active |= IFM_100_TX;
468 else
469 mii->mii_media_active |= IFM_10_T;
470 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
471 mii->mii_media_active |= IFM_FDX;
472
473 return;

--- 67 unchanged lines hidden --- 		429 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SCRAMBLER)
430 mii->mii_media_active |= IFM_100_TX;
431 else
432 mii->mii_media_active |= IFM_10_T;
433 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
434 mii->mii_media_active |= IFM_FDX;
435
436 return;

--- 67 unchanged lines hidden ---