1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28
|
29$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $
|
| 29$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170869 2007-06-17 04:33:38Z kmacy $ |
30
31***************************************************************************/
32
33
34
35#ifndef _CXGB_ADAPTER_H_
36#define _CXGB_ADAPTER_H_
37
38#include <sys/cdefs.h>
|
39__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $");
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| 39__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170869 2007-06-17 04:33:38Z kmacy $"); |
40
41#include <sys/lock.h>
42#include <sys/mutex.h>
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| 43#include <sys/sx.h> |
44#include <sys/rman.h>
45#include <sys/mbuf.h>
46#include <sys/socket.h>
47#include <sys/sockio.h>
48
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_media.h>
52
53#include <machine/bus.h>
54#include <machine/resource.h>
55#include <sys/bus_dma.h>
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pcivar.h>
58
59#ifdef CONFIG_DEFINED
60#include <cxgb_osdep.h>
61#include <ulp/toecore/toedev.h>
62#include <sys/mbufq.h>
63#else
64#include <dev/cxgb/cxgb_osdep.h>
65#include <dev/cxgb/sys/mbufq.h>
66#include <dev/cxgb/ulp/toecore/toedev.h>
67#endif
68
|
69#define USE_SX
70 |
71struct adapter;
72struct sge_qset;
73extern int cxgb_debug;
74
|
75#ifdef DEBUG_LOCKING
76#define MTX_INIT(lock, lockname, class, flags) \
77 do { \
78 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
79 mtx_init((lock), lockname, class, flags); \
80 } while (0)
81
82#define MTX_DESTROY(lock) \
83 do { \
84 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
85 mtx_destroy((lock)); \
86 } while (0)
87
88#define SX_INIT(lock, lockname) \
89 do { \
90 printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \
91 sx_init((lock), lockname); \
92 } while (0)
93
94#define SX_DESTROY(lock) \
95 do { \
96 printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \
97 sx_destroy((lock)); \
98 } while (0)
99#else
100#define MTX_INIT mtx_init
101#define MTX_DESTROY mtx_destroy
102#define SX_INIT sx_init
103#define SX_DESTROY sx_destroy
104#endif
105 |
106struct port_info {
107 struct adapter *adapter;
108 struct ifnet *ifp;
109 int if_flags;
110 const struct port_type_info *port_type;
111 struct cphy phy;
112 struct cmac mac;
113 struct link_config link_config;
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80 struct ifmedia media;
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114 struct ifmedia media;
115#ifdef USE_SX
116 struct sx lock;
117#else |
118 struct mtx lock;
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82
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| 119#endif |
120 int port;
121 uint8_t hw_addr[ETHER_ADDR_LEN];
122 uint8_t nqsets;
123 uint8_t first_qset;
124 struct taskqueue *tq;
125 struct task start_task;
126 struct task timer_reclaim_task;
127 struct cdev *port_cdev;
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128
129#define PORT_NAME_LEN 32
130#define TASKQ_NAME_LEN 32
131 char lockbuf[PORT_NAME_LEN];
132 char taskqbuf[TASKQ_NAME_LEN]; |
133};
134
135enum { /* adapter flags */
136 FULL_INIT_DONE = (1 << 0),
137 USING_MSI = (1 << 1),
138 USING_MSIX = (1 << 2),
139 QUEUES_BOUND = (1 << 3),
140 FW_UPTODATE = (1 << 4),
141};
142
143
144#define FL_Q_SIZE 4096
145#define JUMBO_Q_SIZE 512
146#define RSPQ_Q_SIZE 1024
147#define TX_ETH_Q_SIZE 1024
148
|
149
150 |
151/*
152 * Types of Tx queues in each queue set. Order here matters, do not change.
153 * XXX TOE is not implemented yet, so the extra queues are just placeholders.
154 */
155enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
156
157
158/* careful, the following are set on priv_flags and must not collide with
159 * IFF_ flags!
160 */
161enum {
162 LRO_ACTIVE = (1 << 8),
163};
164
165/* Max concurrent LRO sessions per queue set */
166#define MAX_LRO_SES 8
167
168struct t3_lro_session {
169 struct mbuf *head;
170 struct mbuf *tail;
171 uint32_t seq;
172 uint16_t ip_len;
173 uint16_t vtag;
174 uint8_t npkts;
175};
176
177struct lro_state {
178 unsigned short enabled;
179 unsigned short active_idx;
180 unsigned int nactive;
181 struct t3_lro_session sess[MAX_LRO_SES];
182};
183
184#define RX_BUNDLE_SIZE 8
185
186struct rsp_desc;
187
188struct sge_rspq {
189 uint32_t credits;
190 uint32_t size;
191 uint32_t cidx;
192 uint32_t gen;
193 uint32_t polling;
194 uint32_t holdoff_tmr;
195 uint32_t next_holdoff;
196 uint32_t imm_data;
197 struct rsp_desc *desc;
198 uint32_t cntxt_id;
199 struct mtx lock;
200 struct mbuf *rx_head; /* offload packet receive queue head */
201 struct mbuf *rx_tail; /* offload packet receive queue tail */
202
203 uint32_t offload_pkts;
204 uint32_t offload_bundles;
205 uint32_t pure_rsps;
206 uint32_t unhandled_irqs;
207
208 bus_addr_t phys_addr;
209 bus_dma_tag_t desc_tag;
210 bus_dmamap_t desc_map;
211 struct mbuf *m;
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212#define RSPQ_NAME_LEN 32
213 char lockbuf[RSPQ_NAME_LEN];
214 |
215};
216
217struct rx_desc;
218struct rx_sw_desc;
219
220struct sge_fl {
221 uint32_t buf_size;
222 uint32_t credits;
223 uint32_t size;
224 uint32_t cidx;
225 uint32_t pidx;
226 uint32_t gen;
227 struct rx_desc *desc;
228 struct rx_sw_desc *sdesc;
229 bus_addr_t phys_addr;
230 uint32_t cntxt_id;
231 uint64_t empty;
232 bus_dma_tag_t desc_tag;
233 bus_dmamap_t desc_map;
234 bus_dma_tag_t entry_tag;
235 uma_zone_t zone;
236 int type;
237};
238
239struct tx_desc;
240struct tx_sw_desc;
241
242struct sge_txq {
243 uint64_t flags;
244 uint32_t in_use;
245 uint32_t size;
246 uint32_t processed;
247 uint32_t cleaned;
248 uint32_t stop_thres;
249 uint32_t cidx;
250 uint32_t pidx;
251 uint32_t gen;
252 uint32_t unacked;
253 struct tx_desc *desc;
254 struct tx_sw_desc *sdesc;
255 uint32_t token;
256 bus_addr_t phys_addr;
257 struct task qresume_tsk;
258 uint32_t cntxt_id;
259 uint64_t stops;
260 uint64_t restarts;
261 bus_dma_tag_t desc_tag;
262 bus_dmamap_t desc_map;
263 bus_dma_tag_t entry_tag;
264 struct mbuf_head sendq;
265 struct mtx lock;
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266#define TXQ_NAME_LEN 32
267 char lockbuf[TXQ_NAME_LEN]; |
268};
269
270
271enum {
272 SGE_PSTAT_TSO, /* # of TSO requests */
273 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
274 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
275 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
276 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
277 SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */
278 SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */
279 SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */
280};
281
282#define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1)
283
284struct sge_qset {
285 struct sge_rspq rspq;
286 struct sge_fl fl[SGE_RXQ_PER_SET];
287 struct lro_state lro;
288 struct sge_txq txq[SGE_TXQ_PER_SET];
289 uint32_t txq_stopped; /* which Tx queues are stopped */
290 uint64_t port_stats[SGE_PSTAT_MAX];
291 struct port_info *port;
292 int idx; /* qset # */
293};
294
295struct sge {
296 struct sge_qset qs[SGE_QSETS];
297 struct mtx reg_lock;
298};
299
300struct adapter {
301 device_t dev;
302 int flags;
303 TAILQ_ENTRY(adapter) adapter_entry;
304
305 /* PCI register resources */
306 uint32_t regs_rid;
307 struct resource *regs_res;
308 bus_space_handle_t bh;
309 bus_space_tag_t bt;
310 bus_size_t mmio_len;
311 uint32_t link_width;
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263
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312
313 /* DMA resources */
314 bus_dma_tag_t parent_dmat;
315 bus_dma_tag_t rx_dmat;
316 bus_dma_tag_t rx_jumbo_dmat;
317 bus_dma_tag_t tx_dmat;
318
319 /* Interrupt resources */
320 struct resource *irq_res;
321 int irq_rid;
322 void *intr_tag;
323
324 uint32_t msix_regs_rid;
325 struct resource *msix_regs_res;
326
327 struct resource *msix_irq_res[SGE_QSETS];
328 int msix_irq_rid[SGE_QSETS];
329 void *msix_intr_tag[SGE_QSETS];
330
331 /* Tasks */
332 struct task ext_intr_task;
333 struct task slow_intr_task;
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| 334 struct task tick_task; |
335 struct task process_responses_task;
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287 struct task mr_refresh_task;
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336 struct taskqueue *tq;
337 struct callout cxgb_tick_ch;
338 struct callout sge_timer_ch;
339
340 /* Register lock for use by the hardware layer */
341 struct mtx mdio_lock;
342 struct mtx elmer_lock;
343
344 /* Bookkeeping for the hardware layer */
345 struct adapter_params params;
346 unsigned int slow_intr_mask;
347 unsigned long irq_stats[IRQ_NUM_STATS];
348
349 struct sge sge;
350 struct mc7 pmrx;
351 struct mc7 pmtx;
352 struct mc7 cm;
353 struct mc5 mc5;
354
355 struct port_info port[MAX_NPORTS];
356 device_t portdev[MAX_NPORTS];
357 struct toedev tdev;
358 char fw_version[64];
359 uint32_t open_device_map;
360 uint32_t registered_device_map;
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361#ifdef USE_SX
362 struct sx lock;
363#else |
364 struct mtx lock;
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| 365#endif |
366 driver_intr_t *cxgb_intr;
367 int msi_count;
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368
369#define ADAPTER_LOCK_NAME_LEN 32
370 char lockbuf[ADAPTER_LOCK_NAME_LEN];
371 char reglockbuf[ADAPTER_LOCK_NAME_LEN];
372 char mdiolockbuf[ADAPTER_LOCK_NAME_LEN];
373 char elmerlockbuf[ADAPTER_LOCK_NAME_LEN]; |
374};
375
376struct t3_rx_mode {
377
378 uint32_t idx;
379 struct port_info *port;
380};
381
382
383#define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
384#define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
385#define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
386#define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
387
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330#define PORT_LOCK(port) mtx_lock(&(port)->lock);
331#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
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388
|
389#ifdef USE_SX
390#define PORT_LOCK(port) sx_xlock(&(port)->lock);
391#define PORT_UNLOCK(port) sx_xunlock(&(port)->lock);
392#define PORT_LOCK_INIT(port, name) SX_INIT(&(port)->lock, name)
393#define PORT_LOCK_DEINIT(port) SX_DESTROY(&(port)->lock)
394#define PORT_LOCK_ASSERT_OWNED(port) sx_assert(&(port)->lock, SA_LOCKED)
395
396#define ADAPTER_LOCK(adap) sx_xlock(&(adap)->lock);
397#define ADAPTER_UNLOCK(adap) sx_xunlock(&(adap)->lock);
398#define ADAPTER_LOCK_INIT(adap, name) SX_INIT(&(adap)->lock, name)
399#define ADAPTER_LOCK_DEINIT(adap) SX_DESTROY(&(adap)->lock)
400#define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) sx_assert(&(adap)->lock, SA_UNLOCKED)
401#else
402#define PORT_LOCK(port) mtx_lock(&(port)->lock);
403#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
404#define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF)
405#define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock)
406#define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED)
407 |
408#define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
409#define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
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410#define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF)
411#define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock)
412#define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MO_NOTOWNED)
413#endif |
414
415
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337
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416static __inline uint32_t
417t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
418{
419 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
420}
421
422static __inline void
423t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
424{
425 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
426}
427
428static __inline void
429t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
430{
431 *val = pci_read_config(adapter->dev, reg, 4);
432}
433
434static __inline void
435t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
436{
437 pci_write_config(adapter->dev, reg, val, 4);
438}
439
440static __inline void
441t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
442{
443 *val = pci_read_config(adapter->dev, reg, 2);
444}
445
446static __inline void
447t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
448{
449 pci_write_config(adapter->dev, reg, val, 2);
450}
451
452static __inline uint8_t *
453t3_get_next_mcaddr(struct t3_rx_mode *rm)
454{
455 uint8_t *macaddr = NULL;
456
457 if (rm->idx == 0)
458 macaddr = rm->port->hw_addr;
459
460 rm->idx++;
461 return (macaddr);
462}
463
464static __inline void
465t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
466{
467 rm->idx = 0;
468 rm->port = port;
469}
470
471static __inline struct port_info *
472adap2pinfo(struct adapter *adap, int idx)
473{
474 return &adap->port[idx];
475}
476
477int t3_os_find_pci_capability(adapter_t *adapter, int cap);
478int t3_os_pci_save_state(struct adapter *adapter);
479int t3_os_pci_restore_state(struct adapter *adapter);
480void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
481 int speed, int duplex, int fc);
482void t3_sge_err_intr_handler(adapter_t *adapter);
483int t3_offload_tx(struct toedev *, struct mbuf *);
484void t3_os_ext_intr_handler(adapter_t *adapter);
485void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
486int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
487
488
489int t3_sge_alloc(struct adapter *);
490int t3_sge_free(struct adapter *);
491int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
492 int, struct port_info *);
493void t3_free_sge_resources(adapter_t *);
494void t3_sge_start(adapter_t *);
495void t3_sge_stop(adapter_t *);
496void t3b_intr(void *data);
497void t3_intr_msi(void *data);
498void t3_intr_msix(void *data);
499int t3_encap(struct port_info *, struct mbuf **);
500
501int t3_sge_init_adapter(adapter_t *);
502int t3_sge_init_port(struct port_info *);
503void t3_sge_deinit_sw(adapter_t *);
504
505void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct mbuf *m,
506 int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro);
507void t3_rx_eth(struct port_info *p, struct sge_rspq *rq, struct mbuf *m, int ethpad);
508void t3_lro_flush(adapter_t *adap, struct sge_qset *qs, struct lro_state *state);
509
510void t3_add_sysctls(adapter_t *sc);
511int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
512 unsigned char *data);
513void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
514/*
515 * XXX figure out how we can return this to being private to sge
516 */
517#define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
518
519#define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
520
521static __inline struct sge_qset *
522fl_to_qset(struct sge_fl *q, int qidx)
523{
524 return container_of(q, struct sge_qset, fl[qidx]);
525}
526
527static __inline struct sge_qset *
528rspq_to_qset(struct sge_rspq *q)
529{
530 return container_of(q, struct sge_qset, rspq);
531}
532
533static __inline struct sge_qset *
534txq_to_qset(struct sge_txq *q, int qidx)
535{
536 return container_of(q, struct sge_qset, txq[qidx]);
537}
538
539static __inline struct adapter *
540tdev2adap(struct toedev *d)
541{
542 return container_of(d, struct adapter, tdev);
543}
544
545#undef container_of
546
547#define OFFLOAD_DEVMAP_BIT 15
548static inline int offload_running(adapter_t *adapter)
549{
550 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
551}
552
553
554#endif
|