1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28
29$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $
30
31***************************************************************************/
32
33
34
35#ifndef _CXGB_ADAPTER_H_
36#define _CXGB_ADAPTER_H_
37
38#include <sys/cdefs.h>
39__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $");
40
41#include <sys/lock.h>
42#include <sys/mutex.h>
43#include <sys/rman.h>
44#include <sys/mbuf.h>
45#include <sys/socket.h>
46#include <sys/sockio.h>
47
48#include <net/ethernet.h>
49#include <net/if.h>
50#include <net/if_media.h>
51
52#include <machine/bus.h>
53#include <machine/resource.h>
54#include <sys/bus_dma.h>
55#include <dev/pci/pcireg.h>
56#include <dev/pci/pcivar.h>
57
58#ifdef CONFIG_DEFINED
59#include <cxgb_osdep.h>
60#include <ulp/toecore/toedev.h>
61#include <sys/mbufq.h>
62#else
63#include <dev/cxgb/cxgb_osdep.h>
64#include <dev/cxgb/sys/mbufq.h>
65#include <dev/cxgb/ulp/toecore/toedev.h>
66#endif
67
68struct adapter;
69struct sge_qset;
70extern int cxgb_debug;
71
72struct port_info {
73 struct adapter *adapter;
74 struct ifnet *ifp;
75 int if_flags;
76 const struct port_type_info *port_type;
77 struct cphy phy;
78 struct cmac mac;
79 struct link_config link_config;
80 struct ifmedia media;
81 struct mtx lock;
82
83 int port;
84 uint8_t hw_addr[ETHER_ADDR_LEN];
85 uint8_t nqsets;
86 uint8_t first_qset;
87 struct taskqueue *tq;
88 struct task start_task;
89 struct task timer_reclaim_task;
90 struct cdev *port_cdev;
91};
92
93enum { /* adapter flags */
94 FULL_INIT_DONE = (1 << 0),
95 USING_MSI = (1 << 1),
96 USING_MSIX = (1 << 2),
97 QUEUES_BOUND = (1 << 3),
98 FW_UPTODATE = (1 << 4),
99};
100
101
102#define FL_Q_SIZE 4096
103#define JUMBO_Q_SIZE 512
104#define RSPQ_Q_SIZE 1024
105#define TX_ETH_Q_SIZE 1024
106
107/*
108 * Types of Tx queues in each queue set. Order here matters, do not change.
109 * XXX TOE is not implemented yet, so the extra queues are just placeholders.
110 */
111enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
112
113
114/* careful, the following are set on priv_flags and must not collide with
115 * IFF_ flags!
116 */
117enum {
118 LRO_ACTIVE = (1 << 8),
119};
120
121/* Max concurrent LRO sessions per queue set */
122#define MAX_LRO_SES 8
123
124struct t3_lro_session {
125 struct mbuf *head;
126 struct mbuf *tail;
127 uint32_t seq;
128 uint16_t ip_len;
129 uint16_t vtag;
130 uint8_t npkts;
131};
132
133struct lro_state {
134 unsigned short enabled;
135 unsigned short active_idx;
136 unsigned int nactive;
137 struct t3_lro_session sess[MAX_LRO_SES];
138};
139
140#define RX_BUNDLE_SIZE 8
141
142struct rsp_desc;
143
144struct sge_rspq {
145 uint32_t credits;
146 uint32_t size;
147 uint32_t cidx;
148 uint32_t gen;
149 uint32_t polling;
150 uint32_t holdoff_tmr;
151 uint32_t next_holdoff;
152 uint32_t imm_data;
153 struct rsp_desc *desc;
154 uint32_t cntxt_id;
155 struct mtx lock;
156 struct mbuf *rx_head; /* offload packet receive queue head */
157 struct mbuf *rx_tail; /* offload packet receive queue tail */
158
159 uint32_t offload_pkts;
160 uint32_t offload_bundles;
161 uint32_t pure_rsps;
162 uint32_t unhandled_irqs;
163
164 bus_addr_t phys_addr;
165 bus_dma_tag_t desc_tag;
166 bus_dmamap_t desc_map;
167 struct mbuf *m;
168};
169
170struct rx_desc;
171struct rx_sw_desc;
172
173struct sge_fl {
174 uint32_t buf_size;
175 uint32_t credits;
176 uint32_t size;
177 uint32_t cidx;
178 uint32_t pidx;
179 uint32_t gen;
180 struct rx_desc *desc;
181 struct rx_sw_desc *sdesc;
182 bus_addr_t phys_addr;
183 uint32_t cntxt_id;
184 uint64_t empty;
185 bus_dma_tag_t desc_tag;
186 bus_dmamap_t desc_map;
187 bus_dma_tag_t entry_tag;
188 uma_zone_t zone;
189 int type;
190};
191
192struct tx_desc;
193struct tx_sw_desc;
194
195struct sge_txq {
196 uint64_t flags;
197 uint32_t in_use;
198 uint32_t size;
199 uint32_t processed;
200 uint32_t cleaned;
201 uint32_t stop_thres;
202 uint32_t cidx;
203 uint32_t pidx;
204 uint32_t gen;
205 uint32_t unacked;
206 struct tx_desc *desc;
207 struct tx_sw_desc *sdesc;
208 uint32_t token;
209 bus_addr_t phys_addr;
210 struct task qresume_tsk;
211 uint32_t cntxt_id;
212 uint64_t stops;
213 uint64_t restarts;
214 bus_dma_tag_t desc_tag;
215 bus_dmamap_t desc_map;
216 bus_dma_tag_t entry_tag;
217 struct mbuf_head sendq;
218 struct mtx lock;
219};
220
221
222enum {
223 SGE_PSTAT_TSO, /* # of TSO requests */
224 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
225 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
226 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
227 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
228 SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */
229 SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */
230 SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */
231};
232
233#define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1)
234
235struct sge_qset {
236 struct sge_rspq rspq;
237 struct sge_fl fl[SGE_RXQ_PER_SET];
238 struct lro_state lro;
239 struct sge_txq txq[SGE_TXQ_PER_SET];
240 uint32_t txq_stopped; /* which Tx queues are stopped */
241 uint64_t port_stats[SGE_PSTAT_MAX];
242 struct port_info *port;
243 int idx; /* qset # */
244};
245
246struct sge {
247 struct sge_qset qs[SGE_QSETS];
248 struct mtx reg_lock;
249};
250
251struct adapter {
252 device_t dev;
253 int flags;
254 TAILQ_ENTRY(adapter) adapter_entry;
255
256 /* PCI register resources */
257 uint32_t regs_rid;
258 struct resource *regs_res;
259 bus_space_handle_t bh;
260 bus_space_tag_t bt;
261 bus_size_t mmio_len;
262 uint32_t link_width;
263
264
265 /* DMA resources */
266 bus_dma_tag_t parent_dmat;
267 bus_dma_tag_t rx_dmat;
268 bus_dma_tag_t rx_jumbo_dmat;
269 bus_dma_tag_t tx_dmat;
270
271 /* Interrupt resources */
272 struct resource *irq_res;
273 int irq_rid;
274 void *intr_tag;
275
276 uint32_t msix_regs_rid;
277 struct resource *msix_regs_res;
278
279 struct resource *msix_irq_res[SGE_QSETS];
280 int msix_irq_rid[SGE_QSETS];
281 void *msix_intr_tag[SGE_QSETS];
282
283 /* Tasks */
284 struct task ext_intr_task;
285 struct task slow_intr_task;
286 struct task process_responses_task;
287 struct task mr_refresh_task;
288 struct taskqueue *tq;
289 struct callout cxgb_tick_ch;
290 struct callout sge_timer_ch;
291
292 /* Register lock for use by the hardware layer */
293 struct mtx mdio_lock;
294 struct mtx elmer_lock;
295
296 /* Bookkeeping for the hardware layer */
297 struct adapter_params params;
298 unsigned int slow_intr_mask;
299 unsigned long irq_stats[IRQ_NUM_STATS];
300
301 struct sge sge;
302 struct mc7 pmrx;
303 struct mc7 pmtx;
304 struct mc7 cm;
305 struct mc5 mc5;
306
307 struct port_info port[MAX_NPORTS];
308 device_t portdev[MAX_NPORTS];
309 struct toedev tdev;
310 char fw_version[64];
311 uint32_t open_device_map;
312 uint32_t registered_device_map;
313 struct mtx lock;
314 driver_intr_t *cxgb_intr;
315 int msi_count;
316};
317
318struct t3_rx_mode {
319
320 uint32_t idx;
321 struct port_info *port;
322};
323
324
325#define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
326#define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
327#define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
328#define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
329
330#define PORT_LOCK(port) mtx_lock(&(port)->lock);
331#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
332
333#define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
334#define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
335
336
337
338static __inline uint32_t
339t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
340{
341 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
342}
343
344static __inline void
345t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
346{
347 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
348}
349
350static __inline void
351t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
352{
353 *val = pci_read_config(adapter->dev, reg, 4);
354}
355
356static __inline void
357t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
358{
359 pci_write_config(adapter->dev, reg, val, 4);
360}
361
362static __inline void
363t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
364{
365 *val = pci_read_config(adapter->dev, reg, 2);
366}
367
368static __inline void
369t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
370{
371 pci_write_config(adapter->dev, reg, val, 2);
372}
373
374static __inline uint8_t *
375t3_get_next_mcaddr(struct t3_rx_mode *rm)
376{
377 uint8_t *macaddr = NULL;
378
379 if (rm->idx == 0)
380 macaddr = rm->port->hw_addr;
381
382 rm->idx++;
383 return (macaddr);
384}
385
386static __inline void
387t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
388{
389 rm->idx = 0;
390 rm->port = port;
391}
392
393static __inline struct port_info *
394adap2pinfo(struct adapter *adap, int idx)
395{
396 return &adap->port[idx];
397}
398
399int t3_os_find_pci_capability(adapter_t *adapter, int cap);
400int t3_os_pci_save_state(struct adapter *adapter);
401int t3_os_pci_restore_state(struct adapter *adapter);
402void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
403 int speed, int duplex, int fc);
404void t3_sge_err_intr_handler(adapter_t *adapter);
405int t3_offload_tx(struct toedev *, struct mbuf *);
406void t3_os_ext_intr_handler(adapter_t *adapter);
407void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
408int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
409
410
411int t3_sge_alloc(struct adapter *);
412int t3_sge_free(struct adapter *);
413int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
414 int, struct port_info *);
415void t3_free_sge_resources(adapter_t *);
416void t3_sge_start(adapter_t *);
417void t3_sge_stop(adapter_t *);
418void t3b_intr(void *data);
419void t3_intr_msi(void *data);
420void t3_intr_msix(void *data);
421int t3_encap(struct port_info *, struct mbuf **);
422
423int t3_sge_init_adapter(adapter_t *);
424int t3_sge_init_port(struct port_info *);
425void t3_sge_deinit_sw(adapter_t *);
426
427void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct mbuf *m,
428 int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro);
429void t3_rx_eth(struct port_info *p, struct sge_rspq *rq, struct mbuf *m, int ethpad);
430void t3_lro_flush(adapter_t *adap, struct sge_qset *qs, struct lro_state *state);
431
432void t3_add_sysctls(adapter_t *sc);
433int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
434 unsigned char *data);
435void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
436/*
437 * XXX figure out how we can return this to being private to sge
438 */
439#define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
440
441#define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
442
443static __inline struct sge_qset *
444fl_to_qset(struct sge_fl *q, int qidx)
445{
446 return container_of(q, struct sge_qset, fl[qidx]);
447}
448
449static __inline struct sge_qset *
450rspq_to_qset(struct sge_rspq *q)
451{
452 return container_of(q, struct sge_qset, rspq);
453}
454
455static __inline struct sge_qset *
456txq_to_qset(struct sge_txq *q, int qidx)
457{
458 return container_of(q, struct sge_qset, txq[qidx]);
459}
460
461static __inline struct adapter *
462tdev2adap(struct toedev *d)
463{
464 return container_of(d, struct adapter, tdev);
465}
466
467#undef container_of
468
469#define OFFLOAD_DEVMAP_BIT 15
470static inline int offload_running(adapter_t *adapter)
471{
472 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
473}
474
475
476#endif
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28
29$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $
30
31***************************************************************************/
32
33
34
35#ifndef _CXGB_ADAPTER_H_
36#define _CXGB_ADAPTER_H_
37
38#include <sys/cdefs.h>
39__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_adapter.h 170654 2007-06-13 05:36:00Z kmacy $");
40
41#include <sys/lock.h>
42#include <sys/mutex.h>
43#include <sys/rman.h>
44#include <sys/mbuf.h>
45#include <sys/socket.h>
46#include <sys/sockio.h>
47
48#include <net/ethernet.h>
49#include <net/if.h>
50#include <net/if_media.h>
51
52#include <machine/bus.h>
53#include <machine/resource.h>
54#include <sys/bus_dma.h>
55#include <dev/pci/pcireg.h>
56#include <dev/pci/pcivar.h>
57
58#ifdef CONFIG_DEFINED
59#include <cxgb_osdep.h>
60#include <ulp/toecore/toedev.h>
61#include <sys/mbufq.h>
62#else
63#include <dev/cxgb/cxgb_osdep.h>
64#include <dev/cxgb/sys/mbufq.h>
65#include <dev/cxgb/ulp/toecore/toedev.h>
66#endif
67
68struct adapter;
69struct sge_qset;
70extern int cxgb_debug;
71
72struct port_info {
73 struct adapter *adapter;
74 struct ifnet *ifp;
75 int if_flags;
76 const struct port_type_info *port_type;
77 struct cphy phy;
78 struct cmac mac;
79 struct link_config link_config;
80 struct ifmedia media;
81 struct mtx lock;
82
83 int port;
84 uint8_t hw_addr[ETHER_ADDR_LEN];
85 uint8_t nqsets;
86 uint8_t first_qset;
87 struct taskqueue *tq;
88 struct task start_task;
89 struct task timer_reclaim_task;
90 struct cdev *port_cdev;
91};
92
93enum { /* adapter flags */
94 FULL_INIT_DONE = (1 << 0),
95 USING_MSI = (1 << 1),
96 USING_MSIX = (1 << 2),
97 QUEUES_BOUND = (1 << 3),
98 FW_UPTODATE = (1 << 4),
99};
100
101
102#define FL_Q_SIZE 4096
103#define JUMBO_Q_SIZE 512
104#define RSPQ_Q_SIZE 1024
105#define TX_ETH_Q_SIZE 1024
106
107/*
108 * Types of Tx queues in each queue set. Order here matters, do not change.
109 * XXX TOE is not implemented yet, so the extra queues are just placeholders.
110 */
111enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
112
113
114/* careful, the following are set on priv_flags and must not collide with
115 * IFF_ flags!
116 */
117enum {
118 LRO_ACTIVE = (1 << 8),
119};
120
121/* Max concurrent LRO sessions per queue set */
122#define MAX_LRO_SES 8
123
124struct t3_lro_session {
125 struct mbuf *head;
126 struct mbuf *tail;
127 uint32_t seq;
128 uint16_t ip_len;
129 uint16_t vtag;
130 uint8_t npkts;
131};
132
133struct lro_state {
134 unsigned short enabled;
135 unsigned short active_idx;
136 unsigned int nactive;
137 struct t3_lro_session sess[MAX_LRO_SES];
138};
139
140#define RX_BUNDLE_SIZE 8
141
142struct rsp_desc;
143
144struct sge_rspq {
145 uint32_t credits;
146 uint32_t size;
147 uint32_t cidx;
148 uint32_t gen;
149 uint32_t polling;
150 uint32_t holdoff_tmr;
151 uint32_t next_holdoff;
152 uint32_t imm_data;
153 struct rsp_desc *desc;
154 uint32_t cntxt_id;
155 struct mtx lock;
156 struct mbuf *rx_head; /* offload packet receive queue head */
157 struct mbuf *rx_tail; /* offload packet receive queue tail */
158
159 uint32_t offload_pkts;
160 uint32_t offload_bundles;
161 uint32_t pure_rsps;
162 uint32_t unhandled_irqs;
163
164 bus_addr_t phys_addr;
165 bus_dma_tag_t desc_tag;
166 bus_dmamap_t desc_map;
167 struct mbuf *m;
168};
169
170struct rx_desc;
171struct rx_sw_desc;
172
173struct sge_fl {
174 uint32_t buf_size;
175 uint32_t credits;
176 uint32_t size;
177 uint32_t cidx;
178 uint32_t pidx;
179 uint32_t gen;
180 struct rx_desc *desc;
181 struct rx_sw_desc *sdesc;
182 bus_addr_t phys_addr;
183 uint32_t cntxt_id;
184 uint64_t empty;
185 bus_dma_tag_t desc_tag;
186 bus_dmamap_t desc_map;
187 bus_dma_tag_t entry_tag;
188 uma_zone_t zone;
189 int type;
190};
191
192struct tx_desc;
193struct tx_sw_desc;
194
195struct sge_txq {
196 uint64_t flags;
197 uint32_t in_use;
198 uint32_t size;
199 uint32_t processed;
200 uint32_t cleaned;
201 uint32_t stop_thres;
202 uint32_t cidx;
203 uint32_t pidx;
204 uint32_t gen;
205 uint32_t unacked;
206 struct tx_desc *desc;
207 struct tx_sw_desc *sdesc;
208 uint32_t token;
209 bus_addr_t phys_addr;
210 struct task qresume_tsk;
211 uint32_t cntxt_id;
212 uint64_t stops;
213 uint64_t restarts;
214 bus_dma_tag_t desc_tag;
215 bus_dmamap_t desc_map;
216 bus_dma_tag_t entry_tag;
217 struct mbuf_head sendq;
218 struct mtx lock;
219};
220
221
222enum {
223 SGE_PSTAT_TSO, /* # of TSO requests */
224 SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
225 SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */
226 SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */
227 SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */
228 SGE_PSTATS_LRO_QUEUED, /* # of LRO appended packets */
229 SGE_PSTATS_LRO_FLUSHED, /* # of LRO flushed packets */
230 SGE_PSTATS_LRO_X_STREAMS, /* # of exceeded LRO contexts */
231};
232
233#define SGE_PSTAT_MAX (SGE_PSTATS_LRO_X_STREAMS+1)
234
235struct sge_qset {
236 struct sge_rspq rspq;
237 struct sge_fl fl[SGE_RXQ_PER_SET];
238 struct lro_state lro;
239 struct sge_txq txq[SGE_TXQ_PER_SET];
240 uint32_t txq_stopped; /* which Tx queues are stopped */
241 uint64_t port_stats[SGE_PSTAT_MAX];
242 struct port_info *port;
243 int idx; /* qset # */
244};
245
246struct sge {
247 struct sge_qset qs[SGE_QSETS];
248 struct mtx reg_lock;
249};
250
251struct adapter {
252 device_t dev;
253 int flags;
254 TAILQ_ENTRY(adapter) adapter_entry;
255
256 /* PCI register resources */
257 uint32_t regs_rid;
258 struct resource *regs_res;
259 bus_space_handle_t bh;
260 bus_space_tag_t bt;
261 bus_size_t mmio_len;
262 uint32_t link_width;
263
264
265 /* DMA resources */
266 bus_dma_tag_t parent_dmat;
267 bus_dma_tag_t rx_dmat;
268 bus_dma_tag_t rx_jumbo_dmat;
269 bus_dma_tag_t tx_dmat;
270
271 /* Interrupt resources */
272 struct resource *irq_res;
273 int irq_rid;
274 void *intr_tag;
275
276 uint32_t msix_regs_rid;
277 struct resource *msix_regs_res;
278
279 struct resource *msix_irq_res[SGE_QSETS];
280 int msix_irq_rid[SGE_QSETS];
281 void *msix_intr_tag[SGE_QSETS];
282
283 /* Tasks */
284 struct task ext_intr_task;
285 struct task slow_intr_task;
286 struct task process_responses_task;
287 struct task mr_refresh_task;
288 struct taskqueue *tq;
289 struct callout cxgb_tick_ch;
290 struct callout sge_timer_ch;
291
292 /* Register lock for use by the hardware layer */
293 struct mtx mdio_lock;
294 struct mtx elmer_lock;
295
296 /* Bookkeeping for the hardware layer */
297 struct adapter_params params;
298 unsigned int slow_intr_mask;
299 unsigned long irq_stats[IRQ_NUM_STATS];
300
301 struct sge sge;
302 struct mc7 pmrx;
303 struct mc7 pmtx;
304 struct mc7 cm;
305 struct mc5 mc5;
306
307 struct port_info port[MAX_NPORTS];
308 device_t portdev[MAX_NPORTS];
309 struct toedev tdev;
310 char fw_version[64];
311 uint32_t open_device_map;
312 uint32_t registered_device_map;
313 struct mtx lock;
314 driver_intr_t *cxgb_intr;
315 int msi_count;
316};
317
318struct t3_rx_mode {
319
320 uint32_t idx;
321 struct port_info *port;
322};
323
324
325#define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock)
326#define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock)
327#define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock)
328#define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock)
329
330#define PORT_LOCK(port) mtx_lock(&(port)->lock);
331#define PORT_UNLOCK(port) mtx_unlock(&(port)->lock);
332
333#define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock);
334#define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock);
335
336
337
338static __inline uint32_t
339t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
340{
341 return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));
342}
343
344static __inline void
345t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
346{
347 bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);
348}
349
350static __inline void
351t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)
352{
353 *val = pci_read_config(adapter->dev, reg, 4);
354}
355
356static __inline void
357t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)
358{
359 pci_write_config(adapter->dev, reg, val, 4);
360}
361
362static __inline void
363t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)
364{
365 *val = pci_read_config(adapter->dev, reg, 2);
366}
367
368static __inline void
369t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)
370{
371 pci_write_config(adapter->dev, reg, val, 2);
372}
373
374static __inline uint8_t *
375t3_get_next_mcaddr(struct t3_rx_mode *rm)
376{
377 uint8_t *macaddr = NULL;
378
379 if (rm->idx == 0)
380 macaddr = rm->port->hw_addr;
381
382 rm->idx++;
383 return (macaddr);
384}
385
386static __inline void
387t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port)
388{
389 rm->idx = 0;
390 rm->port = port;
391}
392
393static __inline struct port_info *
394adap2pinfo(struct adapter *adap, int idx)
395{
396 return &adap->port[idx];
397}
398
399int t3_os_find_pci_capability(adapter_t *adapter, int cap);
400int t3_os_pci_save_state(struct adapter *adapter);
401int t3_os_pci_restore_state(struct adapter *adapter);
402void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
403 int speed, int duplex, int fc);
404void t3_sge_err_intr_handler(adapter_t *adapter);
405int t3_offload_tx(struct toedev *, struct mbuf *);
406void t3_os_ext_intr_handler(adapter_t *adapter);
407void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]);
408int t3_mgmt_tx(adapter_t *adap, struct mbuf *m);
409
410
411int t3_sge_alloc(struct adapter *);
412int t3_sge_free(struct adapter *);
413int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *,
414 int, struct port_info *);
415void t3_free_sge_resources(adapter_t *);
416void t3_sge_start(adapter_t *);
417void t3_sge_stop(adapter_t *);
418void t3b_intr(void *data);
419void t3_intr_msi(void *data);
420void t3_intr_msix(void *data);
421int t3_encap(struct port_info *, struct mbuf **);
422
423int t3_sge_init_adapter(adapter_t *);
424int t3_sge_init_port(struct port_info *);
425void t3_sge_deinit_sw(adapter_t *);
426
427void t3_rx_eth_lro(adapter_t *adap, struct sge_rspq *rq, struct mbuf *m,
428 int ethpad, uint32_t rss_hash, uint32_t rss_csum, int lro);
429void t3_rx_eth(struct port_info *p, struct sge_rspq *rq, struct mbuf *m, int ethpad);
430void t3_lro_flush(adapter_t *adap, struct sge_qset *qs, struct lro_state *state);
431
432void t3_add_sysctls(adapter_t *sc);
433int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
434 unsigned char *data);
435void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
436/*
437 * XXX figure out how we can return this to being private to sge
438 */
439#define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC))
440
441#define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field)))
442
443static __inline struct sge_qset *
444fl_to_qset(struct sge_fl *q, int qidx)
445{
446 return container_of(q, struct sge_qset, fl[qidx]);
447}
448
449static __inline struct sge_qset *
450rspq_to_qset(struct sge_rspq *q)
451{
452 return container_of(q, struct sge_qset, rspq);
453}
454
455static __inline struct sge_qset *
456txq_to_qset(struct sge_txq *q, int qidx)
457{
458 return container_of(q, struct sge_qset, txq[qidx]);
459}
460
461static __inline struct adapter *
462tdev2adap(struct toedev *d)
463{
464 return container_of(d, struct adapter, tdev);
465}
466
467#undef container_of
468
469#define OFFLOAD_DEVMAP_BIT 15
470static inline int offload_running(adapter_t *adapter)
471{
472 return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
473}
474
475
476#endif