1/*
| 1/*
|
2 * Copyright (c) 1998 HAYAKAWA Koichi. All rights reserved.
| 2 * Copyright (c) 2000,2001 Jonathan Chen.
3 * All rights reserved.
|
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
| 4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
|
8 * notice, this list of conditions and the following disclaimer.
| 9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
|
9 * 2. Redistributions in binary form must reproduce the above copyright
| 11 * 2. Redistributions in binary form must reproduce the above copyright
|
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the author.
15 * 4. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
| 12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
|
17 *
| 15 *
|
| 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
|
18 *
| 27 *
|
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
| 28 * $FreeBSD: head/sys/dev/cardbus/cardbusreg.h 67276 2000-10-18 03:25:13Z jon $
|
30 */
| 29 */
|
31/* $FreeBSD: head/sys/dev/cardbus/cardbusreg.h 53343 1999-11-18 07:21:51Z imp $ */
| |
32
| 30
|
33typedef u_int32_t cardbusreg_t;
34typedef int cardbus_intr_line_t;
| 31/*
32 * Register definitions for the Cardbus Bus
33 */
|
35
| 34
|
36typedef void *cardbus_chipset_tag_t;
37typedef int cardbus_intr_handle_t;
| |
38
| 35
|
39typedef u_int16_t cardbus_vendor_id_t;
40typedef u_int16_t cardbus_product_id_t;
| 36/* Cardbus bus constants */
37#define CARDBUS_SLOTMAX 0
38#define CARDBUS_FUNCMAX 7
|
41
| 39
|
42#define CARDBUS_ID_REG 0x00
| 40/* Cardbus configuration header registers */
41#define CARDBUS_BASE0_REG 0x10
42#define CARDBUS_BASE1_REG 0x14
43#define CARDBUS_BASE2_REG 0x18
44#define CARDBUS_BASE3_REG 0x1C
45#define CARDBUS_BASE4_REG 0x20
46#define CARDBUS_BASE5_REG 0x24
47#define CARDBUS_CIS_REG 0x28
48# define CARDBUS_CIS_ASIMASK 0x07
49# define CARDBUS_CIS_ADDRMASK 0x0ffffff8
50# define CARDBUS_CIS_ASI_TUPLE 0x00
51# define CARDBUS_CIS_ASI_BAR0 0x01
52# define CARDBUS_CIS_ASI_BAR1 0x02
53# define CARDBUS_CIS_ASI_BAR2 0x03
54# define CARDBUS_CIS_ASI_BAR3 0x04
55# define CARDBUS_CIS_ASI_BAR4 0x05
56# define CARDBUS_CIS_ASI_BAR5 0x06
57# define CARDBUS_CIS_ASI_ROM 0x07
58#define CARDBUS_ROM_REG 0x30
|
43
| 59
|
44# define CARDBUS_VENDOR_SHIFT 0
45# define CARDBUS_VENDOR_MASK 0xffff
46# define CARDBUS_VENDOR(id) \
47 (((id) >> CARDBUS_VENDOR_SHIFT) & CARDBUS_VENDOR_MASK)
| 60/* EXROM offsets for reading CIS */
61#define CARDBUS_EXROM_SIGNATURE 0x00
62#define CARDBUS_EXROM_DATA_PTR 0x18
|
48
| 63
|
49# define CARDBUS_PRODUCT_SHIFT 16
50# define CARDBUS_PRODUCT_MASK 0xffff
51# define CARDBUS_PRODUCT(id) \
52 (((id) >> CARDBUS_PRODUCT_SHIFT) & CARDBUS_PRODUCT_MASK)
| 64#define CARDBUS_EXROM_DATA_SIGNATURE 0x00 /* Signature ("PCIR") */
65#define CARDBUS_EXROM_DATA_VENDOR_ID 0x04 /* Vendor Identification */
66#define CARDBUS_EXROM_DATA_DEVICE_ID 0x06 /* Device Identification */
67#define CARDBUS_EXROM_DATA_LENGTH 0x0a /* PCI Data Structure Length */
68#define CARDBUS_EXROM_DATA_REV 0x0c /* PCI Data Structure Revision */
69#define CARDBUS_EXROM_DATA_CLASS_CODE 0x0d /* Class Code */
70#define CARDBUS_EXROM_DATA_IMAGE_LENGTH 0x10 /* Image Length */
71#define CARDBUS_EXROM_DATA_DATA_REV 0x12 /* Revision Level of Code/Data */
72#define CARDBUS_EXROM_DATA_CODE_TYPE 0x14 /* Code Type */
73#define CARDBUS_EXROM_DATA_INDICATOR 0x15 /* Indicator */
|
53
| 74
|
| 75/* useful macros */
76#define CARDBUS_CIS_ADDR(x) \
77 (CARDBUS_CIS_ADDRMASK & (x))
78#define CARDBUS_CIS_ASI_BAR(x) \
79 (((CARDBUS_CIS_ASIMASK & (x))-1)*4+0x10)
80#define CARDBUS_CIS_ASI_ROM_IMAGE(x) \
81 (((x) >> 28) & 0xf)
|
54
| 82
|
55#define CARDBUS_COMMAND_STATUS_REG 0x04
56
57# define CARDBUS_COMMAND_IO_ENABLE 0x00000001
58# define CARDBUS_COMMAND_MEM_ENABLE 0x00000002
59# define CARDBUS_COMMAND_MASTER_ENABLE 0x00000004
60
61
62#define CARDBUS_CLASS_REG 0x08
63
64/* BIST, Header Type, Latency Timer, Cache Line Size */
65#define CARDBUS_BHLC_REG 0x0c
66
67#define CARDBUS_BIST_SHIFT 24
68#define CARDBUS_BIST_MASK 0xff
69#define CARDBUS_BIST(bhlcr) \
70 (((bhlcr) >> CARDBUS_BIST_SHIFT) & CARDBUS_BIST_MASK)
71
72#define CARDBUS_HDRTYPE_SHIFT 16
73#define CARDBUS_HDRTYPE_MASK 0xff
74#define CARDBUS_HDRTYPE(bhlcr) \
75 (((bhlcr) >> CARDBUS_HDRTYPE_SHIFT) & CARDBUS_HDRTYPE_MASK)
76
77#define CARDBUS_HDRTYPE_TYPE(bhlcr) \
78 (CARDBUS_HDRTYPE(bhlcr) & 0x7f)
79#define CARDBUS_HDRTYPE_MULTIFN(bhlcr) \
80 ((CARDBUS_HDRTYPE(bhlcr) & 0x80) != 0)
81
82#define CARDBUS_LATTIMER_SHIFT 8
83#define CARDBUS_LATTIMER_MASK 0xff
84#define CARDBUS_LATTIMER(bhlcr) \
85 (((bhlcr) >> CARDBUS_LATTIMER_SHIFT) & CARDBUS_LATTIMER_MASK)
86
87#define CARDBUS_CACHELINE_SHIFT 0
88#define CARDBUS_CACHELINE_MASK 0xff
89#define CARDBUS_CACHELINE(bhlcr) \
90 (((bhlcr) >> CARDBUS_CACHELINE_SHIFT) & CARDBUS_CACHELINE_MASK)
91
92
93/* Base Resisters */
94#define CARDBUS_BASE0_REG 0x10
95#define CARDBUS_BASE1_REG 0x14
96#define CARDBUS_BASE2_REG 0x18
97#define CARDBUS_BASE3_REG 0x1C
98#define CARDBUS_BASE4_REG 0x20
99#define CARDBUS_BASE5_REG 0x24
100#define CARDBUS_CIS_REG 0x28
101# define CARDBUS_CIS_ASIMASK 0x07
102# define CARDBUS_CIS_ADDRMASK 0x0ffffff8
103
104#define CARDBUS_INTERRUPT_REG 0x3c
105
| 83#define CARDBUS_MAPREG_MEM_ADDR_MASK 0x0ffffff0
84#define CARDBUS_MAPREG_MEM_ADDR(mr) \
85 ((mr) & CARDBUS_MAPREG_MEM_ADDR_MASK)
86#define CARDBUS_MAPREG_MEM_SIZE(mr) \
87 (CARDBUS_MAPREG_MEM_ADDR(mr) & -CARDBUS_MAPREG_MEM_ADDR(mr))
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