1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 240899 2012-09-24 20:35:56Z adrian $");
32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42/*
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
45 *
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
48 */
49#include "opt_ah.h"
50#include "opt_wlan.h"
51
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysctl.h>
55#include <sys/mbuf.h>
56#include <sys/malloc.h>
57#include <sys/lock.h>
58#include <sys/mutex.h>
59#include <sys/kernel.h>
60#include <sys/socket.h>
61#include <sys/sockio.h>
62#include <sys/errno.h>
63#include <sys/callout.h>
64#include <sys/bus.h>
65#include <sys/endian.h>
66#include <sys/kthread.h>
67#include <sys/taskqueue.h>
68#include <sys/priv.h>
69#include <sys/module.h>
70#include <sys/ktr.h>
71#include <sys/smp.h> /* for mp_ncpus */
72
73#include <machine/bus.h>
74
75#include <net/if.h>
76#include <net/if_dl.h>
77#include <net/if_media.h>
78#include <net/if_types.h>
79#include <net/if_arp.h>
80#include <net/ethernet.h>
81#include <net/if_llc.h>
82
83#include <net80211/ieee80211_var.h>
84#include <net80211/ieee80211_regdomain.h>
85#ifdef IEEE80211_SUPPORT_SUPERG
86#include <net80211/ieee80211_superg.h>
87#endif
88#ifdef IEEE80211_SUPPORT_TDMA
89#include <net80211/ieee80211_tdma.h>
90#endif
91
92#include <net/bpf.h>
93
94#ifdef INET
95#include <netinet/in.h>
96#include <netinet/if_ether.h>
97#endif
98
99#include <dev/ath/if_athvar.h>
100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101#include <dev/ath/ath_hal/ah_diagcodes.h>
102
103#include <dev/ath/if_ath_debug.h>
104#include <dev/ath/if_ath_misc.h>
105#include <dev/ath/if_ath_tsf.h>
106#include <dev/ath/if_ath_tx.h>
107#include <dev/ath/if_ath_sysctl.h>
108#include <dev/ath/if_ath_led.h>
109#include <dev/ath/if_ath_keycache.h>
110#include <dev/ath/if_ath_rx.h>
111#include <dev/ath/if_ath_rx_edma.h>
112#include <dev/ath/if_ath_tx_edma.h>
113#include <dev/ath/if_ath_beacon.h>
114#include <dev/ath/if_athdfs.h>
115
116#ifdef ATH_TX99_DIAG
117#include <dev/ath/ath_tx99/ath_tx99.h>
118#endif
119
120/*
121 * ATH_BCBUF determines the number of vap's that can transmit
122 * beacons and also (currently) the number of vap's that can
123 * have unique mac addresses/bssid. When staggering beacons
124 * 4 is probably a good max as otherwise the beacons become
125 * very closely spaced and there is limited time for cab q traffic
126 * to go out. You can burst beacons instead but that is not good
127 * for stations in power save and at some point you really want
128 * another radio (and channel).
129 *
130 * The limit on the number of mac addresses is tied to our use of
131 * the U/L bit and tracking addresses in a byte; it would be
132 * worthwhile to allow more for applications like proxy sta.
133 */
134CTASSERT(ATH_BCBUF <= 8);
135
136static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
137 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
138 const uint8_t [IEEE80211_ADDR_LEN],
139 const uint8_t [IEEE80211_ADDR_LEN]);
140static void ath_vap_delete(struct ieee80211vap *);
141static void ath_init(void *);
142static void ath_stop_locked(struct ifnet *);
143static void ath_stop(struct ifnet *);
144static int ath_reset_vap(struct ieee80211vap *, u_long);
145static int ath_media_change(struct ifnet *);
146static void ath_watchdog(void *);
147static int ath_ioctl(struct ifnet *, u_long, caddr_t);
148static void ath_fatal_proc(void *, int);
149static void ath_bmiss_vap(struct ieee80211vap *);
150static void ath_bmiss_proc(void *, int);
151static void ath_key_update_begin(struct ieee80211vap *);
152static void ath_key_update_end(struct ieee80211vap *);
153static void ath_update_mcast(struct ifnet *);
154static void ath_update_promisc(struct ifnet *);
155static void ath_updateslot(struct ifnet *);
156static void ath_bstuck_proc(void *, int);
157static void ath_reset_proc(void *, int);
158static int ath_desc_alloc(struct ath_softc *);
159static void ath_desc_free(struct ath_softc *);
160static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
161 const uint8_t [IEEE80211_ADDR_LEN]);
162static void ath_node_cleanup(struct ieee80211_node *);
163static void ath_node_free(struct ieee80211_node *);
164static void ath_node_getsignal(const struct ieee80211_node *,
165 int8_t *, int8_t *);
166static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
167static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
168static int ath_tx_setup(struct ath_softc *, int, int);
169static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
170static void ath_tx_cleanup(struct ath_softc *);
171static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
172 int dosched);
173static void ath_tx_proc_q0(void *, int);
174static void ath_tx_proc_q0123(void *, int);
175static void ath_tx_proc(void *, int);
176static void ath_txq_sched_tasklet(void *, int);
177static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
178static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
179static void ath_scan_start(struct ieee80211com *);
180static void ath_scan_end(struct ieee80211com *);
181static void ath_set_channel(struct ieee80211com *);
182#ifdef ATH_ENABLE_11N
183static void ath_update_chw(struct ieee80211com *);
184#endif /* ATH_ENABLE_11N */
185static void ath_calibrate(void *);
186static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
187static void ath_setup_stationkey(struct ieee80211_node *);
188static void ath_newassoc(struct ieee80211_node *, int);
189static int ath_setregdomain(struct ieee80211com *,
190 struct ieee80211_regdomain *, int,
191 struct ieee80211_channel []);
192static void ath_getradiocaps(struct ieee80211com *, int, int *,
193 struct ieee80211_channel []);
194static int ath_getchannels(struct ath_softc *);
195
196static int ath_rate_setup(struct ath_softc *, u_int mode);
197static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
198
199static void ath_announce(struct ath_softc *);
200
201static void ath_dfs_tasklet(void *, int);
202
203#ifdef IEEE80211_SUPPORT_TDMA
204#include <dev/ath/if_ath_tdma.h>
205#endif
206
207SYSCTL_DECL(_hw_ath);
208
209/* XXX validate sysctl values */
210static int ath_longcalinterval = 30; /* long cals every 30 secs */
211SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
212 0, "long chip calibration interval (secs)");
213static int ath_shortcalinterval = 100; /* short cals every 100 ms */
214SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
215 0, "short chip calibration interval (msecs)");
216static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
217SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
218 0, "reset chip calibration results (secs)");
219static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
220SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
221 0, "ANI calibration (msecs)");
222
223int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
224SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
225 0, "rx buffers allocated");
226TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
227int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
228SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
229 0, "tx buffers allocated");
230TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
231int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
232SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RW, &ath_txbuf_mgmt,
233 0, "tx (mgmt) buffers allocated");
234TUNABLE_INT("hw.ath.txbuf_mgmt", &ath_txbuf_mgmt);
235
236int ath_bstuck_threshold = 4; /* max missed beacons */
237SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
238 0, "max missed beacon xmits before chip reset");
239
240MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
241
242void
243ath_legacy_attach_comp_func(struct ath_softc *sc)
244{
245
246 /*
247 * Special case certain configurations. Note the
248 * CAB queue is handled by these specially so don't
249 * include them when checking the txq setup mask.
250 */
251 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
252 case 0x01:
253 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
254 break;
255 case 0x0f:
256 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
257 break;
258 default:
259 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
260 break;
261 }
262}
263
264#define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
265#define HAL_MODE_HT40 \
266 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
267 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
268int
269ath_attach(u_int16_t devid, struct ath_softc *sc)
270{
271 struct ifnet *ifp;
272 struct ieee80211com *ic;
273 struct ath_hal *ah = NULL;
274 HAL_STATUS status;
275 int error = 0, i;
276 u_int wmodes;
277 uint8_t macaddr[IEEE80211_ADDR_LEN];
278 int rx_chainmask, tx_chainmask;
279
280 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
281
282 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
283 if (ifp == NULL) {
284 device_printf(sc->sc_dev, "can not if_alloc()\n");
285 error = ENOSPC;
286 goto bad;
287 }
288 ic = ifp->if_l2com;
289
290 /* set these up early for if_printf use */
291 if_initname(ifp, device_get_name(sc->sc_dev),
292 device_get_unit(sc->sc_dev));
293
294 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
295 sc->sc_eepromdata, &status);
296 if (ah == NULL) {
297 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
298 status);
299 error = ENXIO;
300 goto bad;
301 }
302 sc->sc_ah = ah;
303 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
304#ifdef ATH_DEBUG
305 sc->sc_debug = ath_debug;
306#endif
307
308 /*
309 * Setup the DMA/EDMA functions based on the current
310 * hardware support.
311 *
312 * This is required before the descriptors are allocated.
313 */
314 if (ath_hal_hasedma(sc->sc_ah)) {
315 sc->sc_isedma = 1;
316 ath_recv_setup_edma(sc);
317 ath_xmit_setup_edma(sc);
318 } else {
319 ath_recv_setup_legacy(sc);
320 ath_xmit_setup_legacy(sc);
321 }
322
323 /*
324 * Check if the MAC has multi-rate retry support.
325 * We do this by trying to setup a fake extended
326 * descriptor. MAC's that don't have support will
327 * return false w/o doing anything. MAC's that do
328 * support it will return true w/o doing anything.
329 */
330 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
331
332 /*
333 * Check if the device has hardware counters for PHY
334 * errors. If so we need to enable the MIB interrupt
335 * so we can act on stat triggers.
336 */
337 if (ath_hal_hwphycounters(ah))
338 sc->sc_needmib = 1;
339
340 /*
341 * Get the hardware key cache size.
342 */
343 sc->sc_keymax = ath_hal_keycachesize(ah);
344 if (sc->sc_keymax > ATH_KEYMAX) {
345 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
346 ATH_KEYMAX, sc->sc_keymax);
347 sc->sc_keymax = ATH_KEYMAX;
348 }
349 /*
350 * Reset the key cache since some parts do not
351 * reset the contents on initial power up.
352 */
353 for (i = 0; i < sc->sc_keymax; i++)
354 ath_hal_keyreset(ah, i);
355
356 /*
357 * Collect the default channel list.
358 */
359 error = ath_getchannels(sc);
360 if (error != 0)
361 goto bad;
362
363 /*
364 * Setup rate tables for all potential media types.
365 */
366 ath_rate_setup(sc, IEEE80211_MODE_11A);
367 ath_rate_setup(sc, IEEE80211_MODE_11B);
368 ath_rate_setup(sc, IEEE80211_MODE_11G);
369 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
370 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
371 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
372 ath_rate_setup(sc, IEEE80211_MODE_11NA);
373 ath_rate_setup(sc, IEEE80211_MODE_11NG);
374 ath_rate_setup(sc, IEEE80211_MODE_HALF);
375 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
376
377 /* NB: setup here so ath_rate_update is happy */
378 ath_setcurmode(sc, IEEE80211_MODE_11A);
379
380 /*
381 * Allocate TX descriptors and populate the lists.
382 */
383 error = ath_desc_alloc(sc);
384 if (error != 0) {
385 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
386 error);
387 goto bad;
388 }
389 error = ath_txdma_setup(sc);
390 if (error != 0) {
391 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
392 error);
393 goto bad;
394 }
395
396 /*
397 * Allocate RX descriptors and populate the lists.
398 */
399 error = ath_rxdma_setup(sc);
400 if (error != 0) {
401 if_printf(ifp, "failed to allocate RX descriptors: %d\n",
402 error);
403 goto bad;
404 }
405
406 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
407 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
408
409 ATH_TXBUF_LOCK_INIT(sc);
410
411 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
412 taskqueue_thread_enqueue, &sc->sc_tq);
413 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
414 "%s taskq", ifp->if_xname);
415
416 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
417 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
418 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
419 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
420 TASK_INIT(&sc->sc_txqtask,0, ath_txq_sched_tasklet, sc);
421 TASK_INIT(&sc->sc_fataltask,0, ath_fatal_proc, sc);
422
423 /*
424 * Allocate hardware transmit queues: one queue for
425 * beacon frames and one data queue for each QoS
426 * priority. Note that the hal handles resetting
427 * these queues at the needed time.
428 *
429 * XXX PS-Poll
430 */
431 sc->sc_bhalq = ath_beaconq_setup(sc);
432 if (sc->sc_bhalq == (u_int) -1) {
433 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
434 error = EIO;
435 goto bad2;
436 }
437 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
438 if (sc->sc_cabq == NULL) {
439 if_printf(ifp, "unable to setup CAB xmit queue!\n");
440 error = EIO;
441 goto bad2;
442 }
443 /* NB: insure BK queue is the lowest priority h/w queue */
444 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
445 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
446 ieee80211_wme_acnames[WME_AC_BK]);
447 error = EIO;
448 goto bad2;
449 }
450 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
451 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
452 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
453 /*
454 * Not enough hardware tx queues to properly do WME;
455 * just punt and assign them all to the same h/w queue.
456 * We could do a better job of this if, for example,
457 * we allocate queues when we switch from station to
458 * AP mode.
459 */
460 if (sc->sc_ac2q[WME_AC_VI] != NULL)
461 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
462 if (sc->sc_ac2q[WME_AC_BE] != NULL)
463 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
464 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
465 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
466 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
467 }
468
469 /*
470 * Attach the TX completion function.
471 *
472 * The non-EDMA chips may have some special case optimisations;
473 * this method gives everyone a chance to attach cleanly.
474 */
475 sc->sc_tx.xmit_attach_comp_func(sc);
476
477 /*
478 * Setup rate control. Some rate control modules
479 * call back to change the anntena state so expose
480 * the necessary entry points.
481 * XXX maybe belongs in struct ath_ratectrl?
482 */
483 sc->sc_setdefantenna = ath_setdefantenna;
484 sc->sc_rc = ath_rate_attach(sc);
485 if (sc->sc_rc == NULL) {
486 error = EIO;
487 goto bad2;
488 }
489
490 /* Attach DFS module */
491 if (! ath_dfs_attach(sc)) {
492 device_printf(sc->sc_dev,
493 "%s: unable to attach DFS\n", __func__);
494 error = EIO;
495 goto bad2;
496 }
497
498 /* Start DFS processing tasklet */
499 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
500
501 /* Configure LED state */
502 sc->sc_blinking = 0;
503 sc->sc_ledstate = 1;
504 sc->sc_ledon = 0; /* low true */
505 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
506 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
507
508 /*
509 * Don't setup hardware-based blinking.
510 *
511 * Although some NICs may have this configured in the
512 * default reset register values, the user may wish
513 * to alter which pins have which function.
514 *
515 * The reference driver attaches the MAC network LED to GPIO1 and
516 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
517 * NIC has these reversed.
518 */
519 sc->sc_hardled = (1 == 0);
520 sc->sc_led_net_pin = -1;
521 sc->sc_led_pwr_pin = -1;
522 /*
523 * Auto-enable soft led processing for IBM cards and for
524 * 5211 minipci cards. Users can also manually enable/disable
525 * support with a sysctl.
526 */
527 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
528 ath_led_config(sc);
529 ath_hal_setledstate(ah, HAL_LED_INIT);
530
531 ifp->if_softc = sc;
532 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
533 ifp->if_start = ath_start;
534 ifp->if_ioctl = ath_ioctl;
535 ifp->if_init = ath_init;
536 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
537 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
538 IFQ_SET_READY(&ifp->if_snd);
539
540 ic->ic_ifp = ifp;
541 /* XXX not right but it's not used anywhere important */
542 ic->ic_phytype = IEEE80211_T_OFDM;
543 ic->ic_opmode = IEEE80211_M_STA;
544 ic->ic_caps =
545 IEEE80211_C_STA /* station mode */
546 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
547 | IEEE80211_C_HOSTAP /* hostap mode */
548 | IEEE80211_C_MONITOR /* monitor mode */
549 | IEEE80211_C_AHDEMO /* adhoc demo mode */
550 | IEEE80211_C_WDS /* 4-address traffic works */
551 | IEEE80211_C_MBSS /* mesh point link mode */
552 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
553 | IEEE80211_C_SHSLOT /* short slot time supported */
554 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
555#ifndef ATH_ENABLE_11N
556 | IEEE80211_C_BGSCAN /* capable of bg scanning */
557#endif
558 | IEEE80211_C_TXFRAG /* handle tx frags */
559#ifdef ATH_ENABLE_DFS
560 | IEEE80211_C_DFS /* Enable radar detection */
561#endif
562 ;
563 /*
564 * Query the hal to figure out h/w crypto support.
565 */
566 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
567 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
568 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
569 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
570 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
571 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
572 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
573 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
574 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
575 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
576 /*
577 * Check if h/w does the MIC and/or whether the
578 * separate key cache entries are required to
579 * handle both tx+rx MIC keys.
580 */
581 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
582 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
583 /*
584 * If the h/w supports storing tx+rx MIC keys
585 * in one cache slot automatically enable use.
586 */
587 if (ath_hal_hastkipsplit(ah) ||
588 !ath_hal_settkipsplit(ah, AH_FALSE))
589 sc->sc_splitmic = 1;
590 /*
591 * If the h/w can do TKIP MIC together with WME then
592 * we use it; otherwise we force the MIC to be done
593 * in software by the net80211 layer.
594 */
595 if (ath_hal_haswmetkipmic(ah))
596 sc->sc_wmetkipmic = 1;
597 }
598 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
599 /*
600 * Check for multicast key search support.
601 */
602 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
603 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
604 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
605 }
606 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
607 /*
608 * Mark key cache slots associated with global keys
609 * as in use. If we knew TKIP was not to be used we
610 * could leave the +32, +64, and +32+64 slots free.
611 */
612 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
613 setbit(sc->sc_keymap, i);
614 setbit(sc->sc_keymap, i+64);
615 if (sc->sc_splitmic) {
616 setbit(sc->sc_keymap, i+32);
617 setbit(sc->sc_keymap, i+32+64);
618 }
619 }
620 /*
621 * TPC support can be done either with a global cap or
622 * per-packet support. The latter is not available on
623 * all parts. We're a bit pedantic here as all parts
624 * support a global cap.
625 */
626 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
627 ic->ic_caps |= IEEE80211_C_TXPMGT;
628
629 /*
630 * Mark WME capability only if we have sufficient
631 * hardware queues to do proper priority scheduling.
632 */
633 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
634 ic->ic_caps |= IEEE80211_C_WME;
635 /*
636 * Check for misc other capabilities.
637 */
638 if (ath_hal_hasbursting(ah))
639 ic->ic_caps |= IEEE80211_C_BURST;
640 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
641 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
642 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
643 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
644 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah);
645 if (ath_hal_hasfastframes(ah))
646 ic->ic_caps |= IEEE80211_C_FF;
647 wmodes = ath_hal_getwirelessmodes(ah);
648 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
649 ic->ic_caps |= IEEE80211_C_TURBOP;
650#ifdef IEEE80211_SUPPORT_TDMA
651 if (ath_hal_macversion(ah) > 0x78) {
652 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
653 ic->ic_tdma_update = ath_tdma_update;
654 }
655#endif
656
657 /*
658 * TODO: enforce that at least this many frames are available
659 * in the txbuf list before allowing data frames (raw or
660 * otherwise) to be transmitted.
661 */
662 sc->sc_txq_data_minfree = 10;
663 /*
664 * Leave this as default to maintain legacy behaviour.
665 * Shortening the cabq/mcastq may end up causing some
666 * undesirable behaviour.
667 */
668 sc->sc_txq_mcastq_maxdepth = ath_txbuf;
669
670 /*
671 * Allow the TX and RX chainmasks to be overridden by
672 * environment variables and/or device.hints.
673 *
674 * This must be done early - before the hardware is
675 * calibrated or before the 802.11n stream calculation
676 * is done.
677 */
678 if (resource_int_value(device_get_name(sc->sc_dev),
679 device_get_unit(sc->sc_dev), "rx_chainmask",
680 &rx_chainmask) == 0) {
681 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
682 rx_chainmask);
683 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
684 }
685 if (resource_int_value(device_get_name(sc->sc_dev),
686 device_get_unit(sc->sc_dev), "tx_chainmask",
687 &tx_chainmask) == 0) {
688 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
689 tx_chainmask);
690 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
691 }
692
693 /*
694 * Disable MRR with protected frames by default.
695 * Only 802.11n series NICs can handle this.
696 */
697 sc->sc_mrrprot = 0; /* XXX should be a capability */
698
699#ifdef ATH_ENABLE_11N
700 /*
701 * Query HT capabilities
702 */
703 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
704 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
705 int rxs, txs;
706
707 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
708
709 sc->sc_mrrprot = 1; /* XXX should be a capability */
710
711 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
712 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
713 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
714 | IEEE80211_HTCAP_MAXAMSDU_3839
715 /* max A-MSDU length */
716 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
717 ;
718
719 /*
720 * Enable short-GI for HT20 only if the hardware
721 * advertises support.
722 * Notably, anything earlier than the AR9287 doesn't.
723 */
724 if ((ath_hal_getcapability(ah,
725 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
726 (wmodes & HAL_MODE_HT20)) {
727 device_printf(sc->sc_dev,
728 "[HT] enabling short-GI in 20MHz mode\n");
729 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
730 }
731
732 if (wmodes & HAL_MODE_HT40)
733 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
734 | IEEE80211_HTCAP_SHORTGI40;
735
736 /*
737 * TX/RX streams need to be taken into account when
738 * negotiating which MCS rates it'll receive and
739 * what MCS rates are available for TX.
740 */
741 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
742 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
743
744 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
745 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
746
747 ic->ic_txstream = txs;
748 ic->ic_rxstream = rxs;
749
750 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
751 &sc->sc_rts_aggr_limit);
752 if (sc->sc_rts_aggr_limit != (64 * 1024))
753 device_printf(sc->sc_dev,
754 "[HT] RTS aggregates limited to %d KiB\n",
755 sc->sc_rts_aggr_limit / 1024);
756
757 device_printf(sc->sc_dev,
758 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
759 }
760#endif
761
762 /*
763 * Initial aggregation settings.
764 */
765 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH;
766 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
767 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
768
769 /*
770 * Check if the hardware requires PCI register serialisation.
771 * Some of the Owl based MACs require this.
772 */
773 if (mp_ncpus > 1 &&
774 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
775 0, NULL) == HAL_OK) {
776 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
777 device_printf(sc->sc_dev,
778 "Enabling register serialisation\n");
779 }
780
781 /*
782 * Indicate we need the 802.11 header padded to a
783 * 32-bit boundary for 4-address and QoS frames.
784 */
785 ic->ic_flags |= IEEE80211_F_DATAPAD;
786
787 /*
788 * Query the hal about antenna support.
789 */
790 sc->sc_defant = ath_hal_getdefantenna(ah);
791
792 /*
793 * Not all chips have the VEOL support we want to
794 * use with IBSS beacons; check here for it.
795 */
796 sc->sc_hasveol = ath_hal_hasveol(ah);
797
798 /* get mac address from hardware */
799 ath_hal_getmac(ah, macaddr);
800 if (sc->sc_hasbmask)
801 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
802
803 /* NB: used to size node table key mapping array */
804 ic->ic_max_keyix = sc->sc_keymax;
805 /* call MI attach routine. */
806 ieee80211_ifattach(ic, macaddr);
807 ic->ic_setregdomain = ath_setregdomain;
808 ic->ic_getradiocaps = ath_getradiocaps;
809 sc->sc_opmode = HAL_M_STA;
810
811 /* override default methods */
812 ic->ic_newassoc = ath_newassoc;
813 ic->ic_updateslot = ath_updateslot;
814 ic->ic_wme.wme_update = ath_wme_update;
815 ic->ic_vap_create = ath_vap_create;
816 ic->ic_vap_delete = ath_vap_delete;
817 ic->ic_raw_xmit = ath_raw_xmit;
818 ic->ic_update_mcast = ath_update_mcast;
819 ic->ic_update_promisc = ath_update_promisc;
820 ic->ic_node_alloc = ath_node_alloc;
821 sc->sc_node_free = ic->ic_node_free;
822 ic->ic_node_free = ath_node_free;
823 sc->sc_node_cleanup = ic->ic_node_cleanup;
824 ic->ic_node_cleanup = ath_node_cleanup;
825 ic->ic_node_getsignal = ath_node_getsignal;
826 ic->ic_scan_start = ath_scan_start;
827 ic->ic_scan_end = ath_scan_end;
828 ic->ic_set_channel = ath_set_channel;
829#ifdef ATH_ENABLE_11N
830 /* 802.11n specific - but just override anyway */
831 sc->sc_addba_request = ic->ic_addba_request;
832 sc->sc_addba_response = ic->ic_addba_response;
833 sc->sc_addba_stop = ic->ic_addba_stop;
834 sc->sc_bar_response = ic->ic_bar_response;
835 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
836
837 ic->ic_addba_request = ath_addba_request;
838 ic->ic_addba_response = ath_addba_response;
839 ic->ic_addba_response_timeout = ath_addba_response_timeout;
840 ic->ic_addba_stop = ath_addba_stop;
841 ic->ic_bar_response = ath_bar_response;
842
843 ic->ic_update_chw = ath_update_chw;
844#endif /* ATH_ENABLE_11N */
845
846#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
847 /*
848 * There's one vendor bitmap entry in the RX radiotap
849 * header; make sure that's taken into account.
850 */
851 ieee80211_radiotap_attachv(ic,
852 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
853 ATH_TX_RADIOTAP_PRESENT,
854 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
855 ATH_RX_RADIOTAP_PRESENT);
856#else
857 /*
858 * No vendor bitmap/extensions are present.
859 */
860 ieee80211_radiotap_attach(ic,
861 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
862 ATH_TX_RADIOTAP_PRESENT,
863 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
864 ATH_RX_RADIOTAP_PRESENT);
865#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
866
867 /*
868 * Setup dynamic sysctl's now that country code and
869 * regdomain are available from the hal.
870 */
871 ath_sysctlattach(sc);
872 ath_sysctl_stats_attach(sc);
873 ath_sysctl_hal_attach(sc);
874
875 if (bootverbose)
876 ieee80211_announce(ic);
877 ath_announce(sc);
878 return 0;
879bad2:
880 ath_tx_cleanup(sc);
881 ath_desc_free(sc);
882 ath_txdma_teardown(sc);
883 ath_rxdma_teardown(sc);
884bad:
885 if (ah)
886 ath_hal_detach(ah);
887 if (ifp != NULL)
888 if_free(ifp);
889 sc->sc_invalid = 1;
890 return error;
891}
892
893int
894ath_detach(struct ath_softc *sc)
895{
896 struct ifnet *ifp = sc->sc_ifp;
897
898 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
899 __func__, ifp->if_flags);
900
901 /*
902 * NB: the order of these is important:
903 * o stop the chip so no more interrupts will fire
904 * o call the 802.11 layer before detaching the hal to
905 * insure callbacks into the driver to delete global
906 * key cache entries can be handled
907 * o free the taskqueue which drains any pending tasks
908 * o reclaim the tx queue data structures after calling
909 * the 802.11 layer as we'll get called back to reclaim
910 * node state and potentially want to use them
911 * o to cleanup the tx queues the hal is called, so detach
912 * it last
913 * Other than that, it's straightforward...
914 */
915 ath_stop(ifp);
916 ieee80211_ifdetach(ifp->if_l2com);
917 taskqueue_free(sc->sc_tq);
918#ifdef ATH_TX99_DIAG
919 if (sc->sc_tx99 != NULL)
920 sc->sc_tx99->detach(sc->sc_tx99);
921#endif
922 ath_rate_detach(sc->sc_rc);
923
924 ath_dfs_detach(sc);
925 ath_desc_free(sc);
926 ath_txdma_teardown(sc);
927 ath_rxdma_teardown(sc);
928 ath_tx_cleanup(sc);
929 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
930 if_free(ifp);
931
932 return 0;
933}
934
935/*
936 * MAC address handling for multiple BSS on the same radio.
937 * The first vap uses the MAC address from the EEPROM. For
938 * subsequent vap's we set the U/L bit (bit 1) in the MAC
939 * address and use the next six bits as an index.
940 */
941static void
942assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
943{
944 int i;
945
946 if (clone && sc->sc_hasbmask) {
947 /* NB: we only do this if h/w supports multiple bssid */
948 for (i = 0; i < 8; i++)
949 if ((sc->sc_bssidmask & (1<<i)) == 0)
950 break;
951 if (i != 0)
952 mac[0] |= (i << 2)|0x2;
953 } else
954 i = 0;
955 sc->sc_bssidmask |= 1<<i;
956 sc->sc_hwbssidmask[0] &= ~mac[0];
957 if (i == 0)
958 sc->sc_nbssid0++;
959}
960
961static void
962reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
963{
964 int i = mac[0] >> 2;
965 uint8_t mask;
966
967 if (i != 0 || --sc->sc_nbssid0 == 0) {
968 sc->sc_bssidmask &= ~(1<<i);
969 /* recalculate bssid mask from remaining addresses */
970 mask = 0xff;
971 for (i = 1; i < 8; i++)
972 if (sc->sc_bssidmask & (1<<i))
973 mask &= ~((i<<2)|0x2);
974 sc->sc_hwbssidmask[0] |= mask;
975 }
976}
977
978/*
979 * Assign a beacon xmit slot. We try to space out
980 * assignments so when beacons are staggered the
981 * traffic coming out of the cab q has maximal time
982 * to go out before the next beacon is scheduled.
983 */
984static int
985assign_bslot(struct ath_softc *sc)
986{
987 u_int slot, free;
988
989 free = 0;
990 for (slot = 0; slot < ATH_BCBUF; slot++)
991 if (sc->sc_bslot[slot] == NULL) {
992 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
993 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
994 return slot;
995 free = slot;
996 /* NB: keep looking for a double slot */
997 }
998 return free;
999}
1000
1001static struct ieee80211vap *
1002ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1003 enum ieee80211_opmode opmode, int flags,
1004 const uint8_t bssid[IEEE80211_ADDR_LEN],
1005 const uint8_t mac0[IEEE80211_ADDR_LEN])
1006{
1007 struct ath_softc *sc = ic->ic_ifp->if_softc;
1008 struct ath_vap *avp;
1009 struct ieee80211vap *vap;
1010 uint8_t mac[IEEE80211_ADDR_LEN];
1011 int needbeacon, error;
1012 enum ieee80211_opmode ic_opmode;
1013
1014 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
1015 M_80211_VAP, M_WAITOK | M_ZERO);
1016 needbeacon = 0;
1017 IEEE80211_ADDR_COPY(mac, mac0);
1018
1019 ATH_LOCK(sc);
1020 ic_opmode = opmode; /* default to opmode of new vap */
1021 switch (opmode) {
1022 case IEEE80211_M_STA:
1023 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1024 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1025 goto bad;
1026 }
1027 if (sc->sc_nvaps) {
1028 /*
1029 * With multiple vaps we must fall back
1030 * to s/w beacon miss handling.
1031 */
1032 flags |= IEEE80211_CLONE_NOBEACONS;
1033 }
1034 if (flags & IEEE80211_CLONE_NOBEACONS) {
1035 /*
1036 * Station mode w/o beacons are implemented w/ AP mode.
1037 */
1038 ic_opmode = IEEE80211_M_HOSTAP;
1039 }
1040 break;
1041 case IEEE80211_M_IBSS:
1042 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1043 device_printf(sc->sc_dev,
1044 "only 1 ibss vap supported\n");
1045 goto bad;
1046 }
1047 needbeacon = 1;
1048 break;
1049 case IEEE80211_M_AHDEMO:
1050#ifdef IEEE80211_SUPPORT_TDMA
1051 if (flags & IEEE80211_CLONE_TDMA) {
1052 if (sc->sc_nvaps != 0) {
1053 device_printf(sc->sc_dev,
1054 "only 1 tdma vap supported\n");
1055 goto bad;
1056 }
1057 needbeacon = 1;
1058 flags |= IEEE80211_CLONE_NOBEACONS;
1059 }
1060 /* fall thru... */
1061#endif
1062 case IEEE80211_M_MONITOR:
1063 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1064 /*
1065 * Adopt existing mode. Adding a monitor or ahdemo
1066 * vap to an existing configuration is of dubious
1067 * value but should be ok.
1068 */
1069 /* XXX not right for monitor mode */
1070 ic_opmode = ic->ic_opmode;
1071 }
1072 break;
1073 case IEEE80211_M_HOSTAP:
1074 case IEEE80211_M_MBSS:
1075 needbeacon = 1;
1076 break;
1077 case IEEE80211_M_WDS:
1078 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1079 device_printf(sc->sc_dev,
1080 "wds not supported in sta mode\n");
1081 goto bad;
1082 }
1083 /*
1084 * Silently remove any request for a unique
1085 * bssid; WDS vap's always share the local
1086 * mac address.
1087 */
1088 flags &= ~IEEE80211_CLONE_BSSID;
1089 if (sc->sc_nvaps == 0)
1090 ic_opmode = IEEE80211_M_HOSTAP;
1091 else
1092 ic_opmode = ic->ic_opmode;
1093 break;
1094 default:
1095 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1096 goto bad;
1097 }
1098 /*
1099 * Check that a beacon buffer is available; the code below assumes it.
1100 */
1101 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1102 device_printf(sc->sc_dev, "no beacon buffer available\n");
1103 goto bad;
1104 }
1105
1106 /* STA, AHDEMO? */
1107 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1108 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1109 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1110 }
1111
1112 vap = &avp->av_vap;
1113 /* XXX can't hold mutex across if_alloc */
1114 ATH_UNLOCK(sc);
1115 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1116 bssid, mac);
1117 ATH_LOCK(sc);
1118 if (error != 0) {
1119 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1120 __func__, error);
1121 goto bad2;
1122 }
1123
1124 /* h/w crypto support */
1125 vap->iv_key_alloc = ath_key_alloc;
1126 vap->iv_key_delete = ath_key_delete;
1127 vap->iv_key_set = ath_key_set;
1128 vap->iv_key_update_begin = ath_key_update_begin;
1129 vap->iv_key_update_end = ath_key_update_end;
1130
1131 /* override various methods */
1132 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1133 vap->iv_recv_mgmt = ath_recv_mgmt;
1134 vap->iv_reset = ath_reset_vap;
1135 vap->iv_update_beacon = ath_beacon_update;
1136 avp->av_newstate = vap->iv_newstate;
1137 vap->iv_newstate = ath_newstate;
1138 avp->av_bmiss = vap->iv_bmiss;
1139 vap->iv_bmiss = ath_bmiss_vap;
1140
1141 /* Set default parameters */
1142
1143 /*
1144 * Anything earlier than some AR9300 series MACs don't
1145 * support a smaller MPDU density.
1146 */
1147 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1148 /*
1149 * All NICs can handle the maximum size, however
1150 * AR5416 based MACs can only TX aggregates w/ RTS
1151 * protection when the total aggregate size is <= 8k.
1152 * However, for now that's enforced by the TX path.
1153 */
1154 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1155
1156 avp->av_bslot = -1;
1157 if (needbeacon) {
1158 /*
1159 * Allocate beacon state and setup the q for buffered
1160 * multicast frames. We know a beacon buffer is
1161 * available because we checked above.
1162 */
1163 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1164 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1165 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1166 /*
1167 * Assign the vap to a beacon xmit slot. As above
1168 * this cannot fail to find a free one.
1169 */
1170 avp->av_bslot = assign_bslot(sc);
1171 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1172 ("beacon slot %u not empty", avp->av_bslot));
1173 sc->sc_bslot[avp->av_bslot] = vap;
1174 sc->sc_nbcnvaps++;
1175 }
1176 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1177 /*
1178 * Multple vaps are to transmit beacons and we
1179 * have h/w support for TSF adjusting; enable
1180 * use of staggered beacons.
1181 */
1182 sc->sc_stagbeacons = 1;
1183 }
1184 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1185 }
1186
1187 ic->ic_opmode = ic_opmode;
1188 if (opmode != IEEE80211_M_WDS) {
1189 sc->sc_nvaps++;
1190 if (opmode == IEEE80211_M_STA)
1191 sc->sc_nstavaps++;
1192 if (opmode == IEEE80211_M_MBSS)
1193 sc->sc_nmeshvaps++;
1194 }
1195 switch (ic_opmode) {
1196 case IEEE80211_M_IBSS:
1197 sc->sc_opmode = HAL_M_IBSS;
1198 break;
1199 case IEEE80211_M_STA:
1200 sc->sc_opmode = HAL_M_STA;
1201 break;
1202 case IEEE80211_M_AHDEMO:
1203#ifdef IEEE80211_SUPPORT_TDMA
1204 if (vap->iv_caps & IEEE80211_C_TDMA) {
1205 sc->sc_tdma = 1;
1206 /* NB: disable tsf adjust */
1207 sc->sc_stagbeacons = 0;
1208 }
1209 /*
1210 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1211 * just ap mode.
1212 */
1213 /* fall thru... */
1214#endif
1215 case IEEE80211_M_HOSTAP:
1216 case IEEE80211_M_MBSS:
1217 sc->sc_opmode = HAL_M_HOSTAP;
1218 break;
1219 case IEEE80211_M_MONITOR:
1220 sc->sc_opmode = HAL_M_MONITOR;
1221 break;
1222 default:
1223 /* XXX should not happen */
1224 break;
1225 }
1226 if (sc->sc_hastsfadd) {
1227 /*
1228 * Configure whether or not TSF adjust should be done.
1229 */
1230 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1231 }
1232 if (flags & IEEE80211_CLONE_NOBEACONS) {
1233 /*
1234 * Enable s/w beacon miss handling.
1235 */
1236 sc->sc_swbmiss = 1;
1237 }
1238 ATH_UNLOCK(sc);
1239
1240 /* complete setup */
1241 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1242 return vap;
1243bad2:
1244 reclaim_address(sc, mac);
1245 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1246bad:
1247 free(avp, M_80211_VAP);
1248 ATH_UNLOCK(sc);
1249 return NULL;
1250}
1251
1252static void
1253ath_vap_delete(struct ieee80211vap *vap)
1254{
1255 struct ieee80211com *ic = vap->iv_ic;
1256 struct ifnet *ifp = ic->ic_ifp;
1257 struct ath_softc *sc = ifp->if_softc;
1258 struct ath_hal *ah = sc->sc_ah;
1259 struct ath_vap *avp = ATH_VAP(vap);
1260
1261 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1262 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1263 /*
1264 * Quiesce the hardware while we remove the vap. In
1265 * particular we need to reclaim all references to
1266 * the vap state by any frames pending on the tx queues.
1267 */
1268 ath_hal_intrset(ah, 0); /* disable interrupts */
1269 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1270 /* XXX Do all frames from all vaps/nodes need draining here? */
1271 ath_stoprecv(sc, 1); /* stop recv side */
1272 }
1273
1274 ieee80211_vap_detach(vap);
1275
1276 /*
1277 * XXX Danger Will Robinson! Danger!
1278 *
1279 * Because ieee80211_vap_detach() can queue a frame (the station
1280 * diassociate message?) after we've drained the TXQ and
1281 * flushed the software TXQ, we will end up with a frame queued
1282 * to a node whose vap is about to be freed.
1283 *
1284 * To work around this, flush the hardware/software again.
1285 * This may be racy - the ath task may be running and the packet
1286 * may be being scheduled between sw->hw txq. Tsk.
1287 *
1288 * TODO: figure out why a new node gets allocated somewhere around
1289 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1290 * call!)
1291 */
1292
1293 ath_draintxq(sc, ATH_RESET_DEFAULT);
1294
1295 ATH_LOCK(sc);
1296 /*
1297 * Reclaim beacon state. Note this must be done before
1298 * the vap instance is reclaimed as we may have a reference
1299 * to it in the buffer for the beacon frame.
1300 */
1301 if (avp->av_bcbuf != NULL) {
1302 if (avp->av_bslot != -1) {
1303 sc->sc_bslot[avp->av_bslot] = NULL;
1304 sc->sc_nbcnvaps--;
1305 }
1306 ath_beacon_return(sc, avp->av_bcbuf);
1307 avp->av_bcbuf = NULL;
1308 if (sc->sc_nbcnvaps == 0) {
1309 sc->sc_stagbeacons = 0;
1310 if (sc->sc_hastsfadd)
1311 ath_hal_settsfadjust(sc->sc_ah, 0);
1312 }
1313 /*
1314 * Reclaim any pending mcast frames for the vap.
1315 */
1316 ath_tx_draintxq(sc, &avp->av_mcastq);
1317 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1318 }
1319 /*
1320 * Update bookkeeping.
1321 */
1322 if (vap->iv_opmode == IEEE80211_M_STA) {
1323 sc->sc_nstavaps--;
1324 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1325 sc->sc_swbmiss = 0;
1326 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1327 vap->iv_opmode == IEEE80211_M_MBSS) {
1328 reclaim_address(sc, vap->iv_myaddr);
1329 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1330 if (vap->iv_opmode == IEEE80211_M_MBSS)
1331 sc->sc_nmeshvaps--;
1332 }
1333 if (vap->iv_opmode != IEEE80211_M_WDS)
1334 sc->sc_nvaps--;
1335#ifdef IEEE80211_SUPPORT_TDMA
1336 /* TDMA operation ceases when the last vap is destroyed */
1337 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1338 sc->sc_tdma = 0;
1339 sc->sc_swbmiss = 0;
1340 }
1341#endif
1342 free(avp, M_80211_VAP);
1343
1344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1345 /*
1346 * Restart rx+tx machines if still running (RUNNING will
1347 * be reset if we just destroyed the last vap).
1348 */
1349 if (ath_startrecv(sc) != 0)
1350 if_printf(ifp, "%s: unable to restart recv logic\n",
1351 __func__);
1352 if (sc->sc_beacons) { /* restart beacons */
1353#ifdef IEEE80211_SUPPORT_TDMA
1354 if (sc->sc_tdma)
1355 ath_tdma_config(sc, NULL);
1356 else
1357#endif
1358 ath_beacon_config(sc, NULL);
1359 }
1360 ath_hal_intrset(ah, sc->sc_imask);
1361 }
1362 ATH_UNLOCK(sc);
1363}
1364
1365void
1366ath_suspend(struct ath_softc *sc)
1367{
1368 struct ifnet *ifp = sc->sc_ifp;
1369 struct ieee80211com *ic = ifp->if_l2com;
1370
1371 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1372 __func__, ifp->if_flags);
1373
1374 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1375
1376 ieee80211_suspend_all(ic);
1377 /*
1378 * NB: don't worry about putting the chip in low power
1379 * mode; pci will power off our socket on suspend and
1380 * CardBus detaches the device.
1381 */
1382
1383 /*
1384 * XXX ensure none of the taskqueues are running
1385 * XXX ensure sc_invalid is 1
1386 * XXX ensure the calibration callout is disabled
1387 */
1388
1389 /* Disable the PCIe PHY, complete with workarounds */
1390 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1391}
1392
1393/*
1394 * Reset the key cache since some parts do not reset the
1395 * contents on resume. First we clear all entries, then
1396 * re-load keys that the 802.11 layer assumes are setup
1397 * in h/w.
1398 */
1399static void
1400ath_reset_keycache(struct ath_softc *sc)
1401{
1402 struct ifnet *ifp = sc->sc_ifp;
1403 struct ieee80211com *ic = ifp->if_l2com;
1404 struct ath_hal *ah = sc->sc_ah;
1405 int i;
1406
1407 for (i = 0; i < sc->sc_keymax; i++)
1408 ath_hal_keyreset(ah, i);
1409 ieee80211_crypto_reload_keys(ic);
1410}
1411
1412void
1413ath_resume(struct ath_softc *sc)
1414{
1415 struct ifnet *ifp = sc->sc_ifp;
1416 struct ieee80211com *ic = ifp->if_l2com;
1417 struct ath_hal *ah = sc->sc_ah;
1418 HAL_STATUS status;
1419
1420 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1421 __func__, ifp->if_flags);
1422
1423 /* Re-enable PCIe, re-enable the PCIe bus */
1424 ath_hal_enablepcie(ah, 0, 0);
1425
1426 /*
1427 * Must reset the chip before we reload the
1428 * keycache as we were powered down on suspend.
1429 */
1430 ath_hal_reset(ah, sc->sc_opmode,
1431 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1432 AH_FALSE, &status);
1433 ath_reset_keycache(sc);
1434
1435 /* Let DFS at it in case it's a DFS channel */
1436 ath_dfs_radar_enable(sc, ic->ic_curchan);
1437
1438 /* Restore the LED configuration */
1439 ath_led_config(sc);
1440 ath_hal_setledstate(ah, HAL_LED_INIT);
1441
1442 if (sc->sc_resume_up)
1443 ieee80211_resume_all(ic);
1444
1445 /* XXX beacons ? */
1446}
1447
1448void
1449ath_shutdown(struct ath_softc *sc)
1450{
1451 struct ifnet *ifp = sc->sc_ifp;
1452
1453 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1454 __func__, ifp->if_flags);
1455
1456 ath_stop(ifp);
1457 /* NB: no point powering down chip as we're about to reboot */
1458}
1459
1460/*
1461 * Interrupt handler. Most of the actual processing is deferred.
1462 */
1463void
1464ath_intr(void *arg)
1465{
1466 struct ath_softc *sc = arg;
1467 struct ifnet *ifp = sc->sc_ifp;
1468 struct ath_hal *ah = sc->sc_ah;
1469 HAL_INT status = 0;
1470 uint32_t txqs;
1471
1472 /*
1473 * If we're inside a reset path, just print a warning and
1474 * clear the ISR. The reset routine will finish it for us.
1475 */
1476 ATH_PCU_LOCK(sc);
1477 if (sc->sc_inreset_cnt) {
1478 HAL_INT status;
1479 ath_hal_getisr(ah, &status); /* clear ISR */
1480 ath_hal_intrset(ah, 0); /* disable further intr's */
1481 DPRINTF(sc, ATH_DEBUG_ANY,
1482 "%s: in reset, ignoring: status=0x%x\n",
1483 __func__, status);
1484 ATH_PCU_UNLOCK(sc);
1485 return;
1486 }
1487
1488 if (sc->sc_invalid) {
1489 /*
1490 * The hardware is not ready/present, don't touch anything.
1491 * Note this can happen early on if the IRQ is shared.
1492 */
1493 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1494 ATH_PCU_UNLOCK(sc);
1495 return;
1496 }
1497 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
1498 ATH_PCU_UNLOCK(sc);
1499 return;
1500 }
1501
1502 if ((ifp->if_flags & IFF_UP) == 0 ||
1503 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1504 HAL_INT status;
1505
1506 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1507 __func__, ifp->if_flags);
1508 ath_hal_getisr(ah, &status); /* clear ISR */
1509 ath_hal_intrset(ah, 0); /* disable further intr's */
1510 ATH_PCU_UNLOCK(sc);
1511 return;
1512 }
1513
1514 /*
1515 * Figure out the reason(s) for the interrupt. Note
1516 * that the hal returns a pseudo-ISR that may include
1517 * bits we haven't explicitly enabled so we mask the
1518 * value to insure we only process bits we requested.
1519 */
1520 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1521 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1522 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
1523#ifdef ATH_KTR_INTR_DEBUG
1524 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
1525 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
1526 ah->ah_intrstate[0],
1527 ah->ah_intrstate[1],
1528 ah->ah_intrstate[2],
1529 ah->ah_intrstate[3],
1530 ah->ah_intrstate[6]);
1531#endif
1532
1533 /* Squirrel away SYNC interrupt debugging */
1534 if (ah->ah_syncstate != 0) {
1535 int i;
1536 for (i = 0; i < 32; i++)
1537 if (ah->ah_syncstate & (i << i))
1538 sc->sc_intr_stats.sync_intr[i]++;
1539 }
1540
1541 status &= sc->sc_imask; /* discard unasked for bits */
1542
1543 /* Short-circuit un-handled interrupts */
1544 if (status == 0x0) {
1545 ATH_PCU_UNLOCK(sc);
1546 return;
1547 }
1548
1549 /*
1550 * Take a note that we're inside the interrupt handler, so
1551 * the reset routines know to wait.
1552 */
1553 sc->sc_intr_cnt++;
1554 ATH_PCU_UNLOCK(sc);
1555
1556 /*
1557 * Handle the interrupt. We won't run concurrent with the reset
1558 * or channel change routines as they'll wait for sc_intr_cnt
1559 * to be 0 before continuing.
1560 */
1561 if (status & HAL_INT_FATAL) {
1562 sc->sc_stats.ast_hardware++;
1563 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1564 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
1565 } else {
1566 if (status & HAL_INT_SWBA) {
1567 /*
1568 * Software beacon alert--time to send a beacon.
1569 * Handle beacon transmission directly; deferring
1570 * this is too slow to meet timing constraints
1571 * under load.
1572 */
1573#ifdef IEEE80211_SUPPORT_TDMA
1574 if (sc->sc_tdma) {
1575 if (sc->sc_tdmaswba == 0) {
1576 struct ieee80211com *ic = ifp->if_l2com;
1577 struct ieee80211vap *vap =
1578 TAILQ_FIRST(&ic->ic_vaps);
1579 ath_tdma_beacon_send(sc, vap);
1580 sc->sc_tdmaswba =
1581 vap->iv_tdma->tdma_bintval;
1582 } else
1583 sc->sc_tdmaswba--;
1584 } else
1585#endif
1586 {
1587 ath_beacon_proc(sc, 0);
1588#ifdef IEEE80211_SUPPORT_SUPERG
1589 /*
1590 * Schedule the rx taskq in case there's no
1591 * traffic so any frames held on the staging
1592 * queue are aged and potentially flushed.
1593 */
1594 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1595#endif
1596 }
1597 }
1598 if (status & HAL_INT_RXEOL) {
1599 int imask;
1600 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
1601 ATH_PCU_LOCK(sc);
1602 /*
1603 * NB: the hardware should re-read the link when
1604 * RXE bit is written, but it doesn't work at
1605 * least on older hardware revs.
1606 */
1607 sc->sc_stats.ast_rxeol++;
1608 /*
1609 * Disable RXEOL/RXORN - prevent an interrupt
1610 * storm until the PCU logic can be reset.
1611 * In case the interface is reset some other
1612 * way before "sc_kickpcu" is called, don't
1613 * modify sc_imask - that way if it is reset
1614 * by a call to ath_reset() somehow, the
1615 * interrupt mask will be correctly reprogrammed.
1616 */
1617 imask = sc->sc_imask;
1618 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
1619 ath_hal_intrset(ah, imask);
1620 /*
1621 * Only blank sc_rxlink if we've not yet kicked
1622 * the PCU.
1623 *
1624 * This isn't entirely correct - the correct solution
1625 * would be to have a PCU lock and engage that for
1626 * the duration of the PCU fiddling; which would include
1627 * running the RX process. Otherwise we could end up
1628 * messing up the RX descriptor chain and making the
1629 * RX desc list much shorter.
1630 */
1631 if (! sc->sc_kickpcu)
1632 sc->sc_rxlink = NULL;
1633 sc->sc_kickpcu = 1;
1634 /*
1635 * Enqueue an RX proc, to handled whatever
1636 * is in the RX queue.
1637 * This will then kick the PCU.
1638 */
1639 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1640 ATH_PCU_UNLOCK(sc);
1641 }
1642 if (status & HAL_INT_TXURN) {
1643 sc->sc_stats.ast_txurn++;
1644 /* bump tx trigger level */
1645 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1646 }
1647 /*
1648 * Handle both the legacy and RX EDMA interrupt bits.
1649 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
1650 */
1651 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
1652 sc->sc_stats.ast_rx_intr++;
1653 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1654 }
1655 if (status & HAL_INT_TX) {
1656 sc->sc_stats.ast_tx_intr++;
1657 /*
1658 * Grab all the currently set bits in the HAL txq bitmap
1659 * and blank them. This is the only place we should be
1660 * doing this.
1661 */
1662 if (! sc->sc_isedma) {
1663 ATH_PCU_LOCK(sc);
1664 txqs = 0xffffffff;
1665 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
1666 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
1667 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
1668 txqs,
1669 sc->sc_txq_active,
1670 sc->sc_txq_active | txqs);
1671 sc->sc_txq_active |= txqs;
1672 ATH_PCU_UNLOCK(sc);
1673 }
1674 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1675 }
1676 if (status & HAL_INT_BMISS) {
1677 sc->sc_stats.ast_bmiss++;
1678 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1679 }
1680 if (status & HAL_INT_GTT)
1681 sc->sc_stats.ast_tx_timeout++;
1682 if (status & HAL_INT_CST)
1683 sc->sc_stats.ast_tx_cst++;
1684 if (status & HAL_INT_MIB) {
1685 sc->sc_stats.ast_mib++;
1686 ATH_PCU_LOCK(sc);
1687 /*
1688 * Disable interrupts until we service the MIB
1689 * interrupt; otherwise it will continue to fire.
1690 */
1691 ath_hal_intrset(ah, 0);
1692 /*
1693 * Let the hal handle the event. We assume it will
1694 * clear whatever condition caused the interrupt.
1695 */
1696 ath_hal_mibevent(ah, &sc->sc_halstats);
1697 /*
1698 * Don't reset the interrupt if we've just
1699 * kicked the PCU, or we may get a nested
1700 * RXEOL before the rxproc has had a chance
1701 * to run.
1702 */
1703 if (sc->sc_kickpcu == 0)
1704 ath_hal_intrset(ah, sc->sc_imask);
1705 ATH_PCU_UNLOCK(sc);
1706 }
1707 if (status & HAL_INT_RXORN) {
1708 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1709 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
1710 sc->sc_stats.ast_rxorn++;
1711 }
1712 }
1713 ATH_PCU_LOCK(sc);
1714 sc->sc_intr_cnt--;
1715 ATH_PCU_UNLOCK(sc);
1716}
1717
1718static void
1719ath_fatal_proc(void *arg, int pending)
1720{
1721 struct ath_softc *sc = arg;
1722 struct ifnet *ifp = sc->sc_ifp;
1723 u_int32_t *state;
1724 u_int32_t len;
1725 void *sp;
1726
1727 if_printf(ifp, "hardware error; resetting\n");
1728 /*
1729 * Fatal errors are unrecoverable. Typically these
1730 * are caused by DMA errors. Collect h/w state from
1731 * the hal so we can diagnose what's going on.
1732 */
1733 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1734 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1735 state = sp;
1736 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1737 state[0], state[1] , state[2], state[3],
1738 state[4], state[5]);
1739 }
1740 ath_reset(ifp, ATH_RESET_NOLOSS);
1741}
1742
1743static void
1744ath_bmiss_vap(struct ieee80211vap *vap)
1745{
1746 /*
1747 * Workaround phantom bmiss interrupts by sanity-checking
1748 * the time of our last rx'd frame. If it is within the
1749 * beacon miss interval then ignore the interrupt. If it's
1750 * truly a bmiss we'll get another interrupt soon and that'll
1751 * be dispatched up for processing. Note this applies only
1752 * for h/w beacon miss events.
1753 */
1754 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1755 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1756 struct ath_softc *sc = ifp->if_softc;
1757 u_int64_t lastrx = sc->sc_lastrx;
1758 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1759 /* XXX should take a locked ref to iv_bss */
1760 u_int bmisstimeout =
1761 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1762
1763 DPRINTF(sc, ATH_DEBUG_BEACON,
1764 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1765 __func__, (unsigned long long) tsf,
1766 (unsigned long long)(tsf - lastrx),
1767 (unsigned long long) lastrx, bmisstimeout);
1768
1769 if (tsf - lastrx <= bmisstimeout) {
1770 sc->sc_stats.ast_bmiss_phantom++;
1771 return;
1772 }
1773 }
1774 ATH_VAP(vap)->av_bmiss(vap);
1775}
1776
1777static int
1778ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1779{
1780 uint32_t rsize;
1781 void *sp;
1782
1783 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
1784 return 0;
1785 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1786 *hangs = *(uint32_t *)sp;
1787 return 1;
1788}
1789
1790static void
1791ath_bmiss_proc(void *arg, int pending)
1792{
1793 struct ath_softc *sc = arg;
1794 struct ifnet *ifp = sc->sc_ifp;
1795 uint32_t hangs;
1796
1797 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1798
1799 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1800 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
1801 ath_reset(ifp, ATH_RESET_NOLOSS);
1802 } else
1803 ieee80211_beacon_miss(ifp->if_l2com);
1804}
1805
1806/*
1807 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1808 * calcs together with WME. If necessary disable the crypto
1809 * hardware and mark the 802.11 state so keys will be setup
1810 * with the MIC work done in software.
1811 */
1812static void
1813ath_settkipmic(struct ath_softc *sc)
1814{
1815 struct ifnet *ifp = sc->sc_ifp;
1816 struct ieee80211com *ic = ifp->if_l2com;
1817
1818 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1819 if (ic->ic_flags & IEEE80211_F_WME) {
1820 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1821 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1822 } else {
1823 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1824 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1825 }
1826 }
1827}
1828
1829static void
1830ath_init(void *arg)
1831{
1832 struct ath_softc *sc = (struct ath_softc *) arg;
1833 struct ifnet *ifp = sc->sc_ifp;
1834 struct ieee80211com *ic = ifp->if_l2com;
1835 struct ath_hal *ah = sc->sc_ah;
1836 HAL_STATUS status;
1837
1838 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1839 __func__, ifp->if_flags);
1840
1841 ATH_LOCK(sc);
1842 /*
1843 * Stop anything previously setup. This is safe
1844 * whether this is the first time through or not.
1845 */
1846 ath_stop_locked(ifp);
1847
1848 /*
1849 * The basic interface to setting the hardware in a good
1850 * state is ``reset''. On return the hardware is known to
1851 * be powered up and with interrupts disabled. This must
1852 * be followed by initialization of the appropriate bits
1853 * and then setup of the interrupt mask.
1854 */
1855 ath_settkipmic(sc);
1856 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
1857 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1858 status);
1859 ATH_UNLOCK(sc);
1860 return;
1861 }
1862 ath_chan_change(sc, ic->ic_curchan);
1863
1864 /* Let DFS at it in case it's a DFS channel */
1865 ath_dfs_radar_enable(sc, ic->ic_curchan);
1866
1867 /*
1868 * Likewise this is set during reset so update
1869 * state cached in the driver.
1870 */
1871 sc->sc_diversity = ath_hal_getdiversity(ah);
1872 sc->sc_lastlongcal = 0;
1873 sc->sc_resetcal = 1;
1874 sc->sc_lastcalreset = 0;
1875 sc->sc_lastani = 0;
1876 sc->sc_lastshortcal = 0;
1877 sc->sc_doresetcal = AH_FALSE;
1878 /*
1879 * Beacon timers were cleared here; give ath_newstate()
1880 * a hint that the beacon timers should be poked when
1881 * things transition to the RUN state.
1882 */
1883 sc->sc_beacons = 0;
1884
1885 /*
1886 * Setup the hardware after reset: the key cache
1887 * is filled as needed and the receive engine is
1888 * set going. Frame transmit is handled entirely
1889 * in the frame output path; there's nothing to do
1890 * here except setup the interrupt mask.
1891 */
1892 if (ath_startrecv(sc) != 0) {
1893 if_printf(ifp, "unable to start recv logic\n");
1894 ATH_UNLOCK(sc);
1895 return;
1896 }
1897
1898 /*
1899 * Enable interrupts.
1900 */
1901 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1902 | HAL_INT_RXEOL | HAL_INT_RXORN
1903 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1904
1905 /*
1906 * Enable RX EDMA bits. Note these overlap with
1907 * HAL_INT_RX and HAL_INT_RXDESC respectively.
1908 */
1909 if (sc->sc_isedma)
1910 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
1911
1912 /*
1913 * Enable MIB interrupts when there are hardware phy counters.
1914 * Note we only do this (at the moment) for station mode.
1915 */
1916 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1917 sc->sc_imask |= HAL_INT_MIB;
1918
1919 /* Enable global TX timeout and carrier sense timeout if available */
1920 if (ath_hal_gtxto_supported(ah))
1921 sc->sc_imask |= HAL_INT_GTT;
1922
1923 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
1924 __func__, sc->sc_imask);
1925
1926 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1927 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
1928 ath_hal_intrset(ah, sc->sc_imask);
1929
1930 ATH_UNLOCK(sc);
1931
1932#ifdef ATH_TX99_DIAG
1933 if (sc->sc_tx99 != NULL)
1934 sc->sc_tx99->start(sc->sc_tx99);
1935 else
1936#endif
1937 ieee80211_start_all(ic); /* start all vap's */
1938}
1939
1940static void
1941ath_stop_locked(struct ifnet *ifp)
1942{
1943 struct ath_softc *sc = ifp->if_softc;
1944 struct ath_hal *ah = sc->sc_ah;
1945
1946 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1947 __func__, sc->sc_invalid, ifp->if_flags);
1948
1949 ATH_LOCK_ASSERT(sc);
1950 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1951 /*
1952 * Shutdown the hardware and driver:
1953 * reset 802.11 state machine
1954 * turn off timers
1955 * disable interrupts
1956 * turn off the radio
1957 * clear transmit machinery
1958 * clear receive machinery
1959 * drain and release tx queues
1960 * reclaim beacon resources
1961 * power down hardware
1962 *
1963 * Note that some of this work is not possible if the
1964 * hardware is gone (invalid).
1965 */
1966#ifdef ATH_TX99_DIAG
1967 if (sc->sc_tx99 != NULL)
1968 sc->sc_tx99->stop(sc->sc_tx99);
1969#endif
1970 callout_stop(&sc->sc_wd_ch);
1971 sc->sc_wd_timer = 0;
1972 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1973 if (!sc->sc_invalid) {
1974 if (sc->sc_softled) {
1975 callout_stop(&sc->sc_ledtimer);
1976 ath_hal_gpioset(ah, sc->sc_ledpin,
1977 !sc->sc_ledon);
1978 sc->sc_blinking = 0;
1979 }
1980 ath_hal_intrset(ah, 0);
1981 }
1982 ath_draintxq(sc, ATH_RESET_DEFAULT);
1983 if (!sc->sc_invalid) {
1984 ath_stoprecv(sc, 1);
1985 ath_hal_phydisable(ah);
1986 } else
1987 sc->sc_rxlink = NULL;
1988 ath_beacon_free(sc); /* XXX not needed */
1989 }
1990}
1991
1992#define MAX_TXRX_ITERATIONS 1000
1993static void
1994ath_txrx_stop_locked(struct ath_softc *sc)
1995{
1996 int i = MAX_TXRX_ITERATIONS;
1997
1998 ATH_UNLOCK_ASSERT(sc);
1999 ATH_PCU_LOCK_ASSERT(sc);
2000
2001 /*
2002 * Sleep until all the pending operations have completed.
2003 *
2004 * The caller must ensure that reset has been incremented
2005 * or the pending operations may continue being queued.
2006 */
2007 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2008 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2009 if (i <= 0)
2010 break;
2011 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1);
2012 i--;
2013 }
2014
2015 if (i <= 0)
2016 device_printf(sc->sc_dev,
2017 "%s: didn't finish after %d iterations\n",
2018 __func__, MAX_TXRX_ITERATIONS);
2019}
2020#undef MAX_TXRX_ITERATIONS
2021
2022#if 0
2023static void
2024ath_txrx_stop(struct ath_softc *sc)
2025{
2026 ATH_UNLOCK_ASSERT(sc);
2027 ATH_PCU_UNLOCK_ASSERT(sc);
2028
2029 ATH_PCU_LOCK(sc);
2030 ath_txrx_stop_locked(sc);
2031 ATH_PCU_UNLOCK(sc);
2032}
2033#endif
2034
2035static void
2036ath_txrx_start(struct ath_softc *sc)
2037{
2038
2039 taskqueue_unblock(sc->sc_tq);
2040}
2041
2042/*
2043 * Grab the reset lock, and wait around until noone else
2044 * is trying to do anything with it.
2045 *
2046 * This is totally horrible but we can't hold this lock for
2047 * long enough to do TX/RX or we end up with net80211/ip stack
2048 * LORs and eventual deadlock.
2049 *
2050 * "dowait" signals whether to spin, waiting for the reset
2051 * lock count to reach 0. This should (for now) only be used
2052 * during the reset path, as the rest of the code may not
2053 * be locking-reentrant enough to behave correctly.
2054 *
2055 * Another, cleaner way should be found to serialise all of
2056 * these operations.
2057 */
2058#define MAX_RESET_ITERATIONS 10
2059static int
2060ath_reset_grablock(struct ath_softc *sc, int dowait)
2061{
2062 int w = 0;
2063 int i = MAX_RESET_ITERATIONS;
2064
2065 ATH_PCU_LOCK_ASSERT(sc);
2066 do {
2067 if (sc->sc_inreset_cnt == 0) {
2068 w = 1;
2069 break;
2070 }
2071 if (dowait == 0) {
2072 w = 0;
2073 break;
2074 }
2075 ATH_PCU_UNLOCK(sc);
2076 pause("ath_reset_grablock", 1);
2077 i--;
2078 ATH_PCU_LOCK(sc);
2079 } while (i > 0);
2080
2081 /*
2082 * We always increment the refcounter, regardless
2083 * of whether we succeeded to get it in an exclusive
2084 * way.
2085 */
2086 sc->sc_inreset_cnt++;
2087
2088 if (i <= 0)
2089 device_printf(sc->sc_dev,
2090 "%s: didn't finish after %d iterations\n",
2091 __func__, MAX_RESET_ITERATIONS);
2092
2093 if (w == 0)
2094 device_printf(sc->sc_dev,
2095 "%s: warning, recursive reset path!\n",
2096 __func__);
2097
2098 return w;
2099}
2100#undef MAX_RESET_ITERATIONS
2101
2102/*
2103 * XXX TODO: write ath_reset_releaselock
2104 */
2105
2106static void
2107ath_stop(struct ifnet *ifp)
2108{
2109 struct ath_softc *sc = ifp->if_softc;
2110
2111 ATH_LOCK(sc);
2112 ath_stop_locked(ifp);
2113 ATH_UNLOCK(sc);
2114}
2115
2116/*
2117 * Reset the hardware w/o losing operational state. This is
2118 * basically a more efficient way of doing ath_stop, ath_init,
2119 * followed by state transitions to the current 802.11
2120 * operational state. Used to recover from various errors and
2121 * to reset or reload hardware state.
2122 */
2123int
2124ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2125{
2126 struct ath_softc *sc = ifp->if_softc;
2127 struct ieee80211com *ic = ifp->if_l2com;
2128 struct ath_hal *ah = sc->sc_ah;
2129 HAL_STATUS status;
2130 int i;
2131
2132 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2133
2134 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2135 ATH_PCU_UNLOCK_ASSERT(sc);
2136 ATH_UNLOCK_ASSERT(sc);
2137
2138 /* Try to (stop any further TX/RX from occuring */
2139 taskqueue_block(sc->sc_tq);
2140
2141 ATH_PCU_LOCK(sc);
2142 ath_hal_intrset(ah, 0); /* disable interrupts */
2143 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */
2144 if (ath_reset_grablock(sc, 1) == 0) {
2145 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2146 __func__);
2147 }
2148 ATH_PCU_UNLOCK(sc);
2149
2150 /*
2151 * Should now wait for pending TX/RX to complete
2152 * and block future ones from occuring. This needs to be
2153 * done before the TX queue is drained.
2154 */
2155 ath_draintxq(sc, reset_type); /* stop xmit side */
2156
2157 /*
2158 * Regardless of whether we're doing a no-loss flush or
2159 * not, stop the PCU and handle what's in the RX queue.
2160 * That way frames aren't dropped which shouldn't be.
2161 */
2162 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2163 ath_rx_flush(sc);
2164
2165 ath_settkipmic(sc); /* configure TKIP MIC handling */
2166 /* NB: indicate channel change so we do a full reset */
2167 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2168 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2169 __func__, status);
2170 sc->sc_diversity = ath_hal_getdiversity(ah);
2171
2172 /* Let DFS at it in case it's a DFS channel */
2173 ath_dfs_radar_enable(sc, ic->ic_curchan);
2174
2175 if (ath_startrecv(sc) != 0) /* restart recv */
2176 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2177 /*
2178 * We may be doing a reset in response to an ioctl
2179 * that changes the channel so update any state that
2180 * might change as a result.
2181 */
2182 ath_chan_change(sc, ic->ic_curchan);
2183 if (sc->sc_beacons) { /* restart beacons */
2184#ifdef IEEE80211_SUPPORT_TDMA
2185 if (sc->sc_tdma)
2186 ath_tdma_config(sc, NULL);
2187 else
2188#endif
2189 ath_beacon_config(sc, NULL);
2190 }
2191
2192 /*
2193 * Release the reset lock and re-enable interrupts here.
2194 * If an interrupt was being processed in ath_intr(),
2195 * it would disable interrupts at this point. So we have
2196 * to atomically enable interrupts and decrement the
2197 * reset counter - this way ath_intr() doesn't end up
2198 * disabling interrupts without a corresponding enable
2199 * in the rest or channel change path.
2200 */
2201 ATH_PCU_LOCK(sc);
2202 sc->sc_inreset_cnt--;
2203 /* XXX only do this if sc_inreset_cnt == 0? */
2204 ath_hal_intrset(ah, sc->sc_imask);
2205 ATH_PCU_UNLOCK(sc);
2206
2207 /*
2208 * TX and RX can be started here. If it were started with
2209 * sc_inreset_cnt > 0, the TX and RX path would abort.
2210 * Thus if this is a nested call through the reset or
2211 * channel change code, TX completion will occur but
2212 * RX completion and ath_start / ath_tx_start will not
2213 * run.
2214 */
2215
2216 /* Restart TX/RX as needed */
2217 ath_txrx_start(sc);
2218
2219 /* XXX Restart TX completion and pending TX */
2220 if (reset_type == ATH_RESET_NOLOSS) {
2221 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2222 if (ATH_TXQ_SETUP(sc, i)) {
2223 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2224 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2225 ath_txq_sched(sc, &sc->sc_txq[i]);
2226 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2227 }
2228 }
2229 }
2230
2231 /*
2232 * This may have been set during an ath_start() call which
2233 * set this once it detected a concurrent TX was going on.
2234 * So, clear it.
2235 */
2236 IF_LOCK(&ifp->if_snd);
2237 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2238 IF_UNLOCK(&ifp->if_snd);
2239
2240 /* Handle any frames in the TX queue */
2241 /*
2242 * XXX should this be done by the caller, rather than
2243 * ath_reset() ?
2244 */
2245 ath_start(ifp); /* restart xmit */
2246 return 0;
2247}
2248
2249static int
2250ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2251{
2252 struct ieee80211com *ic = vap->iv_ic;
2253 struct ifnet *ifp = ic->ic_ifp;
2254 struct ath_softc *sc = ifp->if_softc;
2255 struct ath_hal *ah = sc->sc_ah;
2256
2257 switch (cmd) {
2258 case IEEE80211_IOC_TXPOWER:
2259 /*
2260 * If per-packet TPC is enabled, then we have nothing
2261 * to do; otherwise we need to force the global limit.
2262 * All this can happen directly; no need to reset.
2263 */
2264 if (!ath_hal_gettpc(ah))
2265 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2266 return 0;
2267 }
2268 /* XXX? Full or NOLOSS? */
2269 return ath_reset(ifp, ATH_RESET_FULL);
2270}
2271
2272struct ath_buf *
2273_ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
2274{
2275 struct ath_buf *bf;
2276
2277 ATH_TXBUF_LOCK_ASSERT(sc);
2278
2279 if (btype == ATH_BUFTYPE_MGMT)
2280 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
2281 else
2282 bf = TAILQ_FIRST(&sc->sc_txbuf);
2283
2284 if (bf == NULL) {
2285 sc->sc_stats.ast_tx_getnobuf++;
2286 } else {
2287 if (bf->bf_flags & ATH_BUF_BUSY) {
2288 sc->sc_stats.ast_tx_getbusybuf++;
2289 bf = NULL;
2290 }
2291 }
2292
2293 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
2294 if (btype == ATH_BUFTYPE_MGMT)
2295 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
2296 else {
2297 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
2298 sc->sc_txbuf_cnt--;
2299
2300 /*
2301 * This shuldn't happen; however just to be
2302 * safe print a warning and fudge the txbuf
2303 * count.
2304 */
2305 if (sc->sc_txbuf_cnt < 0) {
2306 device_printf(sc->sc_dev,
2307 "%s: sc_txbuf_cnt < 0?\n",
2308 __func__);
2309 sc->sc_txbuf_cnt = 0;
2310 }
2311 }
2312 } else
2313 bf = NULL;
2314
2315 if (bf == NULL) {
2316 /* XXX should check which list, mgmt or otherwise */
2317 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
2318 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
2319 "out of xmit buffers" : "xmit buffer busy");
2320 return NULL;
2321 }
2322
2323 /* XXX TODO: should do this at buffer list initialisation */
2324 /* XXX (then, ensure the buffer has the right flag set) */
2325 if (btype == ATH_BUFTYPE_MGMT)
2326 bf->bf_flags |= ATH_BUF_MGMT;
2327 else
2328 bf->bf_flags &= (~ATH_BUF_MGMT);
2329
2330 /* Valid bf here; clear some basic fields */
2331 bf->bf_next = NULL; /* XXX just to be sure */
2332 bf->bf_last = NULL; /* XXX again, just to be sure */
2333 bf->bf_comp = NULL; /* XXX again, just to be sure */
2334 bzero(&bf->bf_state, sizeof(bf->bf_state));
2335
2336 /*
2337 * Track the descriptor ID only if doing EDMA
2338 */
2339 if (sc->sc_isedma) {
2340 bf->bf_descid = sc->sc_txbuf_descid;
2341 sc->sc_txbuf_descid++;
2342 }
2343
2344 return bf;
2345}
2346
2347/*
2348 * When retrying a software frame, buffers marked ATH_BUF_BUSY
2349 * can't be thrown back on the queue as they could still be
2350 * in use by the hardware.
2351 *
2352 * This duplicates the buffer, or returns NULL.
2353 *
2354 * The descriptor is also copied but the link pointers and
2355 * the DMA segments aren't copied; this frame should thus
2356 * be again passed through the descriptor setup/chain routines
2357 * so the link is correct.
2358 *
2359 * The caller must free the buffer using ath_freebuf().
2360 *
2361 * XXX TODO: this call shouldn't fail as it'll cause packet loss
2362 * XXX in the TX pathway when retries are needed.
2363 * XXX Figure out how to keep some buffers free, or factor the
2364 * XXX number of busy buffers into the xmit path (ath_start())
2365 * XXX so we don't over-commit.
2366 */
2367struct ath_buf *
2368ath_buf_clone(struct ath_softc *sc, const struct ath_buf *bf)
2369{
2370 struct ath_buf *tbf;
2371
2372 tbf = ath_getbuf(sc,
2373 (bf->bf_flags & ATH_BUF_MGMT) ?
2374 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
2375 if (tbf == NULL)
2376 return NULL; /* XXX failure? Why? */
2377
2378 /* Copy basics */
2379 tbf->bf_next = NULL;
2380 tbf->bf_nseg = bf->bf_nseg;
2381 tbf->bf_flags = bf->bf_flags & ~ATH_BUF_BUSY;
2382 tbf->bf_status = bf->bf_status;
2383 tbf->bf_m = bf->bf_m;
2384 tbf->bf_node = bf->bf_node;
2385 /* will be setup by the chain/setup function */
2386 tbf->bf_lastds = NULL;
2387 /* for now, last == self */
2388 tbf->bf_last = tbf;
2389 tbf->bf_comp = bf->bf_comp;
2390
2391 /* NOTE: DMA segments will be setup by the setup/chain functions */
2392
2393 /* The caller has to re-init the descriptor + links */
2394
2395 /* Copy state */
2396 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
2397
2398 return tbf;
2399}
2400
2401struct ath_buf *
2402ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
2403{
2404 struct ath_buf *bf;
2405
2406 ATH_TXBUF_LOCK(sc);
2407 bf = _ath_getbuf_locked(sc, btype);
2408 /*
2409 * If a mgmt buffer was requested but we're out of those,
2410 * try requesting a normal one.
2411 */
2412 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
2413 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
2414 ATH_TXBUF_UNLOCK(sc);
2415 if (bf == NULL) {
2416 struct ifnet *ifp = sc->sc_ifp;
2417
2418 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
2419 sc->sc_stats.ast_tx_qstop++;
2420 IF_LOCK(&ifp->if_snd);
2421 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2422 IF_UNLOCK(&ifp->if_snd);
2423 }
2424 return bf;
2425}
2426
2427void
2428ath_start(struct ifnet *ifp)
2429{
2430 struct ath_softc *sc = ifp->if_softc;
2431 struct ieee80211_node *ni;
2432 struct ath_buf *bf;
2433 struct mbuf *m, *next;
2434 ath_bufhead frags;
2435
2436 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
2437 return;
2438
2439 /* XXX is it ok to hold the ATH_LOCK here? */
2440 ATH_PCU_LOCK(sc);
2441 if (sc->sc_inreset_cnt > 0) {
2442 device_printf(sc->sc_dev,
2443 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2444 ATH_PCU_UNLOCK(sc);
2445 IF_LOCK(&ifp->if_snd);
2446 sc->sc_stats.ast_tx_qstop++;
2447 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2448 IF_UNLOCK(&ifp->if_snd);
2449 return;
2450 }
2451 sc->sc_txstart_cnt++;
2452 ATH_PCU_UNLOCK(sc);
2453
2454 for (;;) {
2455 ATH_TXBUF_LOCK(sc);
2456 if (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree) {
2457 /* XXX increment counter? */
2458 ATH_TXBUF_UNLOCK(sc);
2459 IF_LOCK(&ifp->if_snd);
2460 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2461 IF_UNLOCK(&ifp->if_snd);
2462 break;
2463 }
2464 ATH_TXBUF_UNLOCK(sc);
2465
2466 /*
2467 * Grab a TX buffer and associated resources.
2468 */
2469 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
2470 if (bf == NULL)
2471 break;
2472
2473 IFQ_DEQUEUE(&ifp->if_snd, m);
2474 if (m == NULL) {
2475 ATH_TXBUF_LOCK(sc);
2476 ath_returnbuf_head(sc, bf);
2477 ATH_TXBUF_UNLOCK(sc);
2478 break;
2479 }
2480 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
2481 /*
2482 * Check for fragmentation. If this frame
2483 * has been broken up verify we have enough
2484 * buffers to send all the fragments so all
2485 * go out or none...
2486 */
2487 TAILQ_INIT(&frags);
2488 if ((m->m_flags & M_FRAG) &&
2489 !ath_txfrag_setup(sc, &frags, m, ni)) {
2490 DPRINTF(sc, ATH_DEBUG_XMIT,
2491 "%s: out of txfrag buffers\n", __func__);
2492 sc->sc_stats.ast_tx_nofrag++;
2493 ifp->if_oerrors++;
2494 ath_freetx(m);
2495 goto bad;
2496 }
2497 ifp->if_opackets++;
2498 nextfrag:
2499 /*
2500 * Pass the frame to the h/w for transmission.
2501 * Fragmented frames have each frag chained together
2502 * with m_nextpkt. We know there are sufficient ath_buf's
2503 * to send all the frags because of work done by
2504 * ath_txfrag_setup. We leave m_nextpkt set while
2505 * calling ath_tx_start so it can use it to extend the
2506 * the tx duration to cover the subsequent frag and
2507 * so it can reclaim all the mbufs in case of an error;
2508 * ath_tx_start clears m_nextpkt once it commits to
2509 * handing the frame to the hardware.
2510 */
2511 next = m->m_nextpkt;
2512 if (ath_tx_start(sc, ni, bf, m)) {
2513 bad:
2514 ifp->if_oerrors++;
2515 reclaim:
2516 bf->bf_m = NULL;
2517 bf->bf_node = NULL;
2518 ATH_TXBUF_LOCK(sc);
2519 ath_returnbuf_head(sc, bf);
2520 ath_txfrag_cleanup(sc, &frags, ni);
2521 ATH_TXBUF_UNLOCK(sc);
2522 if (ni != NULL)
2523 ieee80211_free_node(ni);
2524 continue;
2525 }
2526 if (next != NULL) {
2527 /*
2528 * Beware of state changing between frags.
2529 * XXX check sta power-save state?
2530 */
2531 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2532 DPRINTF(sc, ATH_DEBUG_XMIT,
2533 "%s: flush fragmented packet, state %s\n",
2534 __func__,
2535 ieee80211_state_name[ni->ni_vap->iv_state]);
2536 ath_freetx(next);
2537 goto reclaim;
2538 }
2539 m = next;
2540 bf = TAILQ_FIRST(&frags);
2541 KASSERT(bf != NULL, ("no buf for txfrag"));
2542 TAILQ_REMOVE(&frags, bf, bf_list);
2543 goto nextfrag;
2544 }
2545
2546 sc->sc_wd_timer = 5;
2547 }
2548
2549 ATH_PCU_LOCK(sc);
2550 sc->sc_txstart_cnt--;
2551 ATH_PCU_UNLOCK(sc);
2552}
2553
2554static int
2555ath_media_change(struct ifnet *ifp)
2556{
2557 int error = ieee80211_media_change(ifp);
2558 /* NB: only the fixed rate can change and that doesn't need a reset */
2559 return (error == ENETRESET ? 0 : error);
2560}
2561
2562/*
2563 * Block/unblock tx+rx processing while a key change is done.
2564 * We assume the caller serializes key management operations
2565 * so we only need to worry about synchronization with other
2566 * uses that originate in the driver.
2567 */
2568static void
2569ath_key_update_begin(struct ieee80211vap *vap)
2570{
2571 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2572 struct ath_softc *sc = ifp->if_softc;
2573
2574 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2575 taskqueue_block(sc->sc_tq);
2576 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2577}
2578
2579static void
2580ath_key_update_end(struct ieee80211vap *vap)
2581{
2582 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2583 struct ath_softc *sc = ifp->if_softc;
2584
2585 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2586 IF_UNLOCK(&ifp->if_snd);
2587 taskqueue_unblock(sc->sc_tq);
2588}
2589
2590static void
2591ath_update_promisc(struct ifnet *ifp)
2592{
2593 struct ath_softc *sc = ifp->if_softc;
2594 u_int32_t rfilt;
2595
2596 /* configure rx filter */
2597 rfilt = ath_calcrxfilter(sc);
2598 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2599
2600 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2601}
2602
2603static void
2604ath_update_mcast(struct ifnet *ifp)
2605{
2606 struct ath_softc *sc = ifp->if_softc;
2607 u_int32_t mfilt[2];
2608
2609 /* calculate and install multicast filter */
2610 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2611 struct ifmultiaddr *ifma;
2612 /*
2613 * Merge multicast addresses to form the hardware filter.
2614 */
2615 mfilt[0] = mfilt[1] = 0;
2616 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2617 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2618 caddr_t dl;
2619 u_int32_t val;
2620 u_int8_t pos;
2621
2622 /* calculate XOR of eight 6bit values */
2623 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2624 val = LE_READ_4(dl + 0);
2625 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2626 val = LE_READ_4(dl + 3);
2627 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2628 pos &= 0x3f;
2629 mfilt[pos / 32] |= (1 << (pos % 32));
2630 }
2631 if_maddr_runlock(ifp);
2632 } else
2633 mfilt[0] = mfilt[1] = ~0;
2634 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2635 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2636 __func__, mfilt[0], mfilt[1]);
2637}
2638
2639void
2640ath_mode_init(struct ath_softc *sc)
2641{
2642 struct ifnet *ifp = sc->sc_ifp;
2643 struct ath_hal *ah = sc->sc_ah;
2644 u_int32_t rfilt;
2645
2646 /* configure rx filter */
2647 rfilt = ath_calcrxfilter(sc);
2648 ath_hal_setrxfilter(ah, rfilt);
2649
2650 /* configure operational mode */
2651 ath_hal_setopmode(ah);
2652
2653 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
2654 "%s: ah=%p, ifp=%p, if_addr=%p\n",
2655 __func__,
2656 ah,
2657 ifp,
2658 (ifp == NULL) ? NULL : ifp->if_addr);
2659
2660 /* handle any link-level address change */
2661 ath_hal_setmac(ah, IF_LLADDR(ifp));
2662
2663 /* calculate and install multicast filter */
2664 ath_update_mcast(ifp);
2665}
2666
2667/*
2668 * Set the slot time based on the current setting.
2669 */
2670void
2671ath_setslottime(struct ath_softc *sc)
2672{
2673 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2674 struct ath_hal *ah = sc->sc_ah;
2675 u_int usec;
2676
2677 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2678 usec = 13;
2679 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2680 usec = 21;
2681 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2682 /* honor short/long slot time only in 11g */
2683 /* XXX shouldn't honor on pure g or turbo g channel */
2684 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2685 usec = HAL_SLOT_TIME_9;
2686 else
2687 usec = HAL_SLOT_TIME_20;
2688 } else
2689 usec = HAL_SLOT_TIME_9;
2690
2691 DPRINTF(sc, ATH_DEBUG_RESET,
2692 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2693 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2694 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2695
2696 ath_hal_setslottime(ah, usec);
2697 sc->sc_updateslot = OK;
2698}
2699
2700/*
2701 * Callback from the 802.11 layer to update the
2702 * slot time based on the current setting.
2703 */
2704static void
2705ath_updateslot(struct ifnet *ifp)
2706{
2707 struct ath_softc *sc = ifp->if_softc;
2708 struct ieee80211com *ic = ifp->if_l2com;
2709
2710 /*
2711 * When not coordinating the BSS, change the hardware
2712 * immediately. For other operation we defer the change
2713 * until beacon updates have propagated to the stations.
2714 */
2715 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2716 ic->ic_opmode == IEEE80211_M_MBSS)
2717 sc->sc_updateslot = UPDATE;
2718 else
2719 ath_setslottime(sc);
2720}
2721
2722/*
2723 * Append the contents of src to dst; both queues
2724 * are assumed to be locked.
2725 */
2726void
2727ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2728{
2729
2730 ATH_TXQ_LOCK_ASSERT(dst);
2731 ATH_TXQ_LOCK_ASSERT(src);
2732
2733 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
2734 dst->axq_link = src->axq_link;
2735 src->axq_link = NULL;
2736 dst->axq_depth += src->axq_depth;
2737 dst->axq_aggr_depth += src->axq_aggr_depth;
2738 src->axq_depth = 0;
2739 src->axq_aggr_depth = 0;
2740}
2741
2742/*
2743 * Reset the hardware, with no loss.
2744 *
2745 * This can't be used for a general case reset.
2746 */
2747static void
2748ath_reset_proc(void *arg, int pending)
2749{
2750 struct ath_softc *sc = arg;
2751 struct ifnet *ifp = sc->sc_ifp;
2752
2753#if 0
2754 if_printf(ifp, "%s: resetting\n", __func__);
2755#endif
2756 ath_reset(ifp, ATH_RESET_NOLOSS);
2757}
2758
2759/*
2760 * Reset the hardware after detecting beacons have stopped.
2761 */
2762static void
2763ath_bstuck_proc(void *arg, int pending)
2764{
2765 struct ath_softc *sc = arg;
2766 struct ifnet *ifp = sc->sc_ifp;
2767 uint32_t hangs = 0;
2768
2769 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
2770 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
2771
2772 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2773 sc->sc_bmisscount);
2774 sc->sc_stats.ast_bstuck++;
2775 /*
2776 * This assumes that there's no simultaneous channel mode change
2777 * occuring.
2778 */
2779 ath_reset(ifp, ATH_RESET_NOLOSS);
2780}
2781
2782static void
2783ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2784{
2785 bus_addr_t *paddr = (bus_addr_t*) arg;
2786 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2787 *paddr = segs->ds_addr;
2788}
2789
2790/*
2791 * Allocate the descriptors and appropriate DMA tag/setup.
2792 *
2793 * For some situations (eg EDMA TX completion), there isn't a requirement
2794 * for the ath_buf entries to be allocated.
2795 */
2796int
2797ath_descdma_alloc_desc(struct ath_softc *sc,
2798 struct ath_descdma *dd, ath_bufhead *head,
2799 const char *name, int ds_size, int ndesc)
2800{
2801#define DS2PHYS(_dd, _ds) \
2802 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2803#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
2804 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
2805 struct ifnet *ifp = sc->sc_ifp;
2806 int error;
2807
2808 dd->dd_descsize = ds_size;
2809
2810 DPRINTF(sc, ATH_DEBUG_RESET,
2811 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
2812 __func__, name, ndesc, dd->dd_descsize);
2813
2814 dd->dd_name = name;
2815 dd->dd_desc_len = dd->dd_descsize * ndesc;
2816
2817 /*
2818 * Merlin work-around:
2819 * Descriptors that cross the 4KB boundary can't be used.
2820 * Assume one skipped descriptor per 4KB page.
2821 */
2822 if (! ath_hal_split4ktrans(sc->sc_ah)) {
2823 int numpages = dd->dd_desc_len / 4096;
2824 dd->dd_desc_len += ds_size * numpages;
2825 }
2826
2827 /*
2828 * Setup DMA descriptor area.
2829 */
2830 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
2831 PAGE_SIZE, 0, /* alignment, bounds */
2832 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2833 BUS_SPACE_MAXADDR, /* highaddr */
2834 NULL, NULL, /* filter, filterarg */
2835 dd->dd_desc_len, /* maxsize */
2836 1, /* nsegments */
2837 dd->dd_desc_len, /* maxsegsize */
2838 BUS_DMA_ALLOCNOW, /* flags */
2839 NULL, /* lockfunc */
2840 NULL, /* lockarg */
2841 &dd->dd_dmat);
2842 if (error != 0) {
2843 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2844 return error;
2845 }
2846
2847 /* allocate descriptors */
2848 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2849 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
2850 &dd->dd_dmamap);
2851 if (error != 0) {
2852 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2853 "error %u\n", ndesc, dd->dd_name, error);
2854 goto fail1;
2855 }
2856
2857 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2858 dd->dd_desc, dd->dd_desc_len,
2859 ath_load_cb, &dd->dd_desc_paddr,
2860 BUS_DMA_NOWAIT);
2861 if (error != 0) {
2862 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2863 dd->dd_name, error);
2864 goto fail2;
2865 }
2866
2867 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2868 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
2869 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
2870 /*XXX*/ (u_long) dd->dd_desc_len);
2871
2872 return (0);
2873
2874fail2:
2875 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2876fail1:
2877 bus_dma_tag_destroy(dd->dd_dmat);
2878 memset(dd, 0, sizeof(*dd));
2879 return error;
2880#undef DS2PHYS
2881#undef ATH_DESC_4KB_BOUND_CHECK
2882}
2883
2884int
2885ath_descdma_setup(struct ath_softc *sc,
2886 struct ath_descdma *dd, ath_bufhead *head,
2887 const char *name, int ds_size, int nbuf, int ndesc)
2888{
2889#define DS2PHYS(_dd, _ds) \
2890 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2891#define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
2892 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
2893 struct ifnet *ifp = sc->sc_ifp;
2894 uint8_t *ds;
2895 struct ath_buf *bf;
2896 int i, bsize, error;
2897
2898 /* Allocate descriptors */
2899 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
2900 nbuf * ndesc);
2901
2902 /* Assume any errors during allocation were dealt with */
2903 if (error != 0) {
2904 return (error);
2905 }
2906
2907 ds = (uint8_t *) dd->dd_desc;
2908
2909 /* allocate rx buffers */
2910 bsize = sizeof(struct ath_buf) * nbuf;
2911 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2912 if (bf == NULL) {
2913 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2914 dd->dd_name, bsize);
2915 goto fail3;
2916 }
2917 dd->dd_bufptr = bf;
2918
2919 TAILQ_INIT(head);
2920 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
2921 bf->bf_desc = (struct ath_desc *) ds;
2922 bf->bf_daddr = DS2PHYS(dd, ds);
2923 if (! ath_hal_split4ktrans(sc->sc_ah)) {
2924 /*
2925 * Merlin WAR: Skip descriptor addresses which
2926 * cause 4KB boundary crossing along any point
2927 * in the descriptor.
2928 */
2929 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
2930 dd->dd_descsize)) {
2931 /* Start at the next page */
2932 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
2933 bf->bf_desc = (struct ath_desc *) ds;
2934 bf->bf_daddr = DS2PHYS(dd, ds);
2935 }
2936 }
2937 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2938 &bf->bf_dmamap);
2939 if (error != 0) {
2940 if_printf(ifp, "unable to create dmamap for %s "
2941 "buffer %u, error %u\n", dd->dd_name, i, error);
2942 ath_descdma_cleanup(sc, dd, head);
2943 return error;
2944 }
2945 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
2946 TAILQ_INSERT_TAIL(head, bf, bf_list);
2947 }
2948
2949 /*
2950 * XXX TODO: ensure that ds doesn't overflow the descriptor
2951 * allocation otherwise weird stuff will occur and crash your
2952 * machine.
2953 */
2954 return 0;
2955 /* XXX this should likely just call ath_descdma_cleanup() */
2956fail3:
2957 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2958 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2959 bus_dma_tag_destroy(dd->dd_dmat);
2960 memset(dd, 0, sizeof(*dd));
2961 return error;
2962#undef DS2PHYS
2963#undef ATH_DESC_4KB_BOUND_CHECK
2964}
2965
2966/*
2967 * Allocate ath_buf entries but no descriptor contents.
2968 *
2969 * This is for RX EDMA where the descriptors are the header part of
2970 * the RX buffer.
2971 */
2972int
2973ath_descdma_setup_rx_edma(struct ath_softc *sc,
2974 struct ath_descdma *dd, ath_bufhead *head,
2975 const char *name, int nbuf, int rx_status_len)
2976{
2977 struct ifnet *ifp = sc->sc_ifp;
2978 struct ath_buf *bf;
2979 int i, bsize, error;
2980
2981 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
2982 __func__, name, nbuf);
2983
2984 dd->dd_name = name;
2985 /*
2986 * This is (mostly) purely for show. We're not allocating any actual
2987 * descriptors here as EDMA RX has the descriptor be part
2988 * of the RX buffer.
2989 *
2990 * However, dd_desc_len is used by ath_descdma_free() to determine
2991 * whether we have already freed this DMA mapping.
2992 */
2993 dd->dd_desc_len = rx_status_len * nbuf;
2994 dd->dd_descsize = rx_status_len;
2995
2996 /* allocate rx buffers */
2997 bsize = sizeof(struct ath_buf) * nbuf;
2998 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2999 if (bf == NULL) {
3000 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3001 dd->dd_name, bsize);
3002 error = ENOMEM;
3003 goto fail3;
3004 }
3005 dd->dd_bufptr = bf;
3006
3007 TAILQ_INIT(head);
3008 for (i = 0; i < nbuf; i++, bf++) {
3009 bf->bf_desc = NULL;
3010 bf->bf_daddr = 0;
3011 bf->bf_lastds = NULL; /* Just an initial value */
3012
3013 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3014 &bf->bf_dmamap);
3015 if (error != 0) {
3016 if_printf(ifp, "unable to create dmamap for %s "
3017 "buffer %u, error %u\n", dd->dd_name, i, error);
3018 ath_descdma_cleanup(sc, dd, head);
3019 return error;
3020 }
3021 TAILQ_INSERT_TAIL(head, bf, bf_list);
3022 }
3023 return 0;
3024fail3:
3025 memset(dd, 0, sizeof(*dd));
3026 return error;
3027}
3028
3029void
3030ath_descdma_cleanup(struct ath_softc *sc,
3031 struct ath_descdma *dd, ath_bufhead *head)
3032{
3033 struct ath_buf *bf;
3034 struct ieee80211_node *ni;
3035
3036 if (dd->dd_dmamap != 0) {
3037 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3038 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3039 bus_dma_tag_destroy(dd->dd_dmat);
3040 }
3041
3042 if (head != NULL) {
3043 TAILQ_FOREACH(bf, head, bf_list) {
3044 if (bf->bf_m) {
3045 m_freem(bf->bf_m);
3046 bf->bf_m = NULL;
3047 }
3048 if (bf->bf_dmamap != NULL) {
3049 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3050 bf->bf_dmamap = NULL;
3051 }
3052 ni = bf->bf_node;
3053 bf->bf_node = NULL;
3054 if (ni != NULL) {
3055 /*
3056 * Reclaim node reference.
3057 */
3058 ieee80211_free_node(ni);
3059 }
3060 }
3061 }
3062
3063 if (head != NULL)
3064 TAILQ_INIT(head);
3065
3066 if (dd->dd_bufptr != NULL)
3067 free(dd->dd_bufptr, M_ATHDEV);
3068 memset(dd, 0, sizeof(*dd));
3069}
3070
3071static int
3072ath_desc_alloc(struct ath_softc *sc)
3073{
3074 int error;
3075
3076 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3077 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_TXDESC);
3078 if (error != 0) {
3079 return error;
3080 }
3081 sc->sc_txbuf_cnt = ath_txbuf;
3082
3083 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3084 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3085 ATH_TXDESC);
3086 if (error != 0) {
3087 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3088 return error;
3089 }
3090
3091 /*
3092 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3093 * flag doesn't have to be set in ath_getbuf_locked().
3094 */
3095
3096 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3097 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3098 if (error != 0) {
3099 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3100 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3101 &sc->sc_txbuf_mgmt);
3102 return error;
3103 }
3104 return 0;
3105}
3106
3107static void
3108ath_desc_free(struct ath_softc *sc)
3109{
3110
3111 if (sc->sc_bdma.dd_desc_len != 0)
3112 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3113 if (sc->sc_txdma.dd_desc_len != 0)
3114 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3115 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3116 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3117 &sc->sc_txbuf_mgmt);
3118}
3119
3120static struct ieee80211_node *
3121ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3122{
3123 struct ieee80211com *ic = vap->iv_ic;
3124 struct ath_softc *sc = ic->ic_ifp->if_softc;
3125 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3126 struct ath_node *an;
3127
3128 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3129 if (an == NULL) {
3130 /* XXX stat+msg */
3131 return NULL;
3132 }
3133 ath_rate_node_init(sc, an);
3134
3135 /* Setup the mutex - there's no associd yet so set the name to NULL */
3136 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3137 device_get_nameunit(sc->sc_dev), an);
3138 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3139
3140 /* XXX setup ath_tid */
3141 ath_tx_tid_init(sc, an);
3142
3143 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3144 return &an->an_node;
3145}
3146
3147static void
3148ath_node_cleanup(struct ieee80211_node *ni)
3149{
3150 struct ieee80211com *ic = ni->ni_ic;
3151 struct ath_softc *sc = ic->ic_ifp->if_softc;
3152
3153 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3154 ath_tx_node_flush(sc, ATH_NODE(ni));
3155 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3156 sc->sc_node_cleanup(ni);
3157}
3158
3159static void
3160ath_node_free(struct ieee80211_node *ni)
3161{
3162 struct ieee80211com *ic = ni->ni_ic;
3163 struct ath_softc *sc = ic->ic_ifp->if_softc;
3164
3165 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3166 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3167 sc->sc_node_free(ni);
3168}
3169
3170static void
3171ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3172{
3173 struct ieee80211com *ic = ni->ni_ic;
3174 struct ath_softc *sc = ic->ic_ifp->if_softc;
3175 struct ath_hal *ah = sc->sc_ah;
3176
3177 *rssi = ic->ic_node_getrssi(ni);
3178 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3179 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3180 else
3181 *noise = -95; /* nominally correct */
3182}
3183
3184/*
3185 * Set the default antenna.
3186 */
3187void
3188ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3189{
3190 struct ath_hal *ah = sc->sc_ah;
3191
3192 /* XXX block beacon interrupts */
3193 ath_hal_setdefantenna(ah, antenna);
3194 if (sc->sc_defant != antenna)
3195 sc->sc_stats.ast_ant_defswitch++;
3196 sc->sc_defant = antenna;
3197 sc->sc_rxotherant = 0;
3198}
3199
3200static void
3201ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3202{
3203 txq->axq_qnum = qnum;
3204 txq->axq_ac = 0;
3205 txq->axq_depth = 0;
3206 txq->axq_aggr_depth = 0;
3207 txq->axq_intrcnt = 0;
3208 txq->axq_link = NULL;
3209 txq->axq_softc = sc;
3210 TAILQ_INIT(&txq->axq_q);
3211 TAILQ_INIT(&txq->axq_tidq);
3212 ATH_TXQ_LOCK_INIT(sc, txq);
3213}
3214
3215/*
3216 * Setup a h/w transmit queue.
3217 */
3218static struct ath_txq *
3219ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3220{
3221#define N(a) (sizeof(a)/sizeof(a[0]))
3222 struct ath_hal *ah = sc->sc_ah;
3223 HAL_TXQ_INFO qi;
3224 int qnum;
3225
3226 memset(&qi, 0, sizeof(qi));
3227 qi.tqi_subtype = subtype;
3228 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3229 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3230 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3231 /*
3232 * Enable interrupts only for EOL and DESC conditions.
3233 * We mark tx descriptors to receive a DESC interrupt
3234 * when a tx queue gets deep; otherwise waiting for the
3235 * EOL to reap descriptors. Note that this is done to
3236 * reduce interrupt load and this only defers reaping
3237 * descriptors, never transmitting frames. Aside from
3238 * reducing interrupts this also permits more concurrency.
3239 * The only potential downside is if the tx queue backs
3240 * up in which case the top half of the kernel may backup
3241 * due to a lack of tx descriptors.
3242 */
3243 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
3244 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3245 if (qnum == -1) {
3246 /*
3247 * NB: don't print a message, this happens
3248 * normally on parts with too few tx queues
3249 */
3250 return NULL;
3251 }
3252 if (qnum >= N(sc->sc_txq)) {
3253 device_printf(sc->sc_dev,
3254 "hal qnum %u out of range, max %zu!\n",
3255 qnum, N(sc->sc_txq));
3256 ath_hal_releasetxqueue(ah, qnum);
3257 return NULL;
3258 }
3259 if (!ATH_TXQ_SETUP(sc, qnum)) {
3260 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3261 sc->sc_txqsetup |= 1<<qnum;
3262 }
3263 return &sc->sc_txq[qnum];
3264#undef N
3265}
3266
3267/*
3268 * Setup a hardware data transmit queue for the specified
3269 * access control. The hal may not support all requested
3270 * queues in which case it will return a reference to a
3271 * previously setup queue. We record the mapping from ac's
3272 * to h/w queues for use by ath_tx_start and also track
3273 * the set of h/w queues being used to optimize work in the
3274 * transmit interrupt handler and related routines.
3275 */
3276static int
3277ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3278{
3279#define N(a) (sizeof(a)/sizeof(a[0]))
3280 struct ath_txq *txq;
3281
3282 if (ac >= N(sc->sc_ac2q)) {
3283 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3284 ac, N(sc->sc_ac2q));
3285 return 0;
3286 }
3287 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3288 if (txq != NULL) {
3289 txq->axq_ac = ac;
3290 sc->sc_ac2q[ac] = txq;
3291 return 1;
3292 } else
3293 return 0;
3294#undef N
3295}
3296
3297/*
3298 * Update WME parameters for a transmit queue.
3299 */
3300static int
3301ath_txq_update(struct ath_softc *sc, int ac)
3302{
3303#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3304#define ATH_TXOP_TO_US(v) (v<<5)
3305 struct ifnet *ifp = sc->sc_ifp;
3306 struct ieee80211com *ic = ifp->if_l2com;
3307 struct ath_txq *txq = sc->sc_ac2q[ac];
3308 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3309 struct ath_hal *ah = sc->sc_ah;
3310 HAL_TXQ_INFO qi;
3311
3312 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3313#ifdef IEEE80211_SUPPORT_TDMA
3314 if (sc->sc_tdma) {
3315 /*
3316 * AIFS is zero so there's no pre-transmit wait. The
3317 * burst time defines the slot duration and is configured
3318 * through net80211. The QCU is setup to not do post-xmit
3319 * back off, lockout all lower-priority QCU's, and fire
3320 * off the DMA beacon alert timer which is setup based
3321 * on the slot configuration.
3322 */
3323 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3324 | HAL_TXQ_TXERRINT_ENABLE
3325 | HAL_TXQ_TXURNINT_ENABLE
3326 | HAL_TXQ_TXEOLINT_ENABLE
3327 | HAL_TXQ_DBA_GATED
3328 | HAL_TXQ_BACKOFF_DISABLE
3329 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
3330 ;
3331 qi.tqi_aifs = 0;
3332 /* XXX +dbaprep? */
3333 qi.tqi_readyTime = sc->sc_tdmaslotlen;
3334 qi.tqi_burstTime = qi.tqi_readyTime;
3335 } else {
3336#endif
3337 /*
3338 * XXX shouldn't this just use the default flags
3339 * used in the previous queue setup?
3340 */
3341 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
3342 | HAL_TXQ_TXERRINT_ENABLE
3343 | HAL_TXQ_TXDESCINT_ENABLE
3344 | HAL_TXQ_TXURNINT_ENABLE
3345 | HAL_TXQ_TXEOLINT_ENABLE
3346 ;
3347 qi.tqi_aifs = wmep->wmep_aifsn;
3348 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3349 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3350 qi.tqi_readyTime = 0;
3351 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3352#ifdef IEEE80211_SUPPORT_TDMA
3353 }
3354#endif
3355
3356 DPRINTF(sc, ATH_DEBUG_RESET,
3357 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
3358 __func__, txq->axq_qnum, qi.tqi_qflags,
3359 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
3360
3361 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3362 if_printf(ifp, "unable to update hardware queue "
3363 "parameters for %s traffic!\n",
3364 ieee80211_wme_acnames[ac]);
3365 return 0;
3366 } else {
3367 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3368 return 1;
3369 }
3370#undef ATH_TXOP_TO_US
3371#undef ATH_EXPONENT_TO_VALUE
3372}
3373
3374/*
3375 * Callback from the 802.11 layer to update WME parameters.
3376 */
3377int
3378ath_wme_update(struct ieee80211com *ic)
3379{
3380 struct ath_softc *sc = ic->ic_ifp->if_softc;
3381
3382 return !ath_txq_update(sc, WME_AC_BE) ||
3383 !ath_txq_update(sc, WME_AC_BK) ||
3384 !ath_txq_update(sc, WME_AC_VI) ||
3385 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3386}
3387
3388/*
3389 * Reclaim resources for a setup queue.
3390 */
3391static void
3392ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3393{
3394
3395 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3396 ATH_TXQ_LOCK_DESTROY(txq);
3397 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3398}
3399
3400/*
3401 * Reclaim all tx queue resources.
3402 */
3403static void
3404ath_tx_cleanup(struct ath_softc *sc)
3405{
3406 int i;
3407
3408 ATH_TXBUF_LOCK_DESTROY(sc);
3409 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3410 if (ATH_TXQ_SETUP(sc, i))
3411 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3412}
3413
3414/*
3415 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
3416 * using the current rates in sc_rixmap.
3417 */
3418int
3419ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
3420{
3421 int rix = sc->sc_rixmap[rate];
3422 /* NB: return lowest rix for invalid rate */
3423 return (rix == 0xff ? 0 : rix);
3424}
3425
3426static void
3427ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
3428 struct ath_buf *bf)
3429{
3430 struct ieee80211_node *ni = bf->bf_node;
3431 struct ifnet *ifp = sc->sc_ifp;
3432 struct ieee80211com *ic = ifp->if_l2com;
3433 int sr, lr, pri;
3434
3435 if (ts->ts_status == 0) {
3436 u_int8_t txant = ts->ts_antenna;
3437 sc->sc_stats.ast_ant_tx[txant]++;
3438 sc->sc_ant_tx[txant]++;
3439 if (ts->ts_finaltsi != 0)
3440 sc->sc_stats.ast_tx_altrate++;
3441 pri = M_WME_GETAC(bf->bf_m);
3442 if (pri >= WME_AC_VO)
3443 ic->ic_wme.wme_hipri_traffic++;
3444 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
3445 ni->ni_inact = ni->ni_inact_reload;
3446 } else {
3447 if (ts->ts_status & HAL_TXERR_XRETRY)
3448 sc->sc_stats.ast_tx_xretries++;
3449 if (ts->ts_status & HAL_TXERR_FIFO)
3450 sc->sc_stats.ast_tx_fifoerr++;
3451 if (ts->ts_status & HAL_TXERR_FILT)
3452 sc->sc_stats.ast_tx_filtered++;
3453 if (ts->ts_status & HAL_TXERR_XTXOP)
3454 sc->sc_stats.ast_tx_xtxop++;
3455 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
3456 sc->sc_stats.ast_tx_timerexpired++;
3457
3458 if (ts->ts_status & HAL_TX_DATA_UNDERRUN)
3459 sc->sc_stats.ast_tx_data_underrun++;
3460 if (ts->ts_status & HAL_TX_DELIM_UNDERRUN)
3461 sc->sc_stats.ast_tx_delim_underrun++;
3462
3463 if (bf->bf_m->m_flags & M_FF)
3464 sc->sc_stats.ast_ff_txerr++;
3465 }
3466 /* XXX when is this valid? */
3467 if (ts->ts_status & HAL_TX_DESC_CFG_ERR)
3468 sc->sc_stats.ast_tx_desccfgerr++;
3469
3470 sr = ts->ts_shortretry;
3471 lr = ts->ts_longretry;
3472 sc->sc_stats.ast_tx_shortretry += sr;
3473 sc->sc_stats.ast_tx_longretry += lr;
3474
3475}
3476
3477/*
3478 * The default completion. If fail is 1, this means
3479 * "please don't retry the frame, and just return -1 status
3480 * to the net80211 stack.
3481 */
3482void
3483ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3484{
3485 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3486 int st;
3487
3488 if (fail == 1)
3489 st = -1;
3490 else
3491 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
3492 ts->ts_status : HAL_TXERR_XRETRY;
3493
3494 if (bf->bf_state.bfs_dobaw)
3495 device_printf(sc->sc_dev,
3496 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
3497 __func__,
3498 bf,
3499 SEQNO(bf->bf_state.bfs_seqno));
3500 if (bf->bf_next != NULL)
3501 device_printf(sc->sc_dev,
3502 "%s: bf %p: seqno %d: bf_next not NULL!\n",
3503 __func__,
3504 bf,
3505 SEQNO(bf->bf_state.bfs_seqno));
3506
3507 /*
3508 * Do any tx complete callback. Note this must
3509 * be done before releasing the node reference.
3510 * This will free the mbuf, release the net80211
3511 * node and recycle the ath_buf.
3512 */
3513 ath_tx_freebuf(sc, bf, st);
3514}
3515
3516/*
3517 * Update rate control with the given completion status.
3518 */
3519void
3520ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
3521 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
3522 int nframes, int nbad)
3523{
3524 struct ath_node *an;
3525
3526 /* Only for unicast frames */
3527 if (ni == NULL)
3528 return;
3529
3530 an = ATH_NODE(ni);
3531
3532 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
3533 ATH_NODE_LOCK(an);
3534 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
3535 ATH_NODE_UNLOCK(an);
3536 }
3537}
3538
3539/*
3540 * Update the busy status of the last frame on the free list.
3541 * When doing TDMA, the busy flag tracks whether the hardware
3542 * currently points to this buffer or not, and thus gated DMA
3543 * may restart by re-reading the last descriptor in this
3544 * buffer.
3545 *
3546 * This should be called in the completion function once one
3547 * of the buffers has been used.
3548 */
3549static void
3550ath_tx_update_busy(struct ath_softc *sc)
3551{
3552 struct ath_buf *last;
3553
3554 /*
3555 * Since the last frame may still be marked
3556 * as ATH_BUF_BUSY, unmark it here before
3557 * finishing the frame processing.
3558 * Since we've completed a frame (aggregate
3559 * or otherwise), the hardware has moved on
3560 * and is no longer referencing the previous
3561 * descriptor.
3562 */
3563 ATH_TXBUF_LOCK_ASSERT(sc);
3564 last = TAILQ_LAST(&sc->sc_txbuf_mgmt, ath_bufhead_s);
3565 if (last != NULL)
3566 last->bf_flags &= ~ATH_BUF_BUSY;
3567 last = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s);
3568 if (last != NULL)
3569 last->bf_flags &= ~ATH_BUF_BUSY;
3570}
3571
3572/*
3573 * Process the completion of the given buffer.
3574 *
3575 * This calls the rate control update and then the buffer completion.
3576 * This will either free the buffer or requeue it. In any case, the
3577 * bf pointer should be treated as invalid after this function is called.
3578 */
3579void
3580ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
3581 struct ath_tx_status *ts, struct ath_buf *bf)
3582{
3583 struct ieee80211_node *ni = bf->bf_node;
3584 struct ath_node *an = NULL;
3585
3586 ATH_TXQ_UNLOCK_ASSERT(txq);
3587
3588 /* If unicast frame, update general statistics */
3589 if (ni != NULL) {
3590 an = ATH_NODE(ni);
3591 /* update statistics */
3592 ath_tx_update_stats(sc, ts, bf);
3593 }
3594
3595 /*
3596 * Call the completion handler.
3597 * The completion handler is responsible for
3598 * calling the rate control code.
3599 *
3600 * Frames with no completion handler get the
3601 * rate control code called here.
3602 */
3603 if (bf->bf_comp == NULL) {
3604 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
3605 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
3606 /*
3607 * XXX assume this isn't an aggregate
3608 * frame.
3609 */
3610 ath_tx_update_ratectrl(sc, ni,
3611 bf->bf_state.bfs_rc, ts,
3612 bf->bf_state.bfs_pktlen, 1,
3613 (ts->ts_status == 0 ? 0 : 1));
3614 }
3615 ath_tx_default_comp(sc, bf, 0);
3616 } else
3617 bf->bf_comp(sc, bf, 0);
3618}
3619
3620
3621
3622/*
3623 * Process completed xmit descriptors from the specified queue.
3624 * Kick the packet scheduler if needed. This can occur from this
3625 * particular task.
3626 */
3627static int
3628ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
3629{
3630 struct ath_hal *ah = sc->sc_ah;
3631 struct ath_buf *bf;
3632 struct ath_desc *ds;
3633 struct ath_tx_status *ts;
3634 struct ieee80211_node *ni;
3635#ifdef IEEE80211_SUPPORT_SUPERG
3636 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3637#endif /* IEEE80211_SUPPORT_SUPERG */
3638 int nacked;
3639 HAL_STATUS status;
3640
3641 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3642 __func__, txq->axq_qnum,
3643 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3644 txq->axq_link);
3645
3646 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
3647 "ath_tx_processq: txq=%u head %p link %p depth %p",
3648 txq->axq_qnum,
3649 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3650 txq->axq_link,
3651 txq->axq_depth);
3652
3653 nacked = 0;
3654 for (;;) {
3655 ATH_TXQ_LOCK(txq);
3656 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3657 bf = TAILQ_FIRST(&txq->axq_q);
3658 if (bf == NULL) {
3659 ATH_TXQ_UNLOCK(txq);
3660 break;
3661 }
3662 ds = bf->bf_lastds; /* XXX must be setup correctly! */
3663 ts = &bf->bf_status.ds_txstat;
3664
3665 status = ath_hal_txprocdesc(ah, ds, ts);
3666#ifdef ATH_DEBUG
3667 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3668 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
3669 status == HAL_OK);
3670 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
3671 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
3672 status == HAL_OK);
3673#endif
3674
3675 if (status == HAL_EINPROGRESS) {
3676 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
3677 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
3678 txq->axq_qnum, bf, ds);
3679 ATH_TXQ_UNLOCK(txq);
3680 break;
3681 }
3682 ATH_TXQ_REMOVE(txq, bf, bf_list);
3683#ifdef IEEE80211_SUPPORT_TDMA
3684 if (txq->axq_depth > 0) {
3685 /*
3686 * More frames follow. Mark the buffer busy
3687 * so it's not re-used while the hardware may
3688 * still re-read the link field in the descriptor.
3689 *
3690 * Use the last buffer in an aggregate as that
3691 * is where the hardware may be - intermediate
3692 * descriptors won't be "busy".
3693 */
3694 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
3695 } else
3696#else
3697 if (txq->axq_depth == 0)
3698#endif
3699 txq->axq_link = NULL;
3700 if (bf->bf_state.bfs_aggr)
3701 txq->axq_aggr_depth--;
3702
3703 ni = bf->bf_node;
3704
3705 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
3706 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
3707 txq->axq_qnum, bf, ds, ni, ts->ts_status);
3708 /*
3709 * If unicast frame was ack'd update RSSI,
3710 * including the last rx time used to
3711 * workaround phantom bmiss interrupts.
3712 */
3713 if (ni != NULL && ts->ts_status == 0 &&
3714 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
3715 nacked++;
3716 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
3717 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3718 ts->ts_rssi);
3719 }
3720 ATH_TXQ_UNLOCK(txq);
3721
3722 /*
3723 * Update statistics and call completion
3724 */
3725 ath_tx_process_buf_completion(sc, txq, ts, bf);
3726 }
3727#ifdef IEEE80211_SUPPORT_SUPERG
3728 /*
3729 * Flush fast-frame staging queue when traffic slows.
3730 */
3731 if (txq->axq_depth <= 1)
3732 ieee80211_ff_flush(ic, txq->axq_ac);
3733#endif
3734
3735 /* Kick the TXQ scheduler */
3736 if (dosched) {
3737 ATH_TXQ_LOCK(txq);
3738 ath_txq_sched(sc, txq);
3739 ATH_TXQ_UNLOCK(txq);
3740 }
3741
3742 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
3743 "ath_tx_processq: txq=%u: done",
3744 txq->axq_qnum);
3745
3746 return nacked;
3747}
3748
3749#define TXQACTIVE(t, q) ( (t) & (1 << (q)))
3750
3751/*
3752 * Deferred processing of transmit interrupt; special-cased
3753 * for a single hardware transmit queue (e.g. 5210 and 5211).
3754 */
3755static void
3756ath_tx_proc_q0(void *arg, int npending)
3757{
3758 struct ath_softc *sc = arg;
3759 struct ifnet *ifp = sc->sc_ifp;
3760 uint32_t txqs;
3761
3762 ATH_PCU_LOCK(sc);
3763 sc->sc_txproc_cnt++;
3764 txqs = sc->sc_txq_active;
3765 sc->sc_txq_active &= ~txqs;
3766 ATH_PCU_UNLOCK(sc);
3767
3768 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
3769 "ath_tx_proc_q0: txqs=0x%08x", txqs);
3770
3771 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
3772 /* XXX why is lastrx updated in tx code? */
3773 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3774 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
3775 ath_tx_processq(sc, sc->sc_cabq, 1);
3776 IF_LOCK(&ifp->if_snd);
3777 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3778 IF_UNLOCK(&ifp->if_snd);
3779 sc->sc_wd_timer = 0;
3780
3781 if (sc->sc_softled)
3782 ath_led_event(sc, sc->sc_txrix);
3783
3784 ATH_PCU_LOCK(sc);
3785 sc->sc_txproc_cnt--;
3786 ATH_PCU_UNLOCK(sc);
3787
3788 ath_tx_kick(sc);
3789}
3790
3791/*
3792 * Deferred processing of transmit interrupt; special-cased
3793 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3794 */
3795static void
3796ath_tx_proc_q0123(void *arg, int npending)
3797{
3798 struct ath_softc *sc = arg;
3799 struct ifnet *ifp = sc->sc_ifp;
3800 int nacked;
3801 uint32_t txqs;
3802
3803 ATH_PCU_LOCK(sc);
3804 sc->sc_txproc_cnt++;
3805 txqs = sc->sc_txq_active;
3806 sc->sc_txq_active &= ~txqs;
3807 ATH_PCU_UNLOCK(sc);
3808
3809 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
3810 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
3811
3812 /*
3813 * Process each active queue.
3814 */
3815 nacked = 0;
3816 if (TXQACTIVE(txqs, 0))
3817 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
3818 if (TXQACTIVE(txqs, 1))
3819 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
3820 if (TXQACTIVE(txqs, 2))
3821 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
3822 if (TXQACTIVE(txqs, 3))
3823 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
3824 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
3825 ath_tx_processq(sc, sc->sc_cabq, 1);
3826 if (nacked)
3827 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3828
3829 IF_LOCK(&ifp->if_snd);
3830 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3831 IF_UNLOCK(&ifp->if_snd);
3832 sc->sc_wd_timer = 0;
3833
3834 if (sc->sc_softled)
3835 ath_led_event(sc, sc->sc_txrix);
3836
3837 ATH_PCU_LOCK(sc);
3838 sc->sc_txproc_cnt--;
3839 ATH_PCU_UNLOCK(sc);
3840
3841 ath_tx_kick(sc);
3842}
3843
3844/*
3845 * Deferred processing of transmit interrupt.
3846 */
3847static void
3848ath_tx_proc(void *arg, int npending)
3849{
3850 struct ath_softc *sc = arg;
3851 struct ifnet *ifp = sc->sc_ifp;
3852 int i, nacked;
3853 uint32_t txqs;
3854
3855 ATH_PCU_LOCK(sc);
3856 sc->sc_txproc_cnt++;
3857 txqs = sc->sc_txq_active;
3858 sc->sc_txq_active &= ~txqs;
3859 ATH_PCU_UNLOCK(sc);
3860
3861 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
3862
3863 /*
3864 * Process each active queue.
3865 */
3866 nacked = 0;
3867 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3868 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
3869 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
3870 if (nacked)
3871 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3872
3873 /* XXX check this inside of IF_LOCK? */
3874 IF_LOCK(&ifp->if_snd);
3875 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3876 IF_UNLOCK(&ifp->if_snd);
3877 sc->sc_wd_timer = 0;
3878
3879 if (sc->sc_softled)
3880 ath_led_event(sc, sc->sc_txrix);
3881
3882 ATH_PCU_LOCK(sc);
3883 sc->sc_txproc_cnt--;
3884 ATH_PCU_UNLOCK(sc);
3885
3886 ath_tx_kick(sc);
3887}
3888#undef TXQACTIVE
3889
3890/*
3891 * Deferred processing of TXQ rescheduling.
3892 */
3893static void
3894ath_txq_sched_tasklet(void *arg, int npending)
3895{
3896 struct ath_softc *sc = arg;
3897 int i;
3898
3899 /* XXX is skipping ok? */
3900 ATH_PCU_LOCK(sc);
3901#if 0
3902 if (sc->sc_inreset_cnt > 0) {
3903 device_printf(sc->sc_dev,
3904 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
3905 ATH_PCU_UNLOCK(sc);
3906 return;
3907 }
3908#endif
3909 sc->sc_txproc_cnt++;
3910 ATH_PCU_UNLOCK(sc);
3911
3912 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
3913 if (ATH_TXQ_SETUP(sc, i)) {
3914 ATH_TXQ_LOCK(&sc->sc_txq[i]);
3915 ath_txq_sched(sc, &sc->sc_txq[i]);
3916 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
3917 }
3918 }
3919
3920 ATH_PCU_LOCK(sc);
3921 sc->sc_txproc_cnt--;
3922 ATH_PCU_UNLOCK(sc);
3923}
3924
3925void
3926ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
3927{
3928
3929 ATH_TXBUF_LOCK_ASSERT(sc);
3930
3931 if (bf->bf_flags & ATH_BUF_MGMT)
3932 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
3933 else {
3934 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3935 sc->sc_txbuf_cnt++;
3936 if (sc->sc_txbuf_cnt > ath_txbuf) {
3937 device_printf(sc->sc_dev,
3938 "%s: sc_txbuf_cnt > %d?\n",
3939 __func__,
3940 ath_txbuf);
3941 sc->sc_txbuf_cnt = ath_txbuf;
3942 }
3943 }
3944}
3945
3946void
3947ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
3948{
3949
3950 ATH_TXBUF_LOCK_ASSERT(sc);
3951
3952 if (bf->bf_flags & ATH_BUF_MGMT)
3953 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
3954 else {
3955 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
3956 sc->sc_txbuf_cnt++;
3957 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
3958 device_printf(sc->sc_dev,
3959 "%s: sc_txbuf_cnt > %d?\n",
3960 __func__,
3961 ATH_TXBUF);
3962 sc->sc_txbuf_cnt = ATH_TXBUF;
3963 }
3964 }
3965}
3966
3967/*
3968 * Return a buffer to the pool and update the 'busy' flag on the
3969 * previous 'tail' entry.
3970 *
3971 * This _must_ only be called when the buffer is involved in a completed
3972 * TX. The logic is that if it was part of an active TX, the previous
3973 * buffer on the list is now not involved in a halted TX DMA queue, waiting
3974 * for restart (eg for TDMA.)
3975 *
3976 * The caller must free the mbuf and recycle the node reference.
3977 */
3978void
3979ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
3980{
3981 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3982 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTWRITE);
3983
3984 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
3985 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
3986
3987 ATH_TXBUF_LOCK(sc);
3988 ath_tx_update_busy(sc);
3989 ath_returnbuf_tail(sc, bf);
3990 ATH_TXBUF_UNLOCK(sc);
3991}
3992
3993/*
3994 * This is currently used by ath_tx_draintxq() and
3995 * ath_tx_tid_free_pkts().
3996 *
3997 * It recycles a single ath_buf.
3998 */
3999void
4000ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4001{
4002 struct ieee80211_node *ni = bf->bf_node;
4003 struct mbuf *m0 = bf->bf_m;
4004
4005 bf->bf_node = NULL;
4006 bf->bf_m = NULL;
4007
4008 /* Free the buffer, it's not needed any longer */
4009 ath_freebuf(sc, bf);
4010
4011 if (ni != NULL) {
4012 /*
4013 * Do any callback and reclaim the node reference.
4014 */
4015 if (m0->m_flags & M_TXCB)
4016 ieee80211_process_callback(ni, m0, status);
4017 ieee80211_free_node(ni);
4018 }
4019 m_freem(m0);
4020
4021 /*
4022 * XXX the buffer used to be freed -after-, but the DMA map was
4023 * freed where ath_freebuf() now is. I've no idea what this
4024 * will do.
4025 */
4026}
4027
4028void
4029ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4030{
4031#ifdef ATH_DEBUG
4032 struct ath_hal *ah = sc->sc_ah;
4033#endif
4034 struct ath_buf *bf;
4035 u_int ix;
4036
4037 /*
4038 * NB: this assumes output has been stopped and
4039 * we do not need to block ath_tx_proc
4040 */
4041 ATH_TXBUF_LOCK(sc);
4042 bf = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s);
4043 if (bf != NULL)
4044 bf->bf_flags &= ~ATH_BUF_BUSY;
4045 bf = TAILQ_LAST(&sc->sc_txbuf_mgmt, ath_bufhead_s);
4046 if (bf != NULL)
4047 bf->bf_flags &= ~ATH_BUF_BUSY;
4048 ATH_TXBUF_UNLOCK(sc);
4049
4050 for (ix = 0;; ix++) {
4051 ATH_TXQ_LOCK(txq);
4052 bf = TAILQ_FIRST(&txq->axq_q);
4053 if (bf == NULL) {
4054 txq->axq_link = NULL;
4055 /*
4056 * There's currently no flag that indicates
4057 * a buffer is on the FIFO. So until that
4058 * occurs, just clear the FIFO counter here.
4059 *
4060 * Yes, this means that if something in parallel
4061 * is pushing things onto this TXQ and pushing
4062 * _that_ into the hardware, things will get
4063 * very fruity very quickly.
4064 */
4065 txq->axq_fifo_depth = 0;
4066 ATH_TXQ_UNLOCK(txq);
4067 break;
4068 }
4069 ATH_TXQ_REMOVE(txq, bf, bf_list);
4070 if (bf->bf_state.bfs_aggr)
4071 txq->axq_aggr_depth--;
4072#ifdef ATH_DEBUG
4073 if (sc->sc_debug & ATH_DEBUG_RESET) {
4074 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4075 int status = 0;
4076
4077 /*
4078 * EDMA operation has a TX completion FIFO
4079 * separate from the TX descriptor, so this
4080 * method of checking the "completion" status
4081 * is wrong.
4082 */
4083 if (! sc->sc_isedma) {
4084 status = (ath_hal_txprocdesc(ah,
4085 bf->bf_lastds,
4086 &bf->bf_status.ds_txstat) == HAL_OK);
4087 }
4088 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
4089 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
4090 bf->bf_m->m_len, 0, -1);
4091 }
4092#endif /* ATH_DEBUG */
4093 /*
4094 * Since we're now doing magic in the completion
4095 * functions, we -must- call it for aggregation
4096 * destinations or BAW tracking will get upset.
4097 */
4098 /*
4099 * Clear ATH_BUF_BUSY; the completion handler
4100 * will free the buffer.
4101 */
4102 ATH_TXQ_UNLOCK(txq);
4103 bf->bf_flags &= ~ATH_BUF_BUSY;
4104 if (bf->bf_comp)
4105 bf->bf_comp(sc, bf, 1);
4106 else
4107 ath_tx_default_comp(sc, bf, 1);
4108 }
4109
4110 /*
4111 * Drain software queued frames which are on
4112 * active TIDs.
4113 */
4114 ath_tx_txq_drain(sc, txq);
4115}
4116
4117static void
4118ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4119{
4120 struct ath_hal *ah = sc->sc_ah;
4121
4122 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4123 __func__, txq->axq_qnum,
4124 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
4125 txq->axq_link);
4126 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
4127}
4128
4129int
4130ath_stoptxdma(struct ath_softc *sc)
4131{
4132 struct ath_hal *ah = sc->sc_ah;
4133 int i;
4134
4135 /* XXX return value */
4136 if (sc->sc_invalid)
4137 return 0;
4138
4139 if (!sc->sc_invalid) {
4140 /* don't touch the hardware if marked invalid */
4141 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4142 __func__, sc->sc_bhalq,
4143 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
4144 NULL);
4145 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
4146 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4147 if (ATH_TXQ_SETUP(sc, i))
4148 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4149 }
4150
4151 return 1;
4152}
4153
4154/*
4155 * Drain the transmit queues and reclaim resources.
4156 */
4157void
4158ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
4159{
4160#ifdef ATH_DEBUG
4161 struct ath_hal *ah = sc->sc_ah;
4162#endif
4163 struct ifnet *ifp = sc->sc_ifp;
4164 int i;
4165
4166 (void) ath_stoptxdma(sc);
4167
4168 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4169 /*
4170 * XXX TODO: should we just handle the completed TX frames
4171 * here, whether or not the reset is a full one or not?
4172 */
4173 if (ATH_TXQ_SETUP(sc, i)) {
4174 if (reset_type == ATH_RESET_NOLOSS)
4175 ath_tx_processq(sc, &sc->sc_txq[i], 0);
4176 else
4177 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4178 }
4179 }
4180#ifdef ATH_DEBUG
4181 if (sc->sc_debug & ATH_DEBUG_RESET) {
4182 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
4183 if (bf != NULL && bf->bf_m != NULL) {
4184 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
4185 ath_hal_txprocdesc(ah, bf->bf_lastds,
4186 &bf->bf_status.ds_txstat) == HAL_OK);
4187 ieee80211_dump_pkt(ifp->if_l2com,
4188 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
4189 0, -1);
4190 }
4191 }
4192#endif /* ATH_DEBUG */
4193 IF_LOCK(&ifp->if_snd);
4194 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4195 IF_UNLOCK(&ifp->if_snd);
4196 sc->sc_wd_timer = 0;
4197}
4198
4199/*
4200 * Update internal state after a channel change.
4201 */
4202static void
4203ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4204{
4205 enum ieee80211_phymode mode;
4206
4207 /*
4208 * Change channels and update the h/w rate map
4209 * if we're switching; e.g. 11a to 11b/g.
4210 */
4211 mode = ieee80211_chan2mode(chan);
4212 if (mode != sc->sc_curmode)
4213 ath_setcurmode(sc, mode);
4214 sc->sc_curchan = chan;
4215}
4216
4217/*
4218 * Set/change channels. If the channel is really being changed,
4219 * it's done by resetting the chip. To accomplish this we must
4220 * first cleanup any pending DMA, then restart stuff after a la
4221 * ath_init.
4222 */
4223static int
4224ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4225{
4226 struct ifnet *ifp = sc->sc_ifp;
4227 struct ieee80211com *ic = ifp->if_l2com;
4228 struct ath_hal *ah = sc->sc_ah;
4229 int ret = 0;
4230
4231 /* Treat this as an interface reset */
4232 ATH_PCU_UNLOCK_ASSERT(sc);
4233 ATH_UNLOCK_ASSERT(sc);
4234
4235 /* (Try to) stop TX/RX from occuring */
4236 taskqueue_block(sc->sc_tq);
4237
4238 ATH_PCU_LOCK(sc);
4239 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */
4240 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */
4241 if (ath_reset_grablock(sc, 1) == 0) {
4242 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
4243 __func__);
4244 }
4245 ATH_PCU_UNLOCK(sc);
4246
4247 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
4248 __func__, ieee80211_chan2ieee(ic, chan),
4249 chan->ic_freq, chan->ic_flags);
4250 if (chan != sc->sc_curchan) {
4251 HAL_STATUS status;
4252 /*
4253 * To switch channels clear any pending DMA operations;
4254 * wait long enough for the RX fifo to drain, reset the
4255 * hardware at the new frequency, and then re-enable
4256 * the relevant bits of the h/w.
4257 */
4258#if 0
4259 ath_hal_intrset(ah, 0); /* disable interrupts */
4260#endif
4261 ath_stoprecv(sc, 1); /* turn off frame recv */
4262 /*
4263 * First, handle completed TX/RX frames.
4264 */
4265 ath_rx_flush(sc);
4266 ath_draintxq(sc, ATH_RESET_NOLOSS);
4267 /*
4268 * Next, flush the non-scheduled frames.
4269 */
4270 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
4271
4272 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
4273 if_printf(ifp, "%s: unable to reset "
4274 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
4275 __func__, ieee80211_chan2ieee(ic, chan),
4276 chan->ic_freq, chan->ic_flags, status);
4277 ret = EIO;
4278 goto finish;
4279 }
4280 sc->sc_diversity = ath_hal_getdiversity(ah);
4281
4282 /* Let DFS at it in case it's a DFS channel */
4283 ath_dfs_radar_enable(sc, chan);
4284
4285 /*
4286 * Re-enable rx framework.
4287 */
4288 if (ath_startrecv(sc) != 0) {
4289 if_printf(ifp, "%s: unable to restart recv logic\n",
4290 __func__);
4291 ret = EIO;
4292 goto finish;
4293 }
4294
4295 /*
4296 * Change channels and update the h/w rate map
4297 * if we're switching; e.g. 11a to 11b/g.
4298 */
4299 ath_chan_change(sc, chan);
4300
4301 /*
4302 * Reset clears the beacon timers; reset them
4303 * here if needed.
4304 */
4305 if (sc->sc_beacons) { /* restart beacons */
4306#ifdef IEEE80211_SUPPORT_TDMA
4307 if (sc->sc_tdma)
4308 ath_tdma_config(sc, NULL);
4309 else
4310#endif
4311 ath_beacon_config(sc, NULL);
4312 }
4313
4314 /*
4315 * Re-enable interrupts.
4316 */
4317#if 0
4318 ath_hal_intrset(ah, sc->sc_imask);
4319#endif
4320 }
4321
4322finish:
4323 ATH_PCU_LOCK(sc);
4324 sc->sc_inreset_cnt--;
4325 /* XXX only do this if sc_inreset_cnt == 0? */
4326 ath_hal_intrset(ah, sc->sc_imask);
4327 ATH_PCU_UNLOCK(sc);
4328
4329 IF_LOCK(&ifp->if_snd);
4330 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4331 IF_UNLOCK(&ifp->if_snd);
4332 ath_txrx_start(sc);
4333 /* XXX ath_start? */
4334
4335 return ret;
4336}
4337
4338/*
4339 * Periodically recalibrate the PHY to account
4340 * for temperature/environment changes.
4341 */
4342static void
4343ath_calibrate(void *arg)
4344{
4345 struct ath_softc *sc = arg;
4346 struct ath_hal *ah = sc->sc_ah;
4347 struct ifnet *ifp = sc->sc_ifp;
4348 struct ieee80211com *ic = ifp->if_l2com;
4349 HAL_BOOL longCal, isCalDone;
4350 HAL_BOOL aniCal, shortCal = AH_FALSE;
4351 int nextcal;
4352
4353 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
4354 goto restart;
4355 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
4356 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
4357 if (sc->sc_doresetcal)
4358 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
4359
4360 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
4361 if (aniCal) {
4362 sc->sc_stats.ast_ani_cal++;
4363 sc->sc_lastani = ticks;
4364 ath_hal_ani_poll(ah, sc->sc_curchan);
4365 }
4366
4367 if (longCal) {
4368 sc->sc_stats.ast_per_cal++;
4369 sc->sc_lastlongcal = ticks;
4370 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4371 /*
4372 * Rfgain is out of bounds, reset the chip
4373 * to load new gain values.
4374 */
4375 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4376 "%s: rfgain change\n", __func__);
4377 sc->sc_stats.ast_per_rfgain++;
4378 sc->sc_resetcal = 0;
4379 sc->sc_doresetcal = AH_TRUE;
4380 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
4381 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
4382 return;
4383 }
4384 /*
4385 * If this long cal is after an idle period, then
4386 * reset the data collection state so we start fresh.
4387 */
4388 if (sc->sc_resetcal) {
4389 (void) ath_hal_calreset(ah, sc->sc_curchan);
4390 sc->sc_lastcalreset = ticks;
4391 sc->sc_lastshortcal = ticks;
4392 sc->sc_resetcal = 0;
4393 sc->sc_doresetcal = AH_TRUE;
4394 }
4395 }
4396
4397 /* Only call if we're doing a short/long cal, not for ANI calibration */
4398 if (shortCal || longCal) {
4399 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
4400 if (longCal) {
4401 /*
4402 * Calibrate noise floor data again in case of change.
4403 */
4404 ath_hal_process_noisefloor(ah);
4405 }
4406 } else {
4407 DPRINTF(sc, ATH_DEBUG_ANY,
4408 "%s: calibration of channel %u failed\n",
4409 __func__, sc->sc_curchan->ic_freq);
4410 sc->sc_stats.ast_per_calfail++;
4411 }
4412 if (shortCal)
4413 sc->sc_lastshortcal = ticks;
4414 }
4415 if (!isCalDone) {
4416restart:
4417 /*
4418 * Use a shorter interval to potentially collect multiple
4419 * data samples required to complete calibration. Once
4420 * we're told the work is done we drop back to a longer
4421 * interval between requests. We're more aggressive doing
4422 * work when operating as an AP to improve operation right
4423 * after startup.
4424 */
4425 sc->sc_lastshortcal = ticks;
4426 nextcal = ath_shortcalinterval*hz/1000;
4427 if (sc->sc_opmode != HAL_M_HOSTAP)
4428 nextcal *= 10;
4429 sc->sc_doresetcal = AH_TRUE;
4430 } else {
4431 /* nextcal should be the shortest time for next event */
4432 nextcal = ath_longcalinterval*hz;
4433 if (sc->sc_lastcalreset == 0)
4434 sc->sc_lastcalreset = sc->sc_lastlongcal;
4435 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
4436 sc->sc_resetcal = 1; /* setup reset next trip */
4437 sc->sc_doresetcal = AH_FALSE;
4438 }
4439 /* ANI calibration may occur more often than short/long/resetcal */
4440 if (ath_anicalinterval > 0)
4441 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
4442
4443 if (nextcal != 0) {
4444 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
4445 __func__, nextcal, isCalDone ? "" : "!");
4446 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
4447 } else {
4448 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
4449 __func__);
4450 /* NB: don't rearm timer */
4451 }
4452}
4453
4454static void
4455ath_scan_start(struct ieee80211com *ic)
4456{
4457 struct ifnet *ifp = ic->ic_ifp;
4458 struct ath_softc *sc = ifp->if_softc;
4459 struct ath_hal *ah = sc->sc_ah;
4460 u_int32_t rfilt;
4461
4462 /* XXX calibration timer? */
4463
4464 ATH_LOCK(sc);
4465 sc->sc_scanning = 1;
4466 sc->sc_syncbeacon = 0;
4467 rfilt = ath_calcrxfilter(sc);
4468 ATH_UNLOCK(sc);
4469
4470 ATH_PCU_LOCK(sc);
4471 ath_hal_setrxfilter(ah, rfilt);
4472 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
4473 ATH_PCU_UNLOCK(sc);
4474
4475 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
4476 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
4477}
4478
4479static void
4480ath_scan_end(struct ieee80211com *ic)
4481{
4482 struct ifnet *ifp = ic->ic_ifp;
4483 struct ath_softc *sc = ifp->if_softc;
4484 struct ath_hal *ah = sc->sc_ah;
4485 u_int32_t rfilt;
4486
4487 ATH_LOCK(sc);
4488 sc->sc_scanning = 0;
4489 rfilt = ath_calcrxfilter(sc);
4490 ATH_UNLOCK(sc);
4491
4492 ATH_PCU_LOCK(sc);
4493 ath_hal_setrxfilter(ah, rfilt);
4494 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
4495
4496 ath_hal_process_noisefloor(ah);
4497 ATH_PCU_UNLOCK(sc);
4498
4499 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
4500 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
4501 sc->sc_curaid);
4502}
4503
4504#ifdef ATH_ENABLE_11N
4505/*
4506 * For now, just do a channel change.
4507 *
4508 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
4509 * control state and resetting the hardware without dropping frames out
4510 * of the queue.
4511 *
4512 * The unfortunate trouble here is making absolutely sure that the
4513 * channel width change has propagated enough so the hardware
4514 * absolutely isn't handed bogus frames for it's current operating
4515 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
4516 * does occur in parallel, we need to make certain we've blocked
4517 * any further ongoing TX (and RX, that can cause raw TX)
4518 * before we do this.
4519 */
4520static void
4521ath_update_chw(struct ieee80211com *ic)
4522{
4523 struct ifnet *ifp = ic->ic_ifp;
4524 struct ath_softc *sc = ifp->if_softc;
4525
4526 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
4527 ath_set_channel(ic);
4528}
4529#endif /* ATH_ENABLE_11N */
4530
4531static void
4532ath_set_channel(struct ieee80211com *ic)
4533{
4534 struct ifnet *ifp = ic->ic_ifp;
4535 struct ath_softc *sc = ifp->if_softc;
4536
4537 (void) ath_chan_set(sc, ic->ic_curchan);
4538 /*
4539 * If we are returning to our bss channel then mark state
4540 * so the next recv'd beacon's tsf will be used to sync the
4541 * beacon timers. Note that since we only hear beacons in
4542 * sta/ibss mode this has no effect in other operating modes.
4543 */
4544 ATH_LOCK(sc);
4545 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
4546 sc->sc_syncbeacon = 1;
4547 ATH_UNLOCK(sc);
4548}
4549
4550/*
4551 * Walk the vap list and check if there any vap's in RUN state.
4552 */
4553static int
4554ath_isanyrunningvaps(struct ieee80211vap *this)
4555{
4556 struct ieee80211com *ic = this->iv_ic;
4557 struct ieee80211vap *vap;
4558
4559 IEEE80211_LOCK_ASSERT(ic);
4560
4561 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
4562 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
4563 return 1;
4564 }
4565 return 0;
4566}
4567
4568static int
4569ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
4570{
4571 struct ieee80211com *ic = vap->iv_ic;
4572 struct ath_softc *sc = ic->ic_ifp->if_softc;
4573 struct ath_vap *avp = ATH_VAP(vap);
4574 struct ath_hal *ah = sc->sc_ah;
4575 struct ieee80211_node *ni = NULL;
4576 int i, error, stamode;
4577 u_int32_t rfilt;
4578 int csa_run_transition = 0;
4579 static const HAL_LED_STATE leds[] = {
4580 HAL_LED_INIT, /* IEEE80211_S_INIT */
4581 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4582 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4583 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4584 HAL_LED_RUN, /* IEEE80211_S_CAC */
4585 HAL_LED_RUN, /* IEEE80211_S_RUN */
4586 HAL_LED_RUN, /* IEEE80211_S_CSA */
4587 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
4588 };
4589
4590 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4591 ieee80211_state_name[vap->iv_state],
4592 ieee80211_state_name[nstate]);
4593
4594 /*
4595 * net80211 _should_ have the comlock asserted at this point.
4596 * There are some comments around the calls to vap->iv_newstate
4597 * which indicate that it (newstate) may end up dropping the
4598 * lock. This and the subsequent lock assert check after newstate
4599 * are an attempt to catch these and figure out how/why.
4600 */
4601 IEEE80211_LOCK_ASSERT(ic);
4602
4603 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
4604 csa_run_transition = 1;
4605
4606 callout_drain(&sc->sc_cal_ch);
4607 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4608
4609 if (nstate == IEEE80211_S_SCAN) {
4610 /*
4611 * Scanning: turn off beacon miss and don't beacon.
4612 * Mark beacon state so when we reach RUN state we'll
4613 * [re]setup beacons. Unblock the task q thread so
4614 * deferred interrupt processing is done.
4615 */
4616 ath_hal_intrset(ah,
4617 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4618 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4619 sc->sc_beacons = 0;
4620 taskqueue_unblock(sc->sc_tq);
4621 }
4622
4623 ni = ieee80211_ref_node(vap->iv_bss);
4624 rfilt = ath_calcrxfilter(sc);
4625 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
4626 vap->iv_opmode == IEEE80211_M_AHDEMO ||
4627 vap->iv_opmode == IEEE80211_M_IBSS);
4628 if (stamode && nstate == IEEE80211_S_RUN) {
4629 sc->sc_curaid = ni->ni_associd;
4630 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
4631 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
4632 }
4633 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
4634 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
4635 ath_hal_setrxfilter(ah, rfilt);
4636
4637 /* XXX is this to restore keycache on resume? */
4638 if (vap->iv_opmode != IEEE80211_M_STA &&
4639 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
4640 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4641 if (ath_hal_keyisvalid(ah, i))
4642 ath_hal_keysetmac(ah, i, ni->ni_bssid);
4643 }
4644
4645 /*
4646 * Invoke the parent method to do net80211 work.
4647 */
4648 error = avp->av_newstate(vap, nstate, arg);
4649 if (error != 0)
4650 goto bad;
4651
4652 /*
4653 * See above: ensure av_newstate() doesn't drop the lock
4654 * on us.
4655 */
4656 IEEE80211_LOCK_ASSERT(ic);
4657
4658 if (nstate == IEEE80211_S_RUN) {
4659 /* NB: collect bss node again, it may have changed */
4660 ieee80211_free_node(ni);
4661 ni = ieee80211_ref_node(vap->iv_bss);
4662
4663 DPRINTF(sc, ATH_DEBUG_STATE,
4664 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
4665 "capinfo 0x%04x chan %d\n", __func__,
4666 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
4667 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
4668
4669 switch (vap->iv_opmode) {
4670#ifdef IEEE80211_SUPPORT_TDMA
4671 case IEEE80211_M_AHDEMO:
4672 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
4673 break;
4674 /* fall thru... */
4675#endif
4676 case IEEE80211_M_HOSTAP:
4677 case IEEE80211_M_IBSS:
4678 case IEEE80211_M_MBSS:
4679 /*
4680 * Allocate and setup the beacon frame.
4681 *
4682 * Stop any previous beacon DMA. This may be
4683 * necessary, for example, when an ibss merge
4684 * causes reconfiguration; there will be a state
4685 * transition from RUN->RUN that means we may
4686 * be called with beacon transmission active.
4687 */
4688 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4689
4690 error = ath_beacon_alloc(sc, ni);
4691 if (error != 0)
4692 goto bad;
4693 /*
4694 * If joining an adhoc network defer beacon timer
4695 * configuration to the next beacon frame so we
4696 * have a current TSF to use. Otherwise we're
4697 * starting an ibss/bss so there's no need to delay;
4698 * if this is the first vap moving to RUN state, then
4699 * beacon state needs to be [re]configured.
4700 */
4701 if (vap->iv_opmode == IEEE80211_M_IBSS &&
4702 ni->ni_tstamp.tsf != 0) {
4703 sc->sc_syncbeacon = 1;
4704 } else if (!sc->sc_beacons) {
4705#ifdef IEEE80211_SUPPORT_TDMA
4706 if (vap->iv_caps & IEEE80211_C_TDMA)
4707 ath_tdma_config(sc, vap);
4708 else
4709#endif
4710 ath_beacon_config(sc, vap);
4711 sc->sc_beacons = 1;
4712 }
4713 break;
4714 case IEEE80211_M_STA:
4715 /*
4716 * Defer beacon timer configuration to the next
4717 * beacon frame so we have a current TSF to use
4718 * (any TSF collected when scanning is likely old).
4719 * However if it's due to a CSA -> RUN transition,
4720 * force a beacon update so we pick up a lack of
4721 * beacons from an AP in CAC and thus force a
4722 * scan.
4723 */
4724 sc->sc_syncbeacon = 1;
4725 if (csa_run_transition)
4726 ath_beacon_config(sc, vap);
4727 break;
4728 case IEEE80211_M_MONITOR:
4729 /*
4730 * Monitor mode vaps have only INIT->RUN and RUN->RUN
4731 * transitions so we must re-enable interrupts here to
4732 * handle the case of a single monitor mode vap.
4733 */
4734 ath_hal_intrset(ah, sc->sc_imask);
4735 break;
4736 case IEEE80211_M_WDS:
4737 break;
4738 default:
4739 break;
4740 }
4741 /*
4742 * Let the hal process statistics collected during a
4743 * scan so it can provide calibrated noise floor data.
4744 */
4745 ath_hal_process_noisefloor(ah);
4746 /*
4747 * Reset rssi stats; maybe not the best place...
4748 */
4749 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4750 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4751 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4752 /*
4753 * Finally, start any timers and the task q thread
4754 * (in case we didn't go through SCAN state).
4755 */
4756 if (ath_longcalinterval != 0) {
4757 /* start periodic recalibration timer */
4758 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
4759 } else {
4760 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4761 "%s: calibration disabled\n", __func__);
4762 }
4763 taskqueue_unblock(sc->sc_tq);
4764 } else if (nstate == IEEE80211_S_INIT) {
4765 /*
4766 * If there are no vaps left in RUN state then
4767 * shutdown host/driver operation:
4768 * o disable interrupts
4769 * o disable the task queue thread
4770 * o mark beacon processing as stopped
4771 */
4772 if (!ath_isanyrunningvaps(vap)) {
4773 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4774 /* disable interrupts */
4775 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4776 taskqueue_block(sc->sc_tq);
4777 sc->sc_beacons = 0;
4778 }
4779#ifdef IEEE80211_SUPPORT_TDMA
4780 ath_hal_setcca(ah, AH_TRUE);
4781#endif
4782 }
4783bad:
4784 ieee80211_free_node(ni);
4785 return error;
4786}
4787
4788/*
4789 * Allocate a key cache slot to the station so we can
4790 * setup a mapping from key index to node. The key cache
4791 * slot is needed for managing antenna state and for
4792 * compression when stations do not use crypto. We do
4793 * it uniliaterally here; if crypto is employed this slot
4794 * will be reassigned.
4795 */
4796static void
4797ath_setup_stationkey(struct ieee80211_node *ni)
4798{
4799 struct ieee80211vap *vap = ni->ni_vap;
4800 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
4801 ieee80211_keyix keyix, rxkeyix;
4802
4803 /* XXX should take a locked ref to vap->iv_bss */
4804 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4805 /*
4806 * Key cache is full; we'll fall back to doing
4807 * the more expensive lookup in software. Note
4808 * this also means no h/w compression.
4809 */
4810 /* XXX msg+statistic */
4811 } else {
4812 /* XXX locking? */
4813 ni->ni_ucastkey.wk_keyix = keyix;
4814 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4815 /* NB: must mark device key to get called back on delete */
4816 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
4817 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
4818 /* NB: this will create a pass-thru key entry */
4819 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
4820 }
4821}
4822
4823/*
4824 * Setup driver-specific state for a newly associated node.
4825 * Note that we're called also on a re-associate, the isnew
4826 * param tells us if this is the first time or not.
4827 */
4828static void
4829ath_newassoc(struct ieee80211_node *ni, int isnew)
4830{
4831 struct ath_node *an = ATH_NODE(ni);
4832 struct ieee80211vap *vap = ni->ni_vap;
4833 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
4834 const struct ieee80211_txparam *tp = ni->ni_txparms;
4835
4836 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
4837 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
4838
4839 ath_rate_newassoc(sc, an, isnew);
4840 if (isnew &&
4841 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
4842 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4843 ath_setup_stationkey(ni);
4844}
4845
4846static int
4847ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
4848 int nchans, struct ieee80211_channel chans[])
4849{
4850 struct ath_softc *sc = ic->ic_ifp->if_softc;
4851 struct ath_hal *ah = sc->sc_ah;
4852 HAL_STATUS status;
4853
4854 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
4855 "%s: rd %u cc %u location %c%s\n",
4856 __func__, reg->regdomain, reg->country, reg->location,
4857 reg->ecm ? " ecm" : "");
4858
4859 status = ath_hal_set_channels(ah, chans, nchans,
4860 reg->country, reg->regdomain);
4861 if (status != HAL_OK) {
4862 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
4863 __func__, status);
4864 return EINVAL; /* XXX */
4865 }
4866
4867 return 0;
4868}
4869
4870static void
4871ath_getradiocaps(struct ieee80211com *ic,
4872 int maxchans, int *nchans, struct ieee80211_channel chans[])
4873{
4874 struct ath_softc *sc = ic->ic_ifp->if_softc;
4875 struct ath_hal *ah = sc->sc_ah;
4876
4877 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
4878 __func__, SKU_DEBUG, CTRY_DEFAULT);
4879
4880 /* XXX check return */
4881 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
4882 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
4883
4884}
4885
4886static int
4887ath_getchannels(struct ath_softc *sc)
4888{
4889 struct ifnet *ifp = sc->sc_ifp;
4890 struct ieee80211com *ic = ifp->if_l2com;
4891 struct ath_hal *ah = sc->sc_ah;
4892 HAL_STATUS status;
4893
4894 /*
4895 * Collect channel set based on EEPROM contents.
4896 */
4897 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
4898 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
4899 if (status != HAL_OK) {
4900 if_printf(ifp, "%s: unable to collect channel list from hal, "
4901 "status %d\n", __func__, status);
4902 return EINVAL;
4903 }
4904 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
4905 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
4906 /* XXX map Atheros sku's to net80211 SKU's */
4907 /* XXX net80211 types too small */
4908 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
4909 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
4910 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
4911 ic->ic_regdomain.isocc[1] = ' ';
4912
4913 ic->ic_regdomain.ecm = 1;
4914 ic->ic_regdomain.location = 'I';
4915
4916 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
4917 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
4918 __func__, sc->sc_eerd, sc->sc_eecc,
4919 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
4920 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
4921 return 0;
4922}
4923
4924static int
4925ath_rate_setup(struct ath_softc *sc, u_int mode)
4926{
4927 struct ath_hal *ah = sc->sc_ah;
4928 const HAL_RATE_TABLE *rt;
4929
4930 switch (mode) {
4931 case IEEE80211_MODE_11A:
4932 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4933 break;
4934 case IEEE80211_MODE_HALF:
4935 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
4936 break;
4937 case IEEE80211_MODE_QUARTER:
4938 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
4939 break;
4940 case IEEE80211_MODE_11B:
4941 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4942 break;
4943 case IEEE80211_MODE_11G:
4944 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4945 break;
4946 case IEEE80211_MODE_TURBO_A:
4947 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
4948 break;
4949 case IEEE80211_MODE_TURBO_G:
4950 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4951 break;
4952 case IEEE80211_MODE_STURBO_A:
4953 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4954 break;
4955 case IEEE80211_MODE_11NA:
4956 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
4957 break;
4958 case IEEE80211_MODE_11NG:
4959 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
4960 break;
4961 default:
4962 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4963 __func__, mode);
4964 return 0;
4965 }
4966 sc->sc_rates[mode] = rt;
4967 return (rt != NULL);
4968}
4969
4970static void
4971ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4972{
4973#define N(a) (sizeof(a)/sizeof(a[0]))
4974 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4975 static const struct {
4976 u_int rate; /* tx/rx 802.11 rate */
4977 u_int16_t timeOn; /* LED on time (ms) */
4978 u_int16_t timeOff; /* LED off time (ms) */
4979 } blinkrates[] = {
4980 { 108, 40, 10 },
4981 { 96, 44, 11 },
4982 { 72, 50, 13 },
4983 { 48, 57, 14 },
4984 { 36, 67, 16 },
4985 { 24, 80, 20 },
4986 { 22, 100, 25 },
4987 { 18, 133, 34 },
4988 { 12, 160, 40 },
4989 { 10, 200, 50 },
4990 { 6, 240, 58 },
4991 { 4, 267, 66 },
4992 { 2, 400, 100 },
4993 { 0, 500, 130 },
4994 /* XXX half/quarter rates */
4995 };
4996 const HAL_RATE_TABLE *rt;
4997 int i, j;
4998
4999 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
5000 rt = sc->sc_rates[mode];
5001 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
5002 for (i = 0; i < rt->rateCount; i++) {
5003 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5004 if (rt->info[i].phy != IEEE80211_T_HT)
5005 sc->sc_rixmap[ieeerate] = i;
5006 else
5007 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
5008 }
5009 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
5010 for (i = 0; i < N(sc->sc_hwmap); i++) {
5011 if (i >= rt->rateCount) {
5012 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5013 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5014 continue;
5015 }
5016 sc->sc_hwmap[i].ieeerate =
5017 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
5018 if (rt->info[i].phy == IEEE80211_T_HT)
5019 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
5020 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5021 if (rt->info[i].shortPreamble ||
5022 rt->info[i].phy == IEEE80211_T_OFDM)
5023 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5024 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
5025 for (j = 0; j < N(blinkrates)-1; j++)
5026 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5027 break;
5028 /* NB: this uses the last entry if the rate isn't found */
5029 /* XXX beware of overlow */
5030 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5031 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5032 }
5033 sc->sc_currates = rt;
5034 sc->sc_curmode = mode;
5035 /*
5036 * All protection frames are transmited at 2Mb/s for
5037 * 11g, otherwise at 1Mb/s.
5038 */
5039 if (mode == IEEE80211_MODE_11G)
5040 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
5041 else
5042 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
5043 /* NB: caller is responsible for resetting rate control state */
5044#undef N
5045}
5046
5047static void
5048ath_watchdog(void *arg)
5049{
5050 struct ath_softc *sc = arg;
5051 int do_reset = 0;
5052
5053 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
5054 struct ifnet *ifp = sc->sc_ifp;
5055 uint32_t hangs;
5056
5057 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
5058 hangs != 0) {
5059 if_printf(ifp, "%s hang detected (0x%x)\n",
5060 hangs & 0xff ? "bb" : "mac", hangs);
5061 } else
5062 if_printf(ifp, "device timeout\n");
5063 do_reset = 1;
5064 ifp->if_oerrors++;
5065 sc->sc_stats.ast_watchdog++;
5066 }
5067
5068 /*
5069 * We can't hold the lock across the ath_reset() call.
5070 *
5071 * And since this routine can't hold a lock and sleep,
5072 * do the reset deferred.
5073 */
5074 if (do_reset) {
5075 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5076 }
5077
5078 callout_schedule(&sc->sc_wd_ch, hz);
5079}
5080
5081/*
5082 * Fetch the rate control statistics for the given node.
5083 */
5084static int
5085ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
5086{
5087 struct ath_node *an;
5088 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5089 struct ieee80211_node *ni;
5090 int error = 0;
5091
5092 /* Perform a lookup on the given node */
5093 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
5094 if (ni == NULL) {
5095 error = EINVAL;
5096 goto bad;
5097 }
5098
5099 /* Lock the ath_node */
5100 an = ATH_NODE(ni);
5101 ATH_NODE_LOCK(an);
5102
5103 /* Fetch the rate control stats for this node */
5104 error = ath_rate_fetch_node_stats(sc, an, rs);
5105
5106 /* No matter what happens here, just drop through */
5107
5108 /* Unlock the ath_node */
5109 ATH_NODE_UNLOCK(an);
5110
5111 /* Unref the node */
5112 ieee80211_node_decref(ni);
5113
5114bad:
5115 return (error);
5116}
5117
5118#ifdef ATH_DIAGAPI
5119/*
5120 * Diagnostic interface to the HAL. This is used by various
5121 * tools to do things like retrieve register contents for
5122 * debugging. The mechanism is intentionally opaque so that
5123 * it can change frequently w/o concern for compatiblity.
5124 */
5125static int
5126ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5127{
5128 struct ath_hal *ah = sc->sc_ah;
5129 u_int id = ad->ad_id & ATH_DIAG_ID;
5130 void *indata = NULL;
5131 void *outdata = NULL;
5132 u_int32_t insize = ad->ad_in_size;
5133 u_int32_t outsize = ad->ad_out_size;
5134 int error = 0;
5135
5136 if (ad->ad_id & ATH_DIAG_IN) {
5137 /*
5138 * Copy in data.
5139 */
5140 indata = malloc(insize, M_TEMP, M_NOWAIT);
5141 if (indata == NULL) {
5142 error = ENOMEM;
5143 goto bad;
5144 }
5145 error = copyin(ad->ad_in_data, indata, insize);
5146 if (error)
5147 goto bad;
5148 }
5149 if (ad->ad_id & ATH_DIAG_DYN) {
5150 /*
5151 * Allocate a buffer for the results (otherwise the HAL
5152 * returns a pointer to a buffer where we can read the
5153 * results). Note that we depend on the HAL leaving this
5154 * pointer for us to use below in reclaiming the buffer;
5155 * may want to be more defensive.
5156 */
5157 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
5158 if (outdata == NULL) {
5159 error = ENOMEM;
5160 goto bad;
5161 }
5162 }
5163 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5164 if (outsize < ad->ad_out_size)
5165 ad->ad_out_size = outsize;
5166 if (outdata != NULL)
5167 error = copyout(outdata, ad->ad_out_data,
5168 ad->ad_out_size);
5169 } else {
5170 error = EINVAL;
5171 }
5172bad:
5173 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5174 free(indata, M_TEMP);
5175 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5176 free(outdata, M_TEMP);
5177 return error;
5178}
5179#endif /* ATH_DIAGAPI */
5180
5181static int
5182ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
5183{
5184#define IS_RUNNING(ifp) \
5185 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
5186 struct ath_softc *sc = ifp->if_softc;
5187 struct ieee80211com *ic = ifp->if_l2com;
5188 struct ifreq *ifr = (struct ifreq *)data;
5189 const HAL_RATE_TABLE *rt;
5190 int error = 0;
5191
5192 switch (cmd) {
5193 case SIOCSIFFLAGS:
5194 ATH_LOCK(sc);
5195 if (IS_RUNNING(ifp)) {
5196 /*
5197 * To avoid rescanning another access point,
5198 * do not call ath_init() here. Instead,
5199 * only reflect promisc mode settings.
5200 */
5201 ath_mode_init(sc);
5202 } else if (ifp->if_flags & IFF_UP) {
5203 /*
5204 * Beware of being called during attach/detach
5205 * to reset promiscuous mode. In that case we
5206 * will still be marked UP but not RUNNING.
5207 * However trying to re-init the interface
5208 * is the wrong thing to do as we've already
5209 * torn down much of our state. There's
5210 * probably a better way to deal with this.
5211 */
5212 if (!sc->sc_invalid)
5213 ath_init(sc); /* XXX lose error */
5214 } else {
5215 ath_stop_locked(ifp);
5216#ifdef notyet
5217 /* XXX must wakeup in places like ath_vap_delete */
5218 if (!sc->sc_invalid)
5219 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
5220#endif
5221 }
5222 ATH_UNLOCK(sc);
5223 break;
5224 case SIOCGIFMEDIA:
5225 case SIOCSIFMEDIA:
5226 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
5227 break;
5228 case SIOCGATHSTATS:
5229 /* NB: embed these numbers to get a consistent view */
5230 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5231 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5232 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
5233 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
5234#ifdef IEEE80211_SUPPORT_TDMA
5235 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
5236 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
5237#endif
5238 rt = sc->sc_currates;
5239 sc->sc_stats.ast_tx_rate =
5240 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
5241 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
5242 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
5243 return copyout(&sc->sc_stats,
5244 ifr->ifr_data, sizeof (sc->sc_stats));
5245 case SIOCGATHAGSTATS:
5246 return copyout(&sc->sc_aggr_stats,
5247 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
5248 case SIOCZATHSTATS:
5249 error = priv_check(curthread, PRIV_DRIVER);
5250 if (error == 0) {
5251 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
5252 memset(&sc->sc_aggr_stats, 0,
5253 sizeof(sc->sc_aggr_stats));
5254 memset(&sc->sc_intr_stats, 0,
5255 sizeof(sc->sc_intr_stats));
5256 }
5257 break;
5258#ifdef ATH_DIAGAPI
5259 case SIOCGATHDIAG:
5260 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
5261 break;
5262 case SIOCGATHPHYERR:
5263 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
5264 break;
5265#endif
5266 case SIOCGATHNODERATESTATS:
5267 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
5268 break;
5269 case SIOCGIFADDR:
5270 error = ether_ioctl(ifp, cmd, data);
5271 break;
5272 default:
5273 error = EINVAL;
5274 break;
5275 }
5276 return error;
5277#undef IS_RUNNING
5278}
5279
5280/*
5281 * Announce various information on device/driver attach.
5282 */
5283static void
5284ath_announce(struct ath_softc *sc)
5285{
5286 struct ifnet *ifp = sc->sc_ifp;
5287 struct ath_hal *ah = sc->sc_ah;
5288
5289 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
5290 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
5291 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5292 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
5293 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
5294 if (bootverbose) {
5295 int i;
5296 for (i = 0; i <= WME_AC_VO; i++) {
5297 struct ath_txq *txq = sc->sc_ac2q[i];
5298 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5299 txq->axq_qnum, ieee80211_wme_acnames[i]);
5300 }
5301 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5302 sc->sc_cabq->axq_qnum);
5303 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5304 }
5305 if (ath_rxbuf != ATH_RXBUF)
5306 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5307 if (ath_txbuf != ATH_TXBUF)
5308 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5309 if (sc->sc_mcastkey && bootverbose)
5310 if_printf(ifp, "using multicast key search\n");
5311}
5312
5313static void
5314ath_dfs_tasklet(void *p, int npending)
5315{
5316 struct ath_softc *sc = (struct ath_softc *) p;
5317 struct ifnet *ifp = sc->sc_ifp;
5318 struct ieee80211com *ic = ifp->if_l2com;
5319
5320 /*
5321 * If previous processing has found a radar event,
5322 * signal this to the net80211 layer to begin DFS
5323 * processing.
5324 */
5325 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
5326 /* DFS event found, initiate channel change */
5327 /*
5328 * XXX doesn't currently tell us whether the event
5329 * XXX was found in the primary or extension
5330 * XXX channel!
5331 */
5332 IEEE80211_LOCK(ic);
5333 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
5334 IEEE80211_UNLOCK(ic);
5335 }
5336}
5337
5338MODULE_VERSION(if_ath, 1);
5339MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
5340#if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ)
5341MODULE_DEPEND(if_ath, alq, 1, 1, 1);
5342#endif