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ar9280_attach.c (203682) ar9280_attach.c (203882)
1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c 203682 2010-02-08 20:12:01Z rpaulo $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c 203882 2010-02-14 16:26:32Z rpaulo $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
26#include "ah_eeprom_v4k.h"
27
28#include "ar5416/ar9280.h"
29#include "ar5416/ar5416reg.h"
30#include "ar5416/ar5416phy.h"
31
32#include "ar5416/ar9280v1.ini"
33#include "ar5416/ar9280v2.ini"
26
27#include "ar5416/ar9280.h"
28#include "ar5416/ar5416reg.h"
29#include "ar5416/ar5416phy.h"
30
31#include "ar5416/ar9280v1.ini"
32#include "ar5416/ar9280v2.ini"
34#include "ar5416/ar9285.ini"
35#include "ar5416/ar9285v2.ini"
36
33
37
38static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
39 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
40 .calNumSamples = MIN_CAL_SAMPLES,
41 .calCountMax = PER_MAX_LOG_COUNT,
42 .calCollect = ar5416IQCalCollect,
43 .calPostProc = ar5416IQCalibration
44};
45static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */

--- 72 unchanged lines hidden (view full) ---

118 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
119 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
120 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
121
122 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
123 AH5416(ah)->ah_writeIni = ar9280WriteIni;
124 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
125 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
34static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
35 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
36 .calNumSamples = MIN_CAL_SAMPLES,
37 .calCountMax = PER_MAX_LOG_COUNT,
38 .calCollect = ar5416IQCalCollect,
39 .calPostProc = ar5416IQCalibration
40};
41static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */

--- 72 unchanged lines hidden (view full) ---

114 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
115 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
116 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
117
118 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
119 AH5416(ah)->ah_writeIni = ar9280WriteIni;
120 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK;
121 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK;
126 if (AR_SREV_KITE(ah)) {
127 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
128 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
129 }
130
131 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
132 /* reset chip */
133 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
134 __func__);
135 ecode = HAL_EIO;
136 goto bad;
137 }

--- 12 unchanged lines hidden (view full) ---

150 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
151 /* NB: include chip type to differentiate from pre-Sowl versions */
152 AH_PRIVATE(ah)->ah_macVersion =
153 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
154 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
155 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
156
157 /* setup common ini data; rf backends handle remainder */
122
123 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
124 /* reset chip */
125 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
126 __func__);
127 ecode = HAL_EIO;
128 goto bad;
129 }

--- 12 unchanged lines hidden (view full) ---

142 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
143 /* NB: include chip type to differentiate from pre-Sowl versions */
144 AH_PRIVATE(ah)->ah_macVersion =
145 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
146 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
147 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
148
149 /* setup common ini data; rf backends handle remainder */
158 /* XXX power consumption higer if clkreq is on */
159 if (AR_SREV_KITE_12_OR_LATER(ah)) {
160 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
161 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
162 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
163 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
164 } else if (AR_SREV_KITE_10_OR_LATER(ah)) {
165 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
166 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
167 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
168 ar9285PciePhy_clkreq_always_on_L1, 2);
169 } else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
150 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
170 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
171 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
172 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
173 ar9280PciePhy_clkreq_always_on_L1_v2, 2);
174 HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
175 ar9280Modes_fast_clock_v2, 3);
176 } else {
177 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
178 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
179 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
180 ar9280PciePhy_v1, 2);
181 }
182 ar5416AttachPCIE(ah);
183
151 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6);
152 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2);
153 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
154 ar9280PciePhy_clkreq_always_on_L1_v2, 2);
155 HAL_INI_INIT(&ahp9280->ah_ini_xmodes,
156 ar9280Modes_fast_clock_v2, 3);
157 } else {
158 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6);
159 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2);
160 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
161 ar9280PciePhy_v1, 2);
162 }
163 ar5416AttachPCIE(ah);
164
184 if (devid == AR9285_DEVID_PCIE)
185 ecode = ath_hal_v4kEepromAttach(ah);
186 else
187 ecode = ath_hal_v14EepromAttach(ah);
165 ecode = ath_hal_v14EepromAttach(ah);
188 if (ecode != HAL_OK)
189 goto bad;
190
191 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
192 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
193 ecode = HAL_EIO;
194 goto bad;
195 }

--- 56 unchanged lines hidden (view full) ---

252 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
253 ar9280Modes_original_rxgain_v2, 6);
254 break;
255 default:
256 HALASSERT(AH_FALSE);
257 goto bad; /* XXX ? try to continue */
258 }
259 }
166 if (ecode != HAL_OK)
167 goto bad;
168
169 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
170 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
171 ecode = HAL_EIO;
172 goto bad;
173 }

--- 56 unchanged lines hidden (view full) ---

230 HAL_INI_INIT(&ahp9280->ah_ini_rxgain,
231 ar9280Modes_original_rxgain_v2, 6);
232 break;
233 default:
234 HALASSERT(AH_FALSE);
235 goto bad; /* XXX ? try to continue */
236 }
237 }
260
261 if (AR_SREV_KITE_12_OR_LATER(ah)) {
262 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
263 case AR5416_EEP_TXGAIN_HIGH_POWER:
264 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
265 ar9285Modes_high_power_tx_gain_v2, 6);
266 break;
267 default:
268 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
269 ar9285Modes_original_tx_gain_v2, 6);
270 break;
271 }
272 } else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
238 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
273 /* setp txgain table */
274 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
275 case AR5416_EEP_TXGAIN_HIGH_POWER:
276 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
277 ar9280Modes_high_power_tx_gain_v2, 6);
278 break;
279 case AR5416_EEP_TXGAIN_ORIG:
280 HAL_INI_INIT(&ahp9280->ah_ini_txgain,

--- 29 unchanged lines hidden (view full) ---

310 * starting from griffin. Set here to make sure that
311 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
312 * placed into hardware.
313 */
314 if (ahp->ah_miscMode != 0)
315 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
316
317 ar9280AniSetup(ah); /* Anti Noise Immunity */
239 /* setp txgain table */
240 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
241 case AR5416_EEP_TXGAIN_HIGH_POWER:
242 HAL_INI_INIT(&ahp9280->ah_ini_txgain,
243 ar9280Modes_high_power_tx_gain_v2, 6);
244 break;
245 case AR5416_EEP_TXGAIN_ORIG:
246 HAL_INI_INIT(&ahp9280->ah_ini_txgain,

--- 29 unchanged lines hidden (view full) ---

276 * starting from griffin. Set here to make sure that
277 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
278 * placed into hardware.
279 */
280 if (ahp->ah_miscMode != 0)
281 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
282
283 ar9280AniSetup(ah); /* Anti Noise Immunity */
318 ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist);
284 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
319
320 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
321
322 return ah;
323bad:
324 if (ah != AH_NULL)
325 ah->ah_detach(ah);
326 if (status)
327 *status = ecode;
328 return AH_NULL;
329}
330
331static void
332ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
333{
334 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
335 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
336 OS_DELAY(1000);
337 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
285
286 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
287
288 return ah;
289bad:
290 if (ah != AH_NULL)
291 ah->ah_detach(ah);
292 if (status)
293 *status = ecode;
294 return AH_NULL;
295}
296
297static void
298ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
299{
300 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
301 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
302 OS_DELAY(1000);
303 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
338 if (AR_SREV_KITE(ah))
339 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
340 else
341 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
304 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
342 }
343}
344
345static void
346ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
347{
348 u_int modesIndex, freqIndex;
349 int regWrites = 0;

--- 26 unchanged lines hidden (view full) ---

376 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
377 modesIndex, regWrites);
378 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
379 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
380 modesIndex, regWrites);
381 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
382 modesIndex, regWrites);
383 }
305 }
306}
307
308static void
309ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
310{
311 u_int modesIndex, freqIndex;
312 int regWrites = 0;

--- 26 unchanged lines hidden (view full) ---

339 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
340 modesIndex, regWrites);
341 if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
342 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
343 modesIndex, regWrites);
344 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
345 modesIndex, regWrites);
346 }
384 if (AR_SREV_KITE_12_OR_LATER(ah))
385 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
386 modesIndex, regWrites);
387
388 /* XXX Merlin 100us delay for shift registers */
389 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
390 1, regWrites);
391
392 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
393 /* 5GHz channels w/ Fast Clock use different modal values */
394 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
395 modesIndex, regWrites);

--- 310 unchanged lines hidden (view full) ---

706 */
707static HAL_BOOL
708ar9280FillCapabilityInfo(struct ath_hal *ah)
709{
710 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
711
712 if (!ar5416FillCapabilityInfo(ah))
713 return AH_FALSE;
347 /* XXX Merlin 100us delay for shift registers */
348 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
349 1, regWrites);
350
351 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
352 /* 5GHz channels w/ Fast Clock use different modal values */
353 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
354 modesIndex, regWrites);

--- 310 unchanged lines hidden (view full) ---

665 */
666static HAL_BOOL
667ar9280FillCapabilityInfo(struct ath_hal *ah)
668{
669 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
670
671 if (!ar5416FillCapabilityInfo(ah))
672 return AH_FALSE;
714 if (AR_SREV_KITE_10_OR_LATER(ah))
715 pCap->halNumGpioPins = 12;
716 else
717 pCap->halNumGpioPins = 10;
673 pCap->halNumGpioPins = 10;
718 pCap->halWowSupport = AH_TRUE;
719 pCap->halWowMatchPatternExact = AH_TRUE;
720#if 0
721 pCap->halWowMatchPatternDword = AH_TRUE;
722#endif
723 pCap->halCSTSupport = AH_TRUE;
724 pCap->halRifsRxSupport = AH_TRUE;
725 pCap->halRifsTxSupport = AH_TRUE;

--- 43 unchanged lines hidden (view full) ---

769 return AH_TRUE;
770#undef ANTENNA0_CHAINMASK
771#undef ANTENNA1_CHAINMASK
772}
773
774static const char*
775ar9280Probe(uint16_t vendorid, uint16_t devid)
776{
674 pCap->halWowSupport = AH_TRUE;
675 pCap->halWowMatchPatternExact = AH_TRUE;
676#if 0
677 pCap->halWowMatchPatternDword = AH_TRUE;
678#endif
679 pCap->halCSTSupport = AH_TRUE;
680 pCap->halRifsRxSupport = AH_TRUE;
681 pCap->halRifsTxSupport = AH_TRUE;

--- 43 unchanged lines hidden (view full) ---

725 return AH_TRUE;
726#undef ANTENNA0_CHAINMASK
727#undef ANTENNA1_CHAINMASK
728}
729
730static const char*
731ar9280Probe(uint16_t vendorid, uint16_t devid)
732{
777 if (vendorid == ATHEROS_VENDOR_ID) {
778 if (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)
779 return "Atheros 9280";
780 else if (devid == AR9285_DEVID_PCIE)
781 return "Atheros 9285";
782 }
733 if (vendorid == ATHEROS_VENDOR_ID &&
734 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE))
735 return "Atheros 9280";
783 return AH_NULL;
784}
785AH_CHIP(AR9280, ar9280Probe, ar9280Attach);
736 return AH_NULL;
737}
738AH_CHIP(AR9280, ar9280Probe, ar9280Attach);