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ar5416_reset.c (203682) ar5416_reset.c (203882)
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 203682 2010-02-08 20:12:01Z rpaulo $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 203882 2010-02-14 16:26:32Z rpaulo $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"
26#include "ah_eeprom_v4k.h"
27
28#include "ar5416/ar5416.h"
29#include "ar5416/ar5416reg.h"
30#include "ar5416/ar5416phy.h"
31
32/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
33#define EEP_MINOR(_ah) \
34 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)

--- 20 unchanged lines hidden (view full) ---

55static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *);
56
57static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
58static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
59static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
60static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *);
61static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
62 struct ar5416eeprom *pEepData,
26
27#include "ar5416/ar5416.h"
28#include "ar5416/ar5416reg.h"
29#include "ar5416/ar5416phy.h"
30
31/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
32#define EEP_MINOR(_ah) \
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)

--- 20 unchanged lines hidden (view full) ---

54static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *);
55
56static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
57static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
58static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
59static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *);
60static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
61 struct ar5416eeprom *pEepData,
63 struct ar5416eeprom_4k *pEepData4k,
64 const struct ieee80211_channel *chan, int16_t *ratesArray,
65 uint16_t cfgCtl, uint16_t AntennaReduction,
66 uint16_t twiceMaxRegulatoryPower,
67 uint16_t powerLimit);
68static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
69 struct ar5416eeprom *pEepData,
62 const struct ieee80211_channel *chan, int16_t *ratesArray,
63 uint16_t cfgCtl, uint16_t AntennaReduction,
64 uint16_t twiceMaxRegulatoryPower,
65 uint16_t powerLimit);
66static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
67 struct ar5416eeprom *pEepData,
70 struct ar5416eeprom_4k *pEepData4k,
71 const struct ieee80211_channel *chan,
72 int16_t *pTxPowerIndexOffset);
68 const struct ieee80211_channel *chan,
69 int16_t *pTxPowerIndexOffset);
73static uint16_t ar5416GetMaxEdgePower(struct ath_hal *ah, uint16_t freq,
70static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
74 CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
75static void ar5416GetTargetPowers(struct ath_hal *ah,
76 const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo,
77 uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
78 uint16_t numRates, HAL_BOOL isHt40Target);
79static void ar5416GetTargetPowersLeg(struct ath_hal *ah,
80 const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo,
81 uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
82 uint16_t numRates, HAL_BOOL isExtTarget);
83
84static int16_t interpolate(uint16_t target, uint16_t srcLeft,
85 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
86static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
87static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
88 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
71 CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
72static void ar5416GetTargetPowers(struct ath_hal *ah,
73 const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo,
74 uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
75 uint16_t numRates, HAL_BOOL isHt40Target);
76static void ar5416GetTargetPowersLeg(struct ath_hal *ah,
77 const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo,
78 uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
79 uint16_t numRates, HAL_BOOL isExtTarget);
80
81static int16_t interpolate(uint16_t target, uint16_t srcLeft,
82 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
83static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
84static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
85 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
89 CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
90 uint8_t * bChans, uint16_t availPiers,
91 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
92 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
93 uint16_t numXpdGains);
94static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
95 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
96static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
97 uint8_t *pPwrList, uint8_t *pVpdList,

--- 378 unchanged lines hidden (view full) ---

476 * Setup receive FIFO threshold to hold off TX activities
477 */
478 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
479
480 /*
481 * reduce the number of usable entries in PCU TXBUF to avoid
482 * wrap around.
483 */
86 uint8_t * bChans, uint16_t availPiers,
87 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
88 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
89 uint16_t numXpdGains);
90static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
91 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
92static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
93 uint8_t *pPwrList, uint8_t *pVpdList,

--- 378 unchanged lines hidden (view full) ---

472 * Setup receive FIFO threshold to hold off TX activities
473 */
474 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
475
476 /*
477 * reduce the number of usable entries in PCU TXBUF to avoid
478 * wrap around.
479 */
484 if (AR_SREV_KITE(ah))
485 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
486 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
487 else
488 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
489 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
480 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
490}
491
492static void
493ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)
494{
495 uint32_t synthDelay;
496
497 /*

--- 307 unchanged lines hidden (view full) ---

805static HAL_BOOL
806ar5416SetTransmitPower(struct ath_hal *ah,
807 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
808{
809#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
810#define N(a) (sizeof (a) / sizeof (a[0]))
811
812 MODAL_EEP_HEADER *pModal;
481}
482
483static void
484ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)
485{
486 uint32_t synthDelay;
487
488 /*

--- 307 unchanged lines hidden (view full) ---

796static HAL_BOOL
797ar5416SetTransmitPower(struct ath_hal *ah,
798 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
799{
800#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
801#define N(a) (sizeof (a) / sizeof (a[0]))
802
803 MODAL_EEP_HEADER *pModal;
813 MODAL_EEP4K_HEADER *pModal4k;
814 struct ath_hal_5212 *ahp = AH5212(ah);
815 int16_t ratesArray[Ar5416RateSize];
816 int16_t txPowerIndexOffset = 0;
817 uint8_t ht40PowerIncForPdadc = 2;
818 int i;
819
820 uint16_t cfgCtl;
821 uint16_t powerLimit;
822 uint16_t twiceAntennaReduction;
823 uint16_t twiceMaxRegulatoryPower;
824 int16_t maxPower;
804 struct ath_hal_5212 *ahp = AH5212(ah);
805 int16_t ratesArray[Ar5416RateSize];
806 int16_t txPowerIndexOffset = 0;
807 uint8_t ht40PowerIncForPdadc = 2;
808 int i;
809
810 uint16_t cfgCtl;
811 uint16_t powerLimit;
812 uint16_t twiceAntennaReduction;
813 uint16_t twiceMaxRegulatoryPower;
814 int16_t maxPower;
825 HAL_EEPROM_v14 *ee;
826 HAL_EEPROM_v4k *ee4k;
827 struct ar5416eeprom *pEepData;
828 struct ar5416eeprom_4k *pEepData4k;
815 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
816 struct ar5416eeprom *pEepData = &ee->ee_base;
829
830 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
831
832 /* Setup info for the actual eeprom */
833 OS_MEMZERO(ratesArray, sizeof(ratesArray));
834 cfgCtl = ath_hal_getctl(ah, chan);
835 powerLimit = chan->ic_maxregpower * 2;
836 twiceAntennaReduction = chan->ic_maxantgain;
837 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
817
818 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
819
820 /* Setup info for the actual eeprom */
821 OS_MEMZERO(ratesArray, sizeof(ratesArray));
822 cfgCtl = ath_hal_getctl(ah, chan);
823 powerLimit = chan->ic_maxregpower * 2;
824 twiceAntennaReduction = chan->ic_maxantgain;
825 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
838 if (AR_SREV_KITE(ah)) {
839 ee4k = AH_PRIVATE(ah)->ah_eeprom;
840 pEepData4k = &ee4k->ee_base;
841 pModal4k = &pEepData4k->modalHeader;
842 ee = NULL;
843 pEepData = NULL;
844 pModal = NULL;
845 } else {
846 ee = AH_PRIVATE(ah)->ah_eeprom;
847 pEepData = &ee->ee_base;
848 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
849 ee4k = NULL;
850 pEepData4k = NULL;
851 pModal4k = NULL;
852 }
826 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
853 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
854 __func__,chan->ic_freq, cfgCtl );
855
856 if (IS_EEP_MINOR_V2(ah)) {
827 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
828 __func__,chan->ic_freq, cfgCtl );
829
830 if (IS_EEP_MINOR_V2(ah)) {
857 if (pModal)
858 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
859 else
860 ht40PowerIncForPdadc = pModal4k->ht40PowerIncForPdadc;
831 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
861 }
832 }
862
863 if (!ar5416SetPowerPerRateTable(ah, pEepData, pEepData4k, chan,
833
834 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan,
864 &ratesArray[0],cfgCtl,
865 twiceAntennaReduction,
866 twiceMaxRegulatoryPower, powerLimit)) {
867 HALDEBUG(ah, HAL_DEBUG_ANY,
868 "%s: unable to set tx power per rate table\n", __func__);
869 return AH_FALSE;
870 }
871
835 &ratesArray[0],cfgCtl,
836 twiceAntennaReduction,
837 twiceMaxRegulatoryPower, powerLimit)) {
838 HALDEBUG(ah, HAL_DEBUG_ANY,
839 "%s: unable to set tx power per rate table\n", __func__);
840 return AH_FALSE;
841 }
842
872 if (!ar5416SetPowerCalTable(ah, pEepData, pEepData4k, chan,
873 &txPowerIndexOffset)) {
843 if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
874 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
875 __func__);
876 return AH_FALSE;
877 }
878
879 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
880
881 if (IEEE80211_IS_CHAN_2GHZ(chan)) {

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893 /*
894 * txPowerIndexOffset is set by the SetPowerTable() call -
895 * adjust the rate table (0 offset if rates EEPROM not loaded)
896 */
897 for (i = 0; i < N(ratesArray); i++) {
898 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
899 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
900 ratesArray[i] = AR5416_MAX_RATE_POWER;
844 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
845 __func__);
846 return AH_FALSE;
847 }
848
849 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
850
851 if (IEEE80211_IS_CHAN_2GHZ(chan)) {

--- 11 unchanged lines hidden (view full) ---

863 /*
864 * txPowerIndexOffset is set by the SetPowerTable() call -
865 * adjust the rate table (0 offset if rates EEPROM not loaded)
866 */
867 for (i = 0; i < N(ratesArray); i++) {
868 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
869 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
870 ratesArray[i] = AR5416_MAX_RATE_POWER;
901 if (AR_SREV_MERLIN_10_OR_LATER(ah))
902 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
903 }
904
905#ifdef AH_EEPROM_DUMP
906 ar5416PrintPowerPerRate(ah, ratesArray);
907#endif
908
909 /* Write the OFDM power per rate set */
910 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,

--- 63 unchanged lines hidden (view full) ---

974 POW_SM(ratesArray[rateExtOfdm], 24)
975 | POW_SM(ratesArray[rateExtCck], 16)
976 | POW_SM(ratesArray[rateDupOfdm], 8)
977 | POW_SM(ratesArray[rateDupCck], 0)
978 );
979 }
980
981 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
871 }
872
873#ifdef AH_EEPROM_DUMP
874 ar5416PrintPowerPerRate(ah, ratesArray);
875#endif
876
877 /* Write the OFDM power per rate set */
878 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,

--- 63 unchanged lines hidden (view full) ---

942 POW_SM(ratesArray[rateExtOfdm], 24)
943 | POW_SM(ratesArray[rateExtCck], 16)
944 | POW_SM(ratesArray[rateDupOfdm], 8)
945 | POW_SM(ratesArray[rateDupCck], 0)
946 );
947 }
948
949 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
982 if (pModal)
983 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
984 POW_SM(pModal->pwrDecreaseFor3Chain, 6)
985 | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
986 );
950 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
951 POW_SM(pModal->pwrDecreaseFor3Chain, 6)
952 | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
953 );
987 return AH_TRUE;
988#undef POW_SM
989#undef N
990}
991
992/*
993 * Exported call to check for a recent gain reading and return
994 * the current state of the thermal calibration gain engine.

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1216
1217/*
1218 * Read EEPROM header info and program the device for correct operation
1219 * given the channel value.
1220 */
1221static HAL_BOOL
1222ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
1223{
954 return AH_TRUE;
955#undef POW_SM
956#undef N
957}
958
959/*
960 * Exported call to check for a recent gain reading and return
961 * the current state of the thermal calibration gain engine.

--- 221 unchanged lines hidden (view full) ---

1183
1184/*
1185 * Read EEPROM header info and program the device for correct operation
1186 * given the channel value.
1187 */
1188static HAL_BOOL
1189ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
1190{
1224 const HAL_EEPROM_v14 *ee;
1225 const HAL_EEPROM_v4k *ee4k;
1226 const struct ar5416eeprom *eep;
1227 const struct ar5416eeprom_4k *eep4k;
1191 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
1192 const struct ar5416eeprom *eep = &ee->ee_base;
1228 const MODAL_EEP_HEADER *pModal;
1193 const MODAL_EEP_HEADER *pModal;
1229 const MODAL_EEP4K_HEADER *pModal4k;
1230 int i, regChainOffset = 0;
1194 int i, regChainOffset;
1231 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
1232
1233 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
1195 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
1196
1197 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
1198 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1234
1199
1235 if (AR_SREV_KITE(ah)) {
1236 ee4k = AH_PRIVATE(ah)->ah_eeprom;
1237 eep4k = &ee4k->ee_base;
1238 pModal4k = &eep4k->modalHeader;
1239 ee = NULL;
1240 eep = NULL;
1241 pModal = NULL;
1242 } else {
1243 ee = AH_PRIVATE(ah)->ah_eeprom;
1244 eep = &ee->ee_base;
1245 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1246 ee4k = NULL;
1247 eep4k = NULL;
1248 pModal4k = NULL;
1249 }
1250
1251 /* NB: workaround for eeprom versions <= 14.2 */
1252 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
1253
1200 /* NB: workaround for eeprom versions <= 14.2 */
1201 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
1202
1254 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM,
1255 (pModal) ? pModal->antCtrlCommon :
1256 pModal4k->antCtrlCommon);
1203 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1257 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1204 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1258// if (AR_SREV_KITE(ah) && i >= 2) break;
1259 if (AR_SREV_MERLIN(ah) && i >= 2) break;
1260 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1205 if (AR_SREV_MERLIN(ah)) {
1206 if (i >= 2) break;
1207 }
1208 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1261 (AH5416(ah)->ah_rx_chainmask == 0x5 ||
1262 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
1263 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1264 * only chains 0 and 2 populated
1265 */
1266 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1267 } else {
1268 regChainOffset = i * 0x1000;
1269 }
1270
1209 (AH5416(ah)->ah_rx_chainmask == 0x5 ||
1210 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
1211 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1212 * only chains 0 and 2 populated
1213 */
1214 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1215 } else {
1216 regChainOffset = i * 0x1000;
1217 }
1218
1271 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1272 (pModal) ? pModal->antCtrlChain[i] : pModal4k->antCtrlChain[i]);
1219 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
1273 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
1274 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
1275 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1220 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
1221 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
1222 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1276 SM((pModal) ? pModal->iqCalICh[i] : pModal4k->iqCalICh[i],
1277 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1278 SM((pModal) ? pModal->iqCalQCh[i] : pModal4k->iqCalQCh[i],
1279 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1223 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1224 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1280
1281 /*
1282 * Large signal upgrade.
1283 * XXX update
1284 */
1285
1286 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
1225
1226 /*
1227 * Large signal upgrade.
1228 * XXX update
1229 */
1230
1231 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
1287 int txRxAtten;
1288 if (IS_EEP_MINOR_V3(ah)) {
1289 if (pModal) txRxAtten = pModal->txRxAttenCh[i];
1290 else txRxAtten = pModal4k->txRxAttenCh[i];
1291 } else
1292 txRxAtten = txRxAttenLocal;
1232 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
1233 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1234 SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
1235 AR_PHY_RXGAIN_TXRX_ATTEN));
1293
1236
1294 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1295 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1296 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
1297 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1298 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1299 (pModal) ? pModal->rxTxMarginCh[i] : pModal4k->rxTxMarginCh[i]);
1300 } else {
1301 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
1302 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1303 SM(txRxAtten, AR_PHY_RXGAIN_TXRX_ATTEN));
1304
1305 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1306 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1307 SM((pModal) ? pModal->rxTxMarginCh[i]:
1308 pModal4k->rxTxMarginCh[i],
1309 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1310 }
1237 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1238 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1239 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1311 }
1312 }
1313
1240 }
1241 }
1242
1314 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1315 (pModal) ? pModal->switchSettling : pModal4k->switchSettling);
1316 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1317 (pModal) ? pModal->adcDesiredSize : pModal4k->adcDesiredSize);
1318 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA,
1319 (pModal) ? pModal->pgaDesiredSize : pModal4k->pgaDesiredSize);
1243 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1244 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1245 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
1320 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
1246 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
1321 SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
1322 AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1323 | SM((pModal) ? pModal->txEndToXpaOff : pModal4k->txEndToXpaOff,
1324 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1325 | SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
1326 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1327 | SM((pModal) ? pModal->txFrameToXpaOn : pModal4k->txFrameToXpaOn,
1328 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1247 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1248 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1249 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1250 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1329
1251
1330 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1331 (pModal) ? pModal->txEndToRxOn : pModal4k->txEndToRxOn);
1252 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1332
1333 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1334 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1253
1254 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1255 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1335 (pModal) ? pModal->thresh62 : pModal4k->thresh62);
1256 pModal->thresh62);
1336 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1257 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1337 (pModal) ? pModal->thresh62 : pModal4k->thresh62);
1258 pModal->thresh62);
1338 } else {
1339 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1259 } else {
1260 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1340 (pModal) ? pModal->thresh62 : pModal4k->thresh62);
1261 pModal->thresh62);
1341 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
1262 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
1342 (pModal) ? pModal->thresh62 : pModal4k->thresh62);
1263 pModal->thresh62);
1343 }
1344
1345 /* Minor Version Specific application */
1346 if (IS_EEP_MINOR_V2(ah)) {
1264 }
1265
1266 /* Minor Version Specific application */
1267 if (IS_EEP_MINOR_V2(ah)) {
1347 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
1348 (pModal) ? pModal->txFrameToDataStart : pModal4k->txFrameToDataStart);
1349 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
1350 (pModal) ? pModal->txFrameToPaOn : pModal4k->txFrameToPaOn);
1268 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
1269 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
1351 }
1352
1353 if (IS_EEP_MINOR_V3(ah)) {
1354 if (IEEE80211_IS_CHAN_HT40(chan)) {
1355 /* Overwrite switch settling with HT40 value */
1270 }
1271
1272 if (IS_EEP_MINOR_V3(ah)) {
1273 if (IEEE80211_IS_CHAN_HT40(chan)) {
1274 /* Overwrite switch settling with HT40 value */
1356 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1357 (pModal) ? pModal->swSettleHt40 : pModal4k->swSettleHt40);
1275 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1358 }
1359
1360 if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
1361 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
1276 }
1277
1278 if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
1279 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
1362 /* NB: no v4k EEPROM */
1363 /* Reg Offsets are swapped for logical mapping */
1364 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1365 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1366 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1367 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1368 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1369 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1370 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1371 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1372 } else {
1280 /* Reg Offsets are swapped for logical mapping */
1281 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1282 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1283 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1284 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1285 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1286 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1287 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1288 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1289 } else {
1373 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1374 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1375 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1376 (pModal) ? pModal->bswMargin[i] : pModal4k->bswMargin[i]);
1377 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1378 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1379 (pModal) ? pModal->bswAtten[i] : pModal4k->bswAtten[i]);
1380 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1381 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1382 (pModal) ? pModal->xatten2Margin[i] : pModal4k->xatten2Margin[i]);
1383 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1384 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1385 (pModal) ? pModal->xatten2Db[i] : pModal4k->xatten2Db[i]);
1386 } else {
1387 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1290 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1388 SM((pModal) ? pModal->bswMargin[1] :
1389 pModal4k->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1291 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1390 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1292 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1391 SM((pModal) ? pModal->bswAtten[1] :
1392 pModal4k->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1293 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1393 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1294 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1394 SM((pModal) ? pModal->bswMargin[2] :
1395 pModal4k->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1295 SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1396 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1296 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1397 SM((pModal) ? pModal->bswAtten[2] :
1398 pModal4k->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1399 }
1297 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1400 }
1298 }
1401 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
1402 (pModal) ? pModal->bswMargin[0] : pModal4k->bswMargin[0]);
1403 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
1404 (pModal) ? pModal->bswAtten[0] : pModal4k->bswAtten[0]);
1299 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
1300 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
1405 }
1406 return AH_TRUE;
1407}
1408
1409/*
1410 * Helper functions common for AP/CB/XB
1411 */
1412
1413/*
1414 * ar5416SetPowerPerRateTable
1415 *
1416 * Sets the transmit power in the baseband for the given
1417 * operating channel and mode.
1418 */
1301 }
1302 return AH_TRUE;
1303}
1304
1305/*
1306 * Helper functions common for AP/CB/XB
1307 */
1308
1309/*
1310 * ar5416SetPowerPerRateTable
1311 *
1312 * Sets the transmit power in the baseband for the given
1313 * operating channel and mode.
1314 */
1419HAL_BOOL
1315static HAL_BOOL
1420ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1316ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1421 struct ar5416eeprom_4k *pEepData4k,
1422 const struct ieee80211_channel *chan,
1423 int16_t *ratesArray, uint16_t cfgCtl,
1424 uint16_t AntennaReduction,
1425 uint16_t twiceMaxRegulatoryPower,
1426 uint16_t powerLimit)
1427{
1428#define N(a) (sizeof(a)/sizeof(a[0]))
1429/* Local defines to distinguish between extension and control CTL's */
1430#define EXT_ADDITIVE (0x8000)
1431#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1432#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1433#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1434
1435 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1436 int i;
1437 int16_t twiceLargestAntenna;
1438 CAL_CTL_DATA *rep;
1317 const struct ieee80211_channel *chan,
1318 int16_t *ratesArray, uint16_t cfgCtl,
1319 uint16_t AntennaReduction,
1320 uint16_t twiceMaxRegulatoryPower,
1321 uint16_t powerLimit)
1322{
1323#define N(a) (sizeof(a)/sizeof(a[0]))
1324/* Local defines to distinguish between extension and control CTL's */
1325#define EXT_ADDITIVE (0x8000)
1326#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1327#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1328#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1329
1330 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1331 int i;
1332 int16_t twiceLargestAntenna;
1333 CAL_CTL_DATA *rep;
1439 CAL_CTL_DATA_4K *rep4k;
1440 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
1441 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
1442 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
1443 int16_t scaledPower, minCtlPower;
1444
1445#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
1446#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
1447 static const uint16_t ctlModesFor11a[] = {
1448 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1449 };
1450 static const uint16_t ctlModesFor11g[] = {
1451 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1452 };
1453 const uint16_t *pCtlMode;
1454 uint16_t numCtlModes, ctlMode, freq;
1455 CHAN_CENTERS centers;
1334 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
1335 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
1336 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
1337 int16_t scaledPower, minCtlPower;
1338
1339#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
1340#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
1341 static const uint16_t ctlModesFor11a[] = {
1342 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1343 };
1344 static const uint16_t ctlModesFor11g[] = {
1345 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1346 };
1347 const uint16_t *pCtlMode;
1348 uint16_t numCtlModes, ctlMode, freq;
1349 CHAN_CENTERS centers;
1456 int n2gcck, n2g20, n2g40, numctls;
1457
1458 ar5416GetChannelCenters(ah, chan, &centers);
1459
1460 /* Compute TxPower reduction due to Antenna Gain */
1461
1350
1351 ar5416GetChannelCenters(ah, chan, &centers);
1352
1353 /* Compute TxPower reduction due to Antenna Gain */
1354
1462 if (pEepData)
1463 twiceLargestAntenna = AH_MAX(AH_MAX(
1464 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1465 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
1466 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1467 else
1468 twiceLargestAntenna = pEepData4k->modalHeader.antennaGainCh[0];
1355 twiceLargestAntenna = AH_MAX(AH_MAX(
1356 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1357 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
1358 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1469#if 0
1470 /* Turn it back on if we need to calculate per chain antenna gain reduction */
1471 /* Use only if the expected gain > 6dbi */
1472 /* Chain 0 is always used */
1473 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0];
1474
1475 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
1476 if (ahp->ah_tx_chainmask & 0x2)

--- 18 unchanged lines hidden (view full) ---

1495 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
1496
1497 /* Reduce scaled Power by number of chains active to get to per chain tx power level */
1498 /* TODO: better value than these? */
1499 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
1500 case 1:
1501 break;
1502 case 2:
1359#if 0
1360 /* Turn it back on if we need to calculate per chain antenna gain reduction */
1361 /* Use only if the expected gain > 6dbi */
1362 /* Chain 0 is always used */
1363 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0];
1364
1365 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
1366 if (ahp->ah_tx_chainmask & 0x2)

--- 18 unchanged lines hidden (view full) ---

1385 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
1386
1387 /* Reduce scaled Power by number of chains active to get to per chain tx power level */
1388 /* TODO: better value than these? */
1389 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
1390 case 1:
1391 break;
1392 case 2:
1503 if (pEepData)
1504 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
1393 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
1505 break;
1506 case 3:
1394 break;
1395 case 3:
1507 if (pEepData)
1508 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
1396 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
1509 break;
1510 default:
1511 return AH_FALSE; /* Unsupported number of chains */
1512 }
1513
1514 scaledPower = AH_MAX(0, scaledPower);
1515
1397 break;
1398 default:
1399 return AH_FALSE; /* Unsupported number of chains */
1400 }
1401
1402 scaledPower = AH_MAX(0, scaledPower);
1403
1516 n2gcck = (pEepData) ? AR5416_NUM_2G_CCK_TARGET_POWERS :
1517 AR5416_4K_NUM_2G_CCK_TARGET_POWERS;
1518 n2g20 = (pEepData) ? AR5416_NUM_2G_20_TARGET_POWERS :
1519 AR5416_4K_NUM_2G_20_TARGET_POWERS;
1520 n2g40 = (pEepData) ? AR5416_NUM_2G_40_TARGET_POWERS :
1521 AR5416_4K_NUM_2G_40_TARGET_POWERS;
1522
1523 /* Get target powers from EEPROM - our baseline for TX Power */
1524 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1525 /* Setup for CTL modes */
1526 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
1527 pCtlMode = ctlModesFor11g;
1528
1404 /* Get target powers from EEPROM - our baseline for TX Power */
1405 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1406 /* Setup for CTL modes */
1407 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
1408 pCtlMode = ctlModesFor11g;
1409
1529 ar5416GetTargetPowersLeg(ah, chan,
1530 (pEepData) ? pEepData->calTargetPowerCck :
1531 pEepData4k->calTargetPowerCck,
1532 n2gcck, &targetPowerCck, 4, AH_FALSE);
1533 ar5416GetTargetPowersLeg(ah, chan,
1534 (pEepData) ? pEepData->calTargetPower2G :
1535 pEepData4k->calTargetPower2G,
1536 n2g20, &targetPowerOfdm, 4, AH_FALSE);
1537 ar5416GetTargetPowers(ah, chan,
1538 (pEepData) ? pEepData->calTargetPower2GHT20 :
1539 pEepData4k->calTargetPower2GHT20,
1540 n2g20, &targetPowerHt20, 8, AH_FALSE);
1410 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1411 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
1412 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1413 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1414 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
1415 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1541
1542 if (IEEE80211_IS_CHAN_HT40(chan)) {
1543 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
1544
1416
1417 if (IEEE80211_IS_CHAN_HT40(chan)) {
1418 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
1419
1545 ar5416GetTargetPowers(ah, chan,
1546 (pEepData) ? pEepData->calTargetPower2GHT40 :
1547 pEepData4k->calTargetPower2GHT40,
1548 n2g40, &targetPowerHt40, 8, AH_TRUE);
1420 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
1421 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
1549 /* Get target powers for extension channels */
1422 /* Get target powers for extension channels */
1550 ar5416GetTargetPowersLeg(ah, chan,
1551 (pEepData) ? pEepData->calTargetPowerCck :
1552 pEepData4k->calTargetPowerCck,
1553 n2gcck, &targetPowerCckExt, 4, AH_TRUE);
1554 ar5416GetTargetPowersLeg(ah, chan,
1555 (pEepData) ? pEepData->calTargetPower2G :
1556 pEepData4k->calTargetPower2G,
1557 n2g20, &targetPowerOfdmExt, 4, AH_TRUE);
1423 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1424 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
1425 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1426 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
1558 }
1559 } else {
1560 /* Setup for CTL modes */
1561 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
1562 pCtlMode = ctlModesFor11a;
1563
1427 }
1428 } else {
1429 /* Setup for CTL modes */
1430 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
1431 pCtlMode = ctlModesFor11a;
1432
1564 /* NB: v4k EEPROM has no 5Ghz info */
1565 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1433 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1566 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1567 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
1568 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1569
1570 if (IEEE80211_IS_CHAN_HT40(chan)) {
1571 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */
1572
1573 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,

--- 7 unchanged lines hidden (view full) ---

1581 * For MIMO, need to apply regulatory caps individually across dynamically
1582 * running modes: CCK, OFDM, HT20, HT40
1583 *
1584 * The outer loop walks through each possible applicable runtime mode.
1585 * The inner loop walks through each ctlIndex entry in EEPROM.
1586 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
1587 *
1588 */
1434 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1435 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
1436 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1437
1438 if (IEEE80211_IS_CHAN_HT40(chan)) {
1439 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */
1440
1441 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,

--- 7 unchanged lines hidden (view full) ---

1449 * For MIMO, need to apply regulatory caps individually across dynamically
1450 * running modes: CCK, OFDM, HT20, HT40
1451 *
1452 * The outer loop walks through each possible applicable runtime mode.
1453 * The inner loop walks through each ctlIndex entry in EEPROM.
1454 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
1455 *
1456 */
1589 numctls = (pEepData) ? AR5416_NUM_CTLS : AR5416_4K_NUM_CTLS;
1590 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1457 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1591 int ctlIndex;
1592 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1593 (pCtlMode[ctlMode] == CTL_2GHT40);
1594 if (isHt40CtlMode) {
1595 freq = centers.ctl_center;
1596 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
1597 freq = centers.ext_center;
1598 } else {
1599 freq = centers.ctl_center;
1600 }
1601
1602 /* walk through each CTL index stored in EEPROM */
1458 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1459 (pCtlMode[ctlMode] == CTL_2GHT40);
1460 if (isHt40CtlMode) {
1461 freq = centers.ctl_center;
1462 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
1463 freq = centers.ext_center;
1464 } else {
1465 freq = centers.ctl_center;
1466 }
1467
1468 /* walk through each CTL index stored in EEPROM */
1603 for (i = 0; i < numctls; i++) {
1469 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1604 uint16_t twiceMinEdgePower;
1470 uint16_t twiceMinEdgePower;
1605 CAL_CTL_EDGES *ctlEdge;
1606
1471
1607 ctlIndex = (pEepData) ? pEepData->ctlIndex[i] :
1608 pEepData4k->ctlIndex[i];
1609 if (!ctlIndex)
1610 break;
1611
1612 /* compare test group from regulatory channel list with test mode from pCtlMode list */
1472 /* compare test group from regulatory channel list with test mode from pCtlMode list */
1613 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == ctlIndex) ||
1473 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
1614 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1474 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1615 ((ctlIndex & CTL_MODE_M) | SD_NO_CTL))) {
1616 if (pEepData) {
1617 rep = &(pEepData->ctlData[i]);
1618 ctlEdge = rep->ctlEdges[
1619 owl_get_ntxchains(
1620 AH5416(ah)->ah_tx_chainmask) - 1];
1621 } else {
1622 rep4k = &(pEepData4k->ctlData[i]);
1623 ctlEdge = rep4k->ctlEdges[
1624 owl_get_ntxchains(
1625 AH5416(ah)->ah_tx_chainmask) - 1];
1626 }
1627 twiceMinEdgePower = ar5416GetMaxEdgePower(ah,
1628 freq, ctlEdge,
1629 IEEE80211_IS_CHAN_2GHZ(chan));
1475 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1476 rep = &(pEepData->ctlData[i]);
1477 twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
1478 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
1479 IEEE80211_IS_CHAN_2GHZ(chan));
1630 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1631 /* Find the minimum of all CTL edge powers that apply to this channel */
1632 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
1633 } else {
1634 /* specific */
1635 twiceMaxEdgePower = twiceMinEdgePower;
1636 break;
1637 }

--- 97 unchanged lines hidden (view full) ---

1735}
1736
1737/*
1738 * ar5416GetMaxEdgePower
1739 *
1740 * Find the maximum conformance test limit for the given channel and CTL info
1741 */
1742static uint16_t
1480 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1481 /* Find the minimum of all CTL edge powers that apply to this channel */
1482 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
1483 } else {
1484 /* specific */
1485 twiceMaxEdgePower = twiceMinEdgePower;
1486 break;
1487 }

--- 97 unchanged lines hidden (view full) ---

1585}
1586
1587/*
1588 * ar5416GetMaxEdgePower
1589 *
1590 * Find the maximum conformance test limit for the given channel and CTL info
1591 */
1592static uint16_t
1743ar5416GetMaxEdgePower(struct ath_hal *ah,
1744 uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
1593ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
1745{
1746 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1594{
1595 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1747 int i, numBand;
1596 int i;
1748
1597
1749 if (AR_SREV_KITE(ah))
1750 numBand = AR5416_4K_NUM_BAND_EDGES;
1751 else
1752 numBand = AR5416_NUM_BAND_EDGES;
1753
1754 /* Get the edge power */
1598 /* Get the edge power */
1755 for (i = 0; (i < numBand) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
1599 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
1756 /*
1757 * If there's an exact channel match or an inband flag set
1758 * on the lower channel use the given rdEdgePower
1759 */
1760 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
1761 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
1762 break;
1763 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) {

--- 130 unchanged lines hidden (view full) ---

1894
1895/**************************************************************
1896 * ar5416SetPowerCalTable
1897 *
1898 * Pull the PDADC piers from cal data and interpolate them across the given
1899 * points as well as from the nearest pier(s) to get a power detector
1900 * linear voltage to power level table.
1901 */
1600 /*
1601 * If there's an exact channel match or an inband flag set
1602 * on the lower channel use the given rdEdgePower
1603 */
1604 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
1605 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
1606 break;
1607 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) {

--- 130 unchanged lines hidden (view full) ---

1738
1739/**************************************************************
1740 * ar5416SetPowerCalTable
1741 *
1742 * Pull the PDADC piers from cal data and interpolate them across the given
1743 * points as well as from the nearest pier(s) to get a power detector
1744 * linear voltage to power level table.
1745 */
1902HAL_BOOL
1746static HAL_BOOL
1903ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1747ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1904 struct ar5416eeprom_4k *pEepData4k,
1905 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
1906{
1748 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
1749{
1907 CAL_DATA_PER_FREQ *pRawDataset = NULL;
1908 CAL_DATA_PER_FREQ_4K *pRawDataset4k = NULL;
1750 CAL_DATA_PER_FREQ *pRawDataset;
1909 uint8_t *pCalBChans = AH_NULL;
1910 uint16_t pdGainOverlap_t2;
1911 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
1912 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1913 uint16_t numPiers, i, j;
1914 int16_t tMinCalPower;
1915 uint16_t numXpdGain, xpdMask;
1916 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
1917 uint32_t reg32, regOffset, regChainOffset;
1918
1919 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
1920
1751 uint8_t *pCalBChans = AH_NULL;
1752 uint16_t pdGainOverlap_t2;
1753 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
1754 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1755 uint16_t numPiers, i, j;
1756 int16_t tMinCalPower;
1757 uint16_t numXpdGain, xpdMask;
1758 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
1759 uint32_t reg32, regOffset, regChainOffset;
1760
1761 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
1762
1921 if (pEepData)
1922 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
1923 else
1924 xpdMask = pEepData4k->modalHeader.xpdGain;
1763 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
1925
1926 if (IS_EEP_MINOR_V2(ah)) {
1764
1765 if (IS_EEP_MINOR_V2(ah)) {
1927 if (pEepData)
1928 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
1929 else
1930 pdGainOverlap_t2 = pEepData4k->modalHeader.pdGainOverlap;
1766 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
1931 } else {
1932 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1933 }
1934
1935 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1767 } else {
1768 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1769 }
1770
1771 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1936 if (pEepData) {
1937 pCalBChans = pEepData->calFreqPier2G;
1938 numPiers = AR5416_NUM_2G_CAL_PIERS;
1939 } else {
1940 pCalBChans = pEepData4k->calFreqPier2G;
1941 numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
1942 }
1772 pCalBChans = pEepData->calFreqPier2G;
1773 numPiers = AR5416_NUM_2G_CAL_PIERS;
1943 } else {
1944 pCalBChans = pEepData->calFreqPier5G;
1945 numPiers = AR5416_NUM_5G_CAL_PIERS;
1946 }
1947
1948 numXpdGain = 0;
1949 /* Calculate the value of xpdgains from the xpdGain Mask */
1950 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {

--- 9 unchanged lines hidden (view full) ---

1960
1961 /* Write the detector gain biases and their number */
1962 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
1963 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
1964 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
1965 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
1966
1967 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1774 } else {
1775 pCalBChans = pEepData->calFreqPier5G;
1776 numPiers = AR5416_NUM_5G_CAL_PIERS;
1777 }
1778
1779 numXpdGain = 0;
1780 /* Calculate the value of xpdgains from the xpdGain Mask */
1781 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {

--- 9 unchanged lines hidden (view full) ---

1791
1792 /* Write the detector gain biases and their number */
1793 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
1794 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
1795 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
1796 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
1797
1798 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1968// if (AR_SREV_KITE(ah) && i >= AR5416_4K_MAX_CHAINS) break;
1799
1969 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1970 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
1971 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1972 * only chains 0 and 2 populated
1973 */
1974 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1975 } else {
1976 regChainOffset = i * 0x1000;
1977 }
1978
1800 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1801 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
1802 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1803 * only chains 0 and 2 populated
1804 */
1805 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1806 } else {
1807 regChainOffset = i * 0x1000;
1808 }
1809
1979 int txMask;
1980 txMask = (pEepData) ? pEepData->baseEepHeader.txMask :
1981 pEepData4k->baseEepHeader.txMask;
1982
1983 if (txMask & (1 << i)) {
1810 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1984 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1811 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1985 if (pEepData)
1986 pRawDataset = pEepData->calPierData2G[i];
1987 else
1988 pRawDataset4k = pEepData4k->calPierData2G[i];
1812 pRawDataset = pEepData->calPierData2G[i];
1989 } else {
1990 pRawDataset = pEepData->calPierData5G[i];
1991 }
1992
1813 } else {
1814 pRawDataset = pEepData->calPierData5G[i];
1815 }
1816
1993 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
1994 pRawDataset4k,
1817 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
1995 pCalBChans, numPiers,
1996 pdGainOverlap_t2,
1997 &tMinCalPower, gainBoundaries,
1998 pdadcValues, numXpdGain);
1999
2000 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
2001 /*
2002 * Note the pdadc table may not start at 0 dBm power, could be
2003 * negative or greater than 0. Need to offset the power
2004 * values by the amount of minPower for griffin
2005 */
1818 pCalBChans, numPiers,
1819 pdGainOverlap_t2,
1820 &tMinCalPower, gainBoundaries,
1821 pdadcValues, numXpdGain);
1822
1823 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
1824 /*
1825 * Note the pdadc table may not start at 0 dBm power, could be
1826 * negative or greater than 0. Need to offset the power
1827 * values by the amount of minPower for griffin
1828 */
1829
2006 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
2007 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2008 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
2009 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
2010 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
2011 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
2012 }
2013

--- 29 unchanged lines hidden (view full) ---

2043 *
2044 * Uses the data points read from EEPROM to reconstruct the pdadc power table
2045 * Called by ar5416SetPowerCalTable only.
2046 */
2047static void
2048ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
2049 const struct ieee80211_channel *chan,
2050 CAL_DATA_PER_FREQ *pRawDataSet,
1830 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1831 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
1832 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
1833 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
1834 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
1835 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1836 }
1837

--- 29 unchanged lines hidden (view full) ---

1867 *
1868 * Uses the data points read from EEPROM to reconstruct the pdadc power table
1869 * Called by ar5416SetPowerCalTable only.
1870 */
1871static void
1872ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
1873 const struct ieee80211_channel *chan,
1874 CAL_DATA_PER_FREQ *pRawDataSet,
2051 CAL_DATA_PER_FREQ_4K *pRawDataSet4k,
2052 uint8_t * bChans, uint16_t availPiers,
1875 uint8_t * bChans, uint16_t availPiers,
2053 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
2054 uint16_t * pPdGainBoundaries,
1876 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
2055 uint8_t * pPDADCValues, uint16_t numXpdGains)
2056{
2057
2058 int i, j, k;
2059 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
2060 uint16_t idxL, idxR, numPiers; /* Pier indexes */
2061
2062 /* filled out Vpd table for all pdGains (chanL) */

--- 26 unchanged lines hidden (view full) ---

2089
2090 /* Find pier indexes around the current channel */
2091 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
2092 bChans, numPiers, &idxL, &idxR);
2093
2094 if (match) {
2095 /* Directly fill both vpd tables from the matching index */
2096 for (i = 0; i < numXpdGains; i++) {
1877 uint8_t * pPDADCValues, uint16_t numXpdGains)
1878{
1879
1880 int i, j, k;
1881 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
1882 uint16_t idxL, idxR, numPiers; /* Pier indexes */
1883
1884 /* filled out Vpd table for all pdGains (chanL) */

--- 26 unchanged lines hidden (view full) ---

1911
1912 /* Find pier indexes around the current channel */
1913 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
1914 bChans, numPiers, &idxL, &idxR);
1915
1916 if (match) {
1917 /* Directly fill both vpd tables from the matching index */
1918 for (i = 0; i < numXpdGains; i++) {
2097 if (pRawDataSet) {
2098 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2099 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2100 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
2101 pRawDataSet[idxL].pwrPdg[i],
2102 pRawDataSet[idxL].vpdPdg[i],
2103 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
2104 } else {
2105 minPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][0];
2106 maxPwrT4[i] = pRawDataSet4k[idxL].pwrPdg[i][4];
2107 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i],
2108 pRawDataSet4k[idxL].pwrPdg[i],
2109 pRawDataSet4k[idxL].vpdPdg[i],
2110 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
2111 }
1919 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
1920 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
1921 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
1922 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
2112 }
2113 } else {
2114 for (i = 0; i < numXpdGains; i++) {
1923 }
1924 } else {
1925 for (i = 0; i < numXpdGains; i++) {
2115 if (pRawDataSet) {
2116 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2117 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2118 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2119 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2120 } else {
2121 pVpdL = pRawDataSet4k[idxL].vpdPdg[i];
2122 pPwrL = pRawDataSet4k[idxL].pwrPdg[i];
2123 pVpdR = pRawDataSet4k[idxR].vpdPdg[i];
2124 pPwrR = pRawDataSet4k[idxR].pwrPdg[i];
2125 }
1926 pVpdL = pRawDataSet[idxL].vpdPdg[i];
1927 pPwrL = pRawDataSet[idxL].pwrPdg[i];
1928 pVpdR = pRawDataSet[idxR].vpdPdg[i];
1929 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2126
2127 /* Start Vpd interpolation from the max of the minimum powers */
2128 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
2129
2130 /* End Vpd interpolation from the min of the max powers */
2131 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2132 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
2133

--- 31 unchanged lines hidden (view full) ---

2165 pPdGainBoundaries[0] = 23;
2166 }
2167 else {
2168 minDelta = 0;
2169 }
2170
2171 /* Find starting index for this pdGain */
2172 if (i == 0) {
1930
1931 /* Start Vpd interpolation from the max of the minimum powers */
1932 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
1933
1934 /* End Vpd interpolation from the min of the max powers */
1935 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
1936 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
1937

--- 31 unchanged lines hidden (view full) ---

1969 pPdGainBoundaries[0] = 23;
1970 }
1971 else {
1972 minDelta = 0;
1973 }
1974
1975 /* Find starting index for this pdGain */
1976 if (i == 0) {
2173 if (AR_SREV_MERLIN_10_OR_LATER(ah))
2174 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2175 else
2176 ss = 0; /* for the first pdGain, start from index 0 */
1977 ss = 0; /* for the first pdGain, start from index 0 */
2177 } else {
2178 /* need overlap entries extrapolated below. */
2179 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
2180 }
2181 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2182 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2183 /*
2184 *-ve ss indicates need to extrapolate data below for this pdGain
2185 */
2186 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2187 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2188 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
2189 ss++;
2190 }
2191
1978 } else {
1979 /* need overlap entries extrapolated below. */
1980 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
1981 }
1982 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
1983 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1984 /*
1985 *-ve ss indicates need to extrapolate data below for this pdGain
1986 */
1987 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1988 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
1989 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
1990 ss++;
1991 }
1992
2192 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
1993 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
2193 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
2194 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
2195
2196 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2197 pPDADCValues[k++] = vpdTableI[i][ss++];
2198 }
2199
2200 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);

--- 132 unchanged lines hidden (view full) ---

2333 return rv;
2334}
2335
2336static void
2337ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
2338{
2339 uint32_t phymode;
2340 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */
1994 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
1995 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
1996
1997 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1998 pPDADCValues[k++] = vpdTableI[i][ss++];
1999 }
2000
2001 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);

--- 132 unchanged lines hidden (view full) ---

2134 return rv;
2135}
2136
2137static void
2138ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
2139{
2140 uint32_t phymode;
2141 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */
2341 uint32_t dacFifo;
2342
2343 if (!IEEE80211_IS_CHAN_HT(chan))
2344 return;
2345
2142
2143 if (!IEEE80211_IS_CHAN_HT(chan))
2144 return;
2145
2346 if (AR_SREV_KITE_10_OR_LATER(ah))
2347 dacFifo = OS_REG_READ(ah, AR_PHY_TURBO)
2348 & AR_PHY_FC_ENABLE_DAC_FIFO;
2349 else
2350 dacFifo = 0;
2351
2352 /* Enable 11n HT, 20 MHz */
2353 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
2146 /* Enable 11n HT, 20 MHz */
2147 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
2354 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | dacFifo;
2148 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
2355
2356 /* Configure baseband for dynamic 20/40 operation */
2357 if (IEEE80211_IS_CHAN_HT40(chan)) {
2358 phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40;
2359
2360 /* Configure control (primary) channel at +-10MHz */
2361 if (IEEE80211_IS_CHAN_HT40U(chan))
2362 phymode |= AR_PHY_FC_DYN2040_PRI_CH;

--- 46 unchanged lines hidden --- 		2149
2150 /* Configure baseband for dynamic 20/40 operation */
2151 if (IEEE80211_IS_CHAN_HT40(chan)) {
2152 phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40;
2153
2154 /* Configure control (primary) channel at +-10MHz */
2155 if (IEEE80211_IS_CHAN_HT40U(chan))
2156 phymode |= AR_PHY_FC_DYN2040_PRI_CH;

--- 46 unchanged lines hidden ---