18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31#include "ah_osdep.h"
32
33/*
34 * The maximum number of TX/RX chains supported.
35 * This is intended to be used by various statistics gathering operations
36 * (NF, RSSI, EVM).
37 */
38#define AH_MIMO_MAX_CHAINS 3
39#define AH_MIMO_MAX_EVM_PILOTS 6
40
41/*
42 * __ahdecl is analogous to _cdecl; it defines the calling
43 * convention used within the HAL. For most systems this
44 * can just default to be empty and the compiler will (should)
45 * use _cdecl. For systems where _cdecl is not compatible this
46 * must be defined. See linux/ah_osdep.h for an example.
47 */
48#ifndef __ahdecl
49#define __ahdecl
50#endif
51
52/*
53 * Status codes that may be returned by the HAL. Note that
54 * interfaces that return a status code set it only when an
55 * error occurs--i.e. you cannot check it for success.
56 */
57typedef enum {
58 HAL_OK = 0, /* No error */
59 HAL_ENXIO = 1, /* No hardware present */
60 HAL_ENOMEM = 2, /* Memory allocation failed */
61 HAL_EIO = 3, /* Hardware didn't respond as expected */
62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
63 HAL_EEVERSION = 5, /* EEPROM version invalid */
64 HAL_EELOCKED = 6, /* EEPROM unreadable */
65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
66 HAL_EEREAD = 8, /* EEPROM read problem */
67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
68 HAL_EESIZE = 10, /* EEPROM size not supported */
69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
70 HAL_EINVAL = 12, /* Invalid parameter to function */
71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
72 HAL_ESELFTEST = 14, /* Hardware self-test failed */
73 HAL_EINPROGRESS = 15, /* Operation incomplete */
74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
75 HAL_EEBADCC = 17, /* EEPROM invalid country code */
76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */
77} HAL_STATUS;
78
79typedef enum {
80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
81 AH_TRUE = 1,
82} HAL_BOOL;
83
84typedef enum {
85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
99 HAL_CAP_TXPOW = 15, /* global tx power limit */
100 HAL_CAP_TPC = 16, /* per-packet tx power control */
101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
105 /* 21 was HAL_CAP_XR */
106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
107 /* 23 was HAL_CAP_CHAN_HALFRATE */
108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
113 HAL_CAP_PCIE_PS = 29,
114 HAL_CAP_HT = 30, /* hardware can support HT */
115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */
118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */
119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
120
121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
122
123 HAL_CAP_RIFS_RX = 39,
124 HAL_CAP_RIFS_TX = 40,
125 HAL_CAP_FORCE_PPM = 41,
126 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
127 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
128 HAL_CAP_DFS_DMN = 44, /* current DFS domain */
129 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
130 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
131
132 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
133 automatically after waking up to receive TIM */
134 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
135 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
136 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
137 HAL_CAP_BB_RIFS_HANG = 52,
138 HAL_CAP_RIFS_RX_ENABLED = 53,
139 HAL_CAP_BB_DFS_HANG = 54,
140
141 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
142 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */
143
144 HAL_CAP_DS = 67, /* 2 stream */
145 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
146 HAL_CAP_MAC_HANG = 69, /* can MAC hang */
147 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */
148
149 HAL_CAP_TS = 72, /* 3 stream */
150
151 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
152 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */
153 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */
154 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */
155 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */
156 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
157 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
158 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
159
160 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
161
162 HAL_CAP_BB_PANIC_WATCHDOG = 92,
163
164 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
165
166 HAL_CAP_LDPC = 99,
167
168 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
169
170 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */
171 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */
172 HAL_CAP_LDPCWAR = 108,
173 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */
174 HAL_CAP_ENABLE_APM = 110, /* APM enabled */
175 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111,
176 HAL_CAP_PCIE_LCR_OFFSET = 112,
177
178 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
179 HAL_CAP_MCI = 118,
180 HAL_CAP_SMARTANTENNA = 119,
181 HAL_CAP_TRAFFIC_FAST_RECOVER = 120,
182 HAL_CAP_TX_DIVERSITY = 121,
183 HAL_CAP_CRDC = 122,
184
185 /* The following are private to the FreeBSD HAL (224 onward) */
186
187 HAL_CAP_INTMIT = 229, /* interference mitigation */
188 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
189 HAL_CAP_BB_HANG = 235, /* can baseband hang */
190 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
191 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
192 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
193 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
194 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */
195 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
196 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */
197} HAL_CAPABILITY_TYPE;
198
199/*
200 * "States" for setting the LED. These correspond to
201 * the possible 802.11 operational states and there may
202 * be a many-to-one mapping between these states and the
203 * actual hardware state for the LED's (i.e. the hardware
204 * may have fewer states).
205 */
206typedef enum {
207 HAL_LED_INIT = 0,
208 HAL_LED_SCAN = 1,
209 HAL_LED_AUTH = 2,
210 HAL_LED_ASSOC = 3,
211 HAL_LED_RUN = 4
212} HAL_LED_STATE;
213
214/*
215 * Transmit queue types/numbers. These are used to tag
216 * each transmit queue in the hardware and to identify a set
217 * of transmit queues for operations such as start/stop dma.
218 */
219typedef enum {
220 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
221 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
222 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
223 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
224 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
225 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
226 HAL_TX_QUEUE_CFEND = 6,
227 HAL_TX_QUEUE_PAPRD = 7,
228} HAL_TX_QUEUE;
229
230#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
231
232typedef enum {
233 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
234 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
235} HAL_RX_QUEUE;
236
237#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */
238
239#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */
240
241/*
242 * Transmit queue subtype. These map directly to
243 * WME Access Categories (except for UPSD). Refer
244 * to Table 5 of the WME spec.
245 */
246typedef enum {
247 HAL_WME_AC_BK = 0, /* background access category */
248 HAL_WME_AC_BE = 1, /* best effort access category*/
249 HAL_WME_AC_VI = 2, /* video access category */
250 HAL_WME_AC_VO = 3, /* voice access category */
251 HAL_WME_UPSD = 4, /* uplink power save */
252} HAL_TX_QUEUE_SUBTYPE;
253
254/*
255 * Transmit queue flags that control various
256 * operational parameters.
257 */
258typedef enum {
259 /*
260 * Per queue interrupt enables. When set the associated
261 * interrupt may be delivered for packets sent through
262 * the queue. Without these enabled no interrupts will
263 * be delivered for transmits through the queue.
264 */
265 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
266 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
267 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
268 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
269 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
270 /*
271 * Enable hardware compression for packets sent through
272 * the queue. The compression buffer must be setup and
273 * packets must have a key entry marked in the tx descriptor.
274 */
275 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
276 /*
277 * Disable queue when veol is hit or ready time expires.
278 * By default the queue is disabled only on reaching the
279 * physical end of queue (i.e. a null link ptr in the
280 * descriptor chain).
281 */
282 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
283 /*
284 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
285 * event. Frames will be transmitted only when this timer
286 * fires, e.g to transmit a beacon in ap or adhoc modes.
287 */
288 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
289 /*
290 * Each transmit queue has a counter that is incremented
291 * each time the queue is enabled and decremented when
292 * the list of frames to transmit is traversed (or when
293 * the ready time for the queue expires). This counter
294 * must be non-zero for frames to be scheduled for
295 * transmission. The following controls disable bumping
296 * this counter under certain conditions. Typically this
297 * is used to gate frames based on the contents of another
298 * queue (e.g. CAB traffic may only follow a beacon frame).
299 * These are meaningful only when frames are scheduled
300 * with a non-ASAP policy (e.g. DBA-gated).
301 */
302 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
303 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
304
305 /*
306 * Fragment burst backoff policy. Normally the no backoff
307 * is done after a successful transmission, the next fragment
308 * is sent at SIFS. If this flag is set backoff is done
309 * after each fragment, regardless whether it was ack'd or
310 * not, after the backoff count reaches zero a normal channel
311 * access procedure is done before the next transmit (i.e.
312 * wait AIFS instead of SIFS).
313 */
314 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
315 /*
316 * Disable post-tx backoff following each frame.
317 */
318 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
319 /*
320 * DCU arbiter lockout control. This controls how
321 * lower priority tx queues are handled with respect to
322 * to a specific queue when multiple queues have frames
323 * to send. No lockout means lower priority queues arbitrate
324 * concurrently with this queue. Intra-frame lockout
325 * means lower priority queues are locked out until the
326 * current frame transmits (e.g. including backoffs and bursting).
327 * Global lockout means nothing lower can arbitrary so
328 * long as there is traffic activity on this queue (frames,
329 * backoff, etc).
330 */
331 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
332 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
333
334 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
335 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
336} HAL_TX_QUEUE_FLAGS;
337
338typedef struct {
339 uint32_t tqi_ver; /* hal TXQ version */
340 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
341 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
342 uint32_t tqi_priority; /* (not used) */
343 uint32_t tqi_aifs; /* aifs */
344 uint32_t tqi_cwmin; /* cwMin */
345 uint32_t tqi_cwmax; /* cwMax */
346 uint16_t tqi_shretry; /* rts retry limit */
347 uint16_t tqi_lgretry; /* long retry limit (not used)*/
348 uint32_t tqi_cbrPeriod; /* CBR period (us) */
349 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
350 uint32_t tqi_burstTime; /* max burst duration (us) */
351 uint32_t tqi_readyTime; /* frame schedule time (us) */
352 uint32_t tqi_compBuf; /* comp buffer phys addr */
353} HAL_TXQ_INFO;
354
355#define HAL_TQI_NONVAL 0xffff
356
357/* token to use for aifs, cwmin, cwmax */
358#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
359
360/* compression definitions */
361#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
362#define HAL_COMP_BUF_ALIGN_SIZE 512
363
364/*
365 * Transmit packet types. This belongs in ah_desc.h, but
366 * is here so we can give a proper type to various parameters
367 * (and not require everyone include the file).
368 *
369 * NB: These values are intentionally assigned for
370 * direct use when setting up h/w descriptors.
371 */
372typedef enum {
373 HAL_PKT_TYPE_NORMAL = 0,
374 HAL_PKT_TYPE_ATIM = 1,
375 HAL_PKT_TYPE_PSPOLL = 2,
376 HAL_PKT_TYPE_BEACON = 3,
377 HAL_PKT_TYPE_PROBE_RESP = 4,
378 HAL_PKT_TYPE_CHIRP = 5,
379 HAL_PKT_TYPE_GRP_POLL = 6,
380 HAL_PKT_TYPE_AMPDU = 7,
381} HAL_PKT_TYPE;
382
383/* Rx Filter Frame Types */
384typedef enum {
385 /*
386 * These bits correspond to AR_RX_FILTER for all chips.
387 * Not all bits are supported by all chips.
388 */
389 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
390 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
391 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
392 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
393 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
394 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
395 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
396 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
397 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
398 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
399 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
400 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
401 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
402 /* Allow all mcast/bcast frames */
403
404 /*
405 * Magic RX filter flags that aren't targetting hardware bits
406 * but instead the HAL sets individual bits - eg PHYERR will result
407 * in OFDM/CCK timing error frames being received.
408 */
409 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
410} HAL_RX_FILTER;
411
412typedef enum {
413 HAL_PM_AWAKE = 0,
414 HAL_PM_FULL_SLEEP = 1,
415 HAL_PM_NETWORK_SLEEP = 2,
416 HAL_PM_UNDEFINED = 3
417} HAL_POWER_MODE;
418
419/*
420 * NOTE WELL:
421 * These are mapped to take advantage of the common locations for many of
422 * the bits on all of the currently supported MAC chips. This is to make
423 * the ISR as efficient as possible, while still abstracting HW differences.
424 * When new hardware breaks this commonality this enumerated type, as well
425 * as the HAL functions using it, must be modified. All values are directly
426 * mapped unless commented otherwise.
427 */
428typedef enum {
429 HAL_INT_RX = 0x00000001, /* Non-common mapping */
430 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
431 HAL_INT_RXERR = 0x00000004,
432 HAL_INT_RXHP = 0x00000001, /* EDMA */
433 HAL_INT_RXLP = 0x00000002, /* EDMA */
434 HAL_INT_RXNOFRM = 0x00000008,
435 HAL_INT_RXEOL = 0x00000010,
436 HAL_INT_RXORN = 0x00000020,
437 HAL_INT_TX = 0x00000040, /* Non-common mapping */
438 HAL_INT_TXDESC = 0x00000080,
439 HAL_INT_TIM_TIMER= 0x00000100,
440 HAL_INT_MCI = 0x00000200,
441 HAL_INT_BBPANIC = 0x00000400,
442 HAL_INT_TXURN = 0x00000800,
443 HAL_INT_MIB = 0x00001000,
444 HAL_INT_RXPHY = 0x00004000,
445 HAL_INT_RXKCM = 0x00008000,
446 HAL_INT_SWBA = 0x00010000,
447 HAL_INT_BRSSI = 0x00020000,
448 HAL_INT_BMISS = 0x00040000,
449 HAL_INT_BNR = 0x00100000,
450 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
451 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
452 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
453 HAL_INT_GPIO = 0x01000000,
454 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
455 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
456 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
457 /* Atheros ref driver has a generic timer interrupt now..*/
458 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
459 HAL_INT_CST = 0x10000000, /* Non-common mapping */
460 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
461 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
462#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
463 HAL_INT_BMISC = HAL_INT_TIM
464 | HAL_INT_DTIM
465 | HAL_INT_DTIMSYNC
466 | HAL_INT_CABEND
467 | HAL_INT_TBTT,
468
469 /* Interrupt bits that map directly to ISR/IMR bits */
470 HAL_INT_COMMON = HAL_INT_RXNOFRM
471 | HAL_INT_RXDESC
472 | HAL_INT_RXEOL
473 | HAL_INT_RXORN
474 | HAL_INT_TXDESC
475 | HAL_INT_TXURN
476 | HAL_INT_MIB
477 | HAL_INT_RXPHY
478 | HAL_INT_RXKCM
479 | HAL_INT_SWBA
480 | HAL_INT_BMISS
481 | HAL_INT_BRSSI
482 | HAL_INT_BNR
483 | HAL_INT_GPIO,
484} HAL_INT;
485
486/*
487 * MSI vector assignments
488 */
489typedef enum {
490 HAL_MSIVEC_MISC = 0,
491 HAL_MSIVEC_TX = 1,
492 HAL_MSIVEC_RXLP = 2,
493 HAL_MSIVEC_RXHP = 3,
494} HAL_MSIVEC;
495
496typedef enum {
497 HAL_INT_LINE = 0,
498 HAL_INT_MSI = 1,
499} HAL_INT_TYPE;
500
501/* For interrupt mitigation registers */
502typedef enum {
503 HAL_INT_RX_FIRSTPKT=0,
504 HAL_INT_RX_LASTPKT,
505 HAL_INT_TX_FIRSTPKT,
506 HAL_INT_TX_LASTPKT,
507 HAL_INT_THRESHOLD
508} HAL_INT_MITIGATION;
509
510typedef enum {
511 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
512 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
513 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2,
514 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3,
515 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4,
516 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5,
517 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6
518} HAL_GPIO_MUX_TYPE;
519
520typedef enum {
521 HAL_GPIO_INTR_LOW = 0,
522 HAL_GPIO_INTR_HIGH = 1,
523 HAL_GPIO_INTR_DISABLE = 2
524} HAL_GPIO_INTR_TYPE;
525
526typedef enum {
527 HAL_RFGAIN_INACTIVE = 0,
528 HAL_RFGAIN_READ_REQUESTED = 1,
529 HAL_RFGAIN_NEED_CHANGE = 2
530} HAL_RFGAIN;
531
532typedef uint16_t HAL_CTRY_CODE; /* country code */
533typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
534
535#define HAL_ANTENNA_MIN_MODE 0
536#define HAL_ANTENNA_FIXED_A 1
537#define HAL_ANTENNA_FIXED_B 2
538#define HAL_ANTENNA_MAX_MODE 3
539
540typedef struct {
541 uint32_t ackrcv_bad;
542 uint32_t rts_bad;
543 uint32_t rts_good;
544 uint32_t fcs_bad;
545 uint32_t beacons;
546} HAL_MIB_STATS;
547
548enum {
549 HAL_MODE_11A = 0x001, /* 11a channels */
550 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
551 HAL_MODE_11B = 0x004, /* 11b channels */
552 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
553#ifdef notdef
554 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
555#else
556 HAL_MODE_11G = 0x008, /* XXX historical */
557#endif
558 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
559 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
560 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
561 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
562 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
563 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
564 HAL_MODE_11NG_HT20 = 0x008000,
565 HAL_MODE_11NA_HT20 = 0x010000,
566 HAL_MODE_11NG_HT40PLUS = 0x020000,
567 HAL_MODE_11NG_HT40MINUS = 0x040000,
568 HAL_MODE_11NA_HT40PLUS = 0x080000,
569 HAL_MODE_11NA_HT40MINUS = 0x100000,
570 HAL_MODE_ALL = 0xffffff
571};
572
573typedef struct {
574 int rateCount; /* NB: for proper padding */
575 uint8_t rateCodeToIndex[256]; /* back mapping */
576 struct {
577 uint8_t valid; /* valid for rate control use */
578 uint8_t phy; /* CCK/OFDM/XR */
579 uint32_t rateKbps; /* transfer rate in kbs */
580 uint8_t rateCode; /* rate for h/w descriptors */
581 uint8_t shortPreamble; /* mask for enabling short
582 * preamble in CCK rate code */
583 uint8_t dot11Rate; /* value for supported rates
584 * info element of MLME */
585 uint8_t controlRate; /* index of next lower basic
586 * rate; used for dur. calcs */
587 uint16_t lpAckDuration; /* long preamble ACK duration */
588 uint16_t spAckDuration; /* short preamble ACK duration*/
589 } info[64];
590} HAL_RATE_TABLE;
591
592typedef struct {
593 u_int rs_count; /* number of valid entries */
594 uint8_t rs_rates[64]; /* rates */
595} HAL_RATE_SET;
596
597/*
598 * 802.11n specific structures and enums
599 */
600typedef enum {
601 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
602 HAL_CHAINTYPE_RX = 2, /* RX chain type */
603} HAL_CHAIN_TYPE;
604
605typedef struct {
606 u_int Tries;
607 u_int Rate; /* hardware rate code */
608 u_int RateIndex; /* rate series table index */
609 u_int PktDuration;
610 u_int ChSel;
611 u_int RateFlags;
612#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
613#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
614#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
615#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
616 u_int tx_power_cap;
617} HAL_11N_RATE_SERIES;
618
619typedef enum {
620 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
621 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
622} HAL_HT_MACMODE;
623
624typedef enum {
625 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
626 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
627} HAL_HT_PHYMODE;
628
629typedef enum {
630 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
631 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
632} HAL_HT_EXTPROTSPACING;
633
634
635typedef enum {
636 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
637 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
638} HAL_HT_RXCLEAR;
639
640/*
641 * Antenna switch control. By default antenna selection
642 * enables multiple (2) antenna use. To force use of the
643 * A or B antenna only specify a fixed setting. Fixing
644 * the antenna will also disable any diversity support.
645 */
646typedef enum {
647 HAL_ANT_VARIABLE = 0, /* variable by programming */
648 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
649 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
650} HAL_ANT_SETTING;
651
652typedef enum {
653 HAL_M_STA = 1, /* infrastructure station */
654 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
655 HAL_M_HOSTAP = 6, /* Software Access Point */
656 HAL_M_MONITOR = 8 /* Monitor mode */
657} HAL_OPMODE;
658
659typedef struct {
660 uint8_t kv_type; /* one of HAL_CIPHER */
661 uint8_t kv_apsd; /* Mask for APSD enabled ACs */
662 uint16_t kv_len; /* length in bits */
663 uint8_t kv_val[16]; /* enough for 128-bit keys */
664 uint8_t kv_mic[8]; /* TKIP MIC key */
665 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
666} HAL_KEYVAL;
667
668typedef enum {
669 HAL_CIPHER_WEP = 0,
670 HAL_CIPHER_AES_OCB = 1,
671 HAL_CIPHER_AES_CCM = 2,
672 HAL_CIPHER_CKIP = 3,
673 HAL_CIPHER_TKIP = 4,
674 HAL_CIPHER_CLR = 5, /* no encryption */
675
676 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
677} HAL_CIPHER;
678
679enum {
680 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
681 HAL_SLOT_TIME_9 = 9,
682 HAL_SLOT_TIME_20 = 20,
683};
684
685/*
686 * Per-station beacon timer state. Note that the specified
687 * beacon interval (given in TU's) can also include flags
688 * to force a TSF reset and to enable the beacon xmit logic.
689 * If bs_cfpmaxduration is non-zero the hardware is setup to
690 * coexist with a PCF-capable AP.
691 */
692typedef struct {
693 uint32_t bs_nexttbtt; /* next beacon in TU */
694 uint32_t bs_nextdtim; /* next DTIM in TU */
695 uint32_t bs_intval; /* beacon interval+flags */
696#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
697#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
698#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
699 uint32_t bs_dtimperiod;
700 uint16_t bs_cfpperiod; /* CFP period in TU */
701 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
702 uint32_t bs_cfpnext; /* next CFP in TU */
703 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
704 uint16_t bs_bmissthreshold; /* beacon miss threshold */
705 uint32_t bs_sleepduration; /* max sleep duration */
706} HAL_BEACON_STATE;
707
708/*
709 * Like HAL_BEACON_STATE but for non-station mode setup.
710 * NB: see above flag definitions for bt_intval.
711 */
712typedef struct {
713 uint32_t bt_intval; /* beacon interval+flags */
714 uint32_t bt_nexttbtt; /* next beacon in TU */
715 uint32_t bt_nextatim; /* next ATIM in TU */
716 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
717 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
718 uint32_t bt_flags; /* timer enables */
719#define HAL_BEACON_TBTT_EN 0x00000001
720#define HAL_BEACON_DBA_EN 0x00000002
721#define HAL_BEACON_SWBA_EN 0x00000004
722} HAL_BEACON_TIMERS;
723
724/*
725 * Per-node statistics maintained by the driver for use in
726 * optimizing signal quality and other operational aspects.
727 */
728typedef struct {
729 uint32_t ns_avgbrssi; /* average beacon rssi */
730 uint32_t ns_avgrssi; /* average data rssi */
731 uint32_t ns_avgtxrssi; /* average tx rssi */
732} HAL_NODE_STATS;
733
734#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
735
736struct ath_desc;
737struct ath_tx_status;
738struct ath_rx_status;
739struct ieee80211_channel;
740
741/*
742 * This is a channel survey sample entry.
743 *
744 * The AR5212 ANI routines fill these samples. The ANI code then uses it
745 * when calculating listen time; it is also exported via a diagnostic
746 * API.
747 */
748typedef struct {
749 uint32_t seq_num;
750 uint32_t tx_busy;
751 uint32_t rx_busy;
752 uint32_t chan_busy;
753 uint32_t ext_chan_busy;
754 uint32_t cycle_count;
755 /* XXX TODO */
756 uint32_t ofdm_phyerr_count;
757 uint32_t cck_phyerr_count;
758} HAL_SURVEY_SAMPLE;
759
760/*
761 * This provides 3.2 seconds of sample space given an
762 * ANI time of 1/10th of a second. This may not be enough!
763 */
764#define CHANNEL_SURVEY_SAMPLE_COUNT 32
765
766typedef struct {
767 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT];
768 uint32_t cur_sample; /* current sample in sequence */
769 uint32_t cur_seq; /* current sequence number */
770} HAL_CHANNEL_SURVEY;
771
772/*
773 * ANI commands.
774 *
775 * These are used both internally and externally via the diagnostic
776 * API.
777 *
778 * Note that this is NOT the ANI commands being used via the INTMIT
779 * capability - that has a different mapping for some reason.
780 */
781typedef enum {
782 HAL_ANI_PRESENT = 0, /* is ANI support present */
783 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */
784 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */
785 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */
786 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */
787 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
788 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
789 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
790 HAL_ANI_MRC_CCK = 8,
791} HAL_ANI_CMD;
792
793/*
794 * This is the layout of the ANI INTMIT capability.
795 *
796 * Notice that the command values differ to HAL_ANI_CMD.
797 */
798typedef enum {
799 HAL_CAP_INTMIT_PRESENT = 0,
800 HAL_CAP_INTMIT_ENABLE = 1,
801 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2,
802 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3,
803 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4,
804 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5,
805 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
806} HAL_CAP_INTMIT_CMD;
807
808/* DFS defines */
809typedef struct {
810 int32_t pe_firpwr; /* FIR pwr out threshold */
811 int32_t pe_rrssi; /* Radar rssi thresh */
812 int32_t pe_height; /* Pulse height thresh */
813 int32_t pe_prssi; /* Pulse rssi thresh */
814 int32_t pe_inband; /* Inband thresh */
815
816 /* The following params are only for AR5413 and later */
817 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
818 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
819 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
820 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */
821 int32_t pe_blockradar; /*
822 * Enable to block radar check if pkt detect is done via OFDM
823 * weak signal detect or pkt is detected immediately after tx
824 * to rx transition
825 */
826 int32_t pe_enmaxrssi; /*
827 * Enable to use the max rssi instead of the last rssi during
828 * fine gain changes for radar detection
829 */
830 int32_t pe_extchannel; /* Enable DFS on ext channel */
831 int32_t pe_enabled; /* Whether radar detection is enabled */
832 int32_t pe_enrelpwr;
833 int32_t pe_en_relstep_check;
834} HAL_PHYERR_PARAM;
835
836#define HAL_PHYERR_PARAM_NOVAL 65535
837
838/*
839 * DFS operating mode flags.
840 */
841typedef enum {
842 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
843 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
844 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
845 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
846} HAL_DFS_DOMAIN;
847
848/*
849 * MFP decryption options for initializing the MAC.
850 */
851
852typedef enum {
853 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
854 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */
855 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */
856} HAL_MFP_OPT_T;
857
858/*
859 * Flag for setting QUIET period
860 */
861typedef enum {
862 HAL_QUIET_DISABLE = 0x0,
863 HAL_QUIET_ENABLE = 0x1,
864 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
865 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
866} HAL_QUIET_FLAG;
867
868#define HAL_DFS_EVENT_PRICH 0x0000001
869#define HAL_DFS_EVENT_EXTCH 0x0000002
870#define HAL_DFS_EVENT_EXTEARLY 0x0000004
871#define HAL_DFS_EVENT_ISDC 0x0000008
872
873struct hal_dfs_event {
874 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */
875 uint32_t re_ts; /* Original 15 bit recv timestamp */
876 uint8_t re_rssi; /* rssi of radar event */
877 uint8_t re_dur; /* duration of radar pulse */
878 uint32_t re_flags; /* Flags (see above) */
879};
880typedef struct hal_dfs_event HAL_DFS_EVENT;
881
882/*
883 * BT Co-existence definitions
884 */
885typedef enum {
886 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
887 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
888 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
889 HAL_MAX_BT_MODULES
890} HAL_BT_MODULE;
891
892typedef struct {
893 HAL_BT_MODULE bt_module;
894 u_int8_t bt_coex_config;
895 u_int8_t bt_gpio_bt_active;
896 u_int8_t bt_gpio_bt_priority;
897 u_int8_t bt_gpio_wlan_active;
898 u_int8_t bt_active_polarity;
899 HAL_BOOL bt_single_ant;
900 u_int8_t bt_dutyCycle;
901 u_int8_t bt_isolation;
902 u_int8_t bt_period;
903} HAL_BT_COEX_INFO;
904
905typedef enum {
906 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
907 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
908 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
909 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
910} HAL_BT_COEX_MODE;
911
912typedef enum {
913 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
914 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
915 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
916 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
917 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
918 HAL_BT_COEX_CFG_MCI /* MCI */
919} HAL_BT_COEX_CFG;
920
921typedef enum {
922 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
923 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
924 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
925} HAL_BT_COEX_SET_PARAMETER;
926
927#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
928#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
929/* Check Rx Diversity is allowed */
930#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
931/* Check Diversity is on or off */
932#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
933
934#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
935/* main: LNA1, alt: LNA2 */
936#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
937#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
938#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
939#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
940#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
941
942#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
943
944#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
945
946#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
947
948#define HAL_BT_COEX_LOW_ACK_POWER 0x0
949#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
950
951typedef enum {
952 HAL_BT_COEX_NO_STOMP = 0,
953 HAL_BT_COEX_STOMP_ALL,
954 HAL_BT_COEX_STOMP_LOW,
955 HAL_BT_COEX_STOMP_NONE,
956 HAL_BT_COEX_STOMP_ALL_FORCE,
957 HAL_BT_COEX_STOMP_LOW_FORCE,
958} HAL_BT_COEX_STOMP_TYPE;
959
960typedef struct {
961 /* extend rx_clear after tx/rx to protect the burst (in usec). */
962 u_int8_t bt_time_extend;
963
964 /*
965 * extend rx_clear as long as txsm is
966 * transmitting or waiting for ack.
967 */
968 HAL_BOOL bt_txstate_extend;
969
970 /*
971 * extend rx_clear so that when tx_frame
972 * is asserted, rx_clear will drop.
973 */
974 HAL_BOOL bt_txframe_extend;
975
976 /*
977 * coexistence mode
978 */
979 HAL_BT_COEX_MODE bt_mode;
980
981 /*
982 * treat BT high priority traffic as
983 * a quiet collision
984 */
985 HAL_BOOL bt_quiet_collision;
986
987 /*
988 * invert rx_clear as WLAN_ACTIVE
989 */
990 HAL_BOOL bt_rxclear_polarity;
991
992 /*
993 * slotted mode only. indicate the time in usec
994 * from the rising edge of BT_ACTIVE to the time
995 * BT_PRIORITY can be sampled to indicate priority.
996 */
997 u_int8_t bt_priority_time;
998
999 /*
1000 * slotted mode only. indicate the time in usec
1001 * from the rising edge of BT_ACTIVE to the time
1002 * BT_PRIORITY can be sampled to indicate tx/rx and
1003 * BT_FREQ is sampled.
1004 */
1005 u_int8_t bt_first_slot_time;
1006
1007 /*
1008 * slotted mode only. rx_clear and bt_ant decision
1009 * will be held the entire time that BT_ACTIVE is asserted,
1010 * otherwise the decision is made before every slot boundry.
1011 */
1012 HAL_BOOL bt_hold_rxclear;
1013} HAL_BT_COEX_CONFIG;
1014
1015typedef struct
1016{
1017 int ah_debug; /* only used if AH_DEBUG is defined */
1018 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */
1019
1020 /* NB: these are deprecated; they exist for now for compatibility */
1021 int ah_dma_beacon_response_time;/* in TU's */
1022 int ah_sw_beacon_response_time; /* in TU's */
1023 int ah_additional_swba_backoff; /* in TU's */
1024 int ah_force_full_reset; /* force full chip reset rather then warm reset */
1025 int ah_serialise_reg_war; /* force serialisation of register IO */
1026} HAL_OPS_CONFIG;
1027
1028/*
1029 * Hardware Access Layer (HAL) API.
1030 *
1031 * Clients of the HAL call ath_hal_attach to obtain a reference to an
1032 * ath_hal structure for use with the device. Hardware-related operations
1033 * that follow must call back into the HAL through interface, supplying
1034 * the reference as the first parameter. Note that before using the
1035 * reference returned by ath_hal_attach the caller should verify the
1036 * ABI version number.
1037 */
1038struct ath_hal {
1039 uint32_t ah_magic; /* consistency check magic number */
1040 uint16_t ah_devid; /* PCI device ID */
1041 uint16_t ah_subvendorid; /* PCI subvendor ID */
1042 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
1043 HAL_BUS_TAG ah_st; /* params for register r+w */
1044 HAL_BUS_HANDLE ah_sh;
1045 HAL_CTRY_CODE ah_countryCode;
1046
1047 uint32_t ah_macVersion; /* MAC version id */
1048 uint16_t ah_macRev; /* MAC revision */
1049 uint16_t ah_phyRev; /* PHY revision */
1050 /* NB: when only one radio is present the rev is in 5Ghz */
1051 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
1052 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
1053
1054 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
1055
1056 uint32_t ah_intrstate[8]; /* last int state */
1057 uint32_t ah_syncstate; /* last sync intr state */
1058
1059 HAL_OPS_CONFIG ah_config;
1060 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
1061 u_int mode);
1062 void __ahdecl(*ah_detach)(struct ath_hal*);
1063
1064 /* Reset functions */
1065 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
1066 struct ieee80211_channel *,
1067 HAL_BOOL bChannelChange, HAL_STATUS *status);
1068 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
1069 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
1070 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore,
1071 HAL_BOOL power_off);
1072 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
1073 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
1074 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
1075 struct ieee80211_channel *, HAL_BOOL *);
1076 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
1077 struct ieee80211_channel *, u_int chainMask,
1078 HAL_BOOL longCal, HAL_BOOL *isCalDone);
1079 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
1080 const struct ieee80211_channel *);
1081 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
1082 const struct ieee80211_channel *, uint16_t *);
1083 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
1084 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
1085 const struct ieee80211_channel *);
1086
1087 /* Transmit functions */
1088 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
1089 HAL_BOOL incTrigLevel);
1090 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
1091 const HAL_TXQ_INFO *qInfo);
1092 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
1093 const HAL_TXQ_INFO *qInfo);
1094 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
1095 HAL_TXQ_INFO *qInfo);
1096 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
1097 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
1098 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
1099 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
1100 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
1101 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
1102 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
1103 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
1104 u_int pktLen, u_int hdrLen,
1105 HAL_PKT_TYPE type, u_int txPower,
1106 u_int txRate0, u_int txTries0,
1107 u_int keyIx, u_int antMode, u_int flags,
1108 u_int rtsctsRate, u_int rtsctsDuration,
1109 u_int compicvLen, u_int compivLen,
1110 u_int comp);
1111 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
1112 u_int txRate1, u_int txTries1,
1113 u_int txRate2, u_int txTries2,
1114 u_int txRate3, u_int txTries3);
1115 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
1116 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
1117 u_int descId, u_int qcuId, HAL_BOOL firstSeg,
1118 HAL_BOOL lastSeg, const struct ath_desc *);
1119 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
1120 struct ath_desc *, struct ath_tx_status *);
1121 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
1122 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
1123 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
1124 const struct ath_desc *ds, int *rates, int *tries);
1125 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,
1126 uint32_t link);
1127 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,
1128 uint32_t *link);
1129 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,
1130 uint32_t **linkptr);
1131 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *,
1132 void *ts_start, uint32_t ts_paddr_start,
1133 uint16_t size);
1134
1135 /* Receive Functions */
1136 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE);
1137 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE);
1138 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
1139 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
1140 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
1141 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
1142 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
1143 uint32_t filter0, uint32_t filter1);
1144 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
1145 uint32_t index);
1146 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
1147 uint32_t index);
1148 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
1149 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
1150 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
1151 uint32_t size, u_int flags);
1152 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
1153 struct ath_desc *, uint32_t phyAddr,
1154 struct ath_desc *next, uint64_t tsf,
1155 struct ath_rx_status *);
1156 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
1157 const HAL_NODE_STATS *,
1158 const struct ieee80211_channel *);
1159 void __ahdecl(*ah_aniPoll)(struct ath_hal *,
1160 const struct ieee80211_channel *);
1161 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
1162 const HAL_NODE_STATS *);
1163 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
1164 struct ath_rx_status *,
1165 unsigned long, int);
1166
1167 /* Misc Functions */
1168 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
1169 HAL_CAPABILITY_TYPE, uint32_t capability,
1170 uint32_t *result);
1171 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
1172 HAL_CAPABILITY_TYPE, uint32_t capability,
1173 uint32_t setting, HAL_STATUS *);
1174 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
1175 const void *args, uint32_t argsize,
1176 void **result, uint32_t *resultsize);
1177 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
1178 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
1179 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
1180 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
1181 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
1182 uint16_t, HAL_STATUS *);
1183 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
1184 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
1185 const uint8_t *bssid, uint16_t assocId);
1186 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
1187 uint32_t gpio, HAL_GPIO_MUX_TYPE);
1188 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
1189 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
1190 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
1191 uint32_t gpio, uint32_t val);
1192 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
1193 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
1194 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
1195 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
1196 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
1197 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
1198 HAL_MIB_STATS*);
1199 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
1200 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
1201 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
1202 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
1203 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
1204 HAL_ANT_SETTING);
1205 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
1206 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
1207 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
1208 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
1209 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
1210 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
1211 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
1212 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
1213 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
1214 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
1215 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
1216 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
1217 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
1218 uint32_t duration, uint32_t nextStart,
1219 HAL_QUIET_FLAG flag);
1220
1221 /* DFS functions */
1222 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
1223 HAL_PHYERR_PARAM *pe);
1224 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
1225 HAL_PHYERR_PARAM *pe);
| 18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31#include "ah_osdep.h"
32
33/*
34 * The maximum number of TX/RX chains supported.
35 * This is intended to be used by various statistics gathering operations
36 * (NF, RSSI, EVM).
37 */
38#define AH_MIMO_MAX_CHAINS 3
39#define AH_MIMO_MAX_EVM_PILOTS 6
40
41/*
42 * __ahdecl is analogous to _cdecl; it defines the calling
43 * convention used within the HAL. For most systems this
44 * can just default to be empty and the compiler will (should)
45 * use _cdecl. For systems where _cdecl is not compatible this
46 * must be defined. See linux/ah_osdep.h for an example.
47 */
48#ifndef __ahdecl
49#define __ahdecl
50#endif
51
52/*
53 * Status codes that may be returned by the HAL. Note that
54 * interfaces that return a status code set it only when an
55 * error occurs--i.e. you cannot check it for success.
56 */
57typedef enum {
58 HAL_OK = 0, /* No error */
59 HAL_ENXIO = 1, /* No hardware present */
60 HAL_ENOMEM = 2, /* Memory allocation failed */
61 HAL_EIO = 3, /* Hardware didn't respond as expected */
62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
63 HAL_EEVERSION = 5, /* EEPROM version invalid */
64 HAL_EELOCKED = 6, /* EEPROM unreadable */
65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
66 HAL_EEREAD = 8, /* EEPROM read problem */
67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
68 HAL_EESIZE = 10, /* EEPROM size not supported */
69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
70 HAL_EINVAL = 12, /* Invalid parameter to function */
71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
72 HAL_ESELFTEST = 14, /* Hardware self-test failed */
73 HAL_EINPROGRESS = 15, /* Operation incomplete */
74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
75 HAL_EEBADCC = 17, /* EEPROM invalid country code */
76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */
77} HAL_STATUS;
78
79typedef enum {
80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
81 AH_TRUE = 1,
82} HAL_BOOL;
83
84typedef enum {
85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
99 HAL_CAP_TXPOW = 15, /* global tx power limit */
100 HAL_CAP_TPC = 16, /* per-packet tx power control */
101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
105 /* 21 was HAL_CAP_XR */
106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
107 /* 23 was HAL_CAP_CHAN_HALFRATE */
108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
113 HAL_CAP_PCIE_PS = 29,
114 HAL_CAP_HT = 30, /* hardware can support HT */
115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */
118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */
119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
120
121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
122
123 HAL_CAP_RIFS_RX = 39,
124 HAL_CAP_RIFS_TX = 40,
125 HAL_CAP_FORCE_PPM = 41,
126 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
127 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
128 HAL_CAP_DFS_DMN = 44, /* current DFS domain */
129 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
130 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
131
132 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
133 automatically after waking up to receive TIM */
134 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
135 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
136 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
137 HAL_CAP_BB_RIFS_HANG = 52,
138 HAL_CAP_RIFS_RX_ENABLED = 53,
139 HAL_CAP_BB_DFS_HANG = 54,
140
141 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
142 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */
143
144 HAL_CAP_DS = 67, /* 2 stream */
145 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
146 HAL_CAP_MAC_HANG = 69, /* can MAC hang */
147 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */
148
149 HAL_CAP_TS = 72, /* 3 stream */
150
151 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
152 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */
153 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */
154 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */
155 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */
156 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
157 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
158 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
159
160 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
161
162 HAL_CAP_BB_PANIC_WATCHDOG = 92,
163
164 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
165
166 HAL_CAP_LDPC = 99,
167
168 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
169
170 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */
171 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */
172 HAL_CAP_LDPCWAR = 108,
173 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */
174 HAL_CAP_ENABLE_APM = 110, /* APM enabled */
175 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111,
176 HAL_CAP_PCIE_LCR_OFFSET = 112,
177
178 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
179 HAL_CAP_MCI = 118,
180 HAL_CAP_SMARTANTENNA = 119,
181 HAL_CAP_TRAFFIC_FAST_RECOVER = 120,
182 HAL_CAP_TX_DIVERSITY = 121,
183 HAL_CAP_CRDC = 122,
184
185 /* The following are private to the FreeBSD HAL (224 onward) */
186
187 HAL_CAP_INTMIT = 229, /* interference mitigation */
188 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
189 HAL_CAP_BB_HANG = 235, /* can baseband hang */
190 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
191 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
192 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
193 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
194 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */
195 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
196 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */
197} HAL_CAPABILITY_TYPE;
198
199/*
200 * "States" for setting the LED. These correspond to
201 * the possible 802.11 operational states and there may
202 * be a many-to-one mapping between these states and the
203 * actual hardware state for the LED's (i.e. the hardware
204 * may have fewer states).
205 */
206typedef enum {
207 HAL_LED_INIT = 0,
208 HAL_LED_SCAN = 1,
209 HAL_LED_AUTH = 2,
210 HAL_LED_ASSOC = 3,
211 HAL_LED_RUN = 4
212} HAL_LED_STATE;
213
214/*
215 * Transmit queue types/numbers. These are used to tag
216 * each transmit queue in the hardware and to identify a set
217 * of transmit queues for operations such as start/stop dma.
218 */
219typedef enum {
220 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
221 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
222 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
223 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
224 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
225 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
226 HAL_TX_QUEUE_CFEND = 6,
227 HAL_TX_QUEUE_PAPRD = 7,
228} HAL_TX_QUEUE;
229
230#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
231
232typedef enum {
233 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
234 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
235} HAL_RX_QUEUE;
236
237#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */
238
239#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */
240
241/*
242 * Transmit queue subtype. These map directly to
243 * WME Access Categories (except for UPSD). Refer
244 * to Table 5 of the WME spec.
245 */
246typedef enum {
247 HAL_WME_AC_BK = 0, /* background access category */
248 HAL_WME_AC_BE = 1, /* best effort access category*/
249 HAL_WME_AC_VI = 2, /* video access category */
250 HAL_WME_AC_VO = 3, /* voice access category */
251 HAL_WME_UPSD = 4, /* uplink power save */
252} HAL_TX_QUEUE_SUBTYPE;
253
254/*
255 * Transmit queue flags that control various
256 * operational parameters.
257 */
258typedef enum {
259 /*
260 * Per queue interrupt enables. When set the associated
261 * interrupt may be delivered for packets sent through
262 * the queue. Without these enabled no interrupts will
263 * be delivered for transmits through the queue.
264 */
265 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
266 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
267 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
268 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
269 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
270 /*
271 * Enable hardware compression for packets sent through
272 * the queue. The compression buffer must be setup and
273 * packets must have a key entry marked in the tx descriptor.
274 */
275 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
276 /*
277 * Disable queue when veol is hit or ready time expires.
278 * By default the queue is disabled only on reaching the
279 * physical end of queue (i.e. a null link ptr in the
280 * descriptor chain).
281 */
282 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
283 /*
284 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
285 * event. Frames will be transmitted only when this timer
286 * fires, e.g to transmit a beacon in ap or adhoc modes.
287 */
288 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
289 /*
290 * Each transmit queue has a counter that is incremented
291 * each time the queue is enabled and decremented when
292 * the list of frames to transmit is traversed (or when
293 * the ready time for the queue expires). This counter
294 * must be non-zero for frames to be scheduled for
295 * transmission. The following controls disable bumping
296 * this counter under certain conditions. Typically this
297 * is used to gate frames based on the contents of another
298 * queue (e.g. CAB traffic may only follow a beacon frame).
299 * These are meaningful only when frames are scheduled
300 * with a non-ASAP policy (e.g. DBA-gated).
301 */
302 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
303 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
304
305 /*
306 * Fragment burst backoff policy. Normally the no backoff
307 * is done after a successful transmission, the next fragment
308 * is sent at SIFS. If this flag is set backoff is done
309 * after each fragment, regardless whether it was ack'd or
310 * not, after the backoff count reaches zero a normal channel
311 * access procedure is done before the next transmit (i.e.
312 * wait AIFS instead of SIFS).
313 */
314 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
315 /*
316 * Disable post-tx backoff following each frame.
317 */
318 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
319 /*
320 * DCU arbiter lockout control. This controls how
321 * lower priority tx queues are handled with respect to
322 * to a specific queue when multiple queues have frames
323 * to send. No lockout means lower priority queues arbitrate
324 * concurrently with this queue. Intra-frame lockout
325 * means lower priority queues are locked out until the
326 * current frame transmits (e.g. including backoffs and bursting).
327 * Global lockout means nothing lower can arbitrary so
328 * long as there is traffic activity on this queue (frames,
329 * backoff, etc).
330 */
331 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
332 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
333
334 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
335 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
336} HAL_TX_QUEUE_FLAGS;
337
338typedef struct {
339 uint32_t tqi_ver; /* hal TXQ version */
340 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
341 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
342 uint32_t tqi_priority; /* (not used) */
343 uint32_t tqi_aifs; /* aifs */
344 uint32_t tqi_cwmin; /* cwMin */
345 uint32_t tqi_cwmax; /* cwMax */
346 uint16_t tqi_shretry; /* rts retry limit */
347 uint16_t tqi_lgretry; /* long retry limit (not used)*/
348 uint32_t tqi_cbrPeriod; /* CBR period (us) */
349 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
350 uint32_t tqi_burstTime; /* max burst duration (us) */
351 uint32_t tqi_readyTime; /* frame schedule time (us) */
352 uint32_t tqi_compBuf; /* comp buffer phys addr */
353} HAL_TXQ_INFO;
354
355#define HAL_TQI_NONVAL 0xffff
356
357/* token to use for aifs, cwmin, cwmax */
358#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
359
360/* compression definitions */
361#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
362#define HAL_COMP_BUF_ALIGN_SIZE 512
363
364/*
365 * Transmit packet types. This belongs in ah_desc.h, but
366 * is here so we can give a proper type to various parameters
367 * (and not require everyone include the file).
368 *
369 * NB: These values are intentionally assigned for
370 * direct use when setting up h/w descriptors.
371 */
372typedef enum {
373 HAL_PKT_TYPE_NORMAL = 0,
374 HAL_PKT_TYPE_ATIM = 1,
375 HAL_PKT_TYPE_PSPOLL = 2,
376 HAL_PKT_TYPE_BEACON = 3,
377 HAL_PKT_TYPE_PROBE_RESP = 4,
378 HAL_PKT_TYPE_CHIRP = 5,
379 HAL_PKT_TYPE_GRP_POLL = 6,
380 HAL_PKT_TYPE_AMPDU = 7,
381} HAL_PKT_TYPE;
382
383/* Rx Filter Frame Types */
384typedef enum {
385 /*
386 * These bits correspond to AR_RX_FILTER for all chips.
387 * Not all bits are supported by all chips.
388 */
389 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
390 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
391 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
392 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
393 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
394 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
395 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
396 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
397 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
398 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
399 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
400 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
401 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
402 /* Allow all mcast/bcast frames */
403
404 /*
405 * Magic RX filter flags that aren't targetting hardware bits
406 * but instead the HAL sets individual bits - eg PHYERR will result
407 * in OFDM/CCK timing error frames being received.
408 */
409 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
410} HAL_RX_FILTER;
411
412typedef enum {
413 HAL_PM_AWAKE = 0,
414 HAL_PM_FULL_SLEEP = 1,
415 HAL_PM_NETWORK_SLEEP = 2,
416 HAL_PM_UNDEFINED = 3
417} HAL_POWER_MODE;
418
419/*
420 * NOTE WELL:
421 * These are mapped to take advantage of the common locations for many of
422 * the bits on all of the currently supported MAC chips. This is to make
423 * the ISR as efficient as possible, while still abstracting HW differences.
424 * When new hardware breaks this commonality this enumerated type, as well
425 * as the HAL functions using it, must be modified. All values are directly
426 * mapped unless commented otherwise.
427 */
428typedef enum {
429 HAL_INT_RX = 0x00000001, /* Non-common mapping */
430 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
431 HAL_INT_RXERR = 0x00000004,
432 HAL_INT_RXHP = 0x00000001, /* EDMA */
433 HAL_INT_RXLP = 0x00000002, /* EDMA */
434 HAL_INT_RXNOFRM = 0x00000008,
435 HAL_INT_RXEOL = 0x00000010,
436 HAL_INT_RXORN = 0x00000020,
437 HAL_INT_TX = 0x00000040, /* Non-common mapping */
438 HAL_INT_TXDESC = 0x00000080,
439 HAL_INT_TIM_TIMER= 0x00000100,
440 HAL_INT_MCI = 0x00000200,
441 HAL_INT_BBPANIC = 0x00000400,
442 HAL_INT_TXURN = 0x00000800,
443 HAL_INT_MIB = 0x00001000,
444 HAL_INT_RXPHY = 0x00004000,
445 HAL_INT_RXKCM = 0x00008000,
446 HAL_INT_SWBA = 0x00010000,
447 HAL_INT_BRSSI = 0x00020000,
448 HAL_INT_BMISS = 0x00040000,
449 HAL_INT_BNR = 0x00100000,
450 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
451 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
452 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
453 HAL_INT_GPIO = 0x01000000,
454 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
455 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
456 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
457 /* Atheros ref driver has a generic timer interrupt now..*/
458 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
459 HAL_INT_CST = 0x10000000, /* Non-common mapping */
460 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
461 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
462#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
463 HAL_INT_BMISC = HAL_INT_TIM
464 | HAL_INT_DTIM
465 | HAL_INT_DTIMSYNC
466 | HAL_INT_CABEND
467 | HAL_INT_TBTT,
468
469 /* Interrupt bits that map directly to ISR/IMR bits */
470 HAL_INT_COMMON = HAL_INT_RXNOFRM
471 | HAL_INT_RXDESC
472 | HAL_INT_RXEOL
473 | HAL_INT_RXORN
474 | HAL_INT_TXDESC
475 | HAL_INT_TXURN
476 | HAL_INT_MIB
477 | HAL_INT_RXPHY
478 | HAL_INT_RXKCM
479 | HAL_INT_SWBA
480 | HAL_INT_BMISS
481 | HAL_INT_BRSSI
482 | HAL_INT_BNR
483 | HAL_INT_GPIO,
484} HAL_INT;
485
486/*
487 * MSI vector assignments
488 */
489typedef enum {
490 HAL_MSIVEC_MISC = 0,
491 HAL_MSIVEC_TX = 1,
492 HAL_MSIVEC_RXLP = 2,
493 HAL_MSIVEC_RXHP = 3,
494} HAL_MSIVEC;
495
496typedef enum {
497 HAL_INT_LINE = 0,
498 HAL_INT_MSI = 1,
499} HAL_INT_TYPE;
500
501/* For interrupt mitigation registers */
502typedef enum {
503 HAL_INT_RX_FIRSTPKT=0,
504 HAL_INT_RX_LASTPKT,
505 HAL_INT_TX_FIRSTPKT,
506 HAL_INT_TX_LASTPKT,
507 HAL_INT_THRESHOLD
508} HAL_INT_MITIGATION;
509
510typedef enum {
511 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
512 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
513 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2,
514 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3,
515 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4,
516 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5,
517 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6
518} HAL_GPIO_MUX_TYPE;
519
520typedef enum {
521 HAL_GPIO_INTR_LOW = 0,
522 HAL_GPIO_INTR_HIGH = 1,
523 HAL_GPIO_INTR_DISABLE = 2
524} HAL_GPIO_INTR_TYPE;
525
526typedef enum {
527 HAL_RFGAIN_INACTIVE = 0,
528 HAL_RFGAIN_READ_REQUESTED = 1,
529 HAL_RFGAIN_NEED_CHANGE = 2
530} HAL_RFGAIN;
531
532typedef uint16_t HAL_CTRY_CODE; /* country code */
533typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
534
535#define HAL_ANTENNA_MIN_MODE 0
536#define HAL_ANTENNA_FIXED_A 1
537#define HAL_ANTENNA_FIXED_B 2
538#define HAL_ANTENNA_MAX_MODE 3
539
540typedef struct {
541 uint32_t ackrcv_bad;
542 uint32_t rts_bad;
543 uint32_t rts_good;
544 uint32_t fcs_bad;
545 uint32_t beacons;
546} HAL_MIB_STATS;
547
548enum {
549 HAL_MODE_11A = 0x001, /* 11a channels */
550 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
551 HAL_MODE_11B = 0x004, /* 11b channels */
552 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
553#ifdef notdef
554 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
555#else
556 HAL_MODE_11G = 0x008, /* XXX historical */
557#endif
558 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
559 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
560 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
561 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
562 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
563 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
564 HAL_MODE_11NG_HT20 = 0x008000,
565 HAL_MODE_11NA_HT20 = 0x010000,
566 HAL_MODE_11NG_HT40PLUS = 0x020000,
567 HAL_MODE_11NG_HT40MINUS = 0x040000,
568 HAL_MODE_11NA_HT40PLUS = 0x080000,
569 HAL_MODE_11NA_HT40MINUS = 0x100000,
570 HAL_MODE_ALL = 0xffffff
571};
572
573typedef struct {
574 int rateCount; /* NB: for proper padding */
575 uint8_t rateCodeToIndex[256]; /* back mapping */
576 struct {
577 uint8_t valid; /* valid for rate control use */
578 uint8_t phy; /* CCK/OFDM/XR */
579 uint32_t rateKbps; /* transfer rate in kbs */
580 uint8_t rateCode; /* rate for h/w descriptors */
581 uint8_t shortPreamble; /* mask for enabling short
582 * preamble in CCK rate code */
583 uint8_t dot11Rate; /* value for supported rates
584 * info element of MLME */
585 uint8_t controlRate; /* index of next lower basic
586 * rate; used for dur. calcs */
587 uint16_t lpAckDuration; /* long preamble ACK duration */
588 uint16_t spAckDuration; /* short preamble ACK duration*/
589 } info[64];
590} HAL_RATE_TABLE;
591
592typedef struct {
593 u_int rs_count; /* number of valid entries */
594 uint8_t rs_rates[64]; /* rates */
595} HAL_RATE_SET;
596
597/*
598 * 802.11n specific structures and enums
599 */
600typedef enum {
601 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
602 HAL_CHAINTYPE_RX = 2, /* RX chain type */
603} HAL_CHAIN_TYPE;
604
605typedef struct {
606 u_int Tries;
607 u_int Rate; /* hardware rate code */
608 u_int RateIndex; /* rate series table index */
609 u_int PktDuration;
610 u_int ChSel;
611 u_int RateFlags;
612#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
613#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
614#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
615#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
616 u_int tx_power_cap;
617} HAL_11N_RATE_SERIES;
618
619typedef enum {
620 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
621 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
622} HAL_HT_MACMODE;
623
624typedef enum {
625 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
626 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
627} HAL_HT_PHYMODE;
628
629typedef enum {
630 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
631 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
632} HAL_HT_EXTPROTSPACING;
633
634
635typedef enum {
636 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
637 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
638} HAL_HT_RXCLEAR;
639
640/*
641 * Antenna switch control. By default antenna selection
642 * enables multiple (2) antenna use. To force use of the
643 * A or B antenna only specify a fixed setting. Fixing
644 * the antenna will also disable any diversity support.
645 */
646typedef enum {
647 HAL_ANT_VARIABLE = 0, /* variable by programming */
648 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
649 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
650} HAL_ANT_SETTING;
651
652typedef enum {
653 HAL_M_STA = 1, /* infrastructure station */
654 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
655 HAL_M_HOSTAP = 6, /* Software Access Point */
656 HAL_M_MONITOR = 8 /* Monitor mode */
657} HAL_OPMODE;
658
659typedef struct {
660 uint8_t kv_type; /* one of HAL_CIPHER */
661 uint8_t kv_apsd; /* Mask for APSD enabled ACs */
662 uint16_t kv_len; /* length in bits */
663 uint8_t kv_val[16]; /* enough for 128-bit keys */
664 uint8_t kv_mic[8]; /* TKIP MIC key */
665 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
666} HAL_KEYVAL;
667
668typedef enum {
669 HAL_CIPHER_WEP = 0,
670 HAL_CIPHER_AES_OCB = 1,
671 HAL_CIPHER_AES_CCM = 2,
672 HAL_CIPHER_CKIP = 3,
673 HAL_CIPHER_TKIP = 4,
674 HAL_CIPHER_CLR = 5, /* no encryption */
675
676 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
677} HAL_CIPHER;
678
679enum {
680 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
681 HAL_SLOT_TIME_9 = 9,
682 HAL_SLOT_TIME_20 = 20,
683};
684
685/*
686 * Per-station beacon timer state. Note that the specified
687 * beacon interval (given in TU's) can also include flags
688 * to force a TSF reset and to enable the beacon xmit logic.
689 * If bs_cfpmaxduration is non-zero the hardware is setup to
690 * coexist with a PCF-capable AP.
691 */
692typedef struct {
693 uint32_t bs_nexttbtt; /* next beacon in TU */
694 uint32_t bs_nextdtim; /* next DTIM in TU */
695 uint32_t bs_intval; /* beacon interval+flags */
696#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
697#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
698#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
699 uint32_t bs_dtimperiod;
700 uint16_t bs_cfpperiod; /* CFP period in TU */
701 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
702 uint32_t bs_cfpnext; /* next CFP in TU */
703 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
704 uint16_t bs_bmissthreshold; /* beacon miss threshold */
705 uint32_t bs_sleepduration; /* max sleep duration */
706} HAL_BEACON_STATE;
707
708/*
709 * Like HAL_BEACON_STATE but for non-station mode setup.
710 * NB: see above flag definitions for bt_intval.
711 */
712typedef struct {
713 uint32_t bt_intval; /* beacon interval+flags */
714 uint32_t bt_nexttbtt; /* next beacon in TU */
715 uint32_t bt_nextatim; /* next ATIM in TU */
716 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
717 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
718 uint32_t bt_flags; /* timer enables */
719#define HAL_BEACON_TBTT_EN 0x00000001
720#define HAL_BEACON_DBA_EN 0x00000002
721#define HAL_BEACON_SWBA_EN 0x00000004
722} HAL_BEACON_TIMERS;
723
724/*
725 * Per-node statistics maintained by the driver for use in
726 * optimizing signal quality and other operational aspects.
727 */
728typedef struct {
729 uint32_t ns_avgbrssi; /* average beacon rssi */
730 uint32_t ns_avgrssi; /* average data rssi */
731 uint32_t ns_avgtxrssi; /* average tx rssi */
732} HAL_NODE_STATS;
733
734#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
735
736struct ath_desc;
737struct ath_tx_status;
738struct ath_rx_status;
739struct ieee80211_channel;
740
741/*
742 * This is a channel survey sample entry.
743 *
744 * The AR5212 ANI routines fill these samples. The ANI code then uses it
745 * when calculating listen time; it is also exported via a diagnostic
746 * API.
747 */
748typedef struct {
749 uint32_t seq_num;
750 uint32_t tx_busy;
751 uint32_t rx_busy;
752 uint32_t chan_busy;
753 uint32_t ext_chan_busy;
754 uint32_t cycle_count;
755 /* XXX TODO */
756 uint32_t ofdm_phyerr_count;
757 uint32_t cck_phyerr_count;
758} HAL_SURVEY_SAMPLE;
759
760/*
761 * This provides 3.2 seconds of sample space given an
762 * ANI time of 1/10th of a second. This may not be enough!
763 */
764#define CHANNEL_SURVEY_SAMPLE_COUNT 32
765
766typedef struct {
767 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT];
768 uint32_t cur_sample; /* current sample in sequence */
769 uint32_t cur_seq; /* current sequence number */
770} HAL_CHANNEL_SURVEY;
771
772/*
773 * ANI commands.
774 *
775 * These are used both internally and externally via the diagnostic
776 * API.
777 *
778 * Note that this is NOT the ANI commands being used via the INTMIT
779 * capability - that has a different mapping for some reason.
780 */
781typedef enum {
782 HAL_ANI_PRESENT = 0, /* is ANI support present */
783 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */
784 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */
785 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */
786 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */
787 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
788 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
789 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
790 HAL_ANI_MRC_CCK = 8,
791} HAL_ANI_CMD;
792
793/*
794 * This is the layout of the ANI INTMIT capability.
795 *
796 * Notice that the command values differ to HAL_ANI_CMD.
797 */
798typedef enum {
799 HAL_CAP_INTMIT_PRESENT = 0,
800 HAL_CAP_INTMIT_ENABLE = 1,
801 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2,
802 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3,
803 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4,
804 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5,
805 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
806} HAL_CAP_INTMIT_CMD;
807
808/* DFS defines */
809typedef struct {
810 int32_t pe_firpwr; /* FIR pwr out threshold */
811 int32_t pe_rrssi; /* Radar rssi thresh */
812 int32_t pe_height; /* Pulse height thresh */
813 int32_t pe_prssi; /* Pulse rssi thresh */
814 int32_t pe_inband; /* Inband thresh */
815
816 /* The following params are only for AR5413 and later */
817 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
818 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
819 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
820 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */
821 int32_t pe_blockradar; /*
822 * Enable to block radar check if pkt detect is done via OFDM
823 * weak signal detect or pkt is detected immediately after tx
824 * to rx transition
825 */
826 int32_t pe_enmaxrssi; /*
827 * Enable to use the max rssi instead of the last rssi during
828 * fine gain changes for radar detection
829 */
830 int32_t pe_extchannel; /* Enable DFS on ext channel */
831 int32_t pe_enabled; /* Whether radar detection is enabled */
832 int32_t pe_enrelpwr;
833 int32_t pe_en_relstep_check;
834} HAL_PHYERR_PARAM;
835
836#define HAL_PHYERR_PARAM_NOVAL 65535
837
838/*
839 * DFS operating mode flags.
840 */
841typedef enum {
842 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
843 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
844 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
845 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
846} HAL_DFS_DOMAIN;
847
848/*
849 * MFP decryption options for initializing the MAC.
850 */
851
852typedef enum {
853 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
854 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */
855 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */
856} HAL_MFP_OPT_T;
857
858/*
859 * Flag for setting QUIET period
860 */
861typedef enum {
862 HAL_QUIET_DISABLE = 0x0,
863 HAL_QUIET_ENABLE = 0x1,
864 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
865 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
866} HAL_QUIET_FLAG;
867
868#define HAL_DFS_EVENT_PRICH 0x0000001
869#define HAL_DFS_EVENT_EXTCH 0x0000002
870#define HAL_DFS_EVENT_EXTEARLY 0x0000004
871#define HAL_DFS_EVENT_ISDC 0x0000008
872
873struct hal_dfs_event {
874 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */
875 uint32_t re_ts; /* Original 15 bit recv timestamp */
876 uint8_t re_rssi; /* rssi of radar event */
877 uint8_t re_dur; /* duration of radar pulse */
878 uint32_t re_flags; /* Flags (see above) */
879};
880typedef struct hal_dfs_event HAL_DFS_EVENT;
881
882/*
883 * BT Co-existence definitions
884 */
885typedef enum {
886 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
887 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
888 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
889 HAL_MAX_BT_MODULES
890} HAL_BT_MODULE;
891
892typedef struct {
893 HAL_BT_MODULE bt_module;
894 u_int8_t bt_coex_config;
895 u_int8_t bt_gpio_bt_active;
896 u_int8_t bt_gpio_bt_priority;
897 u_int8_t bt_gpio_wlan_active;
898 u_int8_t bt_active_polarity;
899 HAL_BOOL bt_single_ant;
900 u_int8_t bt_dutyCycle;
901 u_int8_t bt_isolation;
902 u_int8_t bt_period;
903} HAL_BT_COEX_INFO;
904
905typedef enum {
906 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
907 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
908 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
909 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
910} HAL_BT_COEX_MODE;
911
912typedef enum {
913 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
914 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
915 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
916 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
917 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
918 HAL_BT_COEX_CFG_MCI /* MCI */
919} HAL_BT_COEX_CFG;
920
921typedef enum {
922 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
923 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
924 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
925} HAL_BT_COEX_SET_PARAMETER;
926
927#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
928#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
929/* Check Rx Diversity is allowed */
930#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
931/* Check Diversity is on or off */
932#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
933
934#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
935/* main: LNA1, alt: LNA2 */
936#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
937#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
938#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
939#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
940#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
941
942#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
943
944#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
945
946#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
947
948#define HAL_BT_COEX_LOW_ACK_POWER 0x0
949#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
950
951typedef enum {
952 HAL_BT_COEX_NO_STOMP = 0,
953 HAL_BT_COEX_STOMP_ALL,
954 HAL_BT_COEX_STOMP_LOW,
955 HAL_BT_COEX_STOMP_NONE,
956 HAL_BT_COEX_STOMP_ALL_FORCE,
957 HAL_BT_COEX_STOMP_LOW_FORCE,
958} HAL_BT_COEX_STOMP_TYPE;
959
960typedef struct {
961 /* extend rx_clear after tx/rx to protect the burst (in usec). */
962 u_int8_t bt_time_extend;
963
964 /*
965 * extend rx_clear as long as txsm is
966 * transmitting or waiting for ack.
967 */
968 HAL_BOOL bt_txstate_extend;
969
970 /*
971 * extend rx_clear so that when tx_frame
972 * is asserted, rx_clear will drop.
973 */
974 HAL_BOOL bt_txframe_extend;
975
976 /*
977 * coexistence mode
978 */
979 HAL_BT_COEX_MODE bt_mode;
980
981 /*
982 * treat BT high priority traffic as
983 * a quiet collision
984 */
985 HAL_BOOL bt_quiet_collision;
986
987 /*
988 * invert rx_clear as WLAN_ACTIVE
989 */
990 HAL_BOOL bt_rxclear_polarity;
991
992 /*
993 * slotted mode only. indicate the time in usec
994 * from the rising edge of BT_ACTIVE to the time
995 * BT_PRIORITY can be sampled to indicate priority.
996 */
997 u_int8_t bt_priority_time;
998
999 /*
1000 * slotted mode only. indicate the time in usec
1001 * from the rising edge of BT_ACTIVE to the time
1002 * BT_PRIORITY can be sampled to indicate tx/rx and
1003 * BT_FREQ is sampled.
1004 */
1005 u_int8_t bt_first_slot_time;
1006
1007 /*
1008 * slotted mode only. rx_clear and bt_ant decision
1009 * will be held the entire time that BT_ACTIVE is asserted,
1010 * otherwise the decision is made before every slot boundry.
1011 */
1012 HAL_BOOL bt_hold_rxclear;
1013} HAL_BT_COEX_CONFIG;
1014
1015typedef struct
1016{
1017 int ah_debug; /* only used if AH_DEBUG is defined */
1018 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */
1019
1020 /* NB: these are deprecated; they exist for now for compatibility */
1021 int ah_dma_beacon_response_time;/* in TU's */
1022 int ah_sw_beacon_response_time; /* in TU's */
1023 int ah_additional_swba_backoff; /* in TU's */
1024 int ah_force_full_reset; /* force full chip reset rather then warm reset */
1025 int ah_serialise_reg_war; /* force serialisation of register IO */
1026} HAL_OPS_CONFIG;
1027
1028/*
1029 * Hardware Access Layer (HAL) API.
1030 *
1031 * Clients of the HAL call ath_hal_attach to obtain a reference to an
1032 * ath_hal structure for use with the device. Hardware-related operations
1033 * that follow must call back into the HAL through interface, supplying
1034 * the reference as the first parameter. Note that before using the
1035 * reference returned by ath_hal_attach the caller should verify the
1036 * ABI version number.
1037 */
1038struct ath_hal {
1039 uint32_t ah_magic; /* consistency check magic number */
1040 uint16_t ah_devid; /* PCI device ID */
1041 uint16_t ah_subvendorid; /* PCI subvendor ID */
1042 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
1043 HAL_BUS_TAG ah_st; /* params for register r+w */
1044 HAL_BUS_HANDLE ah_sh;
1045 HAL_CTRY_CODE ah_countryCode;
1046
1047 uint32_t ah_macVersion; /* MAC version id */
1048 uint16_t ah_macRev; /* MAC revision */
1049 uint16_t ah_phyRev; /* PHY revision */
1050 /* NB: when only one radio is present the rev is in 5Ghz */
1051 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
1052 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
1053
1054 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
1055
1056 uint32_t ah_intrstate[8]; /* last int state */
1057 uint32_t ah_syncstate; /* last sync intr state */
1058
1059 HAL_OPS_CONFIG ah_config;
1060 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
1061 u_int mode);
1062 void __ahdecl(*ah_detach)(struct ath_hal*);
1063
1064 /* Reset functions */
1065 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
1066 struct ieee80211_channel *,
1067 HAL_BOOL bChannelChange, HAL_STATUS *status);
1068 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
1069 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
1070 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore,
1071 HAL_BOOL power_off);
1072 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
1073 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
1074 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
1075 struct ieee80211_channel *, HAL_BOOL *);
1076 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
1077 struct ieee80211_channel *, u_int chainMask,
1078 HAL_BOOL longCal, HAL_BOOL *isCalDone);
1079 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
1080 const struct ieee80211_channel *);
1081 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
1082 const struct ieee80211_channel *, uint16_t *);
1083 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
1084 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
1085 const struct ieee80211_channel *);
1086
1087 /* Transmit functions */
1088 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
1089 HAL_BOOL incTrigLevel);
1090 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
1091 const HAL_TXQ_INFO *qInfo);
1092 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
1093 const HAL_TXQ_INFO *qInfo);
1094 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
1095 HAL_TXQ_INFO *qInfo);
1096 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
1097 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
1098 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
1099 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
1100 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
1101 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
1102 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
1103 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
1104 u_int pktLen, u_int hdrLen,
1105 HAL_PKT_TYPE type, u_int txPower,
1106 u_int txRate0, u_int txTries0,
1107 u_int keyIx, u_int antMode, u_int flags,
1108 u_int rtsctsRate, u_int rtsctsDuration,
1109 u_int compicvLen, u_int compivLen,
1110 u_int comp);
1111 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
1112 u_int txRate1, u_int txTries1,
1113 u_int txRate2, u_int txTries2,
1114 u_int txRate3, u_int txTries3);
1115 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
1116 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
1117 u_int descId, u_int qcuId, HAL_BOOL firstSeg,
1118 HAL_BOOL lastSeg, const struct ath_desc *);
1119 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
1120 struct ath_desc *, struct ath_tx_status *);
1121 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
1122 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
1123 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
1124 const struct ath_desc *ds, int *rates, int *tries);
1125 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,
1126 uint32_t link);
1127 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,
1128 uint32_t *link);
1129 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,
1130 uint32_t **linkptr);
1131 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *,
1132 void *ts_start, uint32_t ts_paddr_start,
1133 uint16_t size);
1134
1135 /* Receive Functions */
1136 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE);
1137 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE);
1138 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
1139 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
1140 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
1141 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
1142 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
1143 uint32_t filter0, uint32_t filter1);
1144 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
1145 uint32_t index);
1146 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
1147 uint32_t index);
1148 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
1149 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
1150 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
1151 uint32_t size, u_int flags);
1152 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
1153 struct ath_desc *, uint32_t phyAddr,
1154 struct ath_desc *next, uint64_t tsf,
1155 struct ath_rx_status *);
1156 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
1157 const HAL_NODE_STATS *,
1158 const struct ieee80211_channel *);
1159 void __ahdecl(*ah_aniPoll)(struct ath_hal *,
1160 const struct ieee80211_channel *);
1161 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
1162 const HAL_NODE_STATS *);
1163 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
1164 struct ath_rx_status *,
1165 unsigned long, int);
1166
1167 /* Misc Functions */
1168 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
1169 HAL_CAPABILITY_TYPE, uint32_t capability,
1170 uint32_t *result);
1171 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
1172 HAL_CAPABILITY_TYPE, uint32_t capability,
1173 uint32_t setting, HAL_STATUS *);
1174 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
1175 const void *args, uint32_t argsize,
1176 void **result, uint32_t *resultsize);
1177 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
1178 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
1179 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
1180 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
1181 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
1182 uint16_t, HAL_STATUS *);
1183 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
1184 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
1185 const uint8_t *bssid, uint16_t assocId);
1186 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
1187 uint32_t gpio, HAL_GPIO_MUX_TYPE);
1188 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
1189 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
1190 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
1191 uint32_t gpio, uint32_t val);
1192 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
1193 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
1194 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
1195 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
1196 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
1197 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
1198 HAL_MIB_STATS*);
1199 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
1200 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
1201 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
1202 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
1203 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
1204 HAL_ANT_SETTING);
1205 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
1206 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
1207 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
1208 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
1209 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
1210 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
1211 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
1212 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
1213 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
1214 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
1215 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
1216 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
1217 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
1218 uint32_t duration, uint32_t nextStart,
1219 HAL_QUIET_FLAG flag);
1220
1221 /* DFS functions */
1222 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
1223 HAL_PHYERR_PARAM *pe);
1224 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
1225 HAL_PHYERR_PARAM *pe);
|
1226 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
1227 struct ath_rx_status *rxs, uint64_t fulltsf,
1228 const char *buf, HAL_DFS_EVENT *event);
1229 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
1230
1231 /* Key Cache Functions */
1232 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
1233 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
1234 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
1235 uint16_t);
1236 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
1237 uint16_t, const HAL_KEYVAL *,
1238 const uint8_t *, int);
1239 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
1240 uint16_t, const uint8_t *);
1241
1242 /* Power Management Functions */
1243 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
1244 HAL_POWER_MODE mode, int setChip);
1245 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
1246 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
1247 const struct ieee80211_channel *);
1248
1249 /* Beacon Management Functions */
1250 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
1251 const HAL_BEACON_TIMERS *);
1252 /* NB: deprecated, use ah_setBeaconTimers instead */
1253 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
1254 uint32_t nexttbtt, uint32_t intval);
1255 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
1256 const HAL_BEACON_STATE *);
1257 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
1258 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *);
1259
1260 /* 802.11n Functions */
1261 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
1262 struct ath_desc *,
1263 HAL_DMA_ADDR *bufAddrList,
1264 uint32_t *segLenList,
1265 u_int, u_int, HAL_PKT_TYPE,
1266 u_int, HAL_CIPHER, uint8_t, HAL_BOOL,
1267 HAL_BOOL, HAL_BOOL);
1268 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
1269 struct ath_desc *, u_int, u_int, u_int,
1270 u_int, u_int, u_int, u_int, u_int);
1271 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *,
1272 struct ath_desc *, const struct ath_desc *);
1273 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
1274 struct ath_desc *, u_int, u_int,
1275 HAL_11N_RATE_SERIES [], u_int, u_int);
1276 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
1277 struct ath_desc *, u_int);
1278 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
1279 struct ath_desc *, u_int);
1280 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
1281 struct ath_desc *);
1282 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
1283 struct ath_desc *);
1284 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
1285 struct ath_desc *, u_int);
1286 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *,
1287 HAL_SURVEY_SAMPLE *);
1288
1289 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
1290 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
1291 HAL_HT_MACMODE);
1292 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);
1293 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *,
1294 HAL_HT_RXCLEAR);
1295
1296 /* Interrupt functions */
1297 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
1298 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
1299 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
1300 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
1301};
1302
1303/*
1304 * Check the PCI vendor ID and device ID against Atheros' values
1305 * and return a printable description for any Atheros hardware.
1306 * AH_NULL is returned if the ID's do not describe Atheros hardware.
1307 */
1308extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
1309
1310/*
1311 * Attach the HAL for use with the specified device. The device is
1312 * defined by the PCI device ID. The caller provides an opaque pointer
1313 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
1314 * HAL state block for later use. Hardware register accesses are done
1315 * using the specified bus tag and handle. On successful return a
1316 * reference to a state block is returned that must be supplied in all
1317 * subsequent HAL calls. Storage associated with this reference is
1318 * dynamically allocated and must be freed by calling the ah_detach
1319 * method when the client is done. If the attach operation fails a
1320 * null (AH_NULL) reference will be returned and a status code will
1321 * be returned if the status parameter is non-zero.
1322 */
1323extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
1324 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status);
1325
1326extern const char *ath_hal_mac_name(struct ath_hal *);
1327extern const char *ath_hal_rf_name(struct ath_hal *);
1328
1329/*
1330 * Regulatory interfaces. Drivers should use ath_hal_init_channels to
1331 * request a set of channels for a particular country code and/or
1332 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
1333 * this list is constructed according to the contents of the EEPROM.
1334 * ath_hal_getchannels acts similarly but does not alter the operating
1335 * state; this can be used to collect information for a particular
1336 * regulatory configuration. Finally ath_hal_set_channels installs a
1337 * channel list constructed outside the driver. The HAL will adopt the
1338 * channel list and setup internal state according to the specified
1339 * regulatory configuration (e.g. conformance test limits).
1340 *
1341 * For all interfaces the channel list is returned in the supplied array.
1342 * maxchans defines the maximum size of this array. nchans contains the
1343 * actual number of channels returned. If a problem occurred then a
1344 * status code != HAL_OK is returned.
1345 */
1346struct ieee80211_channel;
1347
1348/*
1349 * Return a list of channels according to the specified regulatory.
1350 */
1351extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
1352 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1353 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
1354 HAL_BOOL enableExtendedChannels);
1355
1356/*
1357 * Return a list of channels and install it as the current operating
1358 * regulatory list.
1359 */
1360extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
1361 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1362 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
1363 HAL_BOOL enableExtendedChannels);
1364
1365/*
1366 * Install the list of channels as the current operating regulatory
1367 * and setup related state according to the country code and sku.
1368 */
1369extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
1370 struct ieee80211_channel *chans, int nchans,
1371 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
1372
1373/*
1374 * Fetch the ctl/ext noise floor values reported by a MIMO
1375 * radio. Returns 1 for valid results, 0 for invalid channel.
1376 */
1377extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
1378 const struct ieee80211_channel *chan, int16_t *nf_ctl,
1379 int16_t *nf_ext);
1380
1381/*
1382 * Calibrate noise floor data following a channel scan or similar.
1383 * This must be called prior retrieving noise floor data.
1384 */
1385extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
1386
1387/*
1388 * Return bit mask of wireless modes supported by the hardware.
1389 */
1390extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
1391
1392/*
1393 * Get the HAL wireless mode for the given channel.
1394 */
1395extern int ath_hal_get_curmode(struct ath_hal *ah,
1396 const struct ieee80211_channel *chan);
1397
1398/*
1399 * Calculate the packet TX time for a legacy or 11n frame
1400 */
1401extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,
1402 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1403 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble);
1404
1405/*
1406 * Calculate the duration of an 11n frame.
1407 */
1408extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate,
1409 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI);
1410
1411/*
1412 * Calculate the transmit duration of a legacy frame.
1413 */
1414extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
1415 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1416 uint16_t rateix, HAL_BOOL shortPreamble);
1417
1418/*
1419 * Adjust the TSF.
1420 */
1421extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta);
1422
1423/*
1424 * Enable or disable CCA.
1425 */
1426void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena);
1427
1428/*
1429 * Get CCA setting.
1430 */
1431int __ahdecl ath_hal_getcca(struct ath_hal *ah);
1432
1433/*
1434 * Read EEPROM data from ah_eepromdata
1435 */
1436HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,
1437 u_int off, uint16_t *data);
1438
1439/*
1440 * For now, simply pass through MFP frames.
1441 */
1442static inline u_int32_t
1443ath_hal_get_mfp_qos(struct ath_hal *ah)
1444{
1445 //return AH_PRIVATE(ah)->ah_mfp_qos;
1446 return HAL_MFP_QOSDATA;
1447}
1448
1449#endif /* _ATH_AH_H_ */
| 1228 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
1229 struct ath_rx_status *rxs, uint64_t fulltsf,
1230 const char *buf, HAL_DFS_EVENT *event);
1231 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
1232
1233 /* Key Cache Functions */
1234 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
1235 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
1236 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
1237 uint16_t);
1238 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
1239 uint16_t, const HAL_KEYVAL *,
1240 const uint8_t *, int);
1241 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
1242 uint16_t, const uint8_t *);
1243
1244 /* Power Management Functions */
1245 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
1246 HAL_POWER_MODE mode, int setChip);
1247 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
1248 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
1249 const struct ieee80211_channel *);
1250
1251 /* Beacon Management Functions */
1252 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
1253 const HAL_BEACON_TIMERS *);
1254 /* NB: deprecated, use ah_setBeaconTimers instead */
1255 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
1256 uint32_t nexttbtt, uint32_t intval);
1257 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
1258 const HAL_BEACON_STATE *);
1259 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
1260 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *);
1261
1262 /* 802.11n Functions */
1263 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
1264 struct ath_desc *,
1265 HAL_DMA_ADDR *bufAddrList,
1266 uint32_t *segLenList,
1267 u_int, u_int, HAL_PKT_TYPE,
1268 u_int, HAL_CIPHER, uint8_t, HAL_BOOL,
1269 HAL_BOOL, HAL_BOOL);
1270 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
1271 struct ath_desc *, u_int, u_int, u_int,
1272 u_int, u_int, u_int, u_int, u_int);
1273 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *,
1274 struct ath_desc *, const struct ath_desc *);
1275 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
1276 struct ath_desc *, u_int, u_int,
1277 HAL_11N_RATE_SERIES [], u_int, u_int);
1278 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
1279 struct ath_desc *, u_int);
1280 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
1281 struct ath_desc *, u_int);
1282 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
1283 struct ath_desc *);
1284 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
1285 struct ath_desc *);
1286 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
1287 struct ath_desc *, u_int);
1288 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *,
1289 HAL_SURVEY_SAMPLE *);
1290
1291 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
1292 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
1293 HAL_HT_MACMODE);
1294 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);
1295 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *,
1296 HAL_HT_RXCLEAR);
1297
1298 /* Interrupt functions */
1299 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
1300 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
1301 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
1302 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
1303};
1304
1305/*
1306 * Check the PCI vendor ID and device ID against Atheros' values
1307 * and return a printable description for any Atheros hardware.
1308 * AH_NULL is returned if the ID's do not describe Atheros hardware.
1309 */
1310extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
1311
1312/*
1313 * Attach the HAL for use with the specified device. The device is
1314 * defined by the PCI device ID. The caller provides an opaque pointer
1315 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
1316 * HAL state block for later use. Hardware register accesses are done
1317 * using the specified bus tag and handle. On successful return a
1318 * reference to a state block is returned that must be supplied in all
1319 * subsequent HAL calls. Storage associated with this reference is
1320 * dynamically allocated and must be freed by calling the ah_detach
1321 * method when the client is done. If the attach operation fails a
1322 * null (AH_NULL) reference will be returned and a status code will
1323 * be returned if the status parameter is non-zero.
1324 */
1325extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
1326 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status);
1327
1328extern const char *ath_hal_mac_name(struct ath_hal *);
1329extern const char *ath_hal_rf_name(struct ath_hal *);
1330
1331/*
1332 * Regulatory interfaces. Drivers should use ath_hal_init_channels to
1333 * request a set of channels for a particular country code and/or
1334 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
1335 * this list is constructed according to the contents of the EEPROM.
1336 * ath_hal_getchannels acts similarly but does not alter the operating
1337 * state; this can be used to collect information for a particular
1338 * regulatory configuration. Finally ath_hal_set_channels installs a
1339 * channel list constructed outside the driver. The HAL will adopt the
1340 * channel list and setup internal state according to the specified
1341 * regulatory configuration (e.g. conformance test limits).
1342 *
1343 * For all interfaces the channel list is returned in the supplied array.
1344 * maxchans defines the maximum size of this array. nchans contains the
1345 * actual number of channels returned. If a problem occurred then a
1346 * status code != HAL_OK is returned.
1347 */
1348struct ieee80211_channel;
1349
1350/*
1351 * Return a list of channels according to the specified regulatory.
1352 */
1353extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
1354 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1355 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
1356 HAL_BOOL enableExtendedChannels);
1357
1358/*
1359 * Return a list of channels and install it as the current operating
1360 * regulatory list.
1361 */
1362extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
1363 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1364 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
1365 HAL_BOOL enableExtendedChannels);
1366
1367/*
1368 * Install the list of channels as the current operating regulatory
1369 * and setup related state according to the country code and sku.
1370 */
1371extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
1372 struct ieee80211_channel *chans, int nchans,
1373 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
1374
1375/*
1376 * Fetch the ctl/ext noise floor values reported by a MIMO
1377 * radio. Returns 1 for valid results, 0 for invalid channel.
1378 */
1379extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
1380 const struct ieee80211_channel *chan, int16_t *nf_ctl,
1381 int16_t *nf_ext);
1382
1383/*
1384 * Calibrate noise floor data following a channel scan or similar.
1385 * This must be called prior retrieving noise floor data.
1386 */
1387extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
1388
1389/*
1390 * Return bit mask of wireless modes supported by the hardware.
1391 */
1392extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
1393
1394/*
1395 * Get the HAL wireless mode for the given channel.
1396 */
1397extern int ath_hal_get_curmode(struct ath_hal *ah,
1398 const struct ieee80211_channel *chan);
1399
1400/*
1401 * Calculate the packet TX time for a legacy or 11n frame
1402 */
1403extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,
1404 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1405 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble);
1406
1407/*
1408 * Calculate the duration of an 11n frame.
1409 */
1410extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate,
1411 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI);
1412
1413/*
1414 * Calculate the transmit duration of a legacy frame.
1415 */
1416extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
1417 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1418 uint16_t rateix, HAL_BOOL shortPreamble);
1419
1420/*
1421 * Adjust the TSF.
1422 */
1423extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta);
1424
1425/*
1426 * Enable or disable CCA.
1427 */
1428void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena);
1429
1430/*
1431 * Get CCA setting.
1432 */
1433int __ahdecl ath_hal_getcca(struct ath_hal *ah);
1434
1435/*
1436 * Read EEPROM data from ah_eepromdata
1437 */
1438HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,
1439 u_int off, uint16_t *data);
1440
1441/*
1442 * For now, simply pass through MFP frames.
1443 */
1444static inline u_int32_t
1445ath_hal_get_mfp_qos(struct ath_hal *ah)
1446{
1447 //return AH_PRIVATE(ah)->ah_mfp_qos;
1448 return HAL_MFP_QOSDATA;
1449}
1450
1451#endif /* _ATH_AH_H_ */
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