1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
| 1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
|
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 224709 2011-08-08 13:15:39Z adrian $
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 224716 2011-08-08 16:22:42Z adrian $
|
18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31#include "ah_osdep.h"
32
33/*
34 * The maximum number of TX/RX chains supported.
35 * This is intended to be used by various statistics gathering operations
36 * (NF, RSSI, EVM).
37 */
38#define AH_MIMO_MAX_CHAINS 3
39#define AH_MIMO_MAX_EVM_PILOTS 6
40
41/*
42 * __ahdecl is analogous to _cdecl; it defines the calling
43 * convention used within the HAL. For most systems this
44 * can just default to be empty and the compiler will (should)
45 * use _cdecl. For systems where _cdecl is not compatible this
46 * must be defined. See linux/ah_osdep.h for an example.
47 */
48#ifndef __ahdecl
49#define __ahdecl
50#endif
51
52/*
53 * Status codes that may be returned by the HAL. Note that
54 * interfaces that return a status code set it only when an
55 * error occurs--i.e. you cannot check it for success.
56 */
57typedef enum {
58 HAL_OK = 0, /* No error */
59 HAL_ENXIO = 1, /* No hardware present */
60 HAL_ENOMEM = 2, /* Memory allocation failed */
61 HAL_EIO = 3, /* Hardware didn't respond as expected */
62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
63 HAL_EEVERSION = 5, /* EEPROM version invalid */
64 HAL_EELOCKED = 6, /* EEPROM unreadable */
65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
66 HAL_EEREAD = 8, /* EEPROM read problem */
67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
68 HAL_EESIZE = 10, /* EEPROM size not supported */
69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
70 HAL_EINVAL = 12, /* Invalid parameter to function */
71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
72 HAL_ESELFTEST = 14, /* Hardware self-test failed */
73 HAL_EINPROGRESS = 15, /* Operation incomplete */
74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
75 HAL_EEBADCC = 17, /* EEPROM invalid country code */
76} HAL_STATUS;
77
78typedef enum {
79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
80 AH_TRUE = 1,
81} HAL_BOOL;
82
83typedef enum {
84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
98 HAL_CAP_TXPOW = 15, /* global tx power limit */
99 HAL_CAP_TPC = 16, /* per-packet tx power control */
100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
104 /* 21 was HAL_CAP_XR */
105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
106 /* 23 was HAL_CAP_CHAN_HALFRATE */
107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
112
113 HAL_CAP_HT = 30, /* hardware can support HT */
114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */
117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */
118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
119
120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
121
122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
124 HAL_CAP_DFS_DMN = 44, /* current DFS domain */
125 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
126 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
127
128 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
129 automatically after waking up to receive TIM */
130 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
131 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
132 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
133
134 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
135
136 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
137
138 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
139 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
140
141 /* The following are private to the FreeBSD HAL (224 onward) */
142
143 HAL_CAP_INTMIT = 229, /* interference mitigation */
144 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
145 HAL_CAP_BB_HANG = 235, /* can baseband hang */
146 HAL_CAP_MAC_HANG = 236, /* can MAC hang */
147 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
148 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
149 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
150 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
151} HAL_CAPABILITY_TYPE;
152
153/*
154 * "States" for setting the LED. These correspond to
155 * the possible 802.11 operational states and there may
156 * be a many-to-one mapping between these states and the
157 * actual hardware state for the LED's (i.e. the hardware
158 * may have fewer states).
159 */
160typedef enum {
161 HAL_LED_INIT = 0,
162 HAL_LED_SCAN = 1,
163 HAL_LED_AUTH = 2,
164 HAL_LED_ASSOC = 3,
165 HAL_LED_RUN = 4
166} HAL_LED_STATE;
167
168/*
169 * Transmit queue types/numbers. These are used to tag
170 * each transmit queue in the hardware and to identify a set
171 * of transmit queues for operations such as start/stop dma.
172 */
173typedef enum {
174 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
175 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
176 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
177 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
178 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
179 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
180} HAL_TX_QUEUE;
181
182#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
183
184/*
185 * Transmit queue subtype. These map directly to
186 * WME Access Categories (except for UPSD). Refer
187 * to Table 5 of the WME spec.
188 */
189typedef enum {
190 HAL_WME_AC_BK = 0, /* background access category */
191 HAL_WME_AC_BE = 1, /* best effort access category*/
192 HAL_WME_AC_VI = 2, /* video access category */
193 HAL_WME_AC_VO = 3, /* voice access category */
194 HAL_WME_UPSD = 4, /* uplink power save */
195} HAL_TX_QUEUE_SUBTYPE;
196
197/*
198 * Transmit queue flags that control various
199 * operational parameters.
200 */
201typedef enum {
202 /*
203 * Per queue interrupt enables. When set the associated
204 * interrupt may be delivered for packets sent through
205 * the queue. Without these enabled no interrupts will
206 * be delivered for transmits through the queue.
207 */
208 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
209 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
210 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
211 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
212 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
213 /*
214 * Enable hardware compression for packets sent through
215 * the queue. The compression buffer must be setup and
216 * packets must have a key entry marked in the tx descriptor.
217 */
218 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
219 /*
220 * Disable queue when veol is hit or ready time expires.
221 * By default the queue is disabled only on reaching the
222 * physical end of queue (i.e. a null link ptr in the
223 * descriptor chain).
224 */
225 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
226 /*
227 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
228 * event. Frames will be transmitted only when this timer
229 * fires, e.g to transmit a beacon in ap or adhoc modes.
230 */
231 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
232 /*
233 * Each transmit queue has a counter that is incremented
234 * each time the queue is enabled and decremented when
235 * the list of frames to transmit is traversed (or when
236 * the ready time for the queue expires). This counter
237 * must be non-zero for frames to be scheduled for
238 * transmission. The following controls disable bumping
239 * this counter under certain conditions. Typically this
240 * is used to gate frames based on the contents of another
241 * queue (e.g. CAB traffic may only follow a beacon frame).
242 * These are meaningful only when frames are scheduled
243 * with a non-ASAP policy (e.g. DBA-gated).
244 */
245 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
246 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
247
248 /*
249 * Fragment burst backoff policy. Normally the no backoff
250 * is done after a successful transmission, the next fragment
251 * is sent at SIFS. If this flag is set backoff is done
252 * after each fragment, regardless whether it was ack'd or
253 * not, after the backoff count reaches zero a normal channel
254 * access procedure is done before the next transmit (i.e.
255 * wait AIFS instead of SIFS).
256 */
257 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
258 /*
259 * Disable post-tx backoff following each frame.
260 */
261 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
262 /*
263 * DCU arbiter lockout control. This controls how
264 * lower priority tx queues are handled with respect to
265 * to a specific queue when multiple queues have frames
266 * to send. No lockout means lower priority queues arbitrate
267 * concurrently with this queue. Intra-frame lockout
268 * means lower priority queues are locked out until the
269 * current frame transmits (e.g. including backoffs and bursting).
270 * Global lockout means nothing lower can arbitrary so
271 * long as there is traffic activity on this queue (frames,
272 * backoff, etc).
273 */
274 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
275 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
276
277 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
278 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
279} HAL_TX_QUEUE_FLAGS;
280
281typedef struct {
282 uint32_t tqi_ver; /* hal TXQ version */
283 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
284 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
285 uint32_t tqi_priority; /* (not used) */
286 uint32_t tqi_aifs; /* aifs */
287 uint32_t tqi_cwmin; /* cwMin */
288 uint32_t tqi_cwmax; /* cwMax */
289 uint16_t tqi_shretry; /* rts retry limit */
290 uint16_t tqi_lgretry; /* long retry limit (not used)*/
291 uint32_t tqi_cbrPeriod; /* CBR period (us) */
292 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
293 uint32_t tqi_burstTime; /* max burst duration (us) */
294 uint32_t tqi_readyTime; /* frame schedule time (us) */
295 uint32_t tqi_compBuf; /* comp buffer phys addr */
296} HAL_TXQ_INFO;
297
298#define HAL_TQI_NONVAL 0xffff
299
300/* token to use for aifs, cwmin, cwmax */
301#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
302
303/* compression definitions */
304#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
305#define HAL_COMP_BUF_ALIGN_SIZE 512
306
307/*
308 * Transmit packet types. This belongs in ah_desc.h, but
309 * is here so we can give a proper type to various parameters
310 * (and not require everyone include the file).
311 *
312 * NB: These values are intentionally assigned for
313 * direct use when setting up h/w descriptors.
314 */
315typedef enum {
316 HAL_PKT_TYPE_NORMAL = 0,
317 HAL_PKT_TYPE_ATIM = 1,
318 HAL_PKT_TYPE_PSPOLL = 2,
319 HAL_PKT_TYPE_BEACON = 3,
320 HAL_PKT_TYPE_PROBE_RESP = 4,
321 HAL_PKT_TYPE_CHIRP = 5,
322 HAL_PKT_TYPE_GRP_POLL = 6,
323 HAL_PKT_TYPE_AMPDU = 7,
324} HAL_PKT_TYPE;
325
326/* Rx Filter Frame Types */
327typedef enum {
328 /*
329 * These bits correspond to AR_RX_FILTER for all chips.
330 * Not all bits are supported by all chips.
331 */
332 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
333 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
334 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
335 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
336 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
337 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
338 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
339 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
340 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
341 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
342 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
343 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
344 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
345 /* Allow all mcast/bcast frames */
346
347 /*
348 * Magic RX filter flags that aren't targetting hardware bits
349 * but instead the HAL sets individual bits - eg PHYERR will result
350 * in OFDM/CCK timing error frames being received.
351 */
352 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
353} HAL_RX_FILTER;
354
355typedef enum {
356 HAL_PM_AWAKE = 0,
357 HAL_PM_FULL_SLEEP = 1,
358 HAL_PM_NETWORK_SLEEP = 2,
359 HAL_PM_UNDEFINED = 3
360} HAL_POWER_MODE;
361
362/*
363 * NOTE WELL:
364 * These are mapped to take advantage of the common locations for many of
365 * the bits on all of the currently supported MAC chips. This is to make
366 * the ISR as efficient as possible, while still abstracting HW differences.
367 * When new hardware breaks this commonality this enumerated type, as well
368 * as the HAL functions using it, must be modified. All values are directly
369 * mapped unless commented otherwise.
370 */
371typedef enum {
372 HAL_INT_RX = 0x00000001, /* Non-common mapping */
373 HAL_INT_RXDESC = 0x00000002,
374 HAL_INT_RXNOFRM = 0x00000008,
375 HAL_INT_RXEOL = 0x00000010,
376 HAL_INT_RXORN = 0x00000020,
377 HAL_INT_TX = 0x00000040, /* Non-common mapping */
378 HAL_INT_TXDESC = 0x00000080,
379 HAL_INT_TIM_TIMER= 0x00000100,
380 HAL_INT_TXURN = 0x00000800,
381 HAL_INT_MIB = 0x00001000,
382 HAL_INT_RXPHY = 0x00004000,
383 HAL_INT_RXKCM = 0x00008000,
384 HAL_INT_SWBA = 0x00010000,
385 HAL_INT_BMISS = 0x00040000,
386 HAL_INT_BNR = 0x00100000,
387 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
388 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
389 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
390 HAL_INT_GPIO = 0x01000000,
391 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
392 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
393 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
394 HAL_INT_CST = 0x10000000, /* Non-common mapping */
395 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
396 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
397#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
398 HAL_INT_BMISC = HAL_INT_TIM
399 | HAL_INT_DTIM
400 | HAL_INT_DTIMSYNC
401 | HAL_INT_CABEND
402 | HAL_INT_TBTT,
403
404 /* Interrupt bits that map directly to ISR/IMR bits */
405 HAL_INT_COMMON = HAL_INT_RXNOFRM
406 | HAL_INT_RXDESC
407 | HAL_INT_RXEOL
408 | HAL_INT_RXORN
409 | HAL_INT_TXDESC
410 | HAL_INT_TXURN
411 | HAL_INT_MIB
412 | HAL_INT_RXPHY
413 | HAL_INT_RXKCM
414 | HAL_INT_SWBA
415 | HAL_INT_BMISS
416 | HAL_INT_BNR
417 | HAL_INT_GPIO,
418} HAL_INT;
419
420typedef enum {
421 HAL_GPIO_MUX_OUTPUT = 0,
422 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
423 HAL_GPIO_MUX_PCIE_POWER_LED = 2,
424 HAL_GPIO_MUX_TX_FRAME = 3,
425 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
426 HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
427 HAL_GPIO_MUX_MAC_POWER_LED = 6
428} HAL_GPIO_MUX_TYPE;
429
430typedef enum {
431 HAL_GPIO_INTR_LOW = 0,
432 HAL_GPIO_INTR_HIGH = 1,
433 HAL_GPIO_INTR_DISABLE = 2
434} HAL_GPIO_INTR_TYPE;
435
436typedef enum {
437 HAL_RFGAIN_INACTIVE = 0,
438 HAL_RFGAIN_READ_REQUESTED = 1,
439 HAL_RFGAIN_NEED_CHANGE = 2
440} HAL_RFGAIN;
441
442typedef uint16_t HAL_CTRY_CODE; /* country code */
443typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
444
445#define HAL_ANTENNA_MIN_MODE 0
446#define HAL_ANTENNA_FIXED_A 1
447#define HAL_ANTENNA_FIXED_B 2
448#define HAL_ANTENNA_MAX_MODE 3
449
450typedef struct {
451 uint32_t ackrcv_bad;
452 uint32_t rts_bad;
453 uint32_t rts_good;
454 uint32_t fcs_bad;
455 uint32_t beacons;
456} HAL_MIB_STATS;
457
458enum {
459 HAL_MODE_11A = 0x001, /* 11a channels */
460 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
461 HAL_MODE_11B = 0x004, /* 11b channels */
462 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
463#ifdef notdef
464 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
465#else
466 HAL_MODE_11G = 0x008, /* XXX historical */
467#endif
468 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
469 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
470 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
471 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
472 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
473 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
474 HAL_MODE_11NG_HT20 = 0x008000,
475 HAL_MODE_11NA_HT20 = 0x010000,
476 HAL_MODE_11NG_HT40PLUS = 0x020000,
477 HAL_MODE_11NG_HT40MINUS = 0x040000,
478 HAL_MODE_11NA_HT40PLUS = 0x080000,
479 HAL_MODE_11NA_HT40MINUS = 0x100000,
480 HAL_MODE_ALL = 0xffffff
481};
482
483typedef struct {
484 int rateCount; /* NB: for proper padding */
485 uint8_t rateCodeToIndex[144]; /* back mapping */
486 struct {
487 uint8_t valid; /* valid for rate control use */
488 uint8_t phy; /* CCK/OFDM/XR */
489 uint32_t rateKbps; /* transfer rate in kbs */
490 uint8_t rateCode; /* rate for h/w descriptors */
491 uint8_t shortPreamble; /* mask for enabling short
492 * preamble in CCK rate code */
493 uint8_t dot11Rate; /* value for supported rates
494 * info element of MLME */
495 uint8_t controlRate; /* index of next lower basic
496 * rate; used for dur. calcs */
497 uint16_t lpAckDuration; /* long preamble ACK duration */
498 uint16_t spAckDuration; /* short preamble ACK duration*/
499 } info[32];
500} HAL_RATE_TABLE;
501
502typedef struct {
503 u_int rs_count; /* number of valid entries */
504 uint8_t rs_rates[32]; /* rates */
505} HAL_RATE_SET;
506
507/*
508 * 802.11n specific structures and enums
509 */
510typedef enum {
511 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
512 HAL_CHAINTYPE_RX = 2, /* RX chain type */
513} HAL_CHAIN_TYPE;
514
515typedef struct {
516 u_int Tries;
517 u_int Rate;
518 u_int PktDuration;
519 u_int ChSel;
520 u_int RateFlags;
521#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
522#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
523#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
524} HAL_11N_RATE_SERIES;
525
526typedef enum {
527 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
528 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
529} HAL_HT_MACMODE;
530
531typedef enum {
532 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
533 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
534} HAL_HT_PHYMODE;
535
536typedef enum {
537 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
538 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
539} HAL_HT_EXTPROTSPACING;
540
541
542typedef enum {
543 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
544 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
545} HAL_HT_RXCLEAR;
546
547/*
548 * Antenna switch control. By default antenna selection
549 * enables multiple (2) antenna use. To force use of the
550 * A or B antenna only specify a fixed setting. Fixing
551 * the antenna will also disable any diversity support.
552 */
553typedef enum {
554 HAL_ANT_VARIABLE = 0, /* variable by programming */
555 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
556 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
557} HAL_ANT_SETTING;
558
559typedef enum {
560 HAL_M_STA = 1, /* infrastructure station */
561 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
562 HAL_M_HOSTAP = 6, /* Software Access Point */
563 HAL_M_MONITOR = 8 /* Monitor mode */
564} HAL_OPMODE;
565
566typedef struct {
567 uint8_t kv_type; /* one of HAL_CIPHER */
568 uint8_t kv_pad;
569 uint16_t kv_len; /* length in bits */
570 uint8_t kv_val[16]; /* enough for 128-bit keys */
571 uint8_t kv_mic[8]; /* TKIP MIC key */
572 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
573} HAL_KEYVAL;
574
575typedef enum {
576 HAL_CIPHER_WEP = 0,
577 HAL_CIPHER_AES_OCB = 1,
578 HAL_CIPHER_AES_CCM = 2,
579 HAL_CIPHER_CKIP = 3,
580 HAL_CIPHER_TKIP = 4,
581 HAL_CIPHER_CLR = 5, /* no encryption */
582
583 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
584} HAL_CIPHER;
585
586enum {
587 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
588 HAL_SLOT_TIME_9 = 9,
589 HAL_SLOT_TIME_20 = 20,
590};
591
592/*
593 * Per-station beacon timer state. Note that the specified
594 * beacon interval (given in TU's) can also include flags
595 * to force a TSF reset and to enable the beacon xmit logic.
596 * If bs_cfpmaxduration is non-zero the hardware is setup to
597 * coexist with a PCF-capable AP.
598 */
599typedef struct {
600 uint32_t bs_nexttbtt; /* next beacon in TU */
601 uint32_t bs_nextdtim; /* next DTIM in TU */
602 uint32_t bs_intval; /* beacon interval+flags */
603#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
604#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
605#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
606 uint32_t bs_dtimperiod;
607 uint16_t bs_cfpperiod; /* CFP period in TU */
608 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
609 uint32_t bs_cfpnext; /* next CFP in TU */
610 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
611 uint16_t bs_bmissthreshold; /* beacon miss threshold */
612 uint32_t bs_sleepduration; /* max sleep duration */
613} HAL_BEACON_STATE;
614
615/*
616 * Like HAL_BEACON_STATE but for non-station mode setup.
617 * NB: see above flag definitions for bt_intval.
618 */
619typedef struct {
620 uint32_t bt_intval; /* beacon interval+flags */
621 uint32_t bt_nexttbtt; /* next beacon in TU */
622 uint32_t bt_nextatim; /* next ATIM in TU */
623 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
624 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
625 uint32_t bt_flags; /* timer enables */
626#define HAL_BEACON_TBTT_EN 0x00000001
627#define HAL_BEACON_DBA_EN 0x00000002
628#define HAL_BEACON_SWBA_EN 0x00000004
629} HAL_BEACON_TIMERS;
630
631/*
632 * Per-node statistics maintained by the driver for use in
633 * optimizing signal quality and other operational aspects.
634 */
635typedef struct {
636 uint32_t ns_avgbrssi; /* average beacon rssi */
637 uint32_t ns_avgrssi; /* average data rssi */
638 uint32_t ns_avgtxrssi; /* average tx rssi */
639} HAL_NODE_STATS;
640
641#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
642
643struct ath_desc;
644struct ath_tx_status;
645struct ath_rx_status;
646struct ieee80211_channel;
647
648/*
649 * This is a channel survey sample entry.
650 *
651 * The AR5212 ANI routines fill these samples. The ANI code then uses it
652 * when calculating listen time; it is also exported via a diagnostic
653 * API.
654 */
655typedef struct {
656 uint32_t seq_num;
657 uint32_t tx_busy;
658 uint32_t rx_busy;
659 uint32_t chan_busy;
660 uint32_t cycle_count;
661} HAL_SURVEY_SAMPLE;
662
663/*
664 * This provides 3.2 seconds of sample space given an
665 * ANI time of 1/10th of a second. This may not be enough!
666 */
667#define CHANNEL_SURVEY_SAMPLE_COUNT 32
668
669typedef struct {
670 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT];
671 uint32_t cur_sample; /* current sample in sequence */
672 uint32_t cur_seq; /* current sequence number */
673} HAL_CHANNEL_SURVEY;
674
675/*
676 * ANI commands.
677 *
678 * These are used both internally and externally via the diagnostic
679 * API.
680 *
681 * Note that this is NOT the ANI commands being used via the INTMIT
682 * capability - that has a different mapping for some reason.
683 */
684typedef enum {
685 HAL_ANI_PRESENT = 0, /* is ANI support present */
686 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */
687 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */
688 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */
689 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */
690 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
691 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
692 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
693} HAL_ANI_CMD;
694
695/*
696 * This is the layout of the ANI INTMIT capability.
697 *
698 * Notice that the command values differ to HAL_ANI_CMD.
699 */
700typedef enum {
701 HAL_CAP_INTMIT_PRESENT = 0,
702 HAL_CAP_INTMIT_ENABLE = 1,
703 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2,
704 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3,
705 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4,
706 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5,
707 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
708} HAL_CAP_INTMIT_CMD;
709
710typedef struct {
711 int32_t pe_firpwr; /* FIR pwr out threshold */
712 int32_t pe_rrssi; /* Radar rssi thresh */
713 int32_t pe_height; /* Pulse height thresh */
714 int32_t pe_prssi; /* Pulse rssi thresh */
715 int32_t pe_inband; /* Inband thresh */
716
717 /* The following params are only for AR5413 and later */
718 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
719 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
720 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
721 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */
722 int32_t pe_blockradar; /*
723 * Enable to block radar check if pkt detect is done via OFDM
724 * weak signal detect or pkt is detected immediately after tx
725 * to rx transition
726 */
727 int32_t pe_enmaxrssi; /*
728 * Enable to use the max rssi instead of the last rssi during
729 * fine gain changes for radar detection
730 */
731 int32_t pe_extchannel; /* Enable DFS on ext channel */
732 int32_t pe_enabled; /* Whether radar detection is enabled */
733} HAL_PHYERR_PARAM;
734
735#define HAL_PHYERR_PARAM_NOVAL 65535
736#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
737
| 18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
26 * structure for use with the device. Hardware-related operations that
27 * follow must call back into the HAL through interface, supplying the
28 * reference as the first parameter.
29 */
30
31#include "ah_osdep.h"
32
33/*
34 * The maximum number of TX/RX chains supported.
35 * This is intended to be used by various statistics gathering operations
36 * (NF, RSSI, EVM).
37 */
38#define AH_MIMO_MAX_CHAINS 3
39#define AH_MIMO_MAX_EVM_PILOTS 6
40
41/*
42 * __ahdecl is analogous to _cdecl; it defines the calling
43 * convention used within the HAL. For most systems this
44 * can just default to be empty and the compiler will (should)
45 * use _cdecl. For systems where _cdecl is not compatible this
46 * must be defined. See linux/ah_osdep.h for an example.
47 */
48#ifndef __ahdecl
49#define __ahdecl
50#endif
51
52/*
53 * Status codes that may be returned by the HAL. Note that
54 * interfaces that return a status code set it only when an
55 * error occurs--i.e. you cannot check it for success.
56 */
57typedef enum {
58 HAL_OK = 0, /* No error */
59 HAL_ENXIO = 1, /* No hardware present */
60 HAL_ENOMEM = 2, /* Memory allocation failed */
61 HAL_EIO = 3, /* Hardware didn't respond as expected */
62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
63 HAL_EEVERSION = 5, /* EEPROM version invalid */
64 HAL_EELOCKED = 6, /* EEPROM unreadable */
65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
66 HAL_EEREAD = 8, /* EEPROM read problem */
67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
68 HAL_EESIZE = 10, /* EEPROM size not supported */
69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
70 HAL_EINVAL = 12, /* Invalid parameter to function */
71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
72 HAL_ESELFTEST = 14, /* Hardware self-test failed */
73 HAL_EINPROGRESS = 15, /* Operation incomplete */
74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
75 HAL_EEBADCC = 17, /* EEPROM invalid country code */
76} HAL_STATUS;
77
78typedef enum {
79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
80 AH_TRUE = 1,
81} HAL_BOOL;
82
83typedef enum {
84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
98 HAL_CAP_TXPOW = 15, /* global tx power limit */
99 HAL_CAP_TPC = 16, /* per-packet tx power control */
100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
104 /* 21 was HAL_CAP_XR */
105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
106 /* 23 was HAL_CAP_CHAN_HALFRATE */
107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */
108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
112
113 HAL_CAP_HT = 30, /* hardware can support HT */
114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */
117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */
118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
119
120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
121
122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
124 HAL_CAP_DFS_DMN = 44, /* current DFS domain */
125 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
126 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
127
128 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
129 automatically after waking up to receive TIM */
130 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
131 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
132 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
133
134 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
135
136 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
137
138 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
139 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
140
141 /* The following are private to the FreeBSD HAL (224 onward) */
142
143 HAL_CAP_INTMIT = 229, /* interference mitigation */
144 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
145 HAL_CAP_BB_HANG = 235, /* can baseband hang */
146 HAL_CAP_MAC_HANG = 236, /* can MAC hang */
147 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
148 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
149 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
150 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
151} HAL_CAPABILITY_TYPE;
152
153/*
154 * "States" for setting the LED. These correspond to
155 * the possible 802.11 operational states and there may
156 * be a many-to-one mapping between these states and the
157 * actual hardware state for the LED's (i.e. the hardware
158 * may have fewer states).
159 */
160typedef enum {
161 HAL_LED_INIT = 0,
162 HAL_LED_SCAN = 1,
163 HAL_LED_AUTH = 2,
164 HAL_LED_ASSOC = 3,
165 HAL_LED_RUN = 4
166} HAL_LED_STATE;
167
168/*
169 * Transmit queue types/numbers. These are used to tag
170 * each transmit queue in the hardware and to identify a set
171 * of transmit queues for operations such as start/stop dma.
172 */
173typedef enum {
174 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
175 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
176 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
177 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
178 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
179 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
180} HAL_TX_QUEUE;
181
182#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
183
184/*
185 * Transmit queue subtype. These map directly to
186 * WME Access Categories (except for UPSD). Refer
187 * to Table 5 of the WME spec.
188 */
189typedef enum {
190 HAL_WME_AC_BK = 0, /* background access category */
191 HAL_WME_AC_BE = 1, /* best effort access category*/
192 HAL_WME_AC_VI = 2, /* video access category */
193 HAL_WME_AC_VO = 3, /* voice access category */
194 HAL_WME_UPSD = 4, /* uplink power save */
195} HAL_TX_QUEUE_SUBTYPE;
196
197/*
198 * Transmit queue flags that control various
199 * operational parameters.
200 */
201typedef enum {
202 /*
203 * Per queue interrupt enables. When set the associated
204 * interrupt may be delivered for packets sent through
205 * the queue. Without these enabled no interrupts will
206 * be delivered for transmits through the queue.
207 */
208 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
209 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
210 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
211 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
212 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
213 /*
214 * Enable hardware compression for packets sent through
215 * the queue. The compression buffer must be setup and
216 * packets must have a key entry marked in the tx descriptor.
217 */
218 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
219 /*
220 * Disable queue when veol is hit or ready time expires.
221 * By default the queue is disabled only on reaching the
222 * physical end of queue (i.e. a null link ptr in the
223 * descriptor chain).
224 */
225 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
226 /*
227 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
228 * event. Frames will be transmitted only when this timer
229 * fires, e.g to transmit a beacon in ap or adhoc modes.
230 */
231 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
232 /*
233 * Each transmit queue has a counter that is incremented
234 * each time the queue is enabled and decremented when
235 * the list of frames to transmit is traversed (or when
236 * the ready time for the queue expires). This counter
237 * must be non-zero for frames to be scheduled for
238 * transmission. The following controls disable bumping
239 * this counter under certain conditions. Typically this
240 * is used to gate frames based on the contents of another
241 * queue (e.g. CAB traffic may only follow a beacon frame).
242 * These are meaningful only when frames are scheduled
243 * with a non-ASAP policy (e.g. DBA-gated).
244 */
245 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
246 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
247
248 /*
249 * Fragment burst backoff policy. Normally the no backoff
250 * is done after a successful transmission, the next fragment
251 * is sent at SIFS. If this flag is set backoff is done
252 * after each fragment, regardless whether it was ack'd or
253 * not, after the backoff count reaches zero a normal channel
254 * access procedure is done before the next transmit (i.e.
255 * wait AIFS instead of SIFS).
256 */
257 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
258 /*
259 * Disable post-tx backoff following each frame.
260 */
261 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
262 /*
263 * DCU arbiter lockout control. This controls how
264 * lower priority tx queues are handled with respect to
265 * to a specific queue when multiple queues have frames
266 * to send. No lockout means lower priority queues arbitrate
267 * concurrently with this queue. Intra-frame lockout
268 * means lower priority queues are locked out until the
269 * current frame transmits (e.g. including backoffs and bursting).
270 * Global lockout means nothing lower can arbitrary so
271 * long as there is traffic activity on this queue (frames,
272 * backoff, etc).
273 */
274 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
275 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
276
277 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
278 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
279} HAL_TX_QUEUE_FLAGS;
280
281typedef struct {
282 uint32_t tqi_ver; /* hal TXQ version */
283 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
284 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
285 uint32_t tqi_priority; /* (not used) */
286 uint32_t tqi_aifs; /* aifs */
287 uint32_t tqi_cwmin; /* cwMin */
288 uint32_t tqi_cwmax; /* cwMax */
289 uint16_t tqi_shretry; /* rts retry limit */
290 uint16_t tqi_lgretry; /* long retry limit (not used)*/
291 uint32_t tqi_cbrPeriod; /* CBR period (us) */
292 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
293 uint32_t tqi_burstTime; /* max burst duration (us) */
294 uint32_t tqi_readyTime; /* frame schedule time (us) */
295 uint32_t tqi_compBuf; /* comp buffer phys addr */
296} HAL_TXQ_INFO;
297
298#define HAL_TQI_NONVAL 0xffff
299
300/* token to use for aifs, cwmin, cwmax */
301#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
302
303/* compression definitions */
304#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
305#define HAL_COMP_BUF_ALIGN_SIZE 512
306
307/*
308 * Transmit packet types. This belongs in ah_desc.h, but
309 * is here so we can give a proper type to various parameters
310 * (and not require everyone include the file).
311 *
312 * NB: These values are intentionally assigned for
313 * direct use when setting up h/w descriptors.
314 */
315typedef enum {
316 HAL_PKT_TYPE_NORMAL = 0,
317 HAL_PKT_TYPE_ATIM = 1,
318 HAL_PKT_TYPE_PSPOLL = 2,
319 HAL_PKT_TYPE_BEACON = 3,
320 HAL_PKT_TYPE_PROBE_RESP = 4,
321 HAL_PKT_TYPE_CHIRP = 5,
322 HAL_PKT_TYPE_GRP_POLL = 6,
323 HAL_PKT_TYPE_AMPDU = 7,
324} HAL_PKT_TYPE;
325
326/* Rx Filter Frame Types */
327typedef enum {
328 /*
329 * These bits correspond to AR_RX_FILTER for all chips.
330 * Not all bits are supported by all chips.
331 */
332 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
333 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
334 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
335 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
336 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
337 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
338 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
339 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
340 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
341 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
342 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
343 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
344 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
345 /* Allow all mcast/bcast frames */
346
347 /*
348 * Magic RX filter flags that aren't targetting hardware bits
349 * but instead the HAL sets individual bits - eg PHYERR will result
350 * in OFDM/CCK timing error frames being received.
351 */
352 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
353} HAL_RX_FILTER;
354
355typedef enum {
356 HAL_PM_AWAKE = 0,
357 HAL_PM_FULL_SLEEP = 1,
358 HAL_PM_NETWORK_SLEEP = 2,
359 HAL_PM_UNDEFINED = 3
360} HAL_POWER_MODE;
361
362/*
363 * NOTE WELL:
364 * These are mapped to take advantage of the common locations for many of
365 * the bits on all of the currently supported MAC chips. This is to make
366 * the ISR as efficient as possible, while still abstracting HW differences.
367 * When new hardware breaks this commonality this enumerated type, as well
368 * as the HAL functions using it, must be modified. All values are directly
369 * mapped unless commented otherwise.
370 */
371typedef enum {
372 HAL_INT_RX = 0x00000001, /* Non-common mapping */
373 HAL_INT_RXDESC = 0x00000002,
374 HAL_INT_RXNOFRM = 0x00000008,
375 HAL_INT_RXEOL = 0x00000010,
376 HAL_INT_RXORN = 0x00000020,
377 HAL_INT_TX = 0x00000040, /* Non-common mapping */
378 HAL_INT_TXDESC = 0x00000080,
379 HAL_INT_TIM_TIMER= 0x00000100,
380 HAL_INT_TXURN = 0x00000800,
381 HAL_INT_MIB = 0x00001000,
382 HAL_INT_RXPHY = 0x00004000,
383 HAL_INT_RXKCM = 0x00008000,
384 HAL_INT_SWBA = 0x00010000,
385 HAL_INT_BMISS = 0x00040000,
386 HAL_INT_BNR = 0x00100000,
387 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
388 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
389 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
390 HAL_INT_GPIO = 0x01000000,
391 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
392 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
393 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
394 HAL_INT_CST = 0x10000000, /* Non-common mapping */
395 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
396 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
397#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
398 HAL_INT_BMISC = HAL_INT_TIM
399 | HAL_INT_DTIM
400 | HAL_INT_DTIMSYNC
401 | HAL_INT_CABEND
402 | HAL_INT_TBTT,
403
404 /* Interrupt bits that map directly to ISR/IMR bits */
405 HAL_INT_COMMON = HAL_INT_RXNOFRM
406 | HAL_INT_RXDESC
407 | HAL_INT_RXEOL
408 | HAL_INT_RXORN
409 | HAL_INT_TXDESC
410 | HAL_INT_TXURN
411 | HAL_INT_MIB
412 | HAL_INT_RXPHY
413 | HAL_INT_RXKCM
414 | HAL_INT_SWBA
415 | HAL_INT_BMISS
416 | HAL_INT_BNR
417 | HAL_INT_GPIO,
418} HAL_INT;
419
420typedef enum {
421 HAL_GPIO_MUX_OUTPUT = 0,
422 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
423 HAL_GPIO_MUX_PCIE_POWER_LED = 2,
424 HAL_GPIO_MUX_TX_FRAME = 3,
425 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
426 HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
427 HAL_GPIO_MUX_MAC_POWER_LED = 6
428} HAL_GPIO_MUX_TYPE;
429
430typedef enum {
431 HAL_GPIO_INTR_LOW = 0,
432 HAL_GPIO_INTR_HIGH = 1,
433 HAL_GPIO_INTR_DISABLE = 2
434} HAL_GPIO_INTR_TYPE;
435
436typedef enum {
437 HAL_RFGAIN_INACTIVE = 0,
438 HAL_RFGAIN_READ_REQUESTED = 1,
439 HAL_RFGAIN_NEED_CHANGE = 2
440} HAL_RFGAIN;
441
442typedef uint16_t HAL_CTRY_CODE; /* country code */
443typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
444
445#define HAL_ANTENNA_MIN_MODE 0
446#define HAL_ANTENNA_FIXED_A 1
447#define HAL_ANTENNA_FIXED_B 2
448#define HAL_ANTENNA_MAX_MODE 3
449
450typedef struct {
451 uint32_t ackrcv_bad;
452 uint32_t rts_bad;
453 uint32_t rts_good;
454 uint32_t fcs_bad;
455 uint32_t beacons;
456} HAL_MIB_STATS;
457
458enum {
459 HAL_MODE_11A = 0x001, /* 11a channels */
460 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
461 HAL_MODE_11B = 0x004, /* 11b channels */
462 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
463#ifdef notdef
464 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
465#else
466 HAL_MODE_11G = 0x008, /* XXX historical */
467#endif
468 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
469 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
470 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
471 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
472 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
473 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
474 HAL_MODE_11NG_HT20 = 0x008000,
475 HAL_MODE_11NA_HT20 = 0x010000,
476 HAL_MODE_11NG_HT40PLUS = 0x020000,
477 HAL_MODE_11NG_HT40MINUS = 0x040000,
478 HAL_MODE_11NA_HT40PLUS = 0x080000,
479 HAL_MODE_11NA_HT40MINUS = 0x100000,
480 HAL_MODE_ALL = 0xffffff
481};
482
483typedef struct {
484 int rateCount; /* NB: for proper padding */
485 uint8_t rateCodeToIndex[144]; /* back mapping */
486 struct {
487 uint8_t valid; /* valid for rate control use */
488 uint8_t phy; /* CCK/OFDM/XR */
489 uint32_t rateKbps; /* transfer rate in kbs */
490 uint8_t rateCode; /* rate for h/w descriptors */
491 uint8_t shortPreamble; /* mask for enabling short
492 * preamble in CCK rate code */
493 uint8_t dot11Rate; /* value for supported rates
494 * info element of MLME */
495 uint8_t controlRate; /* index of next lower basic
496 * rate; used for dur. calcs */
497 uint16_t lpAckDuration; /* long preamble ACK duration */
498 uint16_t spAckDuration; /* short preamble ACK duration*/
499 } info[32];
500} HAL_RATE_TABLE;
501
502typedef struct {
503 u_int rs_count; /* number of valid entries */
504 uint8_t rs_rates[32]; /* rates */
505} HAL_RATE_SET;
506
507/*
508 * 802.11n specific structures and enums
509 */
510typedef enum {
511 HAL_CHAINTYPE_TX = 1, /* Tx chain type */
512 HAL_CHAINTYPE_RX = 2, /* RX chain type */
513} HAL_CHAIN_TYPE;
514
515typedef struct {
516 u_int Tries;
517 u_int Rate;
518 u_int PktDuration;
519 u_int ChSel;
520 u_int RateFlags;
521#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
522#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
523#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
524} HAL_11N_RATE_SERIES;
525
526typedef enum {
527 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
528 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
529} HAL_HT_MACMODE;
530
531typedef enum {
532 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
533 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
534} HAL_HT_PHYMODE;
535
536typedef enum {
537 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
538 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
539} HAL_HT_EXTPROTSPACING;
540
541
542typedef enum {
543 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
544 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
545} HAL_HT_RXCLEAR;
546
547/*
548 * Antenna switch control. By default antenna selection
549 * enables multiple (2) antenna use. To force use of the
550 * A or B antenna only specify a fixed setting. Fixing
551 * the antenna will also disable any diversity support.
552 */
553typedef enum {
554 HAL_ANT_VARIABLE = 0, /* variable by programming */
555 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
556 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
557} HAL_ANT_SETTING;
558
559typedef enum {
560 HAL_M_STA = 1, /* infrastructure station */
561 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
562 HAL_M_HOSTAP = 6, /* Software Access Point */
563 HAL_M_MONITOR = 8 /* Monitor mode */
564} HAL_OPMODE;
565
566typedef struct {
567 uint8_t kv_type; /* one of HAL_CIPHER */
568 uint8_t kv_pad;
569 uint16_t kv_len; /* length in bits */
570 uint8_t kv_val[16]; /* enough for 128-bit keys */
571 uint8_t kv_mic[8]; /* TKIP MIC key */
572 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
573} HAL_KEYVAL;
574
575typedef enum {
576 HAL_CIPHER_WEP = 0,
577 HAL_CIPHER_AES_OCB = 1,
578 HAL_CIPHER_AES_CCM = 2,
579 HAL_CIPHER_CKIP = 3,
580 HAL_CIPHER_TKIP = 4,
581 HAL_CIPHER_CLR = 5, /* no encryption */
582
583 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
584} HAL_CIPHER;
585
586enum {
587 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
588 HAL_SLOT_TIME_9 = 9,
589 HAL_SLOT_TIME_20 = 20,
590};
591
592/*
593 * Per-station beacon timer state. Note that the specified
594 * beacon interval (given in TU's) can also include flags
595 * to force a TSF reset and to enable the beacon xmit logic.
596 * If bs_cfpmaxduration is non-zero the hardware is setup to
597 * coexist with a PCF-capable AP.
598 */
599typedef struct {
600 uint32_t bs_nexttbtt; /* next beacon in TU */
601 uint32_t bs_nextdtim; /* next DTIM in TU */
602 uint32_t bs_intval; /* beacon interval+flags */
603#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
604#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
605#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
606 uint32_t bs_dtimperiod;
607 uint16_t bs_cfpperiod; /* CFP period in TU */
608 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
609 uint32_t bs_cfpnext; /* next CFP in TU */
610 uint16_t bs_timoffset; /* byte offset to TIM bitmap */
611 uint16_t bs_bmissthreshold; /* beacon miss threshold */
612 uint32_t bs_sleepduration; /* max sleep duration */
613} HAL_BEACON_STATE;
614
615/*
616 * Like HAL_BEACON_STATE but for non-station mode setup.
617 * NB: see above flag definitions for bt_intval.
618 */
619typedef struct {
620 uint32_t bt_intval; /* beacon interval+flags */
621 uint32_t bt_nexttbtt; /* next beacon in TU */
622 uint32_t bt_nextatim; /* next ATIM in TU */
623 uint32_t bt_nextdba; /* next DBA in 1/8th TU */
624 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
625 uint32_t bt_flags; /* timer enables */
626#define HAL_BEACON_TBTT_EN 0x00000001
627#define HAL_BEACON_DBA_EN 0x00000002
628#define HAL_BEACON_SWBA_EN 0x00000004
629} HAL_BEACON_TIMERS;
630
631/*
632 * Per-node statistics maintained by the driver for use in
633 * optimizing signal quality and other operational aspects.
634 */
635typedef struct {
636 uint32_t ns_avgbrssi; /* average beacon rssi */
637 uint32_t ns_avgrssi; /* average data rssi */
638 uint32_t ns_avgtxrssi; /* average tx rssi */
639} HAL_NODE_STATS;
640
641#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
642
643struct ath_desc;
644struct ath_tx_status;
645struct ath_rx_status;
646struct ieee80211_channel;
647
648/*
649 * This is a channel survey sample entry.
650 *
651 * The AR5212 ANI routines fill these samples. The ANI code then uses it
652 * when calculating listen time; it is also exported via a diagnostic
653 * API.
654 */
655typedef struct {
656 uint32_t seq_num;
657 uint32_t tx_busy;
658 uint32_t rx_busy;
659 uint32_t chan_busy;
660 uint32_t cycle_count;
661} HAL_SURVEY_SAMPLE;
662
663/*
664 * This provides 3.2 seconds of sample space given an
665 * ANI time of 1/10th of a second. This may not be enough!
666 */
667#define CHANNEL_SURVEY_SAMPLE_COUNT 32
668
669typedef struct {
670 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT];
671 uint32_t cur_sample; /* current sample in sequence */
672 uint32_t cur_seq; /* current sequence number */
673} HAL_CHANNEL_SURVEY;
674
675/*
676 * ANI commands.
677 *
678 * These are used both internally and externally via the diagnostic
679 * API.
680 *
681 * Note that this is NOT the ANI commands being used via the INTMIT
682 * capability - that has a different mapping for some reason.
683 */
684typedef enum {
685 HAL_ANI_PRESENT = 0, /* is ANI support present */
686 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */
687 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */
688 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */
689 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */
690 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
691 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
692 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
693} HAL_ANI_CMD;
694
695/*
696 * This is the layout of the ANI INTMIT capability.
697 *
698 * Notice that the command values differ to HAL_ANI_CMD.
699 */
700typedef enum {
701 HAL_CAP_INTMIT_PRESENT = 0,
702 HAL_CAP_INTMIT_ENABLE = 1,
703 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2,
704 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3,
705 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4,
706 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5,
707 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
708} HAL_CAP_INTMIT_CMD;
709
710typedef struct {
711 int32_t pe_firpwr; /* FIR pwr out threshold */
712 int32_t pe_rrssi; /* Radar rssi thresh */
713 int32_t pe_height; /* Pulse height thresh */
714 int32_t pe_prssi; /* Pulse rssi thresh */
715 int32_t pe_inband; /* Inband thresh */
716
717 /* The following params are only for AR5413 and later */
718 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
719 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
720 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
721 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */
722 int32_t pe_blockradar; /*
723 * Enable to block radar check if pkt detect is done via OFDM
724 * weak signal detect or pkt is detected immediately after tx
725 * to rx transition
726 */
727 int32_t pe_enmaxrssi; /*
728 * Enable to use the max rssi instead of the last rssi during
729 * fine gain changes for radar detection
730 */
731 int32_t pe_extchannel; /* Enable DFS on ext channel */
732 int32_t pe_enabled; /* Whether radar detection is enabled */
733} HAL_PHYERR_PARAM;
734
735#define HAL_PHYERR_PARAM_NOVAL 65535
736#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
737
|
| 738/*
739 * DFS operating mode flags.
740 */
741typedef enum {
742 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
743 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
744 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
745 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
746} HAL_DFS_DOMAIN;
|
738
739/*
740 * Flag for setting QUIET period
741 */
742typedef enum {
743 HAL_QUIET_DISABLE = 0x0,
744 HAL_QUIET_ENABLE = 0x1,
745 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
746 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
747} HAL_QUIET_FLAG;
748
749#define HAL_DFS_EVENT_PRICH 0x0000001
750#define HAL_DFS_EVENT_EXTCH 0x0000002
751#define HAL_DFS_EVENT_EXTEARLY 0x0000004
752#define HAL_DFS_EVENT_ISDC 0x0000008
753
754struct hal_dfs_event {
755 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */
756 uint32_t re_ts; /* Original 15 bit recv timestamp */
757 uint8_t re_rssi; /* rssi of radar event */
758 uint8_t re_dur; /* duration of radar pulse */
759 uint32_t re_flags; /* Flags (see above) */
760};
761typedef struct hal_dfs_event HAL_DFS_EVENT;
762
763typedef struct
764{
765 int ah_debug; /* only used if AH_DEBUG is defined */
766 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */
767
768 /* NB: these are deprecated; they exist for now for compatibility */
769 int ah_dma_beacon_response_time;/* in TU's */
770 int ah_sw_beacon_response_time; /* in TU's */
771 int ah_additional_swba_backoff; /* in TU's */
772} HAL_OPS_CONFIG;
773
774/*
775 * Hardware Access Layer (HAL) API.
776 *
777 * Clients of the HAL call ath_hal_attach to obtain a reference to an
778 * ath_hal structure for use with the device. Hardware-related operations
779 * that follow must call back into the HAL through interface, supplying
780 * the reference as the first parameter. Note that before using the
781 * reference returned by ath_hal_attach the caller should verify the
782 * ABI version number.
783 */
784struct ath_hal {
785 uint32_t ah_magic; /* consistency check magic number */
786 uint16_t ah_devid; /* PCI device ID */
787 uint16_t ah_subvendorid; /* PCI subvendor ID */
788 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
789 HAL_BUS_TAG ah_st; /* params for register r+w */
790 HAL_BUS_HANDLE ah_sh;
791 HAL_CTRY_CODE ah_countryCode;
792
793 uint32_t ah_macVersion; /* MAC version id */
794 uint16_t ah_macRev; /* MAC revision */
795 uint16_t ah_phyRev; /* PHY revision */
796 /* NB: when only one radio is present the rev is in 5Ghz */
797 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
798 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
799
800 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
801
802 HAL_OPS_CONFIG ah_config;
803 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
804 u_int mode);
805 void __ahdecl(*ah_detach)(struct ath_hal*);
806
807 /* Reset functions */
808 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
809 struct ieee80211_channel *,
810 HAL_BOOL bChannelChange, HAL_STATUS *status);
811 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
812 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
813 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
814 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
815 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
816 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
817 struct ieee80211_channel *, HAL_BOOL *);
818 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
819 struct ieee80211_channel *, u_int chainMask,
820 HAL_BOOL longCal, HAL_BOOL *isCalDone);
821 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
822 const struct ieee80211_channel *);
823 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
824 const struct ieee80211_channel *, uint16_t *);
825 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
826 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
827 const struct ieee80211_channel *);
828
829 /* Transmit functions */
830 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
831 HAL_BOOL incTrigLevel);
832 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
833 const HAL_TXQ_INFO *qInfo);
834 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
835 const HAL_TXQ_INFO *qInfo);
836 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
837 HAL_TXQ_INFO *qInfo);
838 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
839 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
840 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
841 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
842 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
843 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
844 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
845 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
846 u_int pktLen, u_int hdrLen,
847 HAL_PKT_TYPE type, u_int txPower,
848 u_int txRate0, u_int txTries0,
849 u_int keyIx, u_int antMode, u_int flags,
850 u_int rtsctsRate, u_int rtsctsDuration,
851 u_int compicvLen, u_int compivLen,
852 u_int comp);
853 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
854 u_int txRate1, u_int txTries1,
855 u_int txRate2, u_int txTries2,
856 u_int txRate3, u_int txTries3);
857 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
858 u_int segLen, HAL_BOOL firstSeg,
859 HAL_BOOL lastSeg, const struct ath_desc *);
860 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
861 struct ath_desc *, struct ath_tx_status *);
862 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
863 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
864 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
865 const struct ath_desc *ds, int *rates, int *tries);
866
867 /* Receive Functions */
868 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
869 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
870 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
871 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
872 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
873 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
874 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
875 uint32_t filter0, uint32_t filter1);
876 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
877 uint32_t index);
878 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
879 uint32_t index);
880 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
881 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
882 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
883 uint32_t size, u_int flags);
884 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
885 struct ath_desc *, uint32_t phyAddr,
886 struct ath_desc *next, uint64_t tsf,
887 struct ath_rx_status *);
888 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
889 const HAL_NODE_STATS *,
890 const struct ieee80211_channel *);
891 void __ahdecl(*ah_aniPoll)(struct ath_hal *,
892 const struct ieee80211_channel *);
893 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
894 const HAL_NODE_STATS *);
895 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
896 struct ath_rx_status *,
897 unsigned long, int);
898
899 /* Misc Functions */
900 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
901 HAL_CAPABILITY_TYPE, uint32_t capability,
902 uint32_t *result);
903 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
904 HAL_CAPABILITY_TYPE, uint32_t capability,
905 uint32_t setting, HAL_STATUS *);
906 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
907 const void *args, uint32_t argsize,
908 void **result, uint32_t *resultsize);
909 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
910 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
911 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
912 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
913 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
914 uint16_t, HAL_STATUS *);
915 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
916 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
917 const uint8_t *bssid, uint16_t assocId);
918 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
919 uint32_t gpio, HAL_GPIO_MUX_TYPE);
920 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
921 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
922 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
923 uint32_t gpio, uint32_t val);
924 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
925 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
926 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
927 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
928 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
929 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
930 HAL_MIB_STATS*);
931 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
932 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
933 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
934 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
935 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
936 HAL_ANT_SETTING);
937 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
938 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
939 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
940 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
941 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
942 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
943 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
944 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
945 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
946 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
947 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
948 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
949 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
950 uint32_t duration, uint32_t nextStart,
951 HAL_QUIET_FLAG flag);
952
953 /* DFS functions */
954 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
955 HAL_PHYERR_PARAM *pe);
956 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
957 HAL_PHYERR_PARAM *pe);
958 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
959 struct ath_rx_status *rxs, uint64_t fulltsf,
960 const char *buf, HAL_DFS_EVENT *event);
961 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
962
963 /* Key Cache Functions */
964 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
965 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
966 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
967 uint16_t);
968 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
969 uint16_t, const HAL_KEYVAL *,
970 const uint8_t *, int);
971 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
972 uint16_t, const uint8_t *);
973
974 /* Power Management Functions */
975 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
976 HAL_POWER_MODE mode, int setChip);
977 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
978 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
979 const struct ieee80211_channel *);
980
981 /* Beacon Management Functions */
982 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
983 const HAL_BEACON_TIMERS *);
984 /* NB: deprecated, use ah_setBeaconTimers instead */
985 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
986 uint32_t nexttbtt, uint32_t intval);
987 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
988 const HAL_BEACON_STATE *);
989 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
990
991 /* 802.11n Functions */
992 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
993 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE,
994 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL,
995 HAL_BOOL);
996 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
997 struct ath_desc *, u_int, u_int, u_int,
998 u_int, u_int, u_int, u_int, u_int);
999 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *,
1000 struct ath_desc *, const struct ath_desc *);
1001 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
1002 struct ath_desc *, u_int, u_int,
1003 HAL_11N_RATE_SERIES [], u_int, u_int);
1004 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
1005 struct ath_desc *, u_int);
1006 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
1007 struct ath_desc *);
1008 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
1009 struct ath_desc *, u_int);
1010 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
1011 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
1012 HAL_HT_MACMODE);
1013 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);
1014 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *,
1015 HAL_HT_RXCLEAR);
1016
1017 /* Interrupt functions */
1018 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
1019 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
1020 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
1021 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
1022};
1023
1024/*
1025 * Check the PCI vendor ID and device ID against Atheros' values
1026 * and return a printable description for any Atheros hardware.
1027 * AH_NULL is returned if the ID's do not describe Atheros hardware.
1028 */
1029extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
1030
1031/*
1032 * Attach the HAL for use with the specified device. The device is
1033 * defined by the PCI device ID. The caller provides an opaque pointer
1034 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
1035 * HAL state block for later use. Hardware register accesses are done
1036 * using the specified bus tag and handle. On successful return a
1037 * reference to a state block is returned that must be supplied in all
1038 * subsequent HAL calls. Storage associated with this reference is
1039 * dynamically allocated and must be freed by calling the ah_detach
1040 * method when the client is done. If the attach operation fails a
1041 * null (AH_NULL) reference will be returned and a status code will
1042 * be returned if the status parameter is non-zero.
1043 */
1044extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
1045 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status);
1046
1047extern const char *ath_hal_mac_name(struct ath_hal *);
1048extern const char *ath_hal_rf_name(struct ath_hal *);
1049
1050/*
1051 * Regulatory interfaces. Drivers should use ath_hal_init_channels to
1052 * request a set of channels for a particular country code and/or
1053 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
1054 * this list is constructed according to the contents of the EEPROM.
1055 * ath_hal_getchannels acts similarly but does not alter the operating
1056 * state; this can be used to collect information for a particular
1057 * regulatory configuration. Finally ath_hal_set_channels installs a
1058 * channel list constructed outside the driver. The HAL will adopt the
1059 * channel list and setup internal state according to the specified
1060 * regulatory configuration (e.g. conformance test limits).
1061 *
1062 * For all interfaces the channel list is returned in the supplied array.
1063 * maxchans defines the maximum size of this array. nchans contains the
1064 * actual number of channels returned. If a problem occurred then a
1065 * status code != HAL_OK is returned.
1066 */
1067struct ieee80211_channel;
1068
1069/*
1070 * Return a list of channels according to the specified regulatory.
1071 */
1072extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
1073 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1074 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
1075 HAL_BOOL enableExtendedChannels);
1076
1077/*
1078 * Return a list of channels and install it as the current operating
1079 * regulatory list.
1080 */
1081extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
1082 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1083 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
1084 HAL_BOOL enableExtendedChannels);
1085
1086/*
1087 * Install the list of channels as the current operating regulatory
1088 * and setup related state according to the country code and sku.
1089 */
1090extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
1091 struct ieee80211_channel *chans, int nchans,
1092 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
1093
1094/*
1095 * Fetch the ctl/ext noise floor values reported by a MIMO
1096 * radio. Returns 1 for valid results, 0 for invalid channel.
1097 */
1098extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
1099 const struct ieee80211_channel *chan, int16_t *nf_ctl,
1100 int16_t *nf_ext);
1101
1102/*
1103 * Calibrate noise floor data following a channel scan or similar.
1104 * This must be called prior retrieving noise floor data.
1105 */
1106extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
1107
1108/*
1109 * Return bit mask of wireless modes supported by the hardware.
1110 */
1111extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
1112
1113/*
1114 * Calculate the packet TX time for a legacy or 11n frame
1115 */
1116extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,
1117 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1118 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble);
1119
1120/*
1121 * Calculate the duration of an 11n frame.
1122 */
1123extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate,
1124 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI);
1125
1126/*
1127 * Calculate the transmit duration of a legacy frame.
1128 */
1129extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
1130 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1131 uint16_t rateix, HAL_BOOL shortPreamble);
1132#endif /* _ATH_AH_H_ */
| 747
748/*
749 * Flag for setting QUIET period
750 */
751typedef enum {
752 HAL_QUIET_DISABLE = 0x0,
753 HAL_QUIET_ENABLE = 0x1,
754 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
755 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
756} HAL_QUIET_FLAG;
757
758#define HAL_DFS_EVENT_PRICH 0x0000001
759#define HAL_DFS_EVENT_EXTCH 0x0000002
760#define HAL_DFS_EVENT_EXTEARLY 0x0000004
761#define HAL_DFS_EVENT_ISDC 0x0000008
762
763struct hal_dfs_event {
764 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */
765 uint32_t re_ts; /* Original 15 bit recv timestamp */
766 uint8_t re_rssi; /* rssi of radar event */
767 uint8_t re_dur; /* duration of radar pulse */
768 uint32_t re_flags; /* Flags (see above) */
769};
770typedef struct hal_dfs_event HAL_DFS_EVENT;
771
772typedef struct
773{
774 int ah_debug; /* only used if AH_DEBUG is defined */
775 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */
776
777 /* NB: these are deprecated; they exist for now for compatibility */
778 int ah_dma_beacon_response_time;/* in TU's */
779 int ah_sw_beacon_response_time; /* in TU's */
780 int ah_additional_swba_backoff; /* in TU's */
781} HAL_OPS_CONFIG;
782
783/*
784 * Hardware Access Layer (HAL) API.
785 *
786 * Clients of the HAL call ath_hal_attach to obtain a reference to an
787 * ath_hal structure for use with the device. Hardware-related operations
788 * that follow must call back into the HAL through interface, supplying
789 * the reference as the first parameter. Note that before using the
790 * reference returned by ath_hal_attach the caller should verify the
791 * ABI version number.
792 */
793struct ath_hal {
794 uint32_t ah_magic; /* consistency check magic number */
795 uint16_t ah_devid; /* PCI device ID */
796 uint16_t ah_subvendorid; /* PCI subvendor ID */
797 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
798 HAL_BUS_TAG ah_st; /* params for register r+w */
799 HAL_BUS_HANDLE ah_sh;
800 HAL_CTRY_CODE ah_countryCode;
801
802 uint32_t ah_macVersion; /* MAC version id */
803 uint16_t ah_macRev; /* MAC revision */
804 uint16_t ah_phyRev; /* PHY revision */
805 /* NB: when only one radio is present the rev is in 5Ghz */
806 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
807 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
808
809 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
810
811 HAL_OPS_CONFIG ah_config;
812 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
813 u_int mode);
814 void __ahdecl(*ah_detach)(struct ath_hal*);
815
816 /* Reset functions */
817 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
818 struct ieee80211_channel *,
819 HAL_BOOL bChannelChange, HAL_STATUS *status);
820 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
821 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
822 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
823 void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
824 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
825 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
826 struct ieee80211_channel *, HAL_BOOL *);
827 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *,
828 struct ieee80211_channel *, u_int chainMask,
829 HAL_BOOL longCal, HAL_BOOL *isCalDone);
830 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
831 const struct ieee80211_channel *);
832 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
833 const struct ieee80211_channel *, uint16_t *);
834 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
835 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
836 const struct ieee80211_channel *);
837
838 /* Transmit functions */
839 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
840 HAL_BOOL incTrigLevel);
841 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
842 const HAL_TXQ_INFO *qInfo);
843 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
844 const HAL_TXQ_INFO *qInfo);
845 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
846 HAL_TXQ_INFO *qInfo);
847 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
848 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
849 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
850 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
851 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
852 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
853 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
854 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
855 u_int pktLen, u_int hdrLen,
856 HAL_PKT_TYPE type, u_int txPower,
857 u_int txRate0, u_int txTries0,
858 u_int keyIx, u_int antMode, u_int flags,
859 u_int rtsctsRate, u_int rtsctsDuration,
860 u_int compicvLen, u_int compivLen,
861 u_int comp);
862 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
863 u_int txRate1, u_int txTries1,
864 u_int txRate2, u_int txTries2,
865 u_int txRate3, u_int txTries3);
866 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
867 u_int segLen, HAL_BOOL firstSeg,
868 HAL_BOOL lastSeg, const struct ath_desc *);
869 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
870 struct ath_desc *, struct ath_tx_status *);
871 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
872 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
873 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
874 const struct ath_desc *ds, int *rates, int *tries);
875
876 /* Receive Functions */
877 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
878 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
879 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
880 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
881 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
882 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
883 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
884 uint32_t filter0, uint32_t filter1);
885 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
886 uint32_t index);
887 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
888 uint32_t index);
889 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
890 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
891 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
892 uint32_t size, u_int flags);
893 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
894 struct ath_desc *, uint32_t phyAddr,
895 struct ath_desc *next, uint64_t tsf,
896 struct ath_rx_status *);
897 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
898 const HAL_NODE_STATS *,
899 const struct ieee80211_channel *);
900 void __ahdecl(*ah_aniPoll)(struct ath_hal *,
901 const struct ieee80211_channel *);
902 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
903 const HAL_NODE_STATS *);
904 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
905 struct ath_rx_status *,
906 unsigned long, int);
907
908 /* Misc Functions */
909 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
910 HAL_CAPABILITY_TYPE, uint32_t capability,
911 uint32_t *result);
912 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
913 HAL_CAPABILITY_TYPE, uint32_t capability,
914 uint32_t setting, HAL_STATUS *);
915 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
916 const void *args, uint32_t argsize,
917 void **result, uint32_t *resultsize);
918 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
919 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
920 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
921 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
922 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
923 uint16_t, HAL_STATUS *);
924 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
925 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
926 const uint8_t *bssid, uint16_t assocId);
927 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *,
928 uint32_t gpio, HAL_GPIO_MUX_TYPE);
929 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
930 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
931 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
932 uint32_t gpio, uint32_t val);
933 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
934 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
935 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
936 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
937 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
938 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
939 HAL_MIB_STATS*);
940 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
941 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
942 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
943 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
944 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
945 HAL_ANT_SETTING);
946 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
947 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
948 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
949 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
950 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
951 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
952 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
953 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
954 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
955 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
956 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
957 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
958 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
959 uint32_t duration, uint32_t nextStart,
960 HAL_QUIET_FLAG flag);
961
962 /* DFS functions */
963 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
964 HAL_PHYERR_PARAM *pe);
965 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
966 HAL_PHYERR_PARAM *pe);
967 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
968 struct ath_rx_status *rxs, uint64_t fulltsf,
969 const char *buf, HAL_DFS_EVENT *event);
970 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
971
972 /* Key Cache Functions */
973 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
974 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
975 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
976 uint16_t);
977 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
978 uint16_t, const HAL_KEYVAL *,
979 const uint8_t *, int);
980 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
981 uint16_t, const uint8_t *);
982
983 /* Power Management Functions */
984 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
985 HAL_POWER_MODE mode, int setChip);
986 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
987 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *,
988 const struct ieee80211_channel *);
989
990 /* Beacon Management Functions */
991 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
992 const HAL_BEACON_TIMERS *);
993 /* NB: deprecated, use ah_setBeaconTimers instead */
994 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
995 uint32_t nexttbtt, uint32_t intval);
996 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
997 const HAL_BEACON_STATE *);
998 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
999
1000 /* 802.11n Functions */
1001 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
1002 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE,
1003 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL,
1004 HAL_BOOL);
1005 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
1006 struct ath_desc *, u_int, u_int, u_int,
1007 u_int, u_int, u_int, u_int, u_int);
1008 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *,
1009 struct ath_desc *, const struct ath_desc *);
1010 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
1011 struct ath_desc *, u_int, u_int,
1012 HAL_11N_RATE_SERIES [], u_int, u_int);
1013 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
1014 struct ath_desc *, u_int);
1015 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
1016 struct ath_desc *);
1017 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
1018 struct ath_desc *, u_int);
1019 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
1020 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
1021 HAL_HT_MACMODE);
1022 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah);
1023 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *,
1024 HAL_HT_RXCLEAR);
1025
1026 /* Interrupt functions */
1027 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
1028 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
1029 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
1030 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
1031};
1032
1033/*
1034 * Check the PCI vendor ID and device ID against Atheros' values
1035 * and return a printable description for any Atheros hardware.
1036 * AH_NULL is returned if the ID's do not describe Atheros hardware.
1037 */
1038extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
1039
1040/*
1041 * Attach the HAL for use with the specified device. The device is
1042 * defined by the PCI device ID. The caller provides an opaque pointer
1043 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
1044 * HAL state block for later use. Hardware register accesses are done
1045 * using the specified bus tag and handle. On successful return a
1046 * reference to a state block is returned that must be supplied in all
1047 * subsequent HAL calls. Storage associated with this reference is
1048 * dynamically allocated and must be freed by calling the ah_detach
1049 * method when the client is done. If the attach operation fails a
1050 * null (AH_NULL) reference will be returned and a status code will
1051 * be returned if the status parameter is non-zero.
1052 */
1053extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
1054 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status);
1055
1056extern const char *ath_hal_mac_name(struct ath_hal *);
1057extern const char *ath_hal_rf_name(struct ath_hal *);
1058
1059/*
1060 * Regulatory interfaces. Drivers should use ath_hal_init_channels to
1061 * request a set of channels for a particular country code and/or
1062 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then
1063 * this list is constructed according to the contents of the EEPROM.
1064 * ath_hal_getchannels acts similarly but does not alter the operating
1065 * state; this can be used to collect information for a particular
1066 * regulatory configuration. Finally ath_hal_set_channels installs a
1067 * channel list constructed outside the driver. The HAL will adopt the
1068 * channel list and setup internal state according to the specified
1069 * regulatory configuration (e.g. conformance test limits).
1070 *
1071 * For all interfaces the channel list is returned in the supplied array.
1072 * maxchans defines the maximum size of this array. nchans contains the
1073 * actual number of channels returned. If a problem occurred then a
1074 * status code != HAL_OK is returned.
1075 */
1076struct ieee80211_channel;
1077
1078/*
1079 * Return a list of channels according to the specified regulatory.
1080 */
1081extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *,
1082 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1083 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
1084 HAL_BOOL enableExtendedChannels);
1085
1086/*
1087 * Return a list of channels and install it as the current operating
1088 * regulatory list.
1089 */
1090extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *,
1091 struct ieee80211_channel *chans, u_int maxchans, int *nchans,
1092 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd,
1093 HAL_BOOL enableExtendedChannels);
1094
1095/*
1096 * Install the list of channels as the current operating regulatory
1097 * and setup related state according to the country code and sku.
1098 */
1099extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *,
1100 struct ieee80211_channel *chans, int nchans,
1101 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn);
1102
1103/*
1104 * Fetch the ctl/ext noise floor values reported by a MIMO
1105 * radio. Returns 1 for valid results, 0 for invalid channel.
1106 */
1107extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
1108 const struct ieee80211_channel *chan, int16_t *nf_ctl,
1109 int16_t *nf_ext);
1110
1111/*
1112 * Calibrate noise floor data following a channel scan or similar.
1113 * This must be called prior retrieving noise floor data.
1114 */
1115extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
1116
1117/*
1118 * Return bit mask of wireless modes supported by the hardware.
1119 */
1120extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
1121
1122/*
1123 * Calculate the packet TX time for a legacy or 11n frame
1124 */
1125extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah,
1126 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1127 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble);
1128
1129/*
1130 * Calculate the duration of an 11n frame.
1131 */
1132extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate,
1133 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI);
1134
1135/*
1136 * Calculate the transmit duration of a legacy frame.
1137 */
1138extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
1139 const HAL_RATE_TABLE *rates, uint32_t frameLen,
1140 uint16_t rateix, HAL_BOOL shortPreamble);
1141#endif /* _ATH_AH_H_ */
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