1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
30 */
31#include "opt_ah.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/sysctl.h>
38#include <sys/bus.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
41
42#include <machine/stdarg.h>
43
44#include <net/ethernet.h> /* XXX for ether_sprintf */
45
46#include <dev/ath/ath_hal/ah.h>
47
48/*
49 * WiSoC boards overload the bus tag with information about the
50 * board layout. We must extract the bus space tag from that
51 * indirect structure. For everyone else the tag is passed in
52 * directly.
53 * XXX cache indirect ref privately
54 */
55#ifdef AH_SUPPORT_AR5312
56#define BUSTAG(ah) \
57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58#else
59#define BUSTAG(ah) ((ah)->ah_st)
60#endif
61
62extern void ath_hal_printf(struct ath_hal *, const char*, ...)
63 __printflike(2,3);
64extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65 __printflike(2, 0);
66extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67extern void *ath_hal_malloc(size_t);
68extern void ath_hal_free(void *);
69#ifdef AH_ASSERT
70extern void ath_hal_assert_failed(const char* filename,
71 int lineno, const char* msg);
72#endif
73#ifdef AH_DEBUG
74extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
75#endif /* AH_DEBUG */
76
77/* NB: put this here instead of the driver to avoid circular references */
78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
80
81#ifdef AH_DEBUG
82int ath_hal_debug = 0;
83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84 0, "Atheros HAL debugging printfs");
85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
86#endif /* AH_DEBUG */
87
88int ath_hal_ar5416_biasadj = 0;
89SYSCTL_INT(_hw_ath_hal, OID_AUTO, ar5416_biasadj, CTLFLAG_RW,
| 30 */
31#include "opt_ah.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/sysctl.h>
38#include <sys/bus.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
41
42#include <machine/stdarg.h>
43
44#include <net/ethernet.h> /* XXX for ether_sprintf */
45
46#include <dev/ath/ath_hal/ah.h>
47
48/*
49 * WiSoC boards overload the bus tag with information about the
50 * board layout. We must extract the bus space tag from that
51 * indirect structure. For everyone else the tag is passed in
52 * directly.
53 * XXX cache indirect ref privately
54 */
55#ifdef AH_SUPPORT_AR5312
56#define BUSTAG(ah) \
57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58#else
59#define BUSTAG(ah) ((ah)->ah_st)
60#endif
61
62extern void ath_hal_printf(struct ath_hal *, const char*, ...)
63 __printflike(2,3);
64extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65 __printflike(2, 0);
66extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67extern void *ath_hal_malloc(size_t);
68extern void ath_hal_free(void *);
69#ifdef AH_ASSERT
70extern void ath_hal_assert_failed(const char* filename,
71 int lineno, const char* msg);
72#endif
73#ifdef AH_DEBUG
74extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
75#endif /* AH_DEBUG */
76
77/* NB: put this here instead of the driver to avoid circular references */
78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
80
81#ifdef AH_DEBUG
82int ath_hal_debug = 0;
83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84 0, "Atheros HAL debugging printfs");
85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
86#endif /* AH_DEBUG */
87
88int ath_hal_ar5416_biasadj = 0;
89SYSCTL_INT(_hw_ath_hal, OID_AUTO, ar5416_biasadj, CTLFLAG_RW,
|
91 " bias adjust");
92
93/* NB: these are deprecated; they exist for now for compatibility */
94int ath_hal_dma_beacon_response_time = 2; /* in TU's */
95SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
96 &ath_hal_dma_beacon_response_time, 0,
97 "Atheros HAL DMA beacon response time");
98int ath_hal_sw_beacon_response_time = 10; /* in TU's */
99SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
100 &ath_hal_sw_beacon_response_time, 0,
101 "Atheros HAL software beacon response time");
102int ath_hal_additional_swba_backoff = 0; /* in TU's */
103SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
104 &ath_hal_additional_swba_backoff, 0,
105 "Atheros HAL additional SWBA backoff time");
106
107MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
108
109void*
110ath_hal_malloc(size_t size)
111{
112 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
113}
114
115void
116ath_hal_free(void* p)
117{
118 free(p, M_ATH_HAL);
119}
120
121void
122ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
123{
124 vprintf(fmt, ap);
125}
126
127void
128ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
129{
130 va_list ap;
131 va_start(ap, fmt);
132 ath_hal_vprintf(ah, fmt, ap);
133 va_end(ap);
134}
135
136const char*
137ath_hal_ether_sprintf(const u_int8_t *mac)
138{
139 return ether_sprintf(mac);
140}
141
142#ifdef AH_DEBUG
143void
144DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
145{
146 if (ath_hal_debug & mask) {
147 __va_list ap;
148 va_start(ap, fmt);
149 ath_hal_vprintf(ah, fmt, ap);
150 va_end(ap);
151 }
152}
153#endif /* AH_DEBUG */
154
155#ifdef AH_DEBUG_ALQ
156/*
157 * ALQ register tracing support.
158 *
159 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
160 * writes to the file /tmp/ath_hal.log. The file format is a simple
161 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
162 * and then decode the file with the arcode program (that is part of the
163 * HAL). If you start+stop tracing the data will be appended to an
164 * existing file.
165 *
166 * NB: doesn't handle multiple devices properly; only one DEVICE record
167 * is emitted and the different devices are not identified.
168 */
169#include <sys/alq.h>
170#include <sys/pcpu.h>
171#include <dev/ath/ath_hal/ah_decode.h>
172
173static struct alq *ath_hal_alq;
174static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
175static u_int ath_hal_alq_lost; /* count of lost records */
176static const char *ath_hal_logfile = "/tmp/ath_hal.log";
177static u_int ath_hal_alq_qsize = 64*1024;
178
179static int
180ath_hal_setlogging(int enable)
181{
182 int error;
183
184 if (enable) {
185 error = alq_open(&ath_hal_alq, ath_hal_logfile,
186 curthread->td_ucred, ALQ_DEFAULT_CMODE,
187 sizeof (struct athregrec), ath_hal_alq_qsize);
188 ath_hal_alq_lost = 0;
189 ath_hal_alq_emitdev = 1;
190 printf("ath_hal: logging to %s enabled\n",
191 ath_hal_logfile);
192 } else {
193 if (ath_hal_alq)
194 alq_close(ath_hal_alq);
195 ath_hal_alq = NULL;
196 printf("ath_hal: logging disabled\n");
197 error = 0;
198 }
199 return (error);
200}
201
202static int
203sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
204{
205 int error, enable;
206
207 enable = (ath_hal_alq != NULL);
208 error = sysctl_handle_int(oidp, &enable, 0, req);
209 if (error || !req->newptr)
210 return (error);
211 else
212 return (ath_hal_setlogging(enable));
213}
214SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
215 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
216SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
217 &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
218SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
219 &ath_hal_alq_lost, 0, "Register operations not logged");
220
221static struct ale *
222ath_hal_alq_get(struct ath_hal *ah)
223{
224 struct ale *ale;
225
226 if (ath_hal_alq_emitdev) {
227 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
228 if (ale) {
229 struct athregrec *r =
230 (struct athregrec *) ale->ae_data;
231 r->op = OP_DEVICE;
232 r->reg = 0;
233 r->val = ah->ah_devid;
234 alq_post(ath_hal_alq, ale);
235 ath_hal_alq_emitdev = 0;
236 } else
237 ath_hal_alq_lost++;
238 }
239 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
240 if (!ale)
241 ath_hal_alq_lost++;
242 return ale;
243}
244
245void
246ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
247{
248 bus_space_tag_t tag = BUSTAG(ah);
249 bus_space_handle_t h = ah->ah_sh;
250
251 if (ath_hal_alq) {
252 struct ale *ale = ath_hal_alq_get(ah);
253 if (ale) {
254 struct athregrec *r = (struct athregrec *) ale->ae_data;
255 r->op = OP_WRITE;
256 r->reg = reg;
257 r->val = val;
258 alq_post(ath_hal_alq, ale);
259 }
260 }
261#if _BYTE_ORDER == _BIG_ENDIAN
262 if (OS_REG_UNSWAPPED(reg))
263 bus_space_write_4(tag, h, reg, val);
264 else
265#endif
266 bus_space_write_stream_4(tag, h, reg, val);
267}
268
269u_int32_t
270ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
271{
272 bus_space_tag_t tag = BUSTAG(ah);
273 bus_space_handle_t h = ah->ah_sh;
274 u_int32_t val;
275
276#if _BYTE_ORDER == _BIG_ENDIAN
277 if (OS_REG_UNSWAPPED(reg))
278 val = bus_space_read_4(tag, h, reg);
279 else
280#endif
281 val = bus_space_read_stream_4(tag, h, reg);
282 if (ath_hal_alq) {
283 struct ale *ale = ath_hal_alq_get(ah);
284 if (ale) {
285 struct athregrec *r = (struct athregrec *) ale->ae_data;
286 r->op = OP_READ;
287 r->reg = reg;
288 r->val = val;
289 alq_post(ath_hal_alq, ale);
290 }
291 }
292 return val;
293}
294
295void
296OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
297{
298 if (ath_hal_alq) {
299 struct ale *ale = ath_hal_alq_get(ah);
300 if (ale) {
301 struct athregrec *r = (struct athregrec *) ale->ae_data;
302 r->op = OP_MARK;
303 r->reg = id;
304 r->val = v;
305 alq_post(ath_hal_alq, ale);
306 }
307 }
308}
309#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
310/*
311 * Memory-mapped device register read/write. These are here
312 * as routines when debugging support is enabled and/or when
313 * explicitly configured to use function calls. The latter is
314 * for architectures that might need to do something before
315 * referencing memory (e.g. remap an i/o window).
316 *
317 * NB: see the comments in ah_osdep.h about byte-swapping register
318 * reads and writes to understand what's going on below.
319 */
320
321void
322ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
323{
324 bus_space_tag_t tag = BUSTAG(ah);
325 bus_space_handle_t h = ah->ah_sh;
326
327#if _BYTE_ORDER == _BIG_ENDIAN
328 if (OS_REG_UNSWAPPED(reg))
329 bus_space_write_4(tag, h, reg, val);
330 else
331#endif
332 bus_space_write_stream_4(tag, h, reg, val);
333}
334
335u_int32_t
336ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
337{
338 bus_space_tag_t tag = BUSTAG(ah);
339 bus_space_handle_t h = ah->ah_sh;
340 u_int32_t val;
341
342#if _BYTE_ORDER == _BIG_ENDIAN
343 if (OS_REG_UNSWAPPED(reg))
344 val = bus_space_read_4(tag, h, reg);
345 else
346#endif
347 val = bus_space_read_stream_4(tag, h, reg);
348 return val;
349}
350#endif /* AH_DEBUG || AH_REGOPS_FUNC */
351
352#ifdef AH_ASSERT
353void
354ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
355{
356 printf("Atheros HAL assertion failure: %s: line %u: %s\n",
357 filename, lineno, msg);
358 panic("ath_hal_assert");
359}
360#endif /* AH_ASSERT */
| 91 " bias adjust");
92
93/* NB: these are deprecated; they exist for now for compatibility */
94int ath_hal_dma_beacon_response_time = 2; /* in TU's */
95SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
96 &ath_hal_dma_beacon_response_time, 0,
97 "Atheros HAL DMA beacon response time");
98int ath_hal_sw_beacon_response_time = 10; /* in TU's */
99SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
100 &ath_hal_sw_beacon_response_time, 0,
101 "Atheros HAL software beacon response time");
102int ath_hal_additional_swba_backoff = 0; /* in TU's */
103SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
104 &ath_hal_additional_swba_backoff, 0,
105 "Atheros HAL additional SWBA backoff time");
106
107MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
108
109void*
110ath_hal_malloc(size_t size)
111{
112 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
113}
114
115void
116ath_hal_free(void* p)
117{
118 free(p, M_ATH_HAL);
119}
120
121void
122ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
123{
124 vprintf(fmt, ap);
125}
126
127void
128ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
129{
130 va_list ap;
131 va_start(ap, fmt);
132 ath_hal_vprintf(ah, fmt, ap);
133 va_end(ap);
134}
135
136const char*
137ath_hal_ether_sprintf(const u_int8_t *mac)
138{
139 return ether_sprintf(mac);
140}
141
142#ifdef AH_DEBUG
143void
144DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
145{
146 if (ath_hal_debug & mask) {
147 __va_list ap;
148 va_start(ap, fmt);
149 ath_hal_vprintf(ah, fmt, ap);
150 va_end(ap);
151 }
152}
153#endif /* AH_DEBUG */
154
155#ifdef AH_DEBUG_ALQ
156/*
157 * ALQ register tracing support.
158 *
159 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
160 * writes to the file /tmp/ath_hal.log. The file format is a simple
161 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
162 * and then decode the file with the arcode program (that is part of the
163 * HAL). If you start+stop tracing the data will be appended to an
164 * existing file.
165 *
166 * NB: doesn't handle multiple devices properly; only one DEVICE record
167 * is emitted and the different devices are not identified.
168 */
169#include <sys/alq.h>
170#include <sys/pcpu.h>
171#include <dev/ath/ath_hal/ah_decode.h>
172
173static struct alq *ath_hal_alq;
174static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
175static u_int ath_hal_alq_lost; /* count of lost records */
176static const char *ath_hal_logfile = "/tmp/ath_hal.log";
177static u_int ath_hal_alq_qsize = 64*1024;
178
179static int
180ath_hal_setlogging(int enable)
181{
182 int error;
183
184 if (enable) {
185 error = alq_open(&ath_hal_alq, ath_hal_logfile,
186 curthread->td_ucred, ALQ_DEFAULT_CMODE,
187 sizeof (struct athregrec), ath_hal_alq_qsize);
188 ath_hal_alq_lost = 0;
189 ath_hal_alq_emitdev = 1;
190 printf("ath_hal: logging to %s enabled\n",
191 ath_hal_logfile);
192 } else {
193 if (ath_hal_alq)
194 alq_close(ath_hal_alq);
195 ath_hal_alq = NULL;
196 printf("ath_hal: logging disabled\n");
197 error = 0;
198 }
199 return (error);
200}
201
202static int
203sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
204{
205 int error, enable;
206
207 enable = (ath_hal_alq != NULL);
208 error = sysctl_handle_int(oidp, &enable, 0, req);
209 if (error || !req->newptr)
210 return (error);
211 else
212 return (ath_hal_setlogging(enable));
213}
214SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
215 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
216SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
217 &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
218SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
219 &ath_hal_alq_lost, 0, "Register operations not logged");
220
221static struct ale *
222ath_hal_alq_get(struct ath_hal *ah)
223{
224 struct ale *ale;
225
226 if (ath_hal_alq_emitdev) {
227 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
228 if (ale) {
229 struct athregrec *r =
230 (struct athregrec *) ale->ae_data;
231 r->op = OP_DEVICE;
232 r->reg = 0;
233 r->val = ah->ah_devid;
234 alq_post(ath_hal_alq, ale);
235 ath_hal_alq_emitdev = 0;
236 } else
237 ath_hal_alq_lost++;
238 }
239 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
240 if (!ale)
241 ath_hal_alq_lost++;
242 return ale;
243}
244
245void
246ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
247{
248 bus_space_tag_t tag = BUSTAG(ah);
249 bus_space_handle_t h = ah->ah_sh;
250
251 if (ath_hal_alq) {
252 struct ale *ale = ath_hal_alq_get(ah);
253 if (ale) {
254 struct athregrec *r = (struct athregrec *) ale->ae_data;
255 r->op = OP_WRITE;
256 r->reg = reg;
257 r->val = val;
258 alq_post(ath_hal_alq, ale);
259 }
260 }
261#if _BYTE_ORDER == _BIG_ENDIAN
262 if (OS_REG_UNSWAPPED(reg))
263 bus_space_write_4(tag, h, reg, val);
264 else
265#endif
266 bus_space_write_stream_4(tag, h, reg, val);
267}
268
269u_int32_t
270ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
271{
272 bus_space_tag_t tag = BUSTAG(ah);
273 bus_space_handle_t h = ah->ah_sh;
274 u_int32_t val;
275
276#if _BYTE_ORDER == _BIG_ENDIAN
277 if (OS_REG_UNSWAPPED(reg))
278 val = bus_space_read_4(tag, h, reg);
279 else
280#endif
281 val = bus_space_read_stream_4(tag, h, reg);
282 if (ath_hal_alq) {
283 struct ale *ale = ath_hal_alq_get(ah);
284 if (ale) {
285 struct athregrec *r = (struct athregrec *) ale->ae_data;
286 r->op = OP_READ;
287 r->reg = reg;
288 r->val = val;
289 alq_post(ath_hal_alq, ale);
290 }
291 }
292 return val;
293}
294
295void
296OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
297{
298 if (ath_hal_alq) {
299 struct ale *ale = ath_hal_alq_get(ah);
300 if (ale) {
301 struct athregrec *r = (struct athregrec *) ale->ae_data;
302 r->op = OP_MARK;
303 r->reg = id;
304 r->val = v;
305 alq_post(ath_hal_alq, ale);
306 }
307 }
308}
309#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
310/*
311 * Memory-mapped device register read/write. These are here
312 * as routines when debugging support is enabled and/or when
313 * explicitly configured to use function calls. The latter is
314 * for architectures that might need to do something before
315 * referencing memory (e.g. remap an i/o window).
316 *
317 * NB: see the comments in ah_osdep.h about byte-swapping register
318 * reads and writes to understand what's going on below.
319 */
320
321void
322ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
323{
324 bus_space_tag_t tag = BUSTAG(ah);
325 bus_space_handle_t h = ah->ah_sh;
326
327#if _BYTE_ORDER == _BIG_ENDIAN
328 if (OS_REG_UNSWAPPED(reg))
329 bus_space_write_4(tag, h, reg, val);
330 else
331#endif
332 bus_space_write_stream_4(tag, h, reg, val);
333}
334
335u_int32_t
336ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
337{
338 bus_space_tag_t tag = BUSTAG(ah);
339 bus_space_handle_t h = ah->ah_sh;
340 u_int32_t val;
341
342#if _BYTE_ORDER == _BIG_ENDIAN
343 if (OS_REG_UNSWAPPED(reg))
344 val = bus_space_read_4(tag, h, reg);
345 else
346#endif
347 val = bus_space_read_stream_4(tag, h, reg);
348 return val;
349}
350#endif /* AH_DEBUG || AH_REGOPS_FUNC */
351
352#ifdef AH_ASSERT
353void
354ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
355{
356 printf("Atheros HAL assertion failure: %s: line %u: %s\n",
357 filename, lineno, msg);
358 panic("ath_hal_assert");
359}
360#endif /* AH_ASSERT */
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