1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
| 1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
|
30 */
31#include "opt_ah.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/sysctl.h>
38#include <sys/bus.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
41
42#include <machine/stdarg.h>
43
44#include <net/ethernet.h> /* XXX for ether_sprintf */
45
46#include <dev/ath/ath_hal/ah.h>
47
48/*
49 * WiSoC boards overload the bus tag with information about the
50 * board layout. We must extract the bus space tag from that
51 * indirect structure. For everyone else the tag is passed in
52 * directly.
53 * XXX cache indirect ref privately
54 */
55#ifdef AH_SUPPORT_AR5312
56#define BUSTAG(ah) \
57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58#else
59#define BUSTAG(ah) ((ah)->ah_st)
60#endif
61
62extern void ath_hal_printf(struct ath_hal *, const char*, ...)
63 __printflike(2,3);
64extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65 __printflike(2, 0);
66extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67extern void *ath_hal_malloc(size_t);
68extern void ath_hal_free(void *);
69#ifdef AH_ASSERT
70extern void ath_hal_assert_failed(const char* filename,
71 int lineno, const char* msg);
72#endif
73#ifdef AH_DEBUG
74extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
75#endif /* AH_DEBUG */
76
77/* NB: put this here instead of the driver to avoid circular references */
78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
80
81#ifdef AH_DEBUG
82static int ath_hal_debug = 0;
83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84 0, "Atheros HAL debugging printfs");
85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
86#endif /* AH_DEBUG */
87
88/* NB: these are deprecated; they exist for now for compatibility */
89int ath_hal_dma_beacon_response_time = 2; /* in TU's */
90SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
91 &ath_hal_dma_beacon_response_time, 0,
92 "Atheros HAL DMA beacon response time");
93int ath_hal_sw_beacon_response_time = 10; /* in TU's */
94SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
95 &ath_hal_sw_beacon_response_time, 0,
96 "Atheros HAL software beacon response time");
97int ath_hal_additional_swba_backoff = 0; /* in TU's */
98SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
99 &ath_hal_additional_swba_backoff, 0,
100 "Atheros HAL additional SWBA backoff time");
101
102MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
103
104void*
105ath_hal_malloc(size_t size)
106{
107 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
108}
109
110void
111ath_hal_free(void* p)
112{
| 30 */
31#include "opt_ah.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/sysctl.h>
38#include <sys/bus.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
41
42#include <machine/stdarg.h>
43
44#include <net/ethernet.h> /* XXX for ether_sprintf */
45
46#include <dev/ath/ath_hal/ah.h>
47
48/*
49 * WiSoC boards overload the bus tag with information about the
50 * board layout. We must extract the bus space tag from that
51 * indirect structure. For everyone else the tag is passed in
52 * directly.
53 * XXX cache indirect ref privately
54 */
55#ifdef AH_SUPPORT_AR5312
56#define BUSTAG(ah) \
57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
58#else
59#define BUSTAG(ah) ((ah)->ah_st)
60#endif
61
62extern void ath_hal_printf(struct ath_hal *, const char*, ...)
63 __printflike(2,3);
64extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
65 __printflike(2, 0);
66extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67extern void *ath_hal_malloc(size_t);
68extern void ath_hal_free(void *);
69#ifdef AH_ASSERT
70extern void ath_hal_assert_failed(const char* filename,
71 int lineno, const char* msg);
72#endif
73#ifdef AH_DEBUG
74extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
75#endif /* AH_DEBUG */
76
77/* NB: put this here instead of the driver to avoid circular references */
78SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
80
81#ifdef AH_DEBUG
82static int ath_hal_debug = 0;
83SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84 0, "Atheros HAL debugging printfs");
85TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
86#endif /* AH_DEBUG */
87
88/* NB: these are deprecated; they exist for now for compatibility */
89int ath_hal_dma_beacon_response_time = 2; /* in TU's */
90SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
91 &ath_hal_dma_beacon_response_time, 0,
92 "Atheros HAL DMA beacon response time");
93int ath_hal_sw_beacon_response_time = 10; /* in TU's */
94SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
95 &ath_hal_sw_beacon_response_time, 0,
96 "Atheros HAL software beacon response time");
97int ath_hal_additional_swba_backoff = 0; /* in TU's */
98SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
99 &ath_hal_additional_swba_backoff, 0,
100 "Atheros HAL additional SWBA backoff time");
101
102MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
103
104void*
105ath_hal_malloc(size_t size)
106{
107 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
108}
109
110void
111ath_hal_free(void* p)
112{
|
114}
115
116void
117ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
118{
119 vprintf(fmt, ap);
120}
121
122void
123ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
124{
125 va_list ap;
126 va_start(ap, fmt);
127 ath_hal_vprintf(ah, fmt, ap);
128 va_end(ap);
129}
130
131const char*
132ath_hal_ether_sprintf(const u_int8_t *mac)
133{
134 return ether_sprintf(mac);
135}
136
137#ifdef AH_DEBUG
138void
139HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
140{
141 if (ath_hal_debug & mask) {
142 __va_list ap;
143 va_start(ap, fmt);
144 ath_hal_vprintf(ah, fmt, ap);
145 va_end(ap);
146 }
147}
148#endif /* AH_DEBUG */
149
150#ifdef AH_DEBUG_ALQ
151/*
152 * ALQ register tracing support.
153 *
154 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
155 * writes to the file /tmp/ath_hal.log. The file format is a simple
156 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
157 * and then decode the file with the arcode program (that is part of the
158 * HAL). If you start+stop tracing the data will be appended to an
159 * existing file.
160 *
161 * NB: doesn't handle multiple devices properly; only one DEVICE record
162 * is emitted and the different devices are not identified.
163 */
164#include <sys/alq.h>
165#include <sys/pcpu.h>
166#include <dev/ath/ath_hal/ah_decode.h>
167
168static struct alq *ath_hal_alq;
169static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
170static u_int ath_hal_alq_lost; /* count of lost records */
171static const char *ath_hal_logfile = "/tmp/ath_hal.log";
172static u_int ath_hal_alq_qsize = 64*1024;
173
174static int
175ath_hal_setlogging(int enable)
176{
177 int error;
178
179 if (enable) {
180 error = alq_open(&ath_hal_alq, ath_hal_logfile,
181 curthread->td_ucred, ALQ_DEFAULT_CMODE,
182 sizeof (struct athregrec), ath_hal_alq_qsize);
183 ath_hal_alq_lost = 0;
184 ath_hal_alq_emitdev = 1;
185 printf("ath_hal: logging to %s enabled\n",
186 ath_hal_logfile);
187 } else {
188 if (ath_hal_alq)
189 alq_close(ath_hal_alq);
190 ath_hal_alq = NULL;
191 printf("ath_hal: logging disabled\n");
192 error = 0;
193 }
194 return (error);
195}
196
197static int
198sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
199{
200 int error, enable;
201
202 enable = (ath_hal_alq != NULL);
203 error = sysctl_handle_int(oidp, &enable, 0, req);
204 if (error || !req->newptr)
205 return (error);
206 else
207 return (ath_hal_setlogging(enable));
208}
209SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
210 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
211SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
212 &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
213SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
214 &ath_hal_alq_lost, 0, "Register operations not logged");
215
216static struct ale *
217ath_hal_alq_get(struct ath_hal *ah)
218{
219 struct ale *ale;
220
221 if (ath_hal_alq_emitdev) {
222 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
223 if (ale) {
224 struct athregrec *r =
225 (struct athregrec *) ale->ae_data;
226 r->op = OP_DEVICE;
227 r->reg = 0;
228 r->val = ah->ah_devid;
229 alq_post(ath_hal_alq, ale);
230 ath_hal_alq_emitdev = 0;
231 } else
232 ath_hal_alq_lost++;
233 }
234 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
235 if (!ale)
236 ath_hal_alq_lost++;
237 return ale;
238}
239
240void
241ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
242{
243 bus_space_tag_t tag = BUSTAG(ah);
244 bus_space_handle_t h = ah->ah_sh;
245
246 if (ath_hal_alq) {
247 struct ale *ale = ath_hal_alq_get(ah);
248 if (ale) {
249 struct athregrec *r = (struct athregrec *) ale->ae_data;
250 r->op = OP_WRITE;
251 r->reg = reg;
252 r->val = val;
253 alq_post(ath_hal_alq, ale);
254 }
255 }
256#if _BYTE_ORDER == _BIG_ENDIAN
257 if (OS_REG_UNSWAPPED(reg))
258 bus_space_write_4(tag, h, reg, val);
259 else
260#endif
261 bus_space_write_stream_4(tag, h, reg, val);
262}
263
264u_int32_t
265ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
266{
267 bus_space_tag_t tag = BUSTAG(ah);
268 bus_space_handle_t h = ah->ah_sh;
269 u_int32_t val;
270
271#if _BYTE_ORDER == _BIG_ENDIAN
272 if (OS_REG_UNSWAPPED(reg))
273 val = bus_space_read_4(tag, h, reg);
274 else
275#endif
276 val = bus_space_read_stream_4(tag, h, reg);
277 if (ath_hal_alq) {
278 struct ale *ale = ath_hal_alq_get(ah);
279 if (ale) {
280 struct athregrec *r = (struct athregrec *) ale->ae_data;
281 r->op = OP_READ;
282 r->reg = reg;
283 r->val = val;
284 alq_post(ath_hal_alq, ale);
285 }
286 }
287 return val;
288}
289
290void
291OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
292{
293 if (ath_hal_alq) {
294 struct ale *ale = ath_hal_alq_get(ah);
295 if (ale) {
296 struct athregrec *r = (struct athregrec *) ale->ae_data;
297 r->op = OP_MARK;
298 r->reg = id;
299 r->val = v;
300 alq_post(ath_hal_alq, ale);
301 }
302 }
303}
304#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
305/*
306 * Memory-mapped device register read/write. These are here
307 * as routines when debugging support is enabled and/or when
308 * explicitly configured to use function calls. The latter is
309 * for architectures that might need to do something before
310 * referencing memory (e.g. remap an i/o window).
311 *
312 * NB: see the comments in ah_osdep.h about byte-swapping register
313 * reads and writes to understand what's going on below.
314 */
315
316void
317ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
318{
319 bus_space_tag_t tag = BUSTAG(ah);
320 bus_space_handle_t h = ah->ah_sh;
321
322#if _BYTE_ORDER == _BIG_ENDIAN
323 if (OS_REG_UNSWAPPED(reg))
324 bus_space_write_4(tag, h, reg, val);
325 else
326#endif
327 bus_space_write_stream_4(tag, h, reg, val);
328}
329
330u_int32_t
331ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
332{
333 bus_space_tag_t tag = BUSTAG(ah);
334 bus_space_handle_t h = ah->ah_sh;
335 u_int32_t val;
336
337#if _BYTE_ORDER == _BIG_ENDIAN
338 if (OS_REG_UNSWAPPED(reg))
339 val = bus_space_read_4(tag, h, reg);
340 else
341#endif
342 val = bus_space_read_stream_4(tag, h, reg);
343 return val;
344}
345#endif /* AH_DEBUG || AH_REGOPS_FUNC */
346
347#ifdef AH_ASSERT
348void
349ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
350{
351 printf("Atheros HAL assertion failure: %s: line %u: %s\n",
352 filename, lineno, msg);
353 panic("ath_hal_assert");
354}
355#endif /* AH_ASSERT */
| 114}
115
116void
117ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
118{
119 vprintf(fmt, ap);
120}
121
122void
123ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
124{
125 va_list ap;
126 va_start(ap, fmt);
127 ath_hal_vprintf(ah, fmt, ap);
128 va_end(ap);
129}
130
131const char*
132ath_hal_ether_sprintf(const u_int8_t *mac)
133{
134 return ether_sprintf(mac);
135}
136
137#ifdef AH_DEBUG
138void
139HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
140{
141 if (ath_hal_debug & mask) {
142 __va_list ap;
143 va_start(ap, fmt);
144 ath_hal_vprintf(ah, fmt, ap);
145 va_end(ap);
146 }
147}
148#endif /* AH_DEBUG */
149
150#ifdef AH_DEBUG_ALQ
151/*
152 * ALQ register tracing support.
153 *
154 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
155 * writes to the file /tmp/ath_hal.log. The file format is a simple
156 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
157 * and then decode the file with the arcode program (that is part of the
158 * HAL). If you start+stop tracing the data will be appended to an
159 * existing file.
160 *
161 * NB: doesn't handle multiple devices properly; only one DEVICE record
162 * is emitted and the different devices are not identified.
163 */
164#include <sys/alq.h>
165#include <sys/pcpu.h>
166#include <dev/ath/ath_hal/ah_decode.h>
167
168static struct alq *ath_hal_alq;
169static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
170static u_int ath_hal_alq_lost; /* count of lost records */
171static const char *ath_hal_logfile = "/tmp/ath_hal.log";
172static u_int ath_hal_alq_qsize = 64*1024;
173
174static int
175ath_hal_setlogging(int enable)
176{
177 int error;
178
179 if (enable) {
180 error = alq_open(&ath_hal_alq, ath_hal_logfile,
181 curthread->td_ucred, ALQ_DEFAULT_CMODE,
182 sizeof (struct athregrec), ath_hal_alq_qsize);
183 ath_hal_alq_lost = 0;
184 ath_hal_alq_emitdev = 1;
185 printf("ath_hal: logging to %s enabled\n",
186 ath_hal_logfile);
187 } else {
188 if (ath_hal_alq)
189 alq_close(ath_hal_alq);
190 ath_hal_alq = NULL;
191 printf("ath_hal: logging disabled\n");
192 error = 0;
193 }
194 return (error);
195}
196
197static int
198sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
199{
200 int error, enable;
201
202 enable = (ath_hal_alq != NULL);
203 error = sysctl_handle_int(oidp, &enable, 0, req);
204 if (error || !req->newptr)
205 return (error);
206 else
207 return (ath_hal_setlogging(enable));
208}
209SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
210 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
211SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
212 &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
213SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
214 &ath_hal_alq_lost, 0, "Register operations not logged");
215
216static struct ale *
217ath_hal_alq_get(struct ath_hal *ah)
218{
219 struct ale *ale;
220
221 if (ath_hal_alq_emitdev) {
222 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
223 if (ale) {
224 struct athregrec *r =
225 (struct athregrec *) ale->ae_data;
226 r->op = OP_DEVICE;
227 r->reg = 0;
228 r->val = ah->ah_devid;
229 alq_post(ath_hal_alq, ale);
230 ath_hal_alq_emitdev = 0;
231 } else
232 ath_hal_alq_lost++;
233 }
234 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
235 if (!ale)
236 ath_hal_alq_lost++;
237 return ale;
238}
239
240void
241ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
242{
243 bus_space_tag_t tag = BUSTAG(ah);
244 bus_space_handle_t h = ah->ah_sh;
245
246 if (ath_hal_alq) {
247 struct ale *ale = ath_hal_alq_get(ah);
248 if (ale) {
249 struct athregrec *r = (struct athregrec *) ale->ae_data;
250 r->op = OP_WRITE;
251 r->reg = reg;
252 r->val = val;
253 alq_post(ath_hal_alq, ale);
254 }
255 }
256#if _BYTE_ORDER == _BIG_ENDIAN
257 if (OS_REG_UNSWAPPED(reg))
258 bus_space_write_4(tag, h, reg, val);
259 else
260#endif
261 bus_space_write_stream_4(tag, h, reg, val);
262}
263
264u_int32_t
265ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
266{
267 bus_space_tag_t tag = BUSTAG(ah);
268 bus_space_handle_t h = ah->ah_sh;
269 u_int32_t val;
270
271#if _BYTE_ORDER == _BIG_ENDIAN
272 if (OS_REG_UNSWAPPED(reg))
273 val = bus_space_read_4(tag, h, reg);
274 else
275#endif
276 val = bus_space_read_stream_4(tag, h, reg);
277 if (ath_hal_alq) {
278 struct ale *ale = ath_hal_alq_get(ah);
279 if (ale) {
280 struct athregrec *r = (struct athregrec *) ale->ae_data;
281 r->op = OP_READ;
282 r->reg = reg;
283 r->val = val;
284 alq_post(ath_hal_alq, ale);
285 }
286 }
287 return val;
288}
289
290void
291OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
292{
293 if (ath_hal_alq) {
294 struct ale *ale = ath_hal_alq_get(ah);
295 if (ale) {
296 struct athregrec *r = (struct athregrec *) ale->ae_data;
297 r->op = OP_MARK;
298 r->reg = id;
299 r->val = v;
300 alq_post(ath_hal_alq, ale);
301 }
302 }
303}
304#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
305/*
306 * Memory-mapped device register read/write. These are here
307 * as routines when debugging support is enabled and/or when
308 * explicitly configured to use function calls. The latter is
309 * for architectures that might need to do something before
310 * referencing memory (e.g. remap an i/o window).
311 *
312 * NB: see the comments in ah_osdep.h about byte-swapping register
313 * reads and writes to understand what's going on below.
314 */
315
316void
317ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
318{
319 bus_space_tag_t tag = BUSTAG(ah);
320 bus_space_handle_t h = ah->ah_sh;
321
322#if _BYTE_ORDER == _BIG_ENDIAN
323 if (OS_REG_UNSWAPPED(reg))
324 bus_space_write_4(tag, h, reg, val);
325 else
326#endif
327 bus_space_write_stream_4(tag, h, reg, val);
328}
329
330u_int32_t
331ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
332{
333 bus_space_tag_t tag = BUSTAG(ah);
334 bus_space_handle_t h = ah->ah_sh;
335 u_int32_t val;
336
337#if _BYTE_ORDER == _BIG_ENDIAN
338 if (OS_REG_UNSWAPPED(reg))
339 val = bus_space_read_4(tag, h, reg);
340 else
341#endif
342 val = bus_space_read_stream_4(tag, h, reg);
343 return val;
344}
345#endif /* AH_DEBUG || AH_REGOPS_FUNC */
346
347#ifdef AH_ASSERT
348void
349ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
350{
351 printf("Atheros HAL assertion failure: %s: line %u: %s\n",
352 filename, lineno, msg);
353 panic("ath_hal_assert");
354}
355#endif /* AH_ASSERT */
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