1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 230627 2012-01-27 21:52:59Z marius $");
| 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-siliconimage.c 233282 2012-03-21 16:59:39Z marius $");
|
29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
57static int ata_cmd_setmode(device_t dev, int target, int mode);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
62static int ata_sii_setmode(device_t dev, int target, int mode);
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71static void ata_siiprb_reset(device_t dev);
72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73static void ata_siiprb_dmainit(device_t dev);
74
75/* misc defines */
76#define SII_MEMIO 1
77#define SII_PRBIO 2
78#define SII_INTR 0x01
79#define SII_SETCLK 0x02
80#define SII_BUG 0x04
81#define SII_4CH 0x08
82
83/*
84 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
85 */
86static int
87ata_sii_probe(device_t dev)
88{
89 struct ata_pci_controller *ctlr = device_get_softc(dev);
| 29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
57static int ata_cmd_setmode(device_t dev, int target, int mode);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
62static int ata_sii_setmode(device_t dev, int target, int mode);
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71static void ata_siiprb_reset(device_t dev);
72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73static void ata_siiprb_dmainit(device_t dev);
74
75/* misc defines */
76#define SII_MEMIO 1
77#define SII_PRBIO 2
78#define SII_INTR 0x01
79#define SII_SETCLK 0x02
80#define SII_BUG 0x04
81#define SII_4CH 0x08
82
83/*
84 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
85 */
86static int
87ata_sii_probe(device_t dev)
88{
89 struct ata_pci_controller *ctlr = device_get_softc(dev);
|
90 static struct ata_chip_id ids[] =
| 90 static const struct ata_chip_id const ids[] =
|
91 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
92 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
93 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
94 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
96 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
97 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
99 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
100 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
107 { 0, 0, 0, 0, 0, 0}};
108
109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
110 return ENXIO;
111
112 if (!(ctlr->chip = ata_match_chip(dev, ids)))
113 return ENXIO;
114
115 ata_set_desc(dev);
116 ctlr->chipinit = ata_sii_chipinit;
117 return (BUS_PROBE_DEFAULT);
118}
119
120int
121ata_sii_chipinit(device_t dev)
122{
123 struct ata_pci_controller *ctlr = device_get_softc(dev);
124
125 if (ata_setup_interrupt(dev, ata_generic_intr))
126 return ENXIO;
127
128 switch (ctlr->chip->cfg1) {
129 case SII_PRBIO:
130 ctlr->r_type1 = SYS_RES_MEMORY;
131 ctlr->r_rid1 = PCIR_BAR(0);
132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
133 &ctlr->r_rid1, RF_ACTIVE)))
134 return ENXIO;
135
136 ctlr->r_rid2 = PCIR_BAR(2);
137 ctlr->r_type2 = SYS_RES_MEMORY;
138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
139 &ctlr->r_rid2, RF_ACTIVE))){
140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
141 return ENXIO;
142 }
143#ifdef __sparc64__
144 if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
145 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
146 BUS_SPACE_MAP_LINEAR, NULL)) {
147 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
148 ctlr->r_res1);
149 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
150 ctlr->r_res2);
151 return (ENXIO);
152 }
153#endif
154 ctlr->ch_attach = ata_siiprb_ch_attach;
155 ctlr->ch_detach = ata_siiprb_ch_detach;
156 ctlr->reset = ata_siiprb_reset;
157 ctlr->setmode = ata_sata_setmode;
158 ctlr->getrev = ata_sata_getrev;
159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
160
161 /* reset controller */
162 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
163 DELAY(10000);
164 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
165 break;
166
167 case SII_MEMIO:
168 ctlr->r_type2 = SYS_RES_MEMORY;
169 ctlr->r_rid2 = PCIR_BAR(5);
170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
171 &ctlr->r_rid2, RF_ACTIVE))){
172 if (ctlr->chip->chipid != ATA_SII0680 ||
173 (pci_read_config(dev, 0x8a, 1) & 1))
174 return ENXIO;
175 }
176
177 if (ctlr->chip->cfg2 & SII_SETCLK) {
178 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
179 pci_write_config(dev, 0x8a,
180 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
181 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
182 device_printf(dev, "%s could not set ATA133 clock\n",
183 ctlr->chip->text);
184 }
185
186 /* if we have 4 channels enable the second set */
187 if (ctlr->chip->cfg2 & SII_4CH) {
188 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
189 ctlr->channels = 4;
190 }
191
192 /* dont block interrupts from any channel */
193 pci_write_config(dev, 0x48,
194 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
195
196 /* enable PCI interrupt as BIOS might not */
197 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
198
199 if (ctlr->r_res2) {
200 ctlr->ch_attach = ata_sii_ch_attach;
201 ctlr->ch_detach = ata_sii_ch_detach;
202 }
203
204 if (ctlr->chip->max_dma >= ATA_SA150) {
205 ctlr->reset = ata_sii_reset;
206 ctlr->setmode = ata_sata_setmode;
207 ctlr->getrev = ata_sata_getrev;
208 }
209 else
210 ctlr->setmode = ata_sii_setmode;
211 break;
212
213 default:
214 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
215 device_printf(dev, "HW has secondary channel disabled\n");
216 ctlr->channels = 1;
217 }
218
219 /* enable interrupt as BIOS might not */
220 pci_write_config(dev, 0x71, 0x01, 1);
221
222 ctlr->ch_attach = ata_cmd_ch_attach;
223 ctlr->ch_detach = ata_pci_ch_detach;
224 ctlr->setmode = ata_cmd_setmode;
225 break;
226 }
227 return 0;
228}
229
230static int
231ata_cmd_ch_attach(device_t dev)
232{
233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
234 struct ata_channel *ch = device_get_softc(dev);
235
236 /* setup the usual register normal pci style */
237 if (ata_pci_ch_attach(dev))
238 return ENXIO;
239
240 if (ctlr->chip->cfg2 & SII_INTR)
241 ch->hw.status = ata_cmd_status;
242
243#ifdef ATA_CAM
244 ch->flags |= ATA_NO_ATAPI_DMA;
245#endif
246
247 return 0;
248}
249
250static int
251ata_cmd_status(device_t dev)
252{
253 struct ata_channel *ch = device_get_softc(dev);
254 u_int8_t reg71;
255
256 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
257 (ch->unit ? 0x08 : 0x04))) {
258 pci_write_config(device_get_parent(dev), 0x71,
259 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
260 return ata_pci_status(dev);
261 }
262 return 0;
263}
264
265static int
266ata_cmd_setmode(device_t dev, int target, int mode)
267{
268 device_t parent = device_get_parent(dev);
269 struct ata_pci_controller *ctlr = device_get_softc(parent);
270 struct ata_channel *ch = device_get_softc(dev);
271 int devno = (ch->unit << 1) + target;
272 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
273 int ureg = ch->unit ? 0x7b : 0x73;
274 int piomode;
| 91 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
92 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
93 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
94 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
96 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
97 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
99 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
100 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
103 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
104 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
105 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
106 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
107 { 0, 0, 0, 0, 0, 0}};
108
109 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
110 return ENXIO;
111
112 if (!(ctlr->chip = ata_match_chip(dev, ids)))
113 return ENXIO;
114
115 ata_set_desc(dev);
116 ctlr->chipinit = ata_sii_chipinit;
117 return (BUS_PROBE_DEFAULT);
118}
119
120int
121ata_sii_chipinit(device_t dev)
122{
123 struct ata_pci_controller *ctlr = device_get_softc(dev);
124
125 if (ata_setup_interrupt(dev, ata_generic_intr))
126 return ENXIO;
127
128 switch (ctlr->chip->cfg1) {
129 case SII_PRBIO:
130 ctlr->r_type1 = SYS_RES_MEMORY;
131 ctlr->r_rid1 = PCIR_BAR(0);
132 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
133 &ctlr->r_rid1, RF_ACTIVE)))
134 return ENXIO;
135
136 ctlr->r_rid2 = PCIR_BAR(2);
137 ctlr->r_type2 = SYS_RES_MEMORY;
138 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
139 &ctlr->r_rid2, RF_ACTIVE))){
140 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
141 return ENXIO;
142 }
143#ifdef __sparc64__
144 if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
145 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
146 BUS_SPACE_MAP_LINEAR, NULL)) {
147 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
148 ctlr->r_res1);
149 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
150 ctlr->r_res2);
151 return (ENXIO);
152 }
153#endif
154 ctlr->ch_attach = ata_siiprb_ch_attach;
155 ctlr->ch_detach = ata_siiprb_ch_detach;
156 ctlr->reset = ata_siiprb_reset;
157 ctlr->setmode = ata_sata_setmode;
158 ctlr->getrev = ata_sata_getrev;
159 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
160
161 /* reset controller */
162 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
163 DELAY(10000);
164 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
165 break;
166
167 case SII_MEMIO:
168 ctlr->r_type2 = SYS_RES_MEMORY;
169 ctlr->r_rid2 = PCIR_BAR(5);
170 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
171 &ctlr->r_rid2, RF_ACTIVE))){
172 if (ctlr->chip->chipid != ATA_SII0680 ||
173 (pci_read_config(dev, 0x8a, 1) & 1))
174 return ENXIO;
175 }
176
177 if (ctlr->chip->cfg2 & SII_SETCLK) {
178 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
179 pci_write_config(dev, 0x8a,
180 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
181 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
182 device_printf(dev, "%s could not set ATA133 clock\n",
183 ctlr->chip->text);
184 }
185
186 /* if we have 4 channels enable the second set */
187 if (ctlr->chip->cfg2 & SII_4CH) {
188 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
189 ctlr->channels = 4;
190 }
191
192 /* dont block interrupts from any channel */
193 pci_write_config(dev, 0x48,
194 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
195
196 /* enable PCI interrupt as BIOS might not */
197 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
198
199 if (ctlr->r_res2) {
200 ctlr->ch_attach = ata_sii_ch_attach;
201 ctlr->ch_detach = ata_sii_ch_detach;
202 }
203
204 if (ctlr->chip->max_dma >= ATA_SA150) {
205 ctlr->reset = ata_sii_reset;
206 ctlr->setmode = ata_sata_setmode;
207 ctlr->getrev = ata_sata_getrev;
208 }
209 else
210 ctlr->setmode = ata_sii_setmode;
211 break;
212
213 default:
214 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
215 device_printf(dev, "HW has secondary channel disabled\n");
216 ctlr->channels = 1;
217 }
218
219 /* enable interrupt as BIOS might not */
220 pci_write_config(dev, 0x71, 0x01, 1);
221
222 ctlr->ch_attach = ata_cmd_ch_attach;
223 ctlr->ch_detach = ata_pci_ch_detach;
224 ctlr->setmode = ata_cmd_setmode;
225 break;
226 }
227 return 0;
228}
229
230static int
231ata_cmd_ch_attach(device_t dev)
232{
233 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
234 struct ata_channel *ch = device_get_softc(dev);
235
236 /* setup the usual register normal pci style */
237 if (ata_pci_ch_attach(dev))
238 return ENXIO;
239
240 if (ctlr->chip->cfg2 & SII_INTR)
241 ch->hw.status = ata_cmd_status;
242
243#ifdef ATA_CAM
244 ch->flags |= ATA_NO_ATAPI_DMA;
245#endif
246
247 return 0;
248}
249
250static int
251ata_cmd_status(device_t dev)
252{
253 struct ata_channel *ch = device_get_softc(dev);
254 u_int8_t reg71;
255
256 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
257 (ch->unit ? 0x08 : 0x04))) {
258 pci_write_config(device_get_parent(dev), 0x71,
259 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
260 return ata_pci_status(dev);
261 }
262 return 0;
263}
264
265static int
266ata_cmd_setmode(device_t dev, int target, int mode)
267{
268 device_t parent = device_get_parent(dev);
269 struct ata_pci_controller *ctlr = device_get_softc(parent);
270 struct ata_channel *ch = device_get_softc(dev);
271 int devno = (ch->unit << 1) + target;
272 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
273 int ureg = ch->unit ? 0x7b : 0x73;
274 int piomode;
|
275 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
276 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
277 { 0x11, 0x42 }, { 0x25, 0x8a },
278 { 0x15, 0x4a }, { 0x05, 0x0a } };
| 275 static const uint8_t piotimings[] =
276 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
277 static const uint8_t udmatimings[][2] =
278 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
279 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
|
279
280 mode = min(mode, ctlr->chip->max_dma);
281 if (mode >= ATA_UDMA0) {
282 u_int8_t umode = pci_read_config(parent, ureg, 1);
283
284 umode &= ~(target == 0 ? 0x35 : 0xca);
285 umode |= udmatimings[mode & ATA_MODE_MASK][target];
286 pci_write_config(parent, ureg, umode, 1);
287 piomode = ATA_PIO4;
288 } else {
289 pci_write_config(parent, ureg,
290 pci_read_config(parent, ureg, 1) &
291 ~(target == 0 ? 0x35 : 0xca), 1);
292 piomode = mode;
293 }
294 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
295 return (mode);
296}
297
298static int
299ata_sii_ch_attach(device_t dev)
300{
301 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
302 struct ata_channel *ch = device_get_softc(dev);
303 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
304 int i;
305
306 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
307 ch->r_io[i].res = ctlr->r_res2;
308 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
309 }
310 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
311 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
312 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
313 ata_default_registers(dev);
314
315 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
316 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
317 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
318 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
319 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
320 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
321
322 if (ctlr->chip->max_dma >= ATA_SA150) {
323 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
324 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
325 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
326 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
327 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
328 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
329 ch->flags |= ATA_NO_SLAVE;
330 ch->flags |= ATA_SATA;
331 ch->flags |= ATA_KNOWN_PRESENCE;
332
333 /* enable PHY state change interrupt */
334 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
335 }
336
337 if (ctlr->chip->cfg2 & SII_BUG) {
338 /* work around errata in early chips */
339 ch->dma.boundary = 8192;
340 ch->dma.segsize = 15 * DEV_BSIZE;
341 }
342
343 ata_pci_hw(dev);
344 ch->hw.status = ata_sii_status;
345 if (ctlr->chip->cfg2 & SII_SETCLK)
346 ch->flags |= ATA_CHECKS_CABLE;
347
348 ata_pci_dmainit(dev);
349
350 return 0;
351}
352
353static int
354ata_sii_ch_detach(device_t dev)
355{
356
357 ata_pci_dmafini(dev);
358 return (0);
359}
360
361static int
362ata_sii_status(device_t dev)
363{
364 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
365 struct ata_channel *ch = device_get_softc(dev);
366 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
367 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
368
369 /* do we have any PHY events ? */
370 if (ctlr->chip->max_dma >= ATA_SA150 &&
371 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
372 ata_sata_phy_check_events(dev, -1);
373
374 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
375 return ata_pci_status(dev);
376 else
377 return 0;
378}
379
380static void
381ata_sii_reset(device_t dev)
382{
383 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
384 struct ata_channel *ch = device_get_softc(dev);
385 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
386 uint32_t val;
387
388 /* Apply R_ERR on DMA activate FIS errata workaround. */
389 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
390 if ((val & 0x3) == 0x1)
391 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
392
393 if (ata_sata_phy_reset(dev, -1, 1))
394 ata_generic_reset(dev);
395 else
396 ch->devices = 0;
397}
398
399static int
400ata_sii_setmode(device_t dev, int target, int mode)
401{
402 device_t parent = device_get_parent(dev);
403 struct ata_pci_controller *ctlr = device_get_softc(parent);
404 struct ata_channel *ch = device_get_softc(dev);
405 int rego = (ch->unit << 4) + (target << 1);
406 int mreg = ch->unit ? 0x84 : 0x80;
407 int mask = 0x03 << (target << 2);
408 int mval = pci_read_config(parent, mreg, 1) & ~mask;
409 int piomode;
410 u_int8_t preg = 0xa4 + rego;
411 u_int8_t dreg = 0xa8 + rego;
412 u_int8_t ureg = 0xac + rego;
| 280
281 mode = min(mode, ctlr->chip->max_dma);
282 if (mode >= ATA_UDMA0) {
283 u_int8_t umode = pci_read_config(parent, ureg, 1);
284
285 umode &= ~(target == 0 ? 0x35 : 0xca);
286 umode |= udmatimings[mode & ATA_MODE_MASK][target];
287 pci_write_config(parent, ureg, umode, 1);
288 piomode = ATA_PIO4;
289 } else {
290 pci_write_config(parent, ureg,
291 pci_read_config(parent, ureg, 1) &
292 ~(target == 0 ? 0x35 : 0xca), 1);
293 piomode = mode;
294 }
295 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
296 return (mode);
297}
298
299static int
300ata_sii_ch_attach(device_t dev)
301{
302 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
303 struct ata_channel *ch = device_get_softc(dev);
304 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
305 int i;
306
307 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
308 ch->r_io[i].res = ctlr->r_res2;
309 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
310 }
311 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
312 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
313 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
314 ata_default_registers(dev);
315
316 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
317 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
318 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
319 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
320 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
321 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
322
323 if (ctlr->chip->max_dma >= ATA_SA150) {
324 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
325 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
326 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
327 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
328 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
329 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
330 ch->flags |= ATA_NO_SLAVE;
331 ch->flags |= ATA_SATA;
332 ch->flags |= ATA_KNOWN_PRESENCE;
333
334 /* enable PHY state change interrupt */
335 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
336 }
337
338 if (ctlr->chip->cfg2 & SII_BUG) {
339 /* work around errata in early chips */
340 ch->dma.boundary = 8192;
341 ch->dma.segsize = 15 * DEV_BSIZE;
342 }
343
344 ata_pci_hw(dev);
345 ch->hw.status = ata_sii_status;
346 if (ctlr->chip->cfg2 & SII_SETCLK)
347 ch->flags |= ATA_CHECKS_CABLE;
348
349 ata_pci_dmainit(dev);
350
351 return 0;
352}
353
354static int
355ata_sii_ch_detach(device_t dev)
356{
357
358 ata_pci_dmafini(dev);
359 return (0);
360}
361
362static int
363ata_sii_status(device_t dev)
364{
365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
366 struct ata_channel *ch = device_get_softc(dev);
367 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
368 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
369
370 /* do we have any PHY events ? */
371 if (ctlr->chip->max_dma >= ATA_SA150 &&
372 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
373 ata_sata_phy_check_events(dev, -1);
374
375 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
376 return ata_pci_status(dev);
377 else
378 return 0;
379}
380
381static void
382ata_sii_reset(device_t dev)
383{
384 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
385 struct ata_channel *ch = device_get_softc(dev);
386 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
387 uint32_t val;
388
389 /* Apply R_ERR on DMA activate FIS errata workaround. */
390 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
391 if ((val & 0x3) == 0x1)
392 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
393
394 if (ata_sata_phy_reset(dev, -1, 1))
395 ata_generic_reset(dev);
396 else
397 ch->devices = 0;
398}
399
400static int
401ata_sii_setmode(device_t dev, int target, int mode)
402{
403 device_t parent = device_get_parent(dev);
404 struct ata_pci_controller *ctlr = device_get_softc(parent);
405 struct ata_channel *ch = device_get_softc(dev);
406 int rego = (ch->unit << 4) + (target << 1);
407 int mreg = ch->unit ? 0x84 : 0x80;
408 int mask = 0x03 << (target << 2);
409 int mval = pci_read_config(parent, mreg, 1) & ~mask;
410 int piomode;
411 u_int8_t preg = 0xa4 + rego;
412 u_int8_t dreg = 0xa8 + rego;
413 u_int8_t ureg = 0xac + rego;
|
413 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
414 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
415 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
| 414 static const uint16_t piotimings[] =
415 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
416 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
417 static const uint8_t udmatimings[] =
418 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
|
416
417 mode = min(mode, ctlr->chip->max_dma);
418
419 if (ctlr->chip->cfg2 & SII_SETCLK) {
420 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
421 (pci_read_config(parent, 0x79, 1) &
422 (ch->unit ? 0x02 : 0x01))) {
423 ata_print_cable(dev, "controller");
424 mode = ATA_UDMA2;
425 }
426 }
427 if (mode >= ATA_UDMA0) {
428 pci_write_config(parent, mreg,
429 mval | (0x03 << (target << 2)), 1);
430 pci_write_config(parent, ureg,
431 (pci_read_config(parent, ureg, 1) & ~0x3f) |
432 udmatimings[mode & ATA_MODE_MASK], 1);
433 piomode = ATA_PIO4;
434 } else if (mode >= ATA_WDMA0) {
435 pci_write_config(parent, mreg,
436 mval | (0x02 << (target << 2)), 1);
437 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
438 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
439 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
440 } else {
441 pci_write_config(parent, mreg,
442 mval | (0x01 << (target << 2)), 1);
443 piomode = mode;
444 }
445 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
446 return (mode);
447}
448
449struct ata_siiprb_dma_prdentry {
450 u_int64_t addr;
451 u_int32_t count;
452 u_int32_t control;
453} __packed;
454
455#define ATA_SIIPRB_DMA_ENTRIES 129
456struct ata_siiprb_ata_command {
457 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
458} __packed;
459
460struct ata_siiprb_atapi_command {
461 u_int8_t ccb[16];
462 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
463} __packed;
464
465struct ata_siiprb_command {
466 u_int16_t control;
467 u_int16_t protocol_override;
468 u_int32_t transfer_count;
469 u_int8_t fis[24];
470 union {
471 struct ata_siiprb_ata_command ata;
472 struct ata_siiprb_atapi_command atapi;
473 } u;
474} __packed;
475
476static int
477ata_siiprb_ch_attach(device_t dev)
478{
479 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
480 struct ata_channel *ch = device_get_softc(dev);
481 int offset = ch->unit * 0x2000;
482
483 ata_siiprb_dmainit(dev);
484
485 /* set the SATA resources */
486 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
487 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
488 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
489 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
490 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
491 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
492 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
493 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
494
495 ch->hw.status = ata_siiprb_status;
496 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
497 ch->hw.end_transaction = ata_siiprb_end_transaction;
498 ch->hw.command = NULL; /* not used here */
499 ch->hw.softreset = ata_siiprb_softreset;
500 ch->hw.pm_read = ata_siiprb_pm_read;
501 ch->hw.pm_write = ata_siiprb_pm_write;
502 ch->flags |= ATA_NO_SLAVE;
503 ch->flags |= ATA_SATA;
504 return 0;
505}
506
507static int
508ata_siiprb_ch_detach(device_t dev)
509{
510 struct ata_channel *ch = device_get_softc(dev);
511
512 if (ch->dma.work_tag && ch->dma.work_map)
513 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
514 BUS_DMASYNC_POSTWRITE);
515 ata_dmafini(dev);
516 return 0;
517}
518
519static int
520ata_siiprb_status(device_t dev)
521{
522 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
523 struct ata_channel *ch = device_get_softc(dev);
524 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
525 int offset = ch->unit * 0x2000;
526
527 if (action & (1 << ch->unit)) {
528 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
529
530 /* do we have any PHY events ? */
531 ata_sata_phy_check_events(dev, -1);
532
533 /* clear interrupt(s) */
534 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
535
536 /* do we have any device action ? */
537 return (istatus & 0x00000003);
538 }
539 return 0;
540}
541
542static int
543ata_siiprb_begin_transaction(struct ata_request *request)
544{
545 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
546 struct ata_channel *ch = device_get_softc(request->parent);
547 struct ata_siiprb_command *prb;
548 struct ata_siiprb_dma_prdentry *prd;
549 int offset = ch->unit * 0x2000;
550 u_int64_t prb_bus;
551
552 /* SOS XXX */
553 if (request->u.ata.command == ATA_DEVICE_RESET) {
554 request->result = 0;
555 return ATA_OP_FINISHED;
556 }
557
558 /* get a piece of the workspace for this request */
559 prb = (struct ata_siiprb_command *)ch->dma.work;
560
561 /* clear the prb structure */
562 bzero(prb, sizeof(struct ata_siiprb_command));
563
564 /* setup the FIS for this request */
565 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
566 device_printf(request->parent, "setting up SATA FIS failed\n");
567 request->result = EIO;
568 return ATA_OP_FINISHED;
569 }
570
571 /* setup transfer type */
572 if (request->flags & ATA_R_ATAPI) {
573 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
574 if (request->flags & ATA_R_ATAPI16)
575 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
576 else
577 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
578 if (request->flags & ATA_R_READ)
579 prb->control = htole16(0x0010);
580 if (request->flags & ATA_R_WRITE)
581 prb->control = htole16(0x0020);
582 prd = &prb->u.atapi.prd[0];
583 }
584 else
585 prd = &prb->u.ata.prd[0];
586
587 /* if request moves data setup and load SG list */
588 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
589 if (ch->dma.load(request, prd, NULL)) {
590 device_printf(request->parent, "setting up DMA failed\n");
591 request->result = EIO;
592 return ATA_OP_FINISHED;
593 }
594 }
595
596 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
597
598 /* activate the prb */
599 prb_bus = ch->dma.work_bus;
600 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
601 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
602
603 /* start the timeout */
604 callout_reset(&request->callout, request->timeout * hz,
605 (timeout_t*)ata_timeout, request);
606 return ATA_OP_CONTINUES;
607}
608
609static int
610ata_siiprb_end_transaction(struct ata_request *request)
611{
612 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
613 struct ata_channel *ch = device_get_softc(request->parent);
614 struct ata_siiprb_command *prb;
615 int offset = ch->unit * 0x2000;
616 int error, timeout;
617
618 /* kill the timeout */
619 callout_stop(&request->callout);
620
621 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
622
623 prb = (struct ata_siiprb_command *)
624 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
625
626 /* any controller errors flagged ? */
627 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
628 if (bootverbose)
629 printf("ata_siiprb_end_transaction %s error=%08x\n",
630 ata_cmd2str(request), error);
631
632 /* if device error status get details */
633 if (error == 1 || error == 2) {
634 request->status = prb->fis[2];
635 if (request->status & ATA_S_ERROR)
636 request->error = prb->fis[3];
637 }
638
639 /* SOS XXX handle other controller errors here */
640
641 /* initialize port */
642 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
643
644 /* poll for port ready */
645 for (timeout = 0; timeout < 1000; timeout++) {
646 DELAY(1000);
647 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
648 break;
649 }
650 if (bootverbose) {
651 if (timeout >= 1000)
652 device_printf(ch->dev, "port initialize timeout\n");
653 else
654 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
655 }
656 }
657
658 /* on control commands read back registers to the request struct */
659 if (request->flags & ATA_R_CONTROL) {
660 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
661 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
662 ((u_int64_t)prb->fis[6] << 16);
663 if (request->flags & ATA_R_48BIT)
664 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
665 ((u_int64_t)prb->fis[9] << 32) |
666 ((u_int64_t)prb->fis[10] << 40);
667 else
668 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
669 }
670
671 /* update progress */
672 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
673 if (request->flags & ATA_R_READ)
674 request->donecount = le32toh(prb->transfer_count);
675 else
676 request->donecount = request->bytecount;
677 }
678
679 /* release SG list etc */
680 ch->dma.unload(request);
681
682 return ATA_OP_FINISHED;
683}
684
685static int
686ata_siiprb_issue_cmd(device_t dev)
687{
688 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
689 struct ata_channel *ch = device_get_softc(dev);
690 u_int64_t prb_bus = ch->dma.work_bus;
691 u_int32_t status;
692 int offset = ch->unit * 0x2000;
693 int timeout;
694
695 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
696
697 /* issue command to chip */
698 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
699 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
700
701 /* poll for command finished */
702 for (timeout = 0; timeout < 10000; timeout++) {
703 DELAY(1000);
704 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
705 break;
706 }
707
708 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
709
710 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
711 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
712
713 if (timeout >= 1000)
714 return EIO;
715
716 if (bootverbose)
717 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
718 timeout, status);
719 return 0;
720}
721
722static int
723ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
724{
725 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
726 struct ata_channel *ch = device_get_softc(dev);
727 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
728 int offset = ch->unit * 0x2000;
729
730 if (port < 0) {
731 *result = ATA_IDX_INL(ch, reg);
732 return (0);
733 }
734 if (port < ATA_PM) {
735 switch (reg) {
736 case ATA_SSTATUS:
737 reg = 0;
738 break;
739 case ATA_SERROR:
740 reg = 1;
741 break;
742 case ATA_SCONTROL:
743 reg = 2;
744 break;
745 default:
746 return (EINVAL);
747 }
748 }
749 bzero(prb, sizeof(struct ata_siiprb_command));
750 prb->fis[0] = 0x27; /* host to device */
751 prb->fis[1] = 0x8f; /* command FIS to PM port */
752 prb->fis[2] = ATA_READ_PM;
753 prb->fis[3] = reg;
754 prb->fis[7] = port;
755 if (ata_siiprb_issue_cmd(dev)) {
756 device_printf(dev, "error reading PM port\n");
757 return EIO;
758 }
759 prb = (struct ata_siiprb_command *)
760 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
761 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
762 return 0;
763}
764
765static int
766ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
767{
768 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
769 struct ata_channel *ch = device_get_softc(dev);
770 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
771 int offset = ch->unit * 0x2000;
772
773 if (port < 0) {
774 ATA_IDX_OUTL(ch, reg, value);
775 return (0);
776 }
777 if (port < ATA_PM) {
778 switch (reg) {
779 case ATA_SSTATUS:
780 reg = 0;
781 break;
782 case ATA_SERROR:
783 reg = 1;
784 break;
785 case ATA_SCONTROL:
786 reg = 2;
787 break;
788 default:
789 return (EINVAL);
790 }
791 }
792 bzero(prb, sizeof(struct ata_siiprb_command));
793 prb->fis[0] = 0x27; /* host to device */
794 prb->fis[1] = 0x8f; /* command FIS to PM port */
795 prb->fis[2] = ATA_WRITE_PM;
796 prb->fis[3] = reg;
797 prb->fis[7] = port;
798 prb->fis[12] = value & 0xff;
799 prb->fis[4] = (value >> 8) & 0xff;
800 prb->fis[5] = (value >> 16) & 0xff;
801 prb->fis[6] = (value >> 24) & 0xff;
802 if (ata_siiprb_issue_cmd(dev)) {
803 device_printf(dev, "error writing PM port\n");
804 return ATA_E_ABORT;
805 }
806 prb = (struct ata_siiprb_command *)
807 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
808 return prb->fis[3];
809}
810
811static u_int32_t
812ata_siiprb_softreset(device_t dev, int port)
813{
814 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
815 struct ata_channel *ch = device_get_softc(dev);
816 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
817 u_int32_t signature;
818 int offset = ch->unit * 0x2000;
819
820 /* setup the workspace for a soft reset command */
821 bzero(prb, sizeof(struct ata_siiprb_command));
822 prb->control = htole16(0x0080);
823 prb->fis[1] = port & 0x0f;
824
825 /* issue soft reset */
826 if (ata_siiprb_issue_cmd(dev))
827 return -1;
828
829 ata_udelay(150000);
830
831 /* get possible signature */
832 prb = (struct ata_siiprb_command *)
833 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
834 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
835
836 /* clear error bits/interrupt */
837 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
838
839 return signature;
840}
841
842static void
843ata_siiprb_reset(device_t dev)
844{
845 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
846 struct ata_channel *ch = device_get_softc(dev);
847 int offset = ch->unit * 0x2000;
848 u_int32_t status, signature;
849 int timeout;
850
851 /* disable interrupts */
852 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
853
854 /* reset channel HW */
855 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
856 DELAY(1000);
857 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
858 DELAY(10000);
859
860 /* poll for channel ready */
861 for (timeout = 0; timeout < 1000; timeout++) {
862 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
863 break;
864 DELAY(1000);
865 }
866
867 if (bootverbose) {
868 if (timeout >= 1000)
869 device_printf(dev, "channel HW reset timeout\n");
870 else
871 device_printf(dev, "channel HW reset time=%dms\n", timeout);
872 }
873
874 /* reset phy */
875 if (!ata_sata_phy_reset(dev, -1, 1)) {
876 if (bootverbose)
877 device_printf(dev, "phy reset found no device\n");
878 ch->devices = 0;
879 goto finish;
880 }
881
882 /* issue soft reset */
883 signature = ata_siiprb_softreset(dev, ATA_PM);
884 if (bootverbose)
885 device_printf(dev, "SIGNATURE=%08x\n", signature);
886
887 /* figure out whats there */
888 switch (signature >> 16) {
889 case 0x0000:
890 ch->devices = ATA_ATA_MASTER;
891 break;
892 case 0x9669:
893 ch->devices = ATA_PORTMULTIPLIER;
894 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
895 //SOS XXX need to clear all PM status and interrupts!!!!
896 ata_pm_identify(dev);
897 break;
898 case 0xeb14:
899 ch->devices = ATA_ATAPI_MASTER;
900 break;
901 default:
902 ch->devices = 0;
903 }
904 if (bootverbose)
905 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
906
907finish:
908 /* clear interrupt(s) */
909 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
910
911 /* require explicit interrupt ack */
912 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
913
914 /* 64bit mode */
915 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
916
917 /* enable interrupts wanted */
918 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
919}
920
921static void
922ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
923{
924 struct ata_dmasetprd_args *args = xsc;
925 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
926 int i;
927
928 if ((args->error = error))
929 return;
930
931 for (i = 0; i < nsegs; i++) {
932 prd[i].addr = htole64(segs[i].ds_addr);
933 prd[i].count = htole32(segs[i].ds_len);
934 }
935 prd[i - 1].control = htole32(ATA_DMA_EOT);
936 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
937 args->nsegs = nsegs;
938}
939
940static void
941ata_siiprb_dmainit(device_t dev)
942{
943 struct ata_channel *ch = device_get_softc(dev);
944
945 /* note start and stop are not used here */
946 ch->dma.setprd = ata_siiprb_dmasetprd;
947 ch->dma.max_address = BUS_SPACE_MAXADDR;
948 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
949 ata_dmainit(dev);
950}
951
952ATA_DECLARE_DRIVER(ata_sii);
| 419
420 mode = min(mode, ctlr->chip->max_dma);
421
422 if (ctlr->chip->cfg2 & SII_SETCLK) {
423 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
424 (pci_read_config(parent, 0x79, 1) &
425 (ch->unit ? 0x02 : 0x01))) {
426 ata_print_cable(dev, "controller");
427 mode = ATA_UDMA2;
428 }
429 }
430 if (mode >= ATA_UDMA0) {
431 pci_write_config(parent, mreg,
432 mval | (0x03 << (target << 2)), 1);
433 pci_write_config(parent, ureg,
434 (pci_read_config(parent, ureg, 1) & ~0x3f) |
435 udmatimings[mode & ATA_MODE_MASK], 1);
436 piomode = ATA_PIO4;
437 } else if (mode >= ATA_WDMA0) {
438 pci_write_config(parent, mreg,
439 mval | (0x02 << (target << 2)), 1);
440 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
441 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
442 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
443 } else {
444 pci_write_config(parent, mreg,
445 mval | (0x01 << (target << 2)), 1);
446 piomode = mode;
447 }
448 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
449 return (mode);
450}
451
452struct ata_siiprb_dma_prdentry {
453 u_int64_t addr;
454 u_int32_t count;
455 u_int32_t control;
456} __packed;
457
458#define ATA_SIIPRB_DMA_ENTRIES 129
459struct ata_siiprb_ata_command {
460 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
461} __packed;
462
463struct ata_siiprb_atapi_command {
464 u_int8_t ccb[16];
465 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
466} __packed;
467
468struct ata_siiprb_command {
469 u_int16_t control;
470 u_int16_t protocol_override;
471 u_int32_t transfer_count;
472 u_int8_t fis[24];
473 union {
474 struct ata_siiprb_ata_command ata;
475 struct ata_siiprb_atapi_command atapi;
476 } u;
477} __packed;
478
479static int
480ata_siiprb_ch_attach(device_t dev)
481{
482 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
483 struct ata_channel *ch = device_get_softc(dev);
484 int offset = ch->unit * 0x2000;
485
486 ata_siiprb_dmainit(dev);
487
488 /* set the SATA resources */
489 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
490 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
491 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
492 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
493 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
494 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
495 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
496 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
497
498 ch->hw.status = ata_siiprb_status;
499 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
500 ch->hw.end_transaction = ata_siiprb_end_transaction;
501 ch->hw.command = NULL; /* not used here */
502 ch->hw.softreset = ata_siiprb_softreset;
503 ch->hw.pm_read = ata_siiprb_pm_read;
504 ch->hw.pm_write = ata_siiprb_pm_write;
505 ch->flags |= ATA_NO_SLAVE;
506 ch->flags |= ATA_SATA;
507 return 0;
508}
509
510static int
511ata_siiprb_ch_detach(device_t dev)
512{
513 struct ata_channel *ch = device_get_softc(dev);
514
515 if (ch->dma.work_tag && ch->dma.work_map)
516 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
517 BUS_DMASYNC_POSTWRITE);
518 ata_dmafini(dev);
519 return 0;
520}
521
522static int
523ata_siiprb_status(device_t dev)
524{
525 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
526 struct ata_channel *ch = device_get_softc(dev);
527 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
528 int offset = ch->unit * 0x2000;
529
530 if (action & (1 << ch->unit)) {
531 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
532
533 /* do we have any PHY events ? */
534 ata_sata_phy_check_events(dev, -1);
535
536 /* clear interrupt(s) */
537 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
538
539 /* do we have any device action ? */
540 return (istatus & 0x00000003);
541 }
542 return 0;
543}
544
545static int
546ata_siiprb_begin_transaction(struct ata_request *request)
547{
548 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
549 struct ata_channel *ch = device_get_softc(request->parent);
550 struct ata_siiprb_command *prb;
551 struct ata_siiprb_dma_prdentry *prd;
552 int offset = ch->unit * 0x2000;
553 u_int64_t prb_bus;
554
555 /* SOS XXX */
556 if (request->u.ata.command == ATA_DEVICE_RESET) {
557 request->result = 0;
558 return ATA_OP_FINISHED;
559 }
560
561 /* get a piece of the workspace for this request */
562 prb = (struct ata_siiprb_command *)ch->dma.work;
563
564 /* clear the prb structure */
565 bzero(prb, sizeof(struct ata_siiprb_command));
566
567 /* setup the FIS for this request */
568 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
569 device_printf(request->parent, "setting up SATA FIS failed\n");
570 request->result = EIO;
571 return ATA_OP_FINISHED;
572 }
573
574 /* setup transfer type */
575 if (request->flags & ATA_R_ATAPI) {
576 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
577 if (request->flags & ATA_R_ATAPI16)
578 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
579 else
580 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
581 if (request->flags & ATA_R_READ)
582 prb->control = htole16(0x0010);
583 if (request->flags & ATA_R_WRITE)
584 prb->control = htole16(0x0020);
585 prd = &prb->u.atapi.prd[0];
586 }
587 else
588 prd = &prb->u.ata.prd[0];
589
590 /* if request moves data setup and load SG list */
591 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
592 if (ch->dma.load(request, prd, NULL)) {
593 device_printf(request->parent, "setting up DMA failed\n");
594 request->result = EIO;
595 return ATA_OP_FINISHED;
596 }
597 }
598
599 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
600
601 /* activate the prb */
602 prb_bus = ch->dma.work_bus;
603 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
604 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
605
606 /* start the timeout */
607 callout_reset(&request->callout, request->timeout * hz,
608 (timeout_t*)ata_timeout, request);
609 return ATA_OP_CONTINUES;
610}
611
612static int
613ata_siiprb_end_transaction(struct ata_request *request)
614{
615 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
616 struct ata_channel *ch = device_get_softc(request->parent);
617 struct ata_siiprb_command *prb;
618 int offset = ch->unit * 0x2000;
619 int error, timeout;
620
621 /* kill the timeout */
622 callout_stop(&request->callout);
623
624 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
625
626 prb = (struct ata_siiprb_command *)
627 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
628
629 /* any controller errors flagged ? */
630 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
631 if (bootverbose)
632 printf("ata_siiprb_end_transaction %s error=%08x\n",
633 ata_cmd2str(request), error);
634
635 /* if device error status get details */
636 if (error == 1 || error == 2) {
637 request->status = prb->fis[2];
638 if (request->status & ATA_S_ERROR)
639 request->error = prb->fis[3];
640 }
641
642 /* SOS XXX handle other controller errors here */
643
644 /* initialize port */
645 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
646
647 /* poll for port ready */
648 for (timeout = 0; timeout < 1000; timeout++) {
649 DELAY(1000);
650 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
651 break;
652 }
653 if (bootverbose) {
654 if (timeout >= 1000)
655 device_printf(ch->dev, "port initialize timeout\n");
656 else
657 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
658 }
659 }
660
661 /* on control commands read back registers to the request struct */
662 if (request->flags & ATA_R_CONTROL) {
663 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
664 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
665 ((u_int64_t)prb->fis[6] << 16);
666 if (request->flags & ATA_R_48BIT)
667 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
668 ((u_int64_t)prb->fis[9] << 32) |
669 ((u_int64_t)prb->fis[10] << 40);
670 else
671 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
672 }
673
674 /* update progress */
675 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
676 if (request->flags & ATA_R_READ)
677 request->donecount = le32toh(prb->transfer_count);
678 else
679 request->donecount = request->bytecount;
680 }
681
682 /* release SG list etc */
683 ch->dma.unload(request);
684
685 return ATA_OP_FINISHED;
686}
687
688static int
689ata_siiprb_issue_cmd(device_t dev)
690{
691 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
692 struct ata_channel *ch = device_get_softc(dev);
693 u_int64_t prb_bus = ch->dma.work_bus;
694 u_int32_t status;
695 int offset = ch->unit * 0x2000;
696 int timeout;
697
698 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
699
700 /* issue command to chip */
701 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
702 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
703
704 /* poll for command finished */
705 for (timeout = 0; timeout < 10000; timeout++) {
706 DELAY(1000);
707 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
708 break;
709 }
710
711 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
712
713 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
714 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
715
716 if (timeout >= 1000)
717 return EIO;
718
719 if (bootverbose)
720 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
721 timeout, status);
722 return 0;
723}
724
725static int
726ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
727{
728 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
729 struct ata_channel *ch = device_get_softc(dev);
730 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
731 int offset = ch->unit * 0x2000;
732
733 if (port < 0) {
734 *result = ATA_IDX_INL(ch, reg);
735 return (0);
736 }
737 if (port < ATA_PM) {
738 switch (reg) {
739 case ATA_SSTATUS:
740 reg = 0;
741 break;
742 case ATA_SERROR:
743 reg = 1;
744 break;
745 case ATA_SCONTROL:
746 reg = 2;
747 break;
748 default:
749 return (EINVAL);
750 }
751 }
752 bzero(prb, sizeof(struct ata_siiprb_command));
753 prb->fis[0] = 0x27; /* host to device */
754 prb->fis[1] = 0x8f; /* command FIS to PM port */
755 prb->fis[2] = ATA_READ_PM;
756 prb->fis[3] = reg;
757 prb->fis[7] = port;
758 if (ata_siiprb_issue_cmd(dev)) {
759 device_printf(dev, "error reading PM port\n");
760 return EIO;
761 }
762 prb = (struct ata_siiprb_command *)
763 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
764 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
765 return 0;
766}
767
768static int
769ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
770{
771 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
772 struct ata_channel *ch = device_get_softc(dev);
773 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
774 int offset = ch->unit * 0x2000;
775
776 if (port < 0) {
777 ATA_IDX_OUTL(ch, reg, value);
778 return (0);
779 }
780 if (port < ATA_PM) {
781 switch (reg) {
782 case ATA_SSTATUS:
783 reg = 0;
784 break;
785 case ATA_SERROR:
786 reg = 1;
787 break;
788 case ATA_SCONTROL:
789 reg = 2;
790 break;
791 default:
792 return (EINVAL);
793 }
794 }
795 bzero(prb, sizeof(struct ata_siiprb_command));
796 prb->fis[0] = 0x27; /* host to device */
797 prb->fis[1] = 0x8f; /* command FIS to PM port */
798 prb->fis[2] = ATA_WRITE_PM;
799 prb->fis[3] = reg;
800 prb->fis[7] = port;
801 prb->fis[12] = value & 0xff;
802 prb->fis[4] = (value >> 8) & 0xff;
803 prb->fis[5] = (value >> 16) & 0xff;
804 prb->fis[6] = (value >> 24) & 0xff;
805 if (ata_siiprb_issue_cmd(dev)) {
806 device_printf(dev, "error writing PM port\n");
807 return ATA_E_ABORT;
808 }
809 prb = (struct ata_siiprb_command *)
810 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
811 return prb->fis[3];
812}
813
814static u_int32_t
815ata_siiprb_softreset(device_t dev, int port)
816{
817 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
818 struct ata_channel *ch = device_get_softc(dev);
819 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
820 u_int32_t signature;
821 int offset = ch->unit * 0x2000;
822
823 /* setup the workspace for a soft reset command */
824 bzero(prb, sizeof(struct ata_siiprb_command));
825 prb->control = htole16(0x0080);
826 prb->fis[1] = port & 0x0f;
827
828 /* issue soft reset */
829 if (ata_siiprb_issue_cmd(dev))
830 return -1;
831
832 ata_udelay(150000);
833
834 /* get possible signature */
835 prb = (struct ata_siiprb_command *)
836 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
837 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
838
839 /* clear error bits/interrupt */
840 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
841
842 return signature;
843}
844
845static void
846ata_siiprb_reset(device_t dev)
847{
848 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
849 struct ata_channel *ch = device_get_softc(dev);
850 int offset = ch->unit * 0x2000;
851 u_int32_t status, signature;
852 int timeout;
853
854 /* disable interrupts */
855 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
856
857 /* reset channel HW */
858 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
859 DELAY(1000);
860 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
861 DELAY(10000);
862
863 /* poll for channel ready */
864 for (timeout = 0; timeout < 1000; timeout++) {
865 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
866 break;
867 DELAY(1000);
868 }
869
870 if (bootverbose) {
871 if (timeout >= 1000)
872 device_printf(dev, "channel HW reset timeout\n");
873 else
874 device_printf(dev, "channel HW reset time=%dms\n", timeout);
875 }
876
877 /* reset phy */
878 if (!ata_sata_phy_reset(dev, -1, 1)) {
879 if (bootverbose)
880 device_printf(dev, "phy reset found no device\n");
881 ch->devices = 0;
882 goto finish;
883 }
884
885 /* issue soft reset */
886 signature = ata_siiprb_softreset(dev, ATA_PM);
887 if (bootverbose)
888 device_printf(dev, "SIGNATURE=%08x\n", signature);
889
890 /* figure out whats there */
891 switch (signature >> 16) {
892 case 0x0000:
893 ch->devices = ATA_ATA_MASTER;
894 break;
895 case 0x9669:
896 ch->devices = ATA_PORTMULTIPLIER;
897 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
898 //SOS XXX need to clear all PM status and interrupts!!!!
899 ata_pm_identify(dev);
900 break;
901 case 0xeb14:
902 ch->devices = ATA_ATAPI_MASTER;
903 break;
904 default:
905 ch->devices = 0;
906 }
907 if (bootverbose)
908 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
909
910finish:
911 /* clear interrupt(s) */
912 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
913
914 /* require explicit interrupt ack */
915 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
916
917 /* 64bit mode */
918 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
919
920 /* enable interrupts wanted */
921 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
922}
923
924static void
925ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
926{
927 struct ata_dmasetprd_args *args = xsc;
928 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
929 int i;
930
931 if ((args->error = error))
932 return;
933
934 for (i = 0; i < nsegs; i++) {
935 prd[i].addr = htole64(segs[i].ds_addr);
936 prd[i].count = htole32(segs[i].ds_len);
937 }
938 prd[i - 1].control = htole32(ATA_DMA_EOT);
939 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
940 args->nsegs = nsegs;
941}
942
943static void
944ata_siiprb_dmainit(device_t dev)
945{
946 struct ata_channel *ch = device_get_softc(dev);
947
948 /* note start and stop are not used here */
949 ch->dma.setprd = ata_siiprb_dmasetprd;
950 ch->dma.max_address = BUS_SPACE_MAXADDR;
951 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
952 ata_dmainit(dev);
953}
954
955ATA_DECLARE_DRIVER(ata_sii);
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