1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-pci.c 77905 2001-06-08 09:51:33Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-pci.c 82053 2001-08-21 11:35:47Z sos $
|
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/disk.h>
35#include <sys/module.h>
36#include <sys/bus.h>
37#include <sys/bio.h>
38#include <sys/malloc.h>
39#include <sys/devicestat.h>
40#include <sys/sysctl.h>
41#include <machine/stdarg.h>
42#include <machine/resource.h>
43#include <machine/bus.h>
44#ifdef __alpha__
45#include <machine/md_var.h>
46#endif
47#include <sys/rman.h>
48#include <pci/pcivar.h>
49#include <pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51
52/* misc defines */
53#define IOMASK 0xfffffffc
54#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
55 (pci_get_progif(dev) & 0x05) != 0x05)
56
57struct ata_pci_softc {
58 struct resource *bmio;
59 int bmaddr;
60 struct resource *irq;
61 int irqcnt;
62};
63
64int
65ata_find_dev(device_t dev, u_int32_t type, u_int32_t revid)
66{
67 device_t *children, child;
68 int nchildren, i;
69
70 if (device_get_children(device_get_parent(dev), &children, &nchildren))
71 return 0;
72
73 for (i = 0; i < nchildren; i++) {
74 child = children[i];
75
76 /* check that it's on the same silicon and the device we want */
77 if (pci_get_slot(dev) == pci_get_slot(child) &&
78 pci_get_vendor(child) == (type & 0xffff) &&
79 pci_get_device(child) == ((type & 0xffff0000) >> 16) &&
80 pci_get_revid(child) >= revid) {
81 free(children, M_TEMP);
82 return 1;
83 }
84 }
85 free(children, M_TEMP);
86 return 0;
87}
88
89static const char *
90ata_pci_match(device_t dev)
91{
92 if (pci_get_class(dev) != PCIC_STORAGE)
93 return NULL;
94
95 switch (pci_get_devid(dev)) {
96 /* supported chipsets */
97 case 0x12308086:
98 return "Intel PIIX ATA controller";
99
100 case 0x70108086:
101 return "Intel PIIX3 ATA controller";
102
103 case 0x71118086:
104 case 0x71998086:
105 return "Intel PIIX4 ATA33 controller";
106
107 case 0x24218086:
108 return "Intel ICH0 ATA33 controller";
109
110 case 0x24118086:
111 return "Intel ICH ATA66 controller";
112
113 case 0x244a8086:
114 case 0x244b8086:
115 return "Intel ICH2 ATA100 controller";
116
117 case 0x522910b9:
118 if (pci_get_revid(dev) < 0x20)
119 return "AcerLabs Aladdin ATA controller";
120 else
121 return "AcerLabs Aladdin ATA33 controller";
122
123 case 0x05711106:
124 if (ata_find_dev(dev, 0x05861106, 0x02))
125 return "VIA 82C586 ATA33 controller";
126 if (ata_find_dev(dev, 0x05861106, 0))
127 return "VIA 82C586 ATA controller";
128 if (ata_find_dev(dev, 0x05961106, 0x12))
129 return "VIA 82C596 ATA66 controller";
130 if (ata_find_dev(dev, 0x05961106, 0))
131 return "VIA 82C596 ATA33 controller";
132 if (ata_find_dev(dev, 0x06861106, 0x40))
133 return "VIA 82C686 ATA100 controller";
134 if (ata_find_dev(dev, 0x06861106, 0))
135 return "VIA 82C686 ATA66 controller";
136 return "VIA Apollo ATA controller";
137
138 case 0x55131039:
139 return "SiS 5591 ATA33 controller";
140
141 case 0x06491095:
142 return "CMD 649 ATA100 controller";
143
144 case 0x06481095:
145 return "CMD 648 ATA66 controller";
146
147 case 0x06461095:
148 return "CMD 646 ATA controller";
149
150 case 0xc6931080:
151 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
152 return "Cypress 82C693 ATA controller";
153 break;
154
155 case 0x01021078:
156 return "Cyrix 5530 ATA33 controller";
157
158 case 0x74091022:
159 return "AMD 756 ATA66 controller";
160
161 case 0x74111022:
162 return "AMD 766 ATA100 controller";
163
164 case 0x02111166:
165 return "ServerWorks ROSB4 ATA33 controller";
166
167 case 0x4d33105a:
168 return "Promise ATA33 controller";
169
170 case 0x4d38105a:
171 return "Promise ATA66 controller";
172
173 case 0x0d30105a:
174 case 0x4d30105a:
175 case 0x4d68105a:
| 29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/disk.h>
35#include <sys/module.h>
36#include <sys/bus.h>
37#include <sys/bio.h>
38#include <sys/malloc.h>
39#include <sys/devicestat.h>
40#include <sys/sysctl.h>
41#include <machine/stdarg.h>
42#include <machine/resource.h>
43#include <machine/bus.h>
44#ifdef __alpha__
45#include <machine/md_var.h>
46#endif
47#include <sys/rman.h>
48#include <pci/pcivar.h>
49#include <pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51
52/* misc defines */
53#define IOMASK 0xfffffffc
54#define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
55 (pci_get_progif(dev) & 0x05) != 0x05)
56
57struct ata_pci_softc {
58 struct resource *bmio;
59 int bmaddr;
60 struct resource *irq;
61 int irqcnt;
62};
63
64int
65ata_find_dev(device_t dev, u_int32_t type, u_int32_t revid)
66{
67 device_t *children, child;
68 int nchildren, i;
69
70 if (device_get_children(device_get_parent(dev), &children, &nchildren))
71 return 0;
72
73 for (i = 0; i < nchildren; i++) {
74 child = children[i];
75
76 /* check that it's on the same silicon and the device we want */
77 if (pci_get_slot(dev) == pci_get_slot(child) &&
78 pci_get_vendor(child) == (type & 0xffff) &&
79 pci_get_device(child) == ((type & 0xffff0000) >> 16) &&
80 pci_get_revid(child) >= revid) {
81 free(children, M_TEMP);
82 return 1;
83 }
84 }
85 free(children, M_TEMP);
86 return 0;
87}
88
89static const char *
90ata_pci_match(device_t dev)
91{
92 if (pci_get_class(dev) != PCIC_STORAGE)
93 return NULL;
94
95 switch (pci_get_devid(dev)) {
96 /* supported chipsets */
97 case 0x12308086:
98 return "Intel PIIX ATA controller";
99
100 case 0x70108086:
101 return "Intel PIIX3 ATA controller";
102
103 case 0x71118086:
104 case 0x71998086:
105 return "Intel PIIX4 ATA33 controller";
106
107 case 0x24218086:
108 return "Intel ICH0 ATA33 controller";
109
110 case 0x24118086:
111 return "Intel ICH ATA66 controller";
112
113 case 0x244a8086:
114 case 0x244b8086:
115 return "Intel ICH2 ATA100 controller";
116
117 case 0x522910b9:
118 if (pci_get_revid(dev) < 0x20)
119 return "AcerLabs Aladdin ATA controller";
120 else
121 return "AcerLabs Aladdin ATA33 controller";
122
123 case 0x05711106:
124 if (ata_find_dev(dev, 0x05861106, 0x02))
125 return "VIA 82C586 ATA33 controller";
126 if (ata_find_dev(dev, 0x05861106, 0))
127 return "VIA 82C586 ATA controller";
128 if (ata_find_dev(dev, 0x05961106, 0x12))
129 return "VIA 82C596 ATA66 controller";
130 if (ata_find_dev(dev, 0x05961106, 0))
131 return "VIA 82C596 ATA33 controller";
132 if (ata_find_dev(dev, 0x06861106, 0x40))
133 return "VIA 82C686 ATA100 controller";
134 if (ata_find_dev(dev, 0x06861106, 0))
135 return "VIA 82C686 ATA66 controller";
136 return "VIA Apollo ATA controller";
137
138 case 0x55131039:
139 return "SiS 5591 ATA33 controller";
140
141 case 0x06491095:
142 return "CMD 649 ATA100 controller";
143
144 case 0x06481095:
145 return "CMD 648 ATA66 controller";
146
147 case 0x06461095:
148 return "CMD 646 ATA controller";
149
150 case 0xc6931080:
151 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
152 return "Cypress 82C693 ATA controller";
153 break;
154
155 case 0x01021078:
156 return "Cyrix 5530 ATA33 controller";
157
158 case 0x74091022:
159 return "AMD 756 ATA66 controller";
160
161 case 0x74111022:
162 return "AMD 766 ATA100 controller";
163
164 case 0x02111166:
165 return "ServerWorks ROSB4 ATA33 controller";
166
167 case 0x4d33105a:
168 return "Promise ATA33 controller";
169
170 case 0x4d38105a:
171 return "Promise ATA66 controller";
172
173 case 0x0d30105a:
174 case 0x4d30105a:
175 case 0x4d68105a:
|
| 176 case 0x6268105a:
|
176 return "Promise ATA100 controller";
177
178 case 0x00041103:
179 switch (pci_get_revid(dev)) {
180 case 0x00:
181 case 0x01:
182 return "HighPoint HPT366 ATA66 controller";
183 case 0x02:
184 return "HighPoint HPT368 ATA66 controller";
185 case 0x03:
186 case 0x04:
187 return "HighPoint HPT370 ATA100 controller";
188 default:
189 return "Unknown revision HighPoint ATA controller";
190 }
191
192 /* unsupported but known chipsets, generic DMA only */
193 case 0x10001042:
194 case 0x10011042:
195 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
196
197 case 0x06401095:
198 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
199
200 /* unknown chipsets, try generic DMA if it seems possible */
201 default:
202 if (pci_get_class(dev) == PCIC_STORAGE &&
203 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
204 return "Generic PCI ATA controller";
205 }
206 return NULL;
207}
208
209static int
210ata_pci_probe(device_t dev)
211{
212 const char *desc = ata_pci_match(dev);
213
214 if (desc) {
215 device_set_desc(dev, desc);
216 return 0;
217 }
218 else
219 return ENXIO;
220}
221
222static int
223ata_pci_add_child(device_t dev, int unit)
224{
225 device_t child;
226
227 /* check if this is located at one of the std addresses */
228 if (ATA_MASTERDEV(dev)) {
229 if (!(child = device_add_child(dev, "ata", unit)))
230 return ENOMEM;
231 }
232 else {
233 if (!(child = device_add_child(dev, "ata", 2)))
234 return ENOMEM;
235 }
236 return 0;
237}
238
239static int
240ata_pci_attach(device_t dev)
241{
242 struct ata_pci_softc *sc = device_get_softc(dev);
243 u_int8_t class, subclass;
244 u_int32_t type, cmd;
245 int rid;
246
247 /* set up vendor-specific stuff */
248 type = pci_get_devid(dev);
249 class = pci_get_class(dev);
250 subclass = pci_get_subclass(dev);
251 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
252
253 if (!(cmd & PCIM_CMD_PORTEN)) {
254 device_printf(dev, "ATA channel disabled by BIOS\n");
255 return 0;
256 }
257
258 /* is busmastering supported ? */
259 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
260 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
261
262 /* is there a valid port range to connect to ? */
263 rid = 0x20;
264 sc->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
265 0, ~0, 1, RF_ACTIVE);
266 if (!sc->bmio)
267 device_printf(dev, "Busmastering DMA not configured\n");
268 }
269 else
270 device_printf(dev, "Busmastering DMA not supported\n");
271
272 /* do extra chipset specific setups */
273 switch (type) {
274 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
275 pci_write_config(dev, 0x53,
276 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
277 break;
278
279 case 0x4d38105a: /* Promise 66 & 100 need their clock changed */
280 case 0x4d30105a:
281 case 0x0d30105a:
282 case 0x4d68105a:
| 177 return "Promise ATA100 controller";
178
179 case 0x00041103:
180 switch (pci_get_revid(dev)) {
181 case 0x00:
182 case 0x01:
183 return "HighPoint HPT366 ATA66 controller";
184 case 0x02:
185 return "HighPoint HPT368 ATA66 controller";
186 case 0x03:
187 case 0x04:
188 return "HighPoint HPT370 ATA100 controller";
189 default:
190 return "Unknown revision HighPoint ATA controller";
191 }
192
193 /* unsupported but known chipsets, generic DMA only */
194 case 0x10001042:
195 case 0x10011042:
196 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
197
198 case 0x06401095:
199 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
200
201 /* unknown chipsets, try generic DMA if it seems possible */
202 default:
203 if (pci_get_class(dev) == PCIC_STORAGE &&
204 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
205 return "Generic PCI ATA controller";
206 }
207 return NULL;
208}
209
210static int
211ata_pci_probe(device_t dev)
212{
213 const char *desc = ata_pci_match(dev);
214
215 if (desc) {
216 device_set_desc(dev, desc);
217 return 0;
218 }
219 else
220 return ENXIO;
221}
222
223static int
224ata_pci_add_child(device_t dev, int unit)
225{
226 device_t child;
227
228 /* check if this is located at one of the std addresses */
229 if (ATA_MASTERDEV(dev)) {
230 if (!(child = device_add_child(dev, "ata", unit)))
231 return ENOMEM;
232 }
233 else {
234 if (!(child = device_add_child(dev, "ata", 2)))
235 return ENOMEM;
236 }
237 return 0;
238}
239
240static int
241ata_pci_attach(device_t dev)
242{
243 struct ata_pci_softc *sc = device_get_softc(dev);
244 u_int8_t class, subclass;
245 u_int32_t type, cmd;
246 int rid;
247
248 /* set up vendor-specific stuff */
249 type = pci_get_devid(dev);
250 class = pci_get_class(dev);
251 subclass = pci_get_subclass(dev);
252 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
253
254 if (!(cmd & PCIM_CMD_PORTEN)) {
255 device_printf(dev, "ATA channel disabled by BIOS\n");
256 return 0;
257 }
258
259 /* is busmastering supported ? */
260 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
261 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
262
263 /* is there a valid port range to connect to ? */
264 rid = 0x20;
265 sc->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
266 0, ~0, 1, RF_ACTIVE);
267 if (!sc->bmio)
268 device_printf(dev, "Busmastering DMA not configured\n");
269 }
270 else
271 device_printf(dev, "Busmastering DMA not supported\n");
272
273 /* do extra chipset specific setups */
274 switch (type) {
275 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
276 pci_write_config(dev, 0x53,
277 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
278 break;
279
280 case 0x4d38105a: /* Promise 66 & 100 need their clock changed */
281 case 0x4d30105a:
282 case 0x0d30105a:
283 case 0x4d68105a:
|
| 284 case 0x6268105a:
|
283 ATA_OUTB(sc->bmio, 0x11, ATA_INB(sc->bmio, 0x11) | 0x0a);
284 /* FALLTHROUGH */
285
286 case 0x4d33105a: /* Promise (all) need burst mode to be turned on */
287 ATA_OUTB(sc->bmio, 0x1f, ATA_INB(sc->bmio, 0x1f) | 0x01);
288 break;
289
290 case 0x00041103: /* HighPoint */
291 switch (pci_get_revid(dev)) {
292 case 0x00:
293 case 0x01:
294 /* turn off interrupt prediction */
295 pci_write_config(dev, 0x51,
296 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
297 break;
298
299 case 0x02:
300 case 0x03:
301 case 0x04:
302 /* turn off interrupt prediction */
303 pci_write_config(dev, 0x51,
304 (pci_read_config(dev, 0x51, 1) & ~0x02), 1);
305 pci_write_config(dev, 0x55,
306 (pci_read_config(dev, 0x55, 1) & ~0x02), 1);
307 /* turn on interrupts */
308 pci_write_config(dev, 0x5a,
309 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
310
311 }
312 break;
313
314 case 0x05711106:
315 case 0x74091022:
316 case 0x74111022: /* VIA 82C586, '596, '686 & AMD 756, '766 default setup */
317
318 /* set prefetch, postwrite */
319 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
320
321 /* set fifo configuration half'n'half */
322 pci_write_config(dev, 0x43,
323 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
324
325 /* set status register read retry */
326 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
327
328 /* set DMA read & end-of-sector fifo flush */
329 pci_write_config(dev, 0x46,
330 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
331
332 /* set sector size */
333 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
334 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
335
336 /* prepare for ATA-66 on the 82C686 and rev 0x12 and newer 82C596's */
337 if (ata_find_dev(dev, 0x06861106, 0) ||
| 285 ATA_OUTB(sc->bmio, 0x11, ATA_INB(sc->bmio, 0x11) | 0x0a);
286 /* FALLTHROUGH */
287
288 case 0x4d33105a: /* Promise (all) need burst mode to be turned on */
289 ATA_OUTB(sc->bmio, 0x1f, ATA_INB(sc->bmio, 0x1f) | 0x01);
290 break;
291
292 case 0x00041103: /* HighPoint */
293 switch (pci_get_revid(dev)) {
294 case 0x00:
295 case 0x01:
296 /* turn off interrupt prediction */
297 pci_write_config(dev, 0x51,
298 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
299 break;
300
301 case 0x02:
302 case 0x03:
303 case 0x04:
304 /* turn off interrupt prediction */
305 pci_write_config(dev, 0x51,
306 (pci_read_config(dev, 0x51, 1) & ~0x02), 1);
307 pci_write_config(dev, 0x55,
308 (pci_read_config(dev, 0x55, 1) & ~0x02), 1);
309 /* turn on interrupts */
310 pci_write_config(dev, 0x5a,
311 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
312
313 }
314 break;
315
316 case 0x05711106:
317 case 0x74091022:
318 case 0x74111022: /* VIA 82C586, '596, '686 & AMD 756, '766 default setup */
319
320 /* set prefetch, postwrite */
321 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
322
323 /* set fifo configuration half'n'half */
324 pci_write_config(dev, 0x43,
325 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
326
327 /* set status register read retry */
328 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
329
330 /* set DMA read & end-of-sector fifo flush */
331 pci_write_config(dev, 0x46,
332 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
333
334 /* set sector size */
335 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
336 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
337
338 /* prepare for ATA-66 on the 82C686 and rev 0x12 and newer 82C596's */
339 if (ata_find_dev(dev, 0x06861106, 0) ||
|
338 ata_find_dev(dev, 0x05961106, 0x12)) {
| 340 ata_find_dev(dev, 0x05961106, 0x12))
|
339 pci_write_config(dev, 0x50, 0x030b030b, 4);
| 341 pci_write_config(dev, 0x50, 0x030b030b, 4);
|
340 }
| 342
|
341 break;
342
343 case 0x10001042: /* RZ 100? known bad, no DMA */
344 case 0x10011042:
345 case 0x06401095: /* CMD 640 known bad, no DMA */
346 sc->bmio = NULL;
347 device_printf(dev, "Busmastering DMA disabled\n");
348 }
349
350 if (sc->bmio) {
351 sc->bmaddr = rman_get_start(sc->bmio);
352 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
353 SYS_RES_IOPORT, rid, sc->bmio);
354 sc->bmio = NULL;
355 }
356
357 /*
358 * the Cypress chip is a mess, it contains two ATA functions, but
359 * both channels are visible on the first one.
360 * simply ignore the second function for now, as the right
361 * solution (ignoring the second channel on the first function)
362 * doesn't work with the crappy ATA interrupt setup on the alpha.
363 */
364 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
365 return 0;
366
367 ata_pci_add_child(dev, 0);
368
369 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
370 ata_pci_add_child(dev, 1);
371
372 return bus_generic_attach(dev);
373}
374
375static int
376ata_pci_intr(struct ata_softc *scp)
377{
378 u_int8_t dmastat;
379
380 /*
381 * since we might share the IRQ with another device, and in some
382 * cases with our twin channel, we only want to process interrupts
383 * that we know this channel generated.
384 */
385 switch (scp->chiptype) {
386 case 0x00041103: /* HighPoint HPT366/368/370 */
387 if (((dmastat = ata_dmastatus(scp)) &
388 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
389 return 1;
390 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
391 DELAY(1);
392 return 0;
393
394 case 0x06481095: /* CMD 648 */
395 case 0x06491095: /* CMD 649 */
396 if (!(pci_read_config(device_get_parent(scp->dev), 0x71, 1) &
397 (scp->channel ? 0x08 : 0x04)))
398 return 1;
399 break;
400
401 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
402 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
403 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
404 case 0x0d30105a: /* Promise OEM ATA100 */
405 case 0x4d68105a: /* Promise TX2 ATA100 */
| 343 break;
344
345 case 0x10001042: /* RZ 100? known bad, no DMA */
346 case 0x10011042:
347 case 0x06401095: /* CMD 640 known bad, no DMA */
348 sc->bmio = NULL;
349 device_printf(dev, "Busmastering DMA disabled\n");
350 }
351
352 if (sc->bmio) {
353 sc->bmaddr = rman_get_start(sc->bmio);
354 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
355 SYS_RES_IOPORT, rid, sc->bmio);
356 sc->bmio = NULL;
357 }
358
359 /*
360 * the Cypress chip is a mess, it contains two ATA functions, but
361 * both channels are visible on the first one.
362 * simply ignore the second function for now, as the right
363 * solution (ignoring the second channel on the first function)
364 * doesn't work with the crappy ATA interrupt setup on the alpha.
365 */
366 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
367 return 0;
368
369 ata_pci_add_child(dev, 0);
370
371 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
372 ata_pci_add_child(dev, 1);
373
374 return bus_generic_attach(dev);
375}
376
377static int
378ata_pci_intr(struct ata_softc *scp)
379{
380 u_int8_t dmastat;
381
382 /*
383 * since we might share the IRQ with another device, and in some
384 * cases with our twin channel, we only want to process interrupts
385 * that we know this channel generated.
386 */
387 switch (scp->chiptype) {
388 case 0x00041103: /* HighPoint HPT366/368/370 */
389 if (((dmastat = ata_dmastatus(scp)) &
390 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
391 return 1;
392 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
393 DELAY(1);
394 return 0;
395
396 case 0x06481095: /* CMD 648 */
397 case 0x06491095: /* CMD 649 */
398 if (!(pci_read_config(device_get_parent(scp->dev), 0x71, 1) &
399 (scp->channel ? 0x08 : 0x04)))
400 return 1;
401 break;
402
403 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
404 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
405 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
406 case 0x0d30105a: /* Promise OEM ATA100 */
407 case 0x4d68105a: /* Promise TX2 ATA100 */
|
| 408 case 0x6268105a: /* Promise TX2v2 ATA100 */
|
406 if (!(ATA_INL(scp->r_bmio, (scp->channel ? 0x14 : 0x1c)) &
407 (scp->channel ? 0x00004000 : 0x00000400)))
408 return 1;
409 break;
410 }
411
412 if (scp->flags & ATA_DMA_ACTIVE) {
413 if (!((dmastat = ata_dmastatus(scp)) & ATA_BMSTAT_INTERRUPT))
414 return 1;
415 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
416 DELAY(1);
417 }
418 return 0;
419}
420
421static int
422ata_pci_print_child(device_t dev, device_t child)
423{
424 struct ata_softc *scp = device_get_softc(child);
425 int retval = 0;
426
427 retval += bus_print_child_header(dev, child);
428 retval += printf(": at 0x%lx", rman_get_start(scp->r_io));
429
430 if (ATA_MASTERDEV(dev))
431 retval += printf(" irq %d", 14 + scp->channel);
432
433 retval += bus_print_child_footer(dev, child);
434
435 return retval;
436}
437
438static struct resource *
439ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
440 u_long start, u_long end, u_long count, u_int flags)
441{
442 struct ata_pci_softc *sc = device_get_softc(dev);
443 struct resource *res = NULL;
444 int channel = ((struct ata_softc *)device_get_softc(child))->channel;
445 int myrid;
446
447 if (type == SYS_RES_IOPORT) {
448 switch (*rid) {
449 case ATA_IOADDR_RID:
450 if (ATA_MASTERDEV(dev)) {
451 myrid = 0;
452 start = (channel ? ATA_SECONDARY : ATA_PRIMARY);
453 end = start + ATA_IOSIZE - 1;
454 count = ATA_IOSIZE;
455 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
456 SYS_RES_IOPORT, &myrid,
457 start, end, count, flags);
458 }
459 else {
460 myrid = 0x10 + 8 * channel;
461 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
462 SYS_RES_IOPORT, &myrid,
463 start, end, count, flags);
464 }
465 break;
466
467 case ATA_ALTADDR_RID:
468 if (ATA_MASTERDEV(dev)) {
469 myrid = 0;
470 start = (channel ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
471 end = start + ATA_ALTIOSIZE - 1;
472 count = ATA_ALTIOSIZE;
473 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
474 SYS_RES_IOPORT, &myrid,
475 start, end, count, flags);
476 }
477 else {
478 myrid = 0x14 + 8 * channel;
479 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
480 SYS_RES_IOPORT, &myrid,
481 start, end, count, flags);
482 if (res) {
483 start = rman_get_start(res) + 2;
484 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
485 count = ATA_ALTIOSIZE;
486 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
487 SYS_RES_IOPORT, myrid, res);
488 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
489 SYS_RES_IOPORT, &myrid,
490 start, end, count, flags);
491 }
492 }
493 break;
494
495 case ATA_BMADDR_RID:
496 if (sc->bmaddr) {
497 myrid = 0x20;
498 start = (channel == 0 ? sc->bmaddr : sc->bmaddr + ATA_BMIOSIZE);
499 end = start + ATA_BMIOSIZE - 1;
500 count = ATA_BMIOSIZE;
501 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
502 SYS_RES_IOPORT, &myrid,
503 start, end, count, flags);
504 }
505 }
506 return res;
507 }
508
509 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
510 if (ATA_MASTERDEV(dev)) {
511#ifdef __alpha__
512 return alpha_platform_alloc_ide_intr(channel);
513#else
514 int irq = (channel == 0 ? 14 : 15);
515
516 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
| 409 if (!(ATA_INL(scp->r_bmio, (scp->channel ? 0x14 : 0x1c)) &
410 (scp->channel ? 0x00004000 : 0x00000400)))
411 return 1;
412 break;
413 }
414
415 if (scp->flags & ATA_DMA_ACTIVE) {
416 if (!((dmastat = ata_dmastatus(scp)) & ATA_BMSTAT_INTERRUPT))
417 return 1;
418 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
419 DELAY(1);
420 }
421 return 0;
422}
423
424static int
425ata_pci_print_child(device_t dev, device_t child)
426{
427 struct ata_softc *scp = device_get_softc(child);
428 int retval = 0;
429
430 retval += bus_print_child_header(dev, child);
431 retval += printf(": at 0x%lx", rman_get_start(scp->r_io));
432
433 if (ATA_MASTERDEV(dev))
434 retval += printf(" irq %d", 14 + scp->channel);
435
436 retval += bus_print_child_footer(dev, child);
437
438 return retval;
439}
440
441static struct resource *
442ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
443 u_long start, u_long end, u_long count, u_int flags)
444{
445 struct ata_pci_softc *sc = device_get_softc(dev);
446 struct resource *res = NULL;
447 int channel = ((struct ata_softc *)device_get_softc(child))->channel;
448 int myrid;
449
450 if (type == SYS_RES_IOPORT) {
451 switch (*rid) {
452 case ATA_IOADDR_RID:
453 if (ATA_MASTERDEV(dev)) {
454 myrid = 0;
455 start = (channel ? ATA_SECONDARY : ATA_PRIMARY);
456 end = start + ATA_IOSIZE - 1;
457 count = ATA_IOSIZE;
458 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
459 SYS_RES_IOPORT, &myrid,
460 start, end, count, flags);
461 }
462 else {
463 myrid = 0x10 + 8 * channel;
464 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
465 SYS_RES_IOPORT, &myrid,
466 start, end, count, flags);
467 }
468 break;
469
470 case ATA_ALTADDR_RID:
471 if (ATA_MASTERDEV(dev)) {
472 myrid = 0;
473 start = (channel ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
474 end = start + ATA_ALTIOSIZE - 1;
475 count = ATA_ALTIOSIZE;
476 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
477 SYS_RES_IOPORT, &myrid,
478 start, end, count, flags);
479 }
480 else {
481 myrid = 0x14 + 8 * channel;
482 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
483 SYS_RES_IOPORT, &myrid,
484 start, end, count, flags);
485 if (res) {
486 start = rman_get_start(res) + 2;
487 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
488 count = ATA_ALTIOSIZE;
489 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
490 SYS_RES_IOPORT, myrid, res);
491 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
492 SYS_RES_IOPORT, &myrid,
493 start, end, count, flags);
494 }
495 }
496 break;
497
498 case ATA_BMADDR_RID:
499 if (sc->bmaddr) {
500 myrid = 0x20;
501 start = (channel == 0 ? sc->bmaddr : sc->bmaddr + ATA_BMIOSIZE);
502 end = start + ATA_BMIOSIZE - 1;
503 count = ATA_BMIOSIZE;
504 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
505 SYS_RES_IOPORT, &myrid,
506 start, end, count, flags);
507 }
508 }
509 return res;
510 }
511
512 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
513 if (ATA_MASTERDEV(dev)) {
514#ifdef __alpha__
515 return alpha_platform_alloc_ide_intr(channel);
516#else
517 int irq = (channel == 0 ? 14 : 15);
518
519 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
517 SYS_RES_IRQ, rid,
518 irq, irq, 1, flags & ~RF_SHAREABLE);
| 520 SYS_RES_IRQ, rid, irq, irq, 1, flags);
|
519#endif
520 }
521 else {
522 /* primary and secondary channels share interrupt, keep track */
523 if (!sc->irq)
524 sc->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
525 SYS_RES_IRQ, rid, 0, ~0, 1, flags);
526 sc->irqcnt++;
527 return sc->irq;
528 }
529 }
530 return 0;
531}
532
533static int
534ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
535 struct resource *r)
536{
537 struct ata_pci_softc *sc = device_get_softc(dev);
538 int channel = ((struct ata_softc *)device_get_softc(child))->channel;
539
540 if (type == SYS_RES_IOPORT) {
541 switch (rid) {
542 case ATA_IOADDR_RID:
543 if (ATA_MASTERDEV(dev))
544 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
545 SYS_RES_IOPORT, 0x0, r);
546 else
547 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
548 SYS_RES_IOPORT, 0x10+8*channel, r);
549 break;
550
551 case ATA_ALTADDR_RID:
552 if (ATA_MASTERDEV(dev))
553 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
554 SYS_RES_IOPORT, 0x0, r);
555 else
556 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
557 SYS_RES_IOPORT, 0x14+8*channel, r);
558 break;
559
560 case ATA_BMADDR_RID:
561 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
562 SYS_RES_IOPORT, 0x20, r);
563 default:
564 return ENOENT;
565 }
566 }
567 if (type == SYS_RES_IRQ) {
568 if (rid != ATA_IRQ_RID)
569 return ENOENT;
570
571 if (ATA_MASTERDEV(dev)) {
572#ifdef __alpha__
573 return alpha_platform_release_ide_intr(channel, r);
574#else
575 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
576 SYS_RES_IRQ, rid, r);
577#endif
578 }
579 else {
580 /* primary and secondary channels share interrupt, keep track */
581 if (--sc->irqcnt)
582 return 0;
583 sc->irq = 0;
584 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
585 SYS_RES_IRQ, rid, r);
586 }
587 }
588 return EINVAL;
589}
590
591static int
592ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
593 int flags, driver_intr_t *intr, void *arg,
594 void **cookiep)
595{
596 if (ATA_MASTERDEV(dev)) {
597#ifdef __alpha__
598 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
599#else
600 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
601 flags, intr, arg, cookiep);
602#endif
603 }
604 else
605 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
606 flags, intr, arg, cookiep);
607}
608
609static int
610ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
611 void *cookie)
612{
613 if (ATA_MASTERDEV(dev)) {
614#ifdef __alpha__
615 return alpha_platform_teardown_ide_intr(child, irq, cookie);
616#else
617 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
618#endif
619 }
620 else
621 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
622}
623
624static device_method_t ata_pci_methods[] = {
625 /* device interface */
626 DEVMETHOD(device_probe, ata_pci_probe),
627 DEVMETHOD(device_attach, ata_pci_attach),
628 DEVMETHOD(device_shutdown, bus_generic_shutdown),
629 DEVMETHOD(device_suspend, bus_generic_suspend),
630 DEVMETHOD(device_resume, bus_generic_resume),
631
632 /* bus methods */
633 DEVMETHOD(bus_print_child, ata_pci_print_child),
634 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
635 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
636 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
637 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
638 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
639 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
640 { 0, 0 }
641};
642
643static driver_t ata_pci_driver = {
644 "atapci",
645 ata_pci_methods,
646 sizeof(struct ata_pci_softc),
647};
648
649static devclass_t ata_pci_devclass;
650
651DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
652
653static int
654ata_pcisub_probe(device_t dev)
655{
656 struct ata_softc *scp = device_get_softc(dev);
657 device_t *children;
658 int count, i;
659
660 /* find channel number on this controller */
661 device_get_children(device_get_parent(dev), &children, &count);
662 for (i = 0; i < count; i++) {
663 if (children[i] == dev)
664 scp->channel = i;
665 }
666 free(children, M_TEMP);
667 scp->chiptype = pci_get_devid(device_get_parent(dev));
668 scp->intr_func = ata_pci_intr;
669 return ata_probe(dev);
670}
671
672static device_method_t ata_pcisub_methods[] = {
673 /* device interface */
674 DEVMETHOD(device_probe, ata_pcisub_probe),
675 DEVMETHOD(device_attach, ata_attach),
676 DEVMETHOD(device_detach, ata_detach),
677 DEVMETHOD(device_resume, ata_resume),
678 { 0, 0 }
679};
680
681static driver_t ata_pcisub_driver = {
682 "ata",
683 ata_pcisub_methods,
684 sizeof(struct ata_softc),
685};
686
687DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
| 521#endif
522 }
523 else {
524 /* primary and secondary channels share interrupt, keep track */
525 if (!sc->irq)
526 sc->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
527 SYS_RES_IRQ, rid, 0, ~0, 1, flags);
528 sc->irqcnt++;
529 return sc->irq;
530 }
531 }
532 return 0;
533}
534
535static int
536ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
537 struct resource *r)
538{
539 struct ata_pci_softc *sc = device_get_softc(dev);
540 int channel = ((struct ata_softc *)device_get_softc(child))->channel;
541
542 if (type == SYS_RES_IOPORT) {
543 switch (rid) {
544 case ATA_IOADDR_RID:
545 if (ATA_MASTERDEV(dev))
546 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
547 SYS_RES_IOPORT, 0x0, r);
548 else
549 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
550 SYS_RES_IOPORT, 0x10+8*channel, r);
551 break;
552
553 case ATA_ALTADDR_RID:
554 if (ATA_MASTERDEV(dev))
555 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
556 SYS_RES_IOPORT, 0x0, r);
557 else
558 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
559 SYS_RES_IOPORT, 0x14+8*channel, r);
560 break;
561
562 case ATA_BMADDR_RID:
563 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
564 SYS_RES_IOPORT, 0x20, r);
565 default:
566 return ENOENT;
567 }
568 }
569 if (type == SYS_RES_IRQ) {
570 if (rid != ATA_IRQ_RID)
571 return ENOENT;
572
573 if (ATA_MASTERDEV(dev)) {
574#ifdef __alpha__
575 return alpha_platform_release_ide_intr(channel, r);
576#else
577 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
578 SYS_RES_IRQ, rid, r);
579#endif
580 }
581 else {
582 /* primary and secondary channels share interrupt, keep track */
583 if (--sc->irqcnt)
584 return 0;
585 sc->irq = 0;
586 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
587 SYS_RES_IRQ, rid, r);
588 }
589 }
590 return EINVAL;
591}
592
593static int
594ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
595 int flags, driver_intr_t *intr, void *arg,
596 void **cookiep)
597{
598 if (ATA_MASTERDEV(dev)) {
599#ifdef __alpha__
600 return alpha_platform_setup_ide_intr(child, irq, intr, arg, cookiep);
601#else
602 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
603 flags, intr, arg, cookiep);
604#endif
605 }
606 else
607 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
608 flags, intr, arg, cookiep);
609}
610
611static int
612ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
613 void *cookie)
614{
615 if (ATA_MASTERDEV(dev)) {
616#ifdef __alpha__
617 return alpha_platform_teardown_ide_intr(child, irq, cookie);
618#else
619 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
620#endif
621 }
622 else
623 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
624}
625
626static device_method_t ata_pci_methods[] = {
627 /* device interface */
628 DEVMETHOD(device_probe, ata_pci_probe),
629 DEVMETHOD(device_attach, ata_pci_attach),
630 DEVMETHOD(device_shutdown, bus_generic_shutdown),
631 DEVMETHOD(device_suspend, bus_generic_suspend),
632 DEVMETHOD(device_resume, bus_generic_resume),
633
634 /* bus methods */
635 DEVMETHOD(bus_print_child, ata_pci_print_child),
636 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
637 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
638 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
639 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
640 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
641 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
642 { 0, 0 }
643};
644
645static driver_t ata_pci_driver = {
646 "atapci",
647 ata_pci_methods,
648 sizeof(struct ata_pci_softc),
649};
650
651static devclass_t ata_pci_devclass;
652
653DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
654
655static int
656ata_pcisub_probe(device_t dev)
657{
658 struct ata_softc *scp = device_get_softc(dev);
659 device_t *children;
660 int count, i;
661
662 /* find channel number on this controller */
663 device_get_children(device_get_parent(dev), &children, &count);
664 for (i = 0; i < count; i++) {
665 if (children[i] == dev)
666 scp->channel = i;
667 }
668 free(children, M_TEMP);
669 scp->chiptype = pci_get_devid(device_get_parent(dev));
670 scp->intr_func = ata_pci_intr;
671 return ata_probe(dev);
672}
673
674static device_method_t ata_pcisub_methods[] = {
675 /* device interface */
676 DEVMETHOD(device_probe, ata_pcisub_probe),
677 DEVMETHOD(device_attach, ata_attach),
678 DEVMETHOD(device_detach, ata_detach),
679 DEVMETHOD(device_resume, ata_resume),
680 { 0, 0 }
681};
682
683static driver_t ata_pcisub_driver = {
684 "ata",
685 ata_pcisub_methods,
686 sizeof(struct ata_softc),
687};
688
689DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);
|