177 case 0x71998086: /* Intel PIIX4e */ 178 case 0x24218086: /* Intel ICH0 */ 179 if (udmamode >= 2) { 180 int32_t mask48, new48; 181 182 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 183 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 184 if (bootverbose) 185 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 186 (error) ? "failed" : "success"); 187 if (!error) { 188 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 189 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 190 pci_write_config(parent, 0x48, 191 (pci_read_config(parent, 0x48, 4) & 192 ~mask48) | new48, 4); 193 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 194 return; 195 } 196 } 197 /* make sure eventual ATA33 mode from the BIOS is disabled */ 198 pci_write_config(parent, 0x48, 199 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 200 /* FALLTHROUGH */ 201 202 case 0x70108086: /* Intel PIIX3 */ 203 if (wdmamode >= 2 && apiomode >= 4) { 204 int32_t mask40, new40, mask44, new44; 205 206 /* if SITRE not set doit for both channels */ 207 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 208 new40 = pci_read_config(parent, 0x40, 4); 209 new44 = pci_read_config(parent, 0x44, 4); 210 if (!(new40 & 0x00004000)) { 211 new44 &= ~0x0000000f; 212 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 213 } 214 if (!(new40 & 0x40000000)) { 215 new44 &= ~0x000000f0; 216 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 217 } 218 new40 |= 0x40004000; 219 pci_write_config(parent, 0x40, new40, 4); 220 pci_write_config(parent, 0x44, new44, 4); 221 } 222 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 223 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 224 if (bootverbose) 225 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 226 (error) ? "failed" : "success"); 227 if (!error) { 228 if (device == ATA_MASTER) { 229 mask40 = 0x0000330f; 230 new40 = 0x00002307; 231 mask44 = 0; 232 new44 = 0; 233 } 234 else { 235 mask40 = 0x000000f0; 236 new40 = 0x00000070; 237 mask44 = 0x0000000f; 238 new44 = 0x0000000b; 239 } 240 if (scp->channel) { 241 mask40 <<= 16; 242 new40 <<= 16; 243 mask44 <<= 4; 244 new44 <<= 4; 245 } 246 pci_write_config(parent, 0x40, 247 (pci_read_config(parent, 0x40, 4) & ~mask40)| 248 new40, 4); 249 pci_write_config(parent, 0x44, 250 (pci_read_config(parent, 0x44, 4) & ~mask44)| 251 new44, 4); 252 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 253 return; 254 } 255 } 256 /* we could set PIO mode timings, but we assume the BIOS did that */ 257 break; 258 259 case 0x12308086: /* Intel PIIX */ 260 if (wdmamode >= 2 && apiomode >= 4) { 261 int32_t word40; 262 263 word40 = pci_read_config(parent, 0x40, 4); 264 word40 >>= scp->channel * 16; 265 266 /* Check for timing config usable for DMA on controller */ 267 if (!((word40 & 0x3300) == 0x2300 && 268 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 269 break; 270 271 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 272 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 273 if (bootverbose) 274 ata_printf(scp, device, 275 "%s setting WDMA2 on Intel chip\n", 276 (error) ? "failed" : "success"); 277 if (!error) { 278 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 279 return; 280 } 281 } 282 break; 283 284 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 286 if (pci_get_revid(parent) < 0xC2 && 287 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 288 ata_printf(scp, device, 289 "Aladdin: two atapi devices on this channel, no DMA\n"); 290 break; 291 } 292 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 293 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 294 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 295 if (bootverbose) 296 ata_printf(scp, device, 297 "%s setting UDMA5 on Acer chip\n", 298 (error) ? "failed" : "success"); 299 if (!error) { 300 int32_t word54 = pci_read_config(parent, 0x54, 4); 301 302 pci_write_config(parent, 0x4b, 303 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000f0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 310 return; 311 } 312 } 313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 316 if (bootverbose) 317 ata_printf(scp, device, 318 "%s setting UDMA4 on Acer chip\n", 319 (error) ? "failed" : "success"); 320 if (!error) { 321 int32_t word54 = pci_read_config(parent, 0x54, 4); 322 323 pci_write_config(parent, 0x4b, 324 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 325 word54 &= ~(0x000f000f << (devno << 2)); 326 word54 |= (0x00080005 << (devno << 2)); 327 pci_write_config(parent, 0x54, word54, 4); 328 pci_write_config(parent, 0x53, 329 pci_read_config(parent, 0x53, 1) | 0x03, 1); 330 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 331 return; 332 } 333 } 334 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 335 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 336 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 337 if (bootverbose) 338 ata_printf(scp, device, 339 "%s setting UDMA2 on Acer chip\n", 340 (error) ? "failed" : "success"); 341 if (!error) { 342 int32_t word54 = pci_read_config(parent, 0x54, 4); 343 344 word54 &= ~(0x000f000f << (devno << 2)); 345 word54 |= (0x000a0005 << (devno << 2)); 346 pci_write_config(parent, 0x54, word54, 4); 347 pci_write_config(parent, 0x53, 348 pci_read_config(parent, 0x53, 1) | 0x03, 1); 349 scp->flags |= ATA_ATAPI_DMA_RO; 350 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 351 return; 352 } 353 } 354 355 /* make sure eventual UDMA mode from the BIOS is disabled */ 356 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 357 ~(0x0008 << (devno << 2)), 2); 358 359 if (wdmamode >= 2 && apiomode >= 4) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 361 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting WDMA2 on Acer chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53, 368 pci_read_config(parent, 0x53, 1) | 0x03, 1); 369 scp->flags |= ATA_ATAPI_DMA_RO; 370 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 371 return; 372 } 373 } 374 pci_write_config(parent, 0x53, 375 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 376 /* we could set PIO mode timings, but we assume the BIOS did that */ 377 break; 378 379 case 0x74111022: /* AMD 766 */ 380 if (udmamode >= 5) { 381 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 382 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 383 if (bootverbose) 384 ata_printf(scp, device, 385 "%s setting UDMA5 on AMD chip\n", 386 (error) ? "failed" : "success"); 387 if (!error) { 388 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 389 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 390 return; 391 } 392 } 393 /* FALLTHROUGH */ 394 395 case 0x74091022: /* AMD 756 */ 396 if (udmamode >= 4) { 397 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 398 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 399 if (bootverbose) 400 ata_printf(scp, device, 401 "%s setting UDMA4 on AMD chip\n", 402 (error) ? "failed" : "success"); 403 if (!error) { 404 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 405 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 406 return; 407 } 408 } 409 goto via_82c586; 410 411 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 412 if (ata_find_dev(parent, 0x06861106, 0x40) || 413 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 414 if (udmamode >= 5) { 415 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 416 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 417 if (bootverbose) 418 ata_printf(scp, device, 419 "%s setting UDMA5 on VIA chip\n", 420 (error) ? "failed" : "success"); 421 if (!error) { 422 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 423 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 424 return; 425 } 426 } 427 if (udmamode >= 4) { 428 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 429 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 430 if (bootverbose) 431 ata_printf(scp, device, 432 "%s setting UDMA4 on VIA chip\n", 433 (error) ? "failed" : "success"); 434 if (!error) { 435 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 436 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 437 return; 438 } 439 } 440 if (udmamode >= 2) { 441 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 442 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 443 if (bootverbose) 444 ata_printf(scp, device, 445 "%s setting UDMA2 on VIA chip\n", 446 (error) ? "failed" : "success"); 447 if (!error) { 448 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 449 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 450 return; 451 } 452 } 453 } 454 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 455 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 456 if (udmamode >= 4) { 457 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 458 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 459 if (bootverbose) 460 ata_printf(scp, device, 461 "%s setting UDMA4 on VIA chip\n", 462 (error) ? "failed" : "success"); 463 if (!error) { 464 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 465 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 466 return; 467 } 468 } 469 if (udmamode >= 2) { 470 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 471 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 472 if (bootverbose) 473 ata_printf(scp, device, 474 "%s setting UDMA2 on VIA chip\n", 475 (error) ? "failed" : "success"); 476 if (!error) { 477 pci_write_config(parent, 0x53 - devno, 0xea, 1); 478 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 479 return; 480 } 481 } 482 } 483 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 484 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 485via_82c586: 486 if (udmamode >= 2) { 487 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 488 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 489 if (bootverbose) 490 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 491 (error) ? "failed" : "success", 492 ((scp->chiptype == 0x74091022) || 493 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 494 if (!error) { 495 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 496 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 497 return; 498 } 499 } 500 } 501 if (wdmamode >= 2 && apiomode >= 4) { 502 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 503 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 504 if (bootverbose) 505 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 506 (error) ? "failed" : "success", 507 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 508 if (!error) { 509 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 510 pci_write_config(parent, 0x4b - devno, 0x31, 1); 511 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 512 return; 513 } 514 } 515 /* we could set PIO mode timings, but we assume the BIOS did that */ 516 break; 517 518 case 0x55131039: /* SiS 5591 */ 519 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 520 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 521 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 522 if (bootverbose) 523 ata_printf(scp, device, 524 "%s setting UDMA2 on SiS chip\n", 525 (error) ? "failed" : "success"); 526 if (!error) { 527 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 528 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 529 return; 530 } 531 } 532 if (wdmamode >=2 && apiomode >= 4) { 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 534 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, 537 "%s setting WDMA2 on SiS chip\n", 538 (error) ? "failed" : "success"); 539 if (!error) { 540 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 541 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 542 return; 543 } 544 } 545 /* we could set PIO mode timings, but we assume the BIOS did that */ 546 break; 547 548 case 0x06491095: /* CMD 649 ATA100 controller */ 549 if (udmamode >= 5) { 550 u_int8_t umode; 551 552 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 553 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 554 if (bootverbose) 555 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 556 (error) ? "failed" : "success"); 557 if (!error) { 558 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 559 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 560 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 561 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 562 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 563 return; 564 } 565 } 566 /* FALLTHROUGH */ 567 568 case 0x06481095: /* CMD 648 ATA66 controller */ 569 if (udmamode >= 4) { 570 u_int8_t umode; 571 572 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 573 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 574 if (bootverbose) 575 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 576 (error) ? "failed" : "success"); 577 if (!error) { 578 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 579 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 580 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 581 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 582 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 583 return; 584 } 585 } 586 if (udmamode >= 2) { 587 u_int8_t umode; 588 589 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 590 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 593 (error) ? "failed" : "success"); 594 if (!error) { 595 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 596 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 597 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 598 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 599 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 600 return; 601 } 602 } 603 /* make sure eventual UDMA mode from the BIOS is disabled */ 604 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 605 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 606 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 607 /* FALLTHROUGH */ 608 609 case 0x06461095: /* CMD 646 ATA controller */ 610 if (wdmamode >= 2 && apiomode >= 4) { 611 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 613 if (bootverbose) 614 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 615 error ? "failed" : "success"); 616 if (!error) { 617 int32_t offset = (devno < 3) ? (devno << 1) : 7; 618 619 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 620 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 621 return; 622 } 623 } 624 /* we could set PIO mode timings, but we assume the BIOS did that */ 625 break; 626 627 case 0xc6931080: /* Cypress 82c693 ATA controller */ 628 if (wdmamode >= 2 && apiomode >= 4) { 629 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 630 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 631 if (bootverbose) 632 ata_printf(scp, device, 633 "%s setting WDMA2 on Cypress chip\n", 634 error ? "failed" : "success"); 635 if (!error) { 636 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 637 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 638 return; 639 } 640 } 641 /* we could set PIO mode timings, but we assume the BIOS did that */ 642 break; 643 644 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 645 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 646 if (udmamode >= 2) { 647 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 648 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 649 if (bootverbose) 650 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 651 (error) ? "failed" : "success"); 652 if (!error) { 653 cyrix_timing(scp, devno, ATA_UDMA2); 654 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 655 return; 656 } 657 } 658 if (wdmamode >= 2 && apiomode >= 4) { 659 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 660 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 661 if (bootverbose) 662 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 663 (error) ? "failed" : "success"); 664 if (!error) { 665 cyrix_timing(scp, devno, ATA_WDMA2); 666 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 667 return; 668 } 669 } 670 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 671 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 672 ATA_WAIT_READY); 673 if (bootverbose) 674 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 675 (error) ? "failed" : "success", 676 ata_mode2str(ATA_PIO0 + apiomode)); 677 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 678 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 679 return; 680 681 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 682 if (udmamode >= 2) { 683 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 684 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_printf(scp, device, 687 "%s setting UDMA2 on ServerWorks chip\n", 688 (error) ? "failed" : "success"); 689 if (!error) { 690 u_int16_t reg56; 691 692 pci_write_config(parent, 0x54, 693 pci_read_config(parent, 0x54, 1) | 694 (0x01 << devno), 1); 695 reg56 = pci_read_config(parent, 0x56, 2); 696 reg56 &= ~(0xf << (devno * 4)); 697 reg56 |= (0x2 << (devno * 4)); 698 pci_write_config(parent, 0x56, reg56, 2); 699 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 700 return; 701 } 702 } 703 if (wdmamode >= 2 && apiomode >= 4) { 704 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 705 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 706 if (bootverbose) 707 ata_printf(scp, device, 708 "%s setting WDMA2 on ServerWorks chip\n", 709 (error) ? "failed" : "success"); 710 if (!error) { 711 int offset = (scp->channel * 2) + (device == ATA_MASTER); 712 int word44 = pci_read_config(parent, 0x44, 4); 713 714 pci_write_config(parent, 0x54, 715 pci_read_config(parent, 0x54, 1) & 716 ~(0x01 << devno), 1); 717 word44 &= ~(0xff << (offset << 8)); 718 word44 |= (0x20 << (offset << 8)); 719 pci_write_config(parent, 0x44, 0x20, 4); 720 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 721 return; 722 } 723 } 724 /* we could set PIO mode timings, but we assume the BIOS did that */ 725 break; 726 727 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 728 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */ 729 case 0x4d69105a: /* Promise ATA133 controllers */ 730 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 731 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 732 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 733 ATA_UDMA + udmamode, ATA_C_F_SETXFER, 734 ATA_WAIT_READY); 735 if (bootverbose) 736 ata_printf(scp, device, "%s setting %s on Promise chip\n", 737 (error) ? "failed" : "success", 738 ata_mode2str(ATA_UDMA + udmamode)); 739 if (!error) { 740 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode; 741 return; 742 } 743 } 744 if (udmamode >= 2) { 745 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 746 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 747 if (bootverbose) 748 ata_printf(scp, device, "%s setting %s on Promise chip\n", 749 (error) ? "failed" : "success", "UDMA2"); 750 if (!error) { 751 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 752 return; 753 } 754 } 755 if (wdmamode >= 2 && apiomode >= 4) { 756 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 757 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 758 if (bootverbose) 759 ata_printf(scp, device, "%s setting %s on Promise chip\n", 760 (error) ? "failed" : "success", "WDMA2"); 761 if (!error) { 762 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 763 return; 764 } 765 } 766 break; 767 768 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 769 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 770 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 771 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 772 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 773 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 774 if (bootverbose) 775 ata_printf(scp, device, 776 "%s setting UDMA5 on Promise chip\n", 777 (error) ? "failed" : "success"); 778 if (!error) { 779 promise_timing(scp, devno, ATA_UDMA5); 780 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 781 return; 782 } 783 } 784 /* FALLTHROUGH */ 785 786 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 787 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 788 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 789 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 790 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting UDMA4 on Promise chip\n", 794 (error) ? "failed" : "success"); 795 if (!error) { 796 promise_timing(scp, devno, ATA_UDMA4); 797 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 798 return; 799 } 800 } 801 /* FALLTHROUGH */ 802 803 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 804 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 805 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 806 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 807 if (bootverbose) 808 ata_printf(scp, device, 809 "%s setting UDMA2 on Promise chip\n", 810 (error) ? "failed" : "success"); 811 if (!error) { 812 promise_timing(scp, devno, ATA_UDMA2); 813 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 814 return; 815 } 816 } 817 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 818 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 819 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 820 if (bootverbose) 821 ata_printf(scp, device, 822 "%s setting WDMA2 on Promise chip\n", 823 (error) ? "failed" : "success"); 824 if (!error) { 825 promise_timing(scp, devno, ATA_WDMA2); 826 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 827 return; 828 } 829 } 830 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 831 ATA_PIO0 + apiomode, 832 ATA_C_F_SETXFER, ATA_WAIT_READY); 833 if (bootverbose) 834 ata_printf(scp, device, 835 "%s setting PIO%d on Promise chip\n", 836 (error) ? "failed" : "success", 837 (apiomode >= 0) ? apiomode : 0); 838 promise_timing(scp, devno, ATA_PIO0 + apiomode); 839 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 840 return; 841 842 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 843 if (!ATAPI_DEVICE(scp, device) && 844 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 845 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 846 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 847 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 848 if (bootverbose) 849 ata_printf(scp, device, 850 "%s setting UDMA6 on HighPoint chip\n", 851 (error) ? "failed" : "success"); 852 if (!error) { 853 hpt_timing(scp, devno, ATA_UDMA6); 854 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 855 return; 856 } 857 } 858 if (!ATAPI_DEVICE(scp, device) && 859 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 860 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 861 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 862 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 863 if (bootverbose) 864 ata_printf(scp, device, 865 "%s setting UDMA5 on HighPoint chip\n", 866 (error) ? "failed" : "success"); 867 if (!error) { 868 hpt_timing(scp, devno, ATA_UDMA5); 869 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 870 return; 871 } 872 } 873 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 874 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 875 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 876 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 877 if (bootverbose) 878 ata_printf(scp, device, 879 "%s setting UDMA4 on HighPoint chip\n", 880 (error) ? "failed" : "success"); 881 if (!error) { 882 hpt_timing(scp, devno, ATA_UDMA4); 883 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 884 return; 885 } 886 } 887 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 888 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 889 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 890 if (bootverbose) 891 ata_printf(scp, device, 892 "%s setting UDMA2 on HighPoint chip\n", 893 (error) ? "failed" : "success"); 894 if (!error) { 895 hpt_timing(scp, devno, ATA_UDMA2); 896 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 897 return; 898 } 899 } 900 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 901 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 902 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 903 if (bootverbose) 904 ata_printf(scp, device, 905 "%s setting WDMA2 on HighPoint chip\n", 906 (error) ? "failed" : "success"); 907 if (!error) { 908 hpt_timing(scp, devno, ATA_WDMA2); 909 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 910 return; 911 } 912 } 913 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 914 ATA_PIO0 + apiomode, 915 ATA_C_F_SETXFER, ATA_WAIT_READY); 916 if (bootverbose) 917 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 918 (error) ? "failed" : "success", 919 (apiomode >= 0) ? apiomode : 0); 920 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 921 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 922 return; 923 924 default: /* unknown controller chip */ 925 /* better not try generic DMA on ATAPI devices it almost never works */ 926 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 927 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 928 break; 929 930 /* if controller says its setup for DMA take the easy way out */ 931 /* the downside is we dont know what DMA mode we are in */ 932 if ((udmamode >= 0 || wdmamode > 1) && 933 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 934 ((device==ATA_MASTER) ? 935 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 936 scp->mode[ATA_DEV(device)] = ATA_DMA; 937 return; 938 } 939 940 /* well, we have no support for this, but try anyways */ 941 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 942 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 943 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 944 if (bootverbose) 945 ata_printf(scp, device, 946 "%s setting WDMA2 on generic chip\n", 947 (error) ? "failed" : "success"); 948 if (!error) { 949 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 950 return; 951 } 952 } 953 } 954 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 955 ATA_C_F_SETXFER,ATA_WAIT_READY); 956 if (bootverbose) 957 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 958 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 959 if (!error) 960 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 961 else { 962 if (bootverbose) 963 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 964 scp->mode[ATA_DEV(device)] = ATA_PIO; 965 } 966} 967 968int 969ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 970 caddr_t data, int32_t count) 971{ 972 u_int32_t dma_count, dma_base; 973 int i = 0; 974 975 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 976 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 977 return -1; 978 } 979 980 if (!count) { 981 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 982 return -1; 983 } 984 985 dma_base = vtophys(data); 986 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 987 data += dma_count; 988 count -= dma_count; 989 990 while (count) { 991 dmatab[i].base = dma_base; 992 dmatab[i].count = (dma_count & 0xffff); 993 i++; 994 if (i >= ATA_DMA_ENTRIES) { 995 ata_printf(scp, device, "too many segments in DMA table\n"); 996 return -1; 997 } 998 dma_base = vtophys(data); 999 dma_count = min(count, PAGE_SIZE); 1000 data += min(count, PAGE_SIZE); 1001 count -= min(count, PAGE_SIZE); 1002 } 1003 dmatab[i].base = dma_base; 1004 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1005 return 0; 1006} 1007 1008void 1009ata_dmastart(struct ata_softc *scp, int device, 1010 struct ata_dmaentry *dmatab, int dir) 1011{ 1012 scp->flags |= ATA_DMA_ACTIVE; 1013 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1014 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1015 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1016 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1017 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1018 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1019 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1020} 1021 1022int 1023ata_dmadone(struct ata_softc *scp) 1024{ 1025 int error; 1026 1027 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1028 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1029 scp->flags &= ~ATA_DMA_ACTIVE; 1030 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1031 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1032 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1033 return error & ATA_BMSTAT_MASK; 1034} 1035 1036int 1037ata_dmastatus(struct ata_softc *scp) 1038{ 1039 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1040} 1041 1042static void 1043cyrix_timing(struct ata_softc *scp, int devno, int mode) 1044{ 1045 u_int32_t reg20 = 0x0000e132; 1046 u_int32_t reg24 = 0x00017771; 1047 1048 switch (mode) { 1049 case ATA_PIO0: reg20 = 0x0000e132; break; 1050 case ATA_PIO1: reg20 = 0x00018121; break; 1051 case ATA_PIO2: reg20 = 0x00024020; break; 1052 case ATA_PIO3: reg20 = 0x00032010; break; 1053 case ATA_PIO4: reg20 = 0x00040010; break; 1054 case ATA_WDMA2: reg24 = 0x00002020; break; 1055 case ATA_UDMA2: reg24 = 0x00911030; break; 1056 } 1057 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1058 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1059} 1060 1061static void 1062promise_timing(struct ata_softc *scp, int devno, int mode) 1063{ 1064 u_int32_t timing = 0; 1065 struct promise_timing { 1066 u_int8_t pa:4; 1067 u_int8_t prefetch:1; 1068 u_int8_t iordy:1; 1069 u_int8_t errdy:1; 1070 u_int8_t syncin:1; 1071 u_int8_t pb:5; 1072 u_int8_t mb:3; 1073 u_int8_t mc:4; 1074 u_int8_t dmaw:1; 1075 u_int8_t dmar:1; 1076 u_int8_t iordyp:1; 1077 u_int8_t dmarqp:1; 1078 u_int8_t reserved:8; 1079 } *t = (struct promise_timing*)&timing; 1080 1081 t->iordy = 1; t->iordyp = 1; 1082 if (mode >= ATA_DMA) { 1083 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1084 } 1085 1086 switch (scp->chiptype) { 1087 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1088 switch (mode) { 1089 default: 1090 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1091 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1092 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1093 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1094 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1095 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1096 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1097 } 1098 break; 1099 1100 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1101 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1102 case 0x0d30105a: /* Promise OEM ATA 100 */ 1103 switch (mode) { 1104 default: 1105 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1106 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1107 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1108 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1109 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1110 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1111 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1112 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1113 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1114 } 1115 break; 1116 } 1117 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1118} 1119 1120static void 1121hpt_timing(struct ata_softc *scp, int devno, int mode) 1122{ 1123 device_t parent = device_get_parent(scp->dev); 1124 u_int32_t timing; 1125 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1126 switch (mode) { 1127 case ATA_PIO0: timing = 0x0d029d5e; break; 1128 case ATA_PIO1: timing = 0x0d029d26; break; 1129 case ATA_PIO2: timing = 0x0c829ca6; break; 1130 case ATA_PIO3: timing = 0x0c829c84; break; 1131 case ATA_PIO4: timing = 0x0c829c62; break; 1132 case ATA_WDMA2: timing = 0x2c829262; break; 1133 case ATA_UDMA2: timing = 0x1c91dc62; break; 1134 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1135 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1136 case ATA_UDMA6: timing = 0x1c81dc62; break; 1137 default: timing = 0x0d029d5e; 1138 } 1139 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1140 pci_write_config(parent, 0x5b, 0x20, 1); 1141 } 1142 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1143 switch (mode) { 1144 case ATA_PIO0: timing = 0x06914e57; break; 1145 case ATA_PIO1: timing = 0x06914e43; break; 1146 case ATA_PIO2: timing = 0x06514e33; break; 1147 case ATA_PIO3: timing = 0x06514e22; break; 1148 case ATA_PIO4: timing = 0x06514e21; break; 1149 case ATA_WDMA2: timing = 0x26514e21; break; 1150 case ATA_UDMA2: timing = 0x16494e31; break; 1151 case ATA_UDMA4: timing = 0x16454e31; break; 1152 case ATA_UDMA5: timing = 0x16454e31; break; 1153 default: timing = 0x06514e57; 1154 } 1155 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1156 pci_write_config(parent, 0x5b, 0x22, 1); 1157 } 1158 else { /* HPT36[68] */ 1159 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1160 case 0x85: /* 25Mhz */ 1161 switch (mode) { 1162 case ATA_PIO0: timing = 0xc0d08585; break; 1163 case ATA_PIO1: timing = 0xc0d08572; break; 1164 case ATA_PIO2: timing = 0xc0ca8542; break; 1165 case ATA_PIO3: timing = 0xc0ca8532; break; 1166 case ATA_PIO4: timing = 0xc0ca8521; break; 1167 case ATA_WDMA2: timing = 0xa0ca8521; break; 1168 case ATA_UDMA2: timing = 0x90cf8521; break; 1169 case ATA_UDMA4: timing = 0x90c98521; break; 1170 default: timing = 0x01208585; 1171 } 1172 break; 1173 default: 1174 case 0xa7: /* 33MHz */ 1175 switch (mode) { 1176 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1177 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1178 case ATA_PIO2: timing = 0xc0d0a753; break; 1179 case ATA_PIO3: timing = 0xc0c8a742; break; 1180 case ATA_PIO4: timing = 0xc0c8a731; break; 1181 case ATA_WDMA2: timing = 0xa0c8a731; break; 1182 case ATA_UDMA2: timing = 0x90caa731; break; 1183 case ATA_UDMA4: timing = 0x90c9a731; break; 1184 default: timing = 0x0120a7a7; 1185 } 1186 break; 1187 case 0xd9: /* 40Mhz */ 1188 switch (mode) { 1189 case ATA_PIO0: timing = 0xc018d9d9; break; 1190 case ATA_PIO1: timing = 0xc010d9c7; break; 1191 case ATA_PIO2: timing = 0xc010d997; break; 1192 case ATA_PIO3: timing = 0xc010d974; break; 1193 case ATA_PIO4: timing = 0xc008d963; break; 1194 case ATA_WDMA2: timing = 0xa008d943; break; 1195 case ATA_UDMA2: timing = 0x900bd943; break; 1196 case ATA_UDMA4: timing = 0x900fd943; break; 1197 default: timing = 0x0120d9d9; 1198 } 1199 } 1200 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1201 } 1202}
| 181 case 0x71998086: /* Intel PIIX4e */ 182 case 0x24218086: /* Intel ICH0 */ 183 if (udmamode >= 2) { 184 int32_t mask48, new48; 185 186 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 187 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 188 if (bootverbose) 189 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 190 (error) ? "failed" : "success"); 191 if (!error) { 192 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 193 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 194 pci_write_config(parent, 0x48, 195 (pci_read_config(parent, 0x48, 4) & 196 ~mask48) | new48, 4); 197 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 198 return; 199 } 200 } 201 /* make sure eventual ATA33 mode from the BIOS is disabled */ 202 pci_write_config(parent, 0x48, 203 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 204 /* FALLTHROUGH */ 205 206 case 0x70108086: /* Intel PIIX3 */ 207 if (wdmamode >= 2 && apiomode >= 4) { 208 int32_t mask40, new40, mask44, new44; 209 210 /* if SITRE not set doit for both channels */ 211 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 212 new40 = pci_read_config(parent, 0x40, 4); 213 new44 = pci_read_config(parent, 0x44, 4); 214 if (!(new40 & 0x00004000)) { 215 new44 &= ~0x0000000f; 216 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 217 } 218 if (!(new40 & 0x40000000)) { 219 new44 &= ~0x000000f0; 220 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 221 } 222 new40 |= 0x40004000; 223 pci_write_config(parent, 0x40, new40, 4); 224 pci_write_config(parent, 0x44, new44, 4); 225 } 226 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 227 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 228 if (bootverbose) 229 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 230 (error) ? "failed" : "success"); 231 if (!error) { 232 if (device == ATA_MASTER) { 233 mask40 = 0x0000330f; 234 new40 = 0x00002307; 235 mask44 = 0; 236 new44 = 0; 237 } 238 else { 239 mask40 = 0x000000f0; 240 new40 = 0x00000070; 241 mask44 = 0x0000000f; 242 new44 = 0x0000000b; 243 } 244 if (scp->channel) { 245 mask40 <<= 16; 246 new40 <<= 16; 247 mask44 <<= 4; 248 new44 <<= 4; 249 } 250 pci_write_config(parent, 0x40, 251 (pci_read_config(parent, 0x40, 4) & ~mask40)| 252 new40, 4); 253 pci_write_config(parent, 0x44, 254 (pci_read_config(parent, 0x44, 4) & ~mask44)| 255 new44, 4); 256 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 257 return; 258 } 259 } 260 /* we could set PIO mode timings, but we assume the BIOS did that */ 261 break; 262 263 case 0x12308086: /* Intel PIIX */ 264 if (wdmamode >= 2 && apiomode >= 4) { 265 int32_t word40; 266 267 word40 = pci_read_config(parent, 0x40, 4); 268 word40 >>= scp->channel * 16; 269 270 /* Check for timing config usable for DMA on controller */ 271 if (!((word40 & 0x3300) == 0x2300 && 272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 273 break; 274 275 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 277 if (bootverbose) 278 ata_printf(scp, device, 279 "%s setting WDMA2 on Intel chip\n", 280 (error) ? "failed" : "success"); 281 if (!error) { 282 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 283 return; 284 } 285 } 286 break; 287 288 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 289 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 290 if (pci_get_revid(parent) < 0xC2 && 291 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 292 ata_printf(scp, device, 293 "Aladdin: two atapi devices on this channel, no DMA\n"); 294 break; 295 } 296 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 298 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA5 on Acer chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 int32_t word54 = pci_read_config(parent, 0x54, 4); 305 306 pci_write_config(parent, 0x4b, 307 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 308 word54 &= ~(0x000f000f << (devno << 2)); 309 word54 |= (0x000f0005 << (devno << 2)); 310 pci_write_config(parent, 0x54, word54, 4); 311 pci_write_config(parent, 0x53, 312 pci_read_config(parent, 0x53, 1) | 0x03, 1); 313 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 314 return; 315 } 316 } 317 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 318 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 319 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 320 if (bootverbose) 321 ata_printf(scp, device, 322 "%s setting UDMA4 on Acer chip\n", 323 (error) ? "failed" : "success"); 324 if (!error) { 325 int32_t word54 = pci_read_config(parent, 0x54, 4); 326 327 pci_write_config(parent, 0x4b, 328 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 329 word54 &= ~(0x000f000f << (devno << 2)); 330 word54 |= (0x00080005 << (devno << 2)); 331 pci_write_config(parent, 0x54, word54, 4); 332 pci_write_config(parent, 0x53, 333 pci_read_config(parent, 0x53, 1) | 0x03, 1); 334 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 335 return; 336 } 337 } 338 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 339 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 340 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 341 if (bootverbose) 342 ata_printf(scp, device, 343 "%s setting UDMA2 on Acer chip\n", 344 (error) ? "failed" : "success"); 345 if (!error) { 346 int32_t word54 = pci_read_config(parent, 0x54, 4); 347 348 word54 &= ~(0x000f000f << (devno << 2)); 349 word54 |= (0x000a0005 << (devno << 2)); 350 pci_write_config(parent, 0x54, word54, 4); 351 pci_write_config(parent, 0x53, 352 pci_read_config(parent, 0x53, 1) | 0x03, 1); 353 scp->flags |= ATA_ATAPI_DMA_RO; 354 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 355 return; 356 } 357 } 358 359 /* make sure eventual UDMA mode from the BIOS is disabled */ 360 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 361 ~(0x0008 << (devno << 2)), 2); 362 363 if (wdmamode >= 2 && apiomode >= 4) { 364 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 365 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 366 if (bootverbose) 367 ata_printf(scp, device, 368 "%s setting WDMA2 on Acer chip\n", 369 (error) ? "failed" : "success"); 370 if (!error) { 371 pci_write_config(parent, 0x53, 372 pci_read_config(parent, 0x53, 1) | 0x03, 1); 373 scp->flags |= ATA_ATAPI_DMA_RO; 374 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 375 return; 376 } 377 } 378 pci_write_config(parent, 0x53, 379 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 380 /* we could set PIO mode timings, but we assume the BIOS did that */ 381 break; 382 383 case 0x74111022: /* AMD 766 */ 384 if (udmamode >= 5) { 385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 386 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 387 if (bootverbose) 388 ata_printf(scp, device, 389 "%s setting UDMA5 on AMD chip\n", 390 (error) ? "failed" : "success"); 391 if (!error) { 392 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 393 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 394 return; 395 } 396 } 397 /* FALLTHROUGH */ 398 399 case 0x74091022: /* AMD 756 */ 400 if (udmamode >= 4) { 401 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 402 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 403 if (bootverbose) 404 ata_printf(scp, device, 405 "%s setting UDMA4 on AMD chip\n", 406 (error) ? "failed" : "success"); 407 if (!error) { 408 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 409 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 410 return; 411 } 412 } 413 goto via_82c586; 414 415 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 416 if (ata_find_dev(parent, 0x06861106, 0x40) || 417 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 418 if (udmamode >= 5) { 419 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 420 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 421 if (bootverbose) 422 ata_printf(scp, device, 423 "%s setting UDMA5 on VIA chip\n", 424 (error) ? "failed" : "success"); 425 if (!error) { 426 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 427 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 428 return; 429 } 430 } 431 if (udmamode >= 4) { 432 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 433 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 434 if (bootverbose) 435 ata_printf(scp, device, 436 "%s setting UDMA4 on VIA chip\n", 437 (error) ? "failed" : "success"); 438 if (!error) { 439 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 440 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 441 return; 442 } 443 } 444 if (udmamode >= 2) { 445 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 446 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 447 if (bootverbose) 448 ata_printf(scp, device, 449 "%s setting UDMA2 on VIA chip\n", 450 (error) ? "failed" : "success"); 451 if (!error) { 452 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 453 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 454 return; 455 } 456 } 457 } 458 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 459 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 460 if (udmamode >= 4) { 461 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 462 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 463 if (bootverbose) 464 ata_printf(scp, device, 465 "%s setting UDMA4 on VIA chip\n", 466 (error) ? "failed" : "success"); 467 if (!error) { 468 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 469 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 470 return; 471 } 472 } 473 if (udmamode >= 2) { 474 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 475 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 476 if (bootverbose) 477 ata_printf(scp, device, 478 "%s setting UDMA2 on VIA chip\n", 479 (error) ? "failed" : "success"); 480 if (!error) { 481 pci_write_config(parent, 0x53 - devno, 0xea, 1); 482 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 483 return; 484 } 485 } 486 } 487 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 488 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 489via_82c586: 490 if (udmamode >= 2) { 491 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 492 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 493 if (bootverbose) 494 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 495 (error) ? "failed" : "success", 496 ((scp->chiptype == 0x74091022) || 497 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 498 if (!error) { 499 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 500 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 501 return; 502 } 503 } 504 } 505 if (wdmamode >= 2 && apiomode >= 4) { 506 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 507 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 508 if (bootverbose) 509 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 510 (error) ? "failed" : "success", 511 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 512 if (!error) { 513 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 514 pci_write_config(parent, 0x4b - devno, 0x31, 1); 515 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 516 return; 517 } 518 } 519 /* we could set PIO mode timings, but we assume the BIOS did that */ 520 break; 521 522 case 0x55131039: /* SiS 5591 */ 523 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 524 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 525 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 526 if (bootverbose) 527 ata_printf(scp, device, 528 "%s setting UDMA2 on SiS chip\n", 529 (error) ? "failed" : "success"); 530 if (!error) { 531 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 532 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 533 return; 534 } 535 } 536 if (wdmamode >=2 && apiomode >= 4) { 537 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 538 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 539 if (bootverbose) 540 ata_printf(scp, device, 541 "%s setting WDMA2 on SiS chip\n", 542 (error) ? "failed" : "success"); 543 if (!error) { 544 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 545 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 546 return; 547 } 548 } 549 /* we could set PIO mode timings, but we assume the BIOS did that */ 550 break; 551 552 case 0x06491095: /* CMD 649 ATA100 controller */ 553 if (udmamode >= 5) { 554 u_int8_t umode; 555 556 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 557 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 558 if (bootverbose) 559 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 560 (error) ? "failed" : "success"); 561 if (!error) { 562 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 563 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 564 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 565 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 566 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 567 return; 568 } 569 } 570 /* FALLTHROUGH */ 571 572 case 0x06481095: /* CMD 648 ATA66 controller */ 573 if (udmamode >= 4) { 574 u_int8_t umode; 575 576 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 577 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 578 if (bootverbose) 579 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 580 (error) ? "failed" : "success"); 581 if (!error) { 582 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 583 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 584 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 585 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 586 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 587 return; 588 } 589 } 590 if (udmamode >= 2) { 591 u_int8_t umode; 592 593 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 595 if (bootverbose) 596 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 597 (error) ? "failed" : "success"); 598 if (!error) { 599 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 600 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 601 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 602 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 603 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 604 return; 605 } 606 } 607 /* make sure eventual UDMA mode from the BIOS is disabled */ 608 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 609 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 610 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 611 /* FALLTHROUGH */ 612 613 case 0x06461095: /* CMD 646 ATA controller */ 614 if (wdmamode >= 2 && apiomode >= 4) { 615 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 616 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 617 if (bootverbose) 618 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 619 error ? "failed" : "success"); 620 if (!error) { 621 int32_t offset = (devno < 3) ? (devno << 1) : 7; 622 623 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 624 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 625 return; 626 } 627 } 628 /* we could set PIO mode timings, but we assume the BIOS did that */ 629 break; 630 631 case 0xc6931080: /* Cypress 82c693 ATA controller */ 632 if (wdmamode >= 2 && apiomode >= 4) { 633 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 634 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 635 if (bootverbose) 636 ata_printf(scp, device, 637 "%s setting WDMA2 on Cypress chip\n", 638 error ? "failed" : "success"); 639 if (!error) { 640 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 641 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 642 return; 643 } 644 } 645 /* we could set PIO mode timings, but we assume the BIOS did that */ 646 break; 647 648 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 649 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 650 if (udmamode >= 2) { 651 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 652 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 653 if (bootverbose) 654 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 655 (error) ? "failed" : "success"); 656 if (!error) { 657 cyrix_timing(scp, devno, ATA_UDMA2); 658 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 659 return; 660 } 661 } 662 if (wdmamode >= 2 && apiomode >= 4) { 663 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 664 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 665 if (bootverbose) 666 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 667 (error) ? "failed" : "success"); 668 if (!error) { 669 cyrix_timing(scp, devno, ATA_WDMA2); 670 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 671 return; 672 } 673 } 674 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 675 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 676 ATA_WAIT_READY); 677 if (bootverbose) 678 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 679 (error) ? "failed" : "success", 680 ata_mode2str(ATA_PIO0 + apiomode)); 681 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 682 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 683 return; 684 685 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 686 if (udmamode >= 2) { 687 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 688 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 689 if (bootverbose) 690 ata_printf(scp, device, 691 "%s setting UDMA2 on ServerWorks chip\n", 692 (error) ? "failed" : "success"); 693 if (!error) { 694 u_int16_t reg56; 695 696 pci_write_config(parent, 0x54, 697 pci_read_config(parent, 0x54, 1) | 698 (0x01 << devno), 1); 699 reg56 = pci_read_config(parent, 0x56, 2); 700 reg56 &= ~(0xf << (devno * 4)); 701 reg56 |= (0x2 << (devno * 4)); 702 pci_write_config(parent, 0x56, reg56, 2); 703 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 704 return; 705 } 706 } 707 if (wdmamode >= 2 && apiomode >= 4) { 708 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 709 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 710 if (bootverbose) 711 ata_printf(scp, device, 712 "%s setting WDMA2 on ServerWorks chip\n", 713 (error) ? "failed" : "success"); 714 if (!error) { 715 int offset = (scp->channel * 2) + (device == ATA_MASTER); 716 int word44 = pci_read_config(parent, 0x44, 4); 717 718 pci_write_config(parent, 0x54, 719 pci_read_config(parent, 0x54, 1) & 720 ~(0x01 << devno), 1); 721 word44 &= ~(0xff << (offset << 8)); 722 word44 |= (0x20 << (offset << 8)); 723 pci_write_config(parent, 0x44, 0x20, 4); 724 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 725 return; 726 } 727 } 728 /* we could set PIO mode timings, but we assume the BIOS did that */ 729 break; 730 731 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 732 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */ 733 case 0x4d69105a: /* Promise ATA133 controllers */ 734 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 735 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 736 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 737 ATA_UDMA + udmamode, ATA_C_F_SETXFER, 738 ATA_WAIT_READY); 739 if (bootverbose) 740 ata_printf(scp, device, "%s setting %s on Promise chip\n", 741 (error) ? "failed" : "success", 742 ata_mode2str(ATA_UDMA + udmamode)); 743 if (!error) { 744 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode; 745 return; 746 } 747 } 748 if (udmamode >= 2) { 749 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 750 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 751 if (bootverbose) 752 ata_printf(scp, device, "%s setting %s on Promise chip\n", 753 (error) ? "failed" : "success", "UDMA2"); 754 if (!error) { 755 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 756 return; 757 } 758 } 759 if (wdmamode >= 2 && apiomode >= 4) { 760 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 761 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 762 if (bootverbose) 763 ata_printf(scp, device, "%s setting %s on Promise chip\n", 764 (error) ? "failed" : "success", "WDMA2"); 765 if (!error) { 766 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 767 return; 768 } 769 } 770 break; 771 772 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 773 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 774 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 775 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 776 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 777 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 778 if (bootverbose) 779 ata_printf(scp, device, 780 "%s setting UDMA5 on Promise chip\n", 781 (error) ? "failed" : "success"); 782 if (!error) { 783 promise_timing(scp, devno, ATA_UDMA5); 784 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 785 return; 786 } 787 } 788 /* FALLTHROUGH */ 789 790 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 791 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 792 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 793 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 794 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 795 if (bootverbose) 796 ata_printf(scp, device, 797 "%s setting UDMA4 on Promise chip\n", 798 (error) ? "failed" : "success"); 799 if (!error) { 800 promise_timing(scp, devno, ATA_UDMA4); 801 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 802 return; 803 } 804 } 805 /* FALLTHROUGH */ 806 807 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 808 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 809 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 810 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 811 if (bootverbose) 812 ata_printf(scp, device, 813 "%s setting UDMA2 on Promise chip\n", 814 (error) ? "failed" : "success"); 815 if (!error) { 816 promise_timing(scp, devno, ATA_UDMA2); 817 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 818 return; 819 } 820 } 821 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 822 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 823 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 824 if (bootverbose) 825 ata_printf(scp, device, 826 "%s setting WDMA2 on Promise chip\n", 827 (error) ? "failed" : "success"); 828 if (!error) { 829 promise_timing(scp, devno, ATA_WDMA2); 830 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 831 return; 832 } 833 } 834 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 835 ATA_PIO0 + apiomode, 836 ATA_C_F_SETXFER, ATA_WAIT_READY); 837 if (bootverbose) 838 ata_printf(scp, device, 839 "%s setting PIO%d on Promise chip\n", 840 (error) ? "failed" : "success", 841 (apiomode >= 0) ? apiomode : 0); 842 promise_timing(scp, devno, ATA_PIO0 + apiomode); 843 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 844 return; 845 846 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 847 if (!ATAPI_DEVICE(scp, device) && 848 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 849 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 850 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 851 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 852 if (bootverbose) 853 ata_printf(scp, device, 854 "%s setting UDMA6 on HighPoint chip\n", 855 (error) ? "failed" : "success"); 856 if (!error) { 857 hpt_timing(scp, devno, ATA_UDMA6); 858 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 859 return; 860 } 861 } 862 if (!ATAPI_DEVICE(scp, device) && 863 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 864 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 865 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 866 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 867 if (bootverbose) 868 ata_printf(scp, device, 869 "%s setting UDMA5 on HighPoint chip\n", 870 (error) ? "failed" : "success"); 871 if (!error) { 872 hpt_timing(scp, devno, ATA_UDMA5); 873 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 874 return; 875 } 876 } 877 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 878 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 879 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 880 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 881 if (bootverbose) 882 ata_printf(scp, device, 883 "%s setting UDMA4 on HighPoint chip\n", 884 (error) ? "failed" : "success"); 885 if (!error) { 886 hpt_timing(scp, devno, ATA_UDMA4); 887 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 888 return; 889 } 890 } 891 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 892 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 893 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 894 if (bootverbose) 895 ata_printf(scp, device, 896 "%s setting UDMA2 on HighPoint chip\n", 897 (error) ? "failed" : "success"); 898 if (!error) { 899 hpt_timing(scp, devno, ATA_UDMA2); 900 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 901 return; 902 } 903 } 904 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 905 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 906 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 907 if (bootverbose) 908 ata_printf(scp, device, 909 "%s setting WDMA2 on HighPoint chip\n", 910 (error) ? "failed" : "success"); 911 if (!error) { 912 hpt_timing(scp, devno, ATA_WDMA2); 913 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 914 return; 915 } 916 } 917 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 918 ATA_PIO0 + apiomode, 919 ATA_C_F_SETXFER, ATA_WAIT_READY); 920 if (bootverbose) 921 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 922 (error) ? "failed" : "success", 923 (apiomode >= 0) ? apiomode : 0); 924 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 925 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 926 return; 927 928 default: /* unknown controller chip */ 929 /* better not try generic DMA on ATAPI devices it almost never works */ 930 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 931 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 932 break; 933 934 /* if controller says its setup for DMA take the easy way out */ 935 /* the downside is we dont know what DMA mode we are in */ 936 if ((udmamode >= 0 || wdmamode > 1) && 937 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 938 ((device==ATA_MASTER) ? 939 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 940 scp->mode[ATA_DEV(device)] = ATA_DMA; 941 return; 942 } 943 944 /* well, we have no support for this, but try anyways */ 945 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 946 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 947 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 948 if (bootverbose) 949 ata_printf(scp, device, 950 "%s setting WDMA2 on generic chip\n", 951 (error) ? "failed" : "success"); 952 if (!error) { 953 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 954 return; 955 } 956 } 957 } 958 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 959 ATA_C_F_SETXFER,ATA_WAIT_READY); 960 if (bootverbose) 961 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 962 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 963 if (!error) 964 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 965 else { 966 if (bootverbose) 967 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 968 scp->mode[ATA_DEV(device)] = ATA_PIO; 969 } 970} 971 972int 973ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 974 caddr_t data, int32_t count) 975{ 976 u_int32_t dma_count, dma_base; 977 int i = 0; 978 979 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 980 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 981 return -1; 982 } 983 984 if (!count) { 985 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 986 return -1; 987 } 988 989 dma_base = vtophys(data); 990 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 991 data += dma_count; 992 count -= dma_count; 993 994 while (count) { 995 dmatab[i].base = dma_base; 996 dmatab[i].count = (dma_count & 0xffff); 997 i++; 998 if (i >= ATA_DMA_ENTRIES) { 999 ata_printf(scp, device, "too many segments in DMA table\n"); 1000 return -1; 1001 } 1002 dma_base = vtophys(data); 1003 dma_count = min(count, PAGE_SIZE); 1004 data += min(count, PAGE_SIZE); 1005 count -= min(count, PAGE_SIZE); 1006 } 1007 dmatab[i].base = dma_base; 1008 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1009 return 0; 1010} 1011 1012void 1013ata_dmastart(struct ata_softc *scp, int device, 1014 struct ata_dmaentry *dmatab, int dir) 1015{ 1016 scp->flags |= ATA_DMA_ACTIVE; 1017 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1018 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1019 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1020 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1021 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1022 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1023 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1024} 1025 1026int 1027ata_dmadone(struct ata_softc *scp) 1028{ 1029 int error; 1030 1031 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1032 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1033 scp->flags &= ~ATA_DMA_ACTIVE; 1034 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1035 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1036 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1037 return error & ATA_BMSTAT_MASK; 1038} 1039 1040int 1041ata_dmastatus(struct ata_softc *scp) 1042{ 1043 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1044} 1045 1046static void 1047cyrix_timing(struct ata_softc *scp, int devno, int mode) 1048{ 1049 u_int32_t reg20 = 0x0000e132; 1050 u_int32_t reg24 = 0x00017771; 1051 1052 switch (mode) { 1053 case ATA_PIO0: reg20 = 0x0000e132; break; 1054 case ATA_PIO1: reg20 = 0x00018121; break; 1055 case ATA_PIO2: reg20 = 0x00024020; break; 1056 case ATA_PIO3: reg20 = 0x00032010; break; 1057 case ATA_PIO4: reg20 = 0x00040010; break; 1058 case ATA_WDMA2: reg24 = 0x00002020; break; 1059 case ATA_UDMA2: reg24 = 0x00911030; break; 1060 } 1061 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1062 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1063} 1064 1065static void 1066promise_timing(struct ata_softc *scp, int devno, int mode) 1067{ 1068 u_int32_t timing = 0; 1069 struct promise_timing { 1070 u_int8_t pa:4; 1071 u_int8_t prefetch:1; 1072 u_int8_t iordy:1; 1073 u_int8_t errdy:1; 1074 u_int8_t syncin:1; 1075 u_int8_t pb:5; 1076 u_int8_t mb:3; 1077 u_int8_t mc:4; 1078 u_int8_t dmaw:1; 1079 u_int8_t dmar:1; 1080 u_int8_t iordyp:1; 1081 u_int8_t dmarqp:1; 1082 u_int8_t reserved:8; 1083 } *t = (struct promise_timing*)&timing; 1084 1085 t->iordy = 1; t->iordyp = 1; 1086 if (mode >= ATA_DMA) { 1087 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1088 } 1089 1090 switch (scp->chiptype) { 1091 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1092 switch (mode) { 1093 default: 1094 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1095 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1096 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1097 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1098 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1099 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1100 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1101 } 1102 break; 1103 1104 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1105 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1106 case 0x0d30105a: /* Promise OEM ATA 100 */ 1107 switch (mode) { 1108 default: 1109 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1110 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1111 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1112 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1113 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1114 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1115 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1116 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1117 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1118 } 1119 break; 1120 } 1121 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1122} 1123 1124static void 1125hpt_timing(struct ata_softc *scp, int devno, int mode) 1126{ 1127 device_t parent = device_get_parent(scp->dev); 1128 u_int32_t timing; 1129 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1130 switch (mode) { 1131 case ATA_PIO0: timing = 0x0d029d5e; break; 1132 case ATA_PIO1: timing = 0x0d029d26; break; 1133 case ATA_PIO2: timing = 0x0c829ca6; break; 1134 case ATA_PIO3: timing = 0x0c829c84; break; 1135 case ATA_PIO4: timing = 0x0c829c62; break; 1136 case ATA_WDMA2: timing = 0x2c829262; break; 1137 case ATA_UDMA2: timing = 0x1c91dc62; break; 1138 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1139 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1140 case ATA_UDMA6: timing = 0x1c81dc62; break; 1141 default: timing = 0x0d029d5e; 1142 } 1143 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1144 pci_write_config(parent, 0x5b, 0x20, 1); 1145 } 1146 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1147 switch (mode) { 1148 case ATA_PIO0: timing = 0x06914e57; break; 1149 case ATA_PIO1: timing = 0x06914e43; break; 1150 case ATA_PIO2: timing = 0x06514e33; break; 1151 case ATA_PIO3: timing = 0x06514e22; break; 1152 case ATA_PIO4: timing = 0x06514e21; break; 1153 case ATA_WDMA2: timing = 0x26514e21; break; 1154 case ATA_UDMA2: timing = 0x16494e31; break; 1155 case ATA_UDMA4: timing = 0x16454e31; break; 1156 case ATA_UDMA5: timing = 0x16454e31; break; 1157 default: timing = 0x06514e57; 1158 } 1159 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1160 pci_write_config(parent, 0x5b, 0x22, 1); 1161 } 1162 else { /* HPT36[68] */ 1163 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1164 case 0x85: /* 25Mhz */ 1165 switch (mode) { 1166 case ATA_PIO0: timing = 0xc0d08585; break; 1167 case ATA_PIO1: timing = 0xc0d08572; break; 1168 case ATA_PIO2: timing = 0xc0ca8542; break; 1169 case ATA_PIO3: timing = 0xc0ca8532; break; 1170 case ATA_PIO4: timing = 0xc0ca8521; break; 1171 case ATA_WDMA2: timing = 0xa0ca8521; break; 1172 case ATA_UDMA2: timing = 0x90cf8521; break; 1173 case ATA_UDMA4: timing = 0x90c98521; break; 1174 default: timing = 0x01208585; 1175 } 1176 break; 1177 default: 1178 case 0xa7: /* 33MHz */ 1179 switch (mode) { 1180 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1181 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1182 case ATA_PIO2: timing = 0xc0d0a753; break; 1183 case ATA_PIO3: timing = 0xc0c8a742; break; 1184 case ATA_PIO4: timing = 0xc0c8a731; break; 1185 case ATA_WDMA2: timing = 0xa0c8a731; break; 1186 case ATA_UDMA2: timing = 0x90caa731; break; 1187 case ATA_UDMA4: timing = 0x90c9a731; break; 1188 default: timing = 0x0120a7a7; 1189 } 1190 break; 1191 case 0xd9: /* 40Mhz */ 1192 switch (mode) { 1193 case ATA_PIO0: timing = 0xc018d9d9; break; 1194 case ATA_PIO1: timing = 0xc010d9c7; break; 1195 case ATA_PIO2: timing = 0xc010d997; break; 1196 case ATA_PIO3: timing = 0xc010d974; break; 1197 case ATA_PIO4: timing = 0xc008d963; break; 1198 case ATA_WDMA2: timing = 0xa008d943; break; 1199 case ATA_UDMA2: timing = 0x900bd943; break; 1200 case ATA_UDMA4: timing = 0x900fd943; break; 1201 default: timing = 0x0120d9d9; 1202 } 1203 } 1204 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1205 } 1206}
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