112 switch (scp->chiptype) { 113 114 case 0x244a8086: /* Intel ICH2 mobile */ 115 case 0x244b8086: /* Intel ICH2 */ 116 if (udmamode >= 5) { 117 int32_t mask48, new48; 118 int16_t word54; 119 120 word54 = pci_read_config(parent, 0x54, 2); 121 if (word54 & (0x10 << devno)) { 122 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 123 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 124 if (bootverbose) 125 ata_printf(scp, device, 126 "%s setting UDMA5 on Intel chip\n", 127 (error) ? "failed" : "success"); 128 if (!error) { 129 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 130 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 131 pci_write_config(parent, 0x48, 132 (pci_read_config(parent, 0x48, 4) & 133 ~mask48) | new48, 4); 134 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 135 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 136 return; 137 } 138 } 139 } 140 /* make sure eventual ATA100 mode from the BIOS is disabled */ 141 pci_write_config(parent, 0x54, 142 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 143 /* FALLTHROUGH */ 144 145 case 0x24118086: /* Intel ICH */ 146 if (udmamode >= 4) { 147 int32_t mask48, new48; 148 int16_t word54; 149 150 word54 = pci_read_config(parent, 0x54, 2); 151 if (word54 & (0x10 << devno)) { 152 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 153 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 154 if (bootverbose) 155 ata_printf(scp, device, 156 "%s setting UDMA4 on Intel chip\n", 157 (error) ? "failed" : "success"); 158 if (!error) { 159 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 160 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 161 pci_write_config(parent, 0x48, 162 (pci_read_config(parent, 0x48, 4) & 163 ~mask48) | new48, 4); 164 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 165 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 166 return; 167 } 168 } 169 } 170 /* make sure eventual ATA66 mode from the BIOS is disabled */ 171 pci_write_config(parent, 0x54, 172 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 173 /* FALLTHROUGH */ 174 175 case 0x71118086: /* Intel PIIX4 */ 176 case 0x71998086: /* Intel PIIX4e */ 177 case 0x24218086: /* Intel ICH0 */ 178 if (udmamode >= 2) { 179 int32_t mask48, new48; 180 181 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 182 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 183 if (bootverbose) 184 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 185 (error) ? "failed" : "success"); 186 if (!error) { 187 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 188 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 189 pci_write_config(parent, 0x48, 190 (pci_read_config(parent, 0x48, 4) & 191 ~mask48) | new48, 4); 192 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 193 return; 194 } 195 } 196 /* make sure eventual ATA33 mode from the BIOS is disabled */ 197 pci_write_config(parent, 0x48, 198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 199 /* FALLTHROUGH */ 200 201 case 0x70108086: /* Intel PIIX3 */ 202 if (wdmamode >= 2 && apiomode >= 4) { 203 int32_t mask40, new40, mask44, new44; 204 205 /* if SITRE not set doit for both channels */ 206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 207 new40 = pci_read_config(parent, 0x40, 4); 208 new44 = pci_read_config(parent, 0x44, 4); 209 if (!(new40 & 0x00004000)) { 210 new44 &= ~0x0000000f; 211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 212 } 213 if (!(new40 & 0x40000000)) { 214 new44 &= ~0x000000f0; 215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 216 } 217 new40 |= 0x40004000; 218 pci_write_config(parent, 0x40, new40, 4); 219 pci_write_config(parent, 0x44, new44, 4); 220 } 221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 223 if (bootverbose) 224 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 225 (error) ? "failed" : "success"); 226 if (!error) { 227 if (device == ATA_MASTER) { 228 mask40 = 0x0000330f; 229 new40 = 0x00002307; 230 mask44 = 0; 231 new44 = 0; 232 } 233 else { 234 mask40 = 0x000000f0; 235 new40 = 0x00000070; 236 mask44 = 0x0000000f; 237 new44 = 0x0000000b; 238 } 239 if (scp->channel) { 240 mask40 <<= 16; 241 new40 <<= 16; 242 mask44 <<= 4; 243 new44 <<= 4; 244 } 245 pci_write_config(parent, 0x40, 246 (pci_read_config(parent, 0x40, 4) & ~mask40)| 247 new40, 4); 248 pci_write_config(parent, 0x44, 249 (pci_read_config(parent, 0x44, 4) & ~mask44)| 250 new44, 4); 251 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 252 return; 253 } 254 } 255 /* we could set PIO mode timings, but we assume the BIOS did that */ 256 break; 257 258 case 0x12308086: /* Intel PIIX */ 259 if (wdmamode >= 2 && apiomode >= 4) { 260 int32_t word40; 261 262 word40 = pci_read_config(parent, 0x40, 4); 263 word40 >>= scp->channel * 16; 264 265 /* Check for timing config usable for DMA on controller */ 266 if (!((word40 & 0x3300) == 0x2300 && 267 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 268 break; 269 270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 272 if (bootverbose) 273 ata_printf(scp, device, 274 "%s setting WDMA2 on Intel chip\n", 275 (error) ? "failed" : "success"); 276 if (!error) { 277 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 278 return; 279 } 280 } 281 break; 282 283 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 284 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 285 if (pci_get_revid(parent) < 0xC2 && 286 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 287 ata_printf(scp, device, 288 "Aladdin: two atapi devices on this channel, no DMA\n"); 289 break; 290 } 291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 ata_printf(scp, device, 296 "%s setting UDMA5 on Acer chip\n", 297 (error) ? "failed" : "success"); 298 if (!error) { 299 int32_t word54 = pci_read_config(parent, 0x54, 4); 300 301 pci_write_config(parent, 0x4b, 302 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 303 word54 &= ~(0x000f000f << (devno << 2)); 304 word54 |= (0x000f0005 << (devno << 2)); 305 pci_write_config(parent, 0x54, word54, 4); 306 pci_write_config(parent, 0x53, 307 pci_read_config(parent, 0x53, 1) | 0x03, 1); 308 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 309 return; 310 } 311 } 312 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 313 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 314 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 315 if (bootverbose) 316 ata_printf(scp, device, 317 "%s setting UDMA4 on Acer chip\n", 318 (error) ? "failed" : "success"); 319 if (!error) { 320 int32_t word54 = pci_read_config(parent, 0x54, 4); 321 322 pci_write_config(parent, 0x4b, 323 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 324 word54 &= ~(0x000f000f << (devno << 2)); 325 word54 |= (0x00080005 << (devno << 2)); 326 pci_write_config(parent, 0x54, word54, 4); 327 pci_write_config(parent, 0x53, 328 pci_read_config(parent, 0x53, 1) | 0x03, 1); 329 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 330 return; 331 } 332 } 333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 336 if (bootverbose) 337 ata_printf(scp, device, 338 "%s setting UDMA2 on Acer chip\n", 339 (error) ? "failed" : "success"); 340 if (!error) { 341 int32_t word54 = pci_read_config(parent, 0x54, 4); 342 343 word54 &= ~(0x000f000f << (devno << 2)); 344 word54 |= (0x000a0005 << (devno << 2)); 345 pci_write_config(parent, 0x54, word54, 4); 346 pci_write_config(parent, 0x53, 347 pci_read_config(parent, 0x53, 1) | 0x03, 1); 348 scp->flags |= ATA_ATAPI_DMA_RO; 349 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 350 return; 351 } 352 } 353 354 /* make sure eventual UDMA mode from the BIOS is disabled */ 355 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 356 ~(0x0008 << (devno << 2)), 2); 357 358 if (wdmamode >= 2 && apiomode >= 4) { 359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 361 if (bootverbose) 362 ata_printf(scp, device, 363 "%s setting WDMA2 on Acer chip\n", 364 (error) ? "failed" : "success"); 365 if (!error) { 366 pci_write_config(parent, 0x53, 367 pci_read_config(parent, 0x53, 1) | 0x03, 1); 368 scp->flags |= ATA_ATAPI_DMA_RO; 369 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 370 return; 371 } 372 } 373 pci_write_config(parent, 0x53, 374 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 375 /* we could set PIO mode timings, but we assume the BIOS did that */ 376 break; 377 378 case 0x74111022: /* AMD 766 */ 379 if (udmamode >= 5) { 380 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 381 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 382 if (bootverbose) 383 ata_printf(scp, device, 384 "%s setting UDMA5 on AMD chip\n", 385 (error) ? "failed" : "success"); 386 if (!error) { 387 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 388 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 389 return; 390 } 391 } 392 /* FALLTHROUGH */ 393 394 case 0x74091022: /* AMD 756 */ 395 if (udmamode >= 4) { 396 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 397 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 398 if (bootverbose) 399 ata_printf(scp, device, 400 "%s setting UDMA4 on AMD chip\n", 401 (error) ? "failed" : "success"); 402 if (!error) { 403 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 404 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 405 return; 406 } 407 } 408 goto via_82c586; 409 410 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 411 if (ata_find_dev(parent, 0x06861106, 0x40) || 412 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 413 if (udmamode >= 5) { 414 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 415 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 416 if (bootverbose) 417 ata_printf(scp, device, 418 "%s setting UDMA5 on VIA chip\n", 419 (error) ? "failed" : "success"); 420 if (!error) { 421 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 422 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 423 return; 424 } 425 } 426 if (udmamode >= 4) { 427 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 428 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 429 if (bootverbose) 430 ata_printf(scp, device, 431 "%s setting UDMA4 on VIA chip\n", 432 (error) ? "failed" : "success"); 433 if (!error) { 434 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 435 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 436 return; 437 } 438 } 439 if (udmamode >= 2) { 440 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 441 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 442 if (bootverbose) 443 ata_printf(scp, device, 444 "%s setting UDMA2 on VIA chip\n", 445 (error) ? "failed" : "success"); 446 if (!error) { 447 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 448 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 449 return; 450 } 451 } 452 } 453 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 454 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 455 if (udmamode >= 4) { 456 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 457 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 458 if (bootverbose) 459 ata_printf(scp, device, 460 "%s setting UDMA4 on VIA chip\n", 461 (error) ? "failed" : "success"); 462 if (!error) { 463 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 464 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 465 return; 466 } 467 } 468 if (udmamode >= 2) { 469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 470 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 471 if (bootverbose) 472 ata_printf(scp, device, 473 "%s setting UDMA2 on VIA chip\n", 474 (error) ? "failed" : "success"); 475 if (!error) { 476 pci_write_config(parent, 0x53 - devno, 0xea, 1); 477 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 478 return; 479 } 480 } 481 } 482 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 483 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 484via_82c586: 485 if (udmamode >= 2) { 486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 487 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 488 if (bootverbose) 489 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 490 (error) ? "failed" : "success", 491 ((scp->chiptype == 0x74091022) || 492 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 493 if (!error) { 494 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 495 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 496 return; 497 } 498 } 499 } 500 if (wdmamode >= 2 && apiomode >= 4) { 501 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 502 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 503 if (bootverbose) 504 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 505 (error) ? "failed" : "success", 506 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 507 if (!error) { 508 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 509 pci_write_config(parent, 0x4b - devno, 0x31, 1); 510 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 511 return; 512 } 513 } 514 /* we could set PIO mode timings, but we assume the BIOS did that */ 515 break; 516 517 case 0x55131039: /* SiS 5591 */ 518 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 519 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 520 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 521 if (bootverbose) 522 ata_printf(scp, device, 523 "%s setting UDMA2 on SiS chip\n", 524 (error) ? "failed" : "success"); 525 if (!error) { 526 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 527 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 528 return; 529 } 530 } 531 if (wdmamode >=2 && apiomode >= 4) { 532 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 533 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 534 if (bootverbose) 535 ata_printf(scp, device, 536 "%s setting WDMA2 on SiS chip\n", 537 (error) ? "failed" : "success"); 538 if (!error) { 539 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 540 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 541 return; 542 } 543 } 544 /* we could set PIO mode timings, but we assume the BIOS did that */ 545 break; 546 547 case 0x06491095: /* CMD 649 ATA100 controller */ 548 if (udmamode >= 5) { 549 u_int8_t umode; 550 551 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 552 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 553 if (bootverbose) 554 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 555 (error) ? "failed" : "success"); 556 if (!error) { 557 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 558 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 559 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 560 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 561 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 562 return; 563 } 564 } 565 /* FALLTHROUGH */ 566 567 case 0x06481095: /* CMD 648 ATA66 controller */ 568 if (udmamode >= 4) { 569 u_int8_t umode; 570 571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 573 if (bootverbose) 574 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 575 (error) ? "failed" : "success"); 576 if (!error) { 577 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 578 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 579 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 580 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 581 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 582 return; 583 } 584 } 585 if (udmamode >= 2) { 586 u_int8_t umode; 587 588 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 589 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 590 if (bootverbose) 591 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 592 (error) ? "failed" : "success"); 593 if (!error) { 594 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 595 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 596 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 597 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 598 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 599 return; 600 } 601 } 602 /* make sure eventual UDMA mode from the BIOS is disabled */ 603 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 604 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 605 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 606 /* FALLTHROUGH */ 607 608 case 0x06461095: /* CMD 646 ATA controller */ 609 if (wdmamode >= 2 && apiomode >= 4) { 610 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 611 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 612 if (bootverbose) 613 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 614 error ? "failed" : "success"); 615 if (!error) { 616 int32_t offset = (devno < 3) ? (devno << 1) : 7; 617 618 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 619 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 620 return; 621 } 622 } 623 /* we could set PIO mode timings, but we assume the BIOS did that */ 624 break; 625 626 case 0xc6931080: /* Cypress 82c693 ATA controller */ 627 if (wdmamode >= 2 && apiomode >= 4) { 628 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 629 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 630 if (bootverbose) 631 ata_printf(scp, device, 632 "%s setting WDMA2 on Cypress chip\n", 633 error ? "failed" : "success"); 634 if (!error) { 635 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 636 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 637 return; 638 } 639 } 640 /* we could set PIO mode timings, but we assume the BIOS did that */ 641 break; 642 643 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 644 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 645 if (udmamode >= 2) { 646 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 647 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 648 if (bootverbose) 649 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 650 (error) ? "failed" : "success"); 651 if (!error) { 652 cyrix_timing(scp, devno, ATA_UDMA2); 653 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 654 return; 655 } 656 } 657 if (wdmamode >= 2 && apiomode >= 4) { 658 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 659 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 660 if (bootverbose) 661 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 662 (error) ? "failed" : "success"); 663 if (!error) { 664 cyrix_timing(scp, devno, ATA_WDMA2); 665 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 666 return; 667 } 668 } 669 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 670 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 671 ATA_WAIT_READY); 672 if (bootverbose) 673 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 674 (error) ? "failed" : "success", 675 ata_mode2str(ATA_PIO0 + apiomode)); 676 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 677 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 678 return; 679 680 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 681 if (udmamode >= 2) { 682 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 683 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_printf(scp, device, 686 "%s setting UDMA2 on ServerWorks chip\n", 687 (error) ? "failed" : "success"); 688 if (!error) { 689 u_int16_t reg56; 690 691 pci_write_config(parent, 0x54, 692 pci_read_config(parent, 0x54, 1) | 693 (0x01 << devno), 1); 694 reg56 = pci_read_config(parent, 0x56, 2); 695 reg56 &= ~(0xf << (devno * 4)); 696 reg56 |= (0x2 << (devno * 4)); 697 pci_write_config(parent, 0x56, reg56, 2); 698 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 699 return; 700 } 701 } 702 if (wdmamode >= 2 && apiomode >= 4) { 703 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 704 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 705 if (bootverbose) 706 ata_printf(scp, device, 707 "%s setting WDMA2 on ServerWorks chip\n", 708 (error) ? "failed" : "success"); 709 if (!error) { 710 int offset = (scp->channel * 2) + (device == ATA_MASTER); 711 int word44 = pci_read_config(parent, 0x44, 4); 712 713 pci_write_config(parent, 0x54, 714 pci_read_config(parent, 0x54, 1) & 715 ~(0x01 << devno), 1); 716 word44 &= ~(0xff << (offset << 8)); 717 word44 |= (0x20 << (offset << 8)); 718 pci_write_config(parent, 0x44, 0x20, 4); 719 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 720 return; 721 } 722 } 723 /* we could set PIO mode timings, but we assume the BIOS did that */ 724 break; 725 726 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 727 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
| 113 switch (scp->chiptype) { 114 115 case 0x244a8086: /* Intel ICH2 mobile */ 116 case 0x244b8086: /* Intel ICH2 */ 117 if (udmamode >= 5) { 118 int32_t mask48, new48; 119 int16_t word54; 120 121 word54 = pci_read_config(parent, 0x54, 2); 122 if (word54 & (0x10 << devno)) { 123 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 124 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 125 if (bootverbose) 126 ata_printf(scp, device, 127 "%s setting UDMA5 on Intel chip\n", 128 (error) ? "failed" : "success"); 129 if (!error) { 130 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 131 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 132 pci_write_config(parent, 0x48, 133 (pci_read_config(parent, 0x48, 4) & 134 ~mask48) | new48, 4); 135 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 136 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 137 return; 138 } 139 } 140 } 141 /* make sure eventual ATA100 mode from the BIOS is disabled */ 142 pci_write_config(parent, 0x54, 143 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 144 /* FALLTHROUGH */ 145 146 case 0x24118086: /* Intel ICH */ 147 if (udmamode >= 4) { 148 int32_t mask48, new48; 149 int16_t word54; 150 151 word54 = pci_read_config(parent, 0x54, 2); 152 if (word54 & (0x10 << devno)) { 153 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 154 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 155 if (bootverbose) 156 ata_printf(scp, device, 157 "%s setting UDMA4 on Intel chip\n", 158 (error) ? "failed" : "success"); 159 if (!error) { 160 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 161 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 162 pci_write_config(parent, 0x48, 163 (pci_read_config(parent, 0x48, 4) & 164 ~mask48) | new48, 4); 165 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 166 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 167 return; 168 } 169 } 170 } 171 /* make sure eventual ATA66 mode from the BIOS is disabled */ 172 pci_write_config(parent, 0x54, 173 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 174 /* FALLTHROUGH */ 175 176 case 0x71118086: /* Intel PIIX4 */ 177 case 0x71998086: /* Intel PIIX4e */ 178 case 0x24218086: /* Intel ICH0 */ 179 if (udmamode >= 2) { 180 int32_t mask48, new48; 181 182 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 183 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 184 if (bootverbose) 185 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 186 (error) ? "failed" : "success"); 187 if (!error) { 188 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 189 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 190 pci_write_config(parent, 0x48, 191 (pci_read_config(parent, 0x48, 4) & 192 ~mask48) | new48, 4); 193 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 194 return; 195 } 196 } 197 /* make sure eventual ATA33 mode from the BIOS is disabled */ 198 pci_write_config(parent, 0x48, 199 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 200 /* FALLTHROUGH */ 201 202 case 0x70108086: /* Intel PIIX3 */ 203 if (wdmamode >= 2 && apiomode >= 4) { 204 int32_t mask40, new40, mask44, new44; 205 206 /* if SITRE not set doit for both channels */ 207 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 208 new40 = pci_read_config(parent, 0x40, 4); 209 new44 = pci_read_config(parent, 0x44, 4); 210 if (!(new40 & 0x00004000)) { 211 new44 &= ~0x0000000f; 212 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 213 } 214 if (!(new40 & 0x40000000)) { 215 new44 &= ~0x000000f0; 216 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 217 } 218 new40 |= 0x40004000; 219 pci_write_config(parent, 0x40, new40, 4); 220 pci_write_config(parent, 0x44, new44, 4); 221 } 222 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 223 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 224 if (bootverbose) 225 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 226 (error) ? "failed" : "success"); 227 if (!error) { 228 if (device == ATA_MASTER) { 229 mask40 = 0x0000330f; 230 new40 = 0x00002307; 231 mask44 = 0; 232 new44 = 0; 233 } 234 else { 235 mask40 = 0x000000f0; 236 new40 = 0x00000070; 237 mask44 = 0x0000000f; 238 new44 = 0x0000000b; 239 } 240 if (scp->channel) { 241 mask40 <<= 16; 242 new40 <<= 16; 243 mask44 <<= 4; 244 new44 <<= 4; 245 } 246 pci_write_config(parent, 0x40, 247 (pci_read_config(parent, 0x40, 4) & ~mask40)| 248 new40, 4); 249 pci_write_config(parent, 0x44, 250 (pci_read_config(parent, 0x44, 4) & ~mask44)| 251 new44, 4); 252 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 253 return; 254 } 255 } 256 /* we could set PIO mode timings, but we assume the BIOS did that */ 257 break; 258 259 case 0x12308086: /* Intel PIIX */ 260 if (wdmamode >= 2 && apiomode >= 4) { 261 int32_t word40; 262 263 word40 = pci_read_config(parent, 0x40, 4); 264 word40 >>= scp->channel * 16; 265 266 /* Check for timing config usable for DMA on controller */ 267 if (!((word40 & 0x3300) == 0x2300 && 268 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 269 break; 270 271 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 272 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 273 if (bootverbose) 274 ata_printf(scp, device, 275 "%s setting WDMA2 on Intel chip\n", 276 (error) ? "failed" : "success"); 277 if (!error) { 278 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 279 return; 280 } 281 } 282 break; 283 284 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 286 if (pci_get_revid(parent) < 0xC2 && 287 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 288 ata_printf(scp, device, 289 "Aladdin: two atapi devices on this channel, no DMA\n"); 290 break; 291 } 292 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 293 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 294 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 295 if (bootverbose) 296 ata_printf(scp, device, 297 "%s setting UDMA5 on Acer chip\n", 298 (error) ? "failed" : "success"); 299 if (!error) { 300 int32_t word54 = pci_read_config(parent, 0x54, 4); 301 302 pci_write_config(parent, 0x4b, 303 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000f0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 310 return; 311 } 312 } 313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 316 if (bootverbose) 317 ata_printf(scp, device, 318 "%s setting UDMA4 on Acer chip\n", 319 (error) ? "failed" : "success"); 320 if (!error) { 321 int32_t word54 = pci_read_config(parent, 0x54, 4); 322 323 pci_write_config(parent, 0x4b, 324 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 325 word54 &= ~(0x000f000f << (devno << 2)); 326 word54 |= (0x00080005 << (devno << 2)); 327 pci_write_config(parent, 0x54, word54, 4); 328 pci_write_config(parent, 0x53, 329 pci_read_config(parent, 0x53, 1) | 0x03, 1); 330 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 331 return; 332 } 333 } 334 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 335 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 336 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 337 if (bootverbose) 338 ata_printf(scp, device, 339 "%s setting UDMA2 on Acer chip\n", 340 (error) ? "failed" : "success"); 341 if (!error) { 342 int32_t word54 = pci_read_config(parent, 0x54, 4); 343 344 word54 &= ~(0x000f000f << (devno << 2)); 345 word54 |= (0x000a0005 << (devno << 2)); 346 pci_write_config(parent, 0x54, word54, 4); 347 pci_write_config(parent, 0x53, 348 pci_read_config(parent, 0x53, 1) | 0x03, 1); 349 scp->flags |= ATA_ATAPI_DMA_RO; 350 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 351 return; 352 } 353 } 354 355 /* make sure eventual UDMA mode from the BIOS is disabled */ 356 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 357 ~(0x0008 << (devno << 2)), 2); 358 359 if (wdmamode >= 2 && apiomode >= 4) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 361 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting WDMA2 on Acer chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53, 368 pci_read_config(parent, 0x53, 1) | 0x03, 1); 369 scp->flags |= ATA_ATAPI_DMA_RO; 370 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 371 return; 372 } 373 } 374 pci_write_config(parent, 0x53, 375 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 376 /* we could set PIO mode timings, but we assume the BIOS did that */ 377 break; 378 379 case 0x74111022: /* AMD 766 */ 380 if (udmamode >= 5) { 381 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 382 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 383 if (bootverbose) 384 ata_printf(scp, device, 385 "%s setting UDMA5 on AMD chip\n", 386 (error) ? "failed" : "success"); 387 if (!error) { 388 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 389 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 390 return; 391 } 392 } 393 /* FALLTHROUGH */ 394 395 case 0x74091022: /* AMD 756 */ 396 if (udmamode >= 4) { 397 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 398 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 399 if (bootverbose) 400 ata_printf(scp, device, 401 "%s setting UDMA4 on AMD chip\n", 402 (error) ? "failed" : "success"); 403 if (!error) { 404 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 405 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 406 return; 407 } 408 } 409 goto via_82c586; 410 411 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 412 if (ata_find_dev(parent, 0x06861106, 0x40) || 413 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 414 if (udmamode >= 5) { 415 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 416 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 417 if (bootverbose) 418 ata_printf(scp, device, 419 "%s setting UDMA5 on VIA chip\n", 420 (error) ? "failed" : "success"); 421 if (!error) { 422 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 423 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 424 return; 425 } 426 } 427 if (udmamode >= 4) { 428 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 429 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 430 if (bootverbose) 431 ata_printf(scp, device, 432 "%s setting UDMA4 on VIA chip\n", 433 (error) ? "failed" : "success"); 434 if (!error) { 435 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 436 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 437 return; 438 } 439 } 440 if (udmamode >= 2) { 441 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 442 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 443 if (bootverbose) 444 ata_printf(scp, device, 445 "%s setting UDMA2 on VIA chip\n", 446 (error) ? "failed" : "success"); 447 if (!error) { 448 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 449 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 450 return; 451 } 452 } 453 } 454 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 455 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 456 if (udmamode >= 4) { 457 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 458 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 459 if (bootverbose) 460 ata_printf(scp, device, 461 "%s setting UDMA4 on VIA chip\n", 462 (error) ? "failed" : "success"); 463 if (!error) { 464 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 465 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 466 return; 467 } 468 } 469 if (udmamode >= 2) { 470 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 471 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 472 if (bootverbose) 473 ata_printf(scp, device, 474 "%s setting UDMA2 on VIA chip\n", 475 (error) ? "failed" : "success"); 476 if (!error) { 477 pci_write_config(parent, 0x53 - devno, 0xea, 1); 478 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 479 return; 480 } 481 } 482 } 483 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 484 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 485via_82c586: 486 if (udmamode >= 2) { 487 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 488 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 489 if (bootverbose) 490 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 491 (error) ? "failed" : "success", 492 ((scp->chiptype == 0x74091022) || 493 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 494 if (!error) { 495 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 496 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 497 return; 498 } 499 } 500 } 501 if (wdmamode >= 2 && apiomode >= 4) { 502 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 503 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 504 if (bootverbose) 505 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 506 (error) ? "failed" : "success", 507 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 508 if (!error) { 509 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 510 pci_write_config(parent, 0x4b - devno, 0x31, 1); 511 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 512 return; 513 } 514 } 515 /* we could set PIO mode timings, but we assume the BIOS did that */ 516 break; 517 518 case 0x55131039: /* SiS 5591 */ 519 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 520 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 521 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 522 if (bootverbose) 523 ata_printf(scp, device, 524 "%s setting UDMA2 on SiS chip\n", 525 (error) ? "failed" : "success"); 526 if (!error) { 527 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 528 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 529 return; 530 } 531 } 532 if (wdmamode >=2 && apiomode >= 4) { 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 534 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, 537 "%s setting WDMA2 on SiS chip\n", 538 (error) ? "failed" : "success"); 539 if (!error) { 540 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 541 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 542 return; 543 } 544 } 545 /* we could set PIO mode timings, but we assume the BIOS did that */ 546 break; 547 548 case 0x06491095: /* CMD 649 ATA100 controller */ 549 if (udmamode >= 5) { 550 u_int8_t umode; 551 552 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 553 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 554 if (bootverbose) 555 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 556 (error) ? "failed" : "success"); 557 if (!error) { 558 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 559 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 560 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 561 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 562 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 563 return; 564 } 565 } 566 /* FALLTHROUGH */ 567 568 case 0x06481095: /* CMD 648 ATA66 controller */ 569 if (udmamode >= 4) { 570 u_int8_t umode; 571 572 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 573 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 574 if (bootverbose) 575 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 576 (error) ? "failed" : "success"); 577 if (!error) { 578 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 579 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 580 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 581 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 582 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 583 return; 584 } 585 } 586 if (udmamode >= 2) { 587 u_int8_t umode; 588 589 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 590 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 593 (error) ? "failed" : "success"); 594 if (!error) { 595 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 596 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 597 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 598 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 599 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 600 return; 601 } 602 } 603 /* make sure eventual UDMA mode from the BIOS is disabled */ 604 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 605 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 606 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 607 /* FALLTHROUGH */ 608 609 case 0x06461095: /* CMD 646 ATA controller */ 610 if (wdmamode >= 2 && apiomode >= 4) { 611 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 613 if (bootverbose) 614 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 615 error ? "failed" : "success"); 616 if (!error) { 617 int32_t offset = (devno < 3) ? (devno << 1) : 7; 618 619 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 620 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 621 return; 622 } 623 } 624 /* we could set PIO mode timings, but we assume the BIOS did that */ 625 break; 626 627 case 0xc6931080: /* Cypress 82c693 ATA controller */ 628 if (wdmamode >= 2 && apiomode >= 4) { 629 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 630 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 631 if (bootverbose) 632 ata_printf(scp, device, 633 "%s setting WDMA2 on Cypress chip\n", 634 error ? "failed" : "success"); 635 if (!error) { 636 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 637 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 638 return; 639 } 640 } 641 /* we could set PIO mode timings, but we assume the BIOS did that */ 642 break; 643 644 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 645 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 646 if (udmamode >= 2) { 647 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 648 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 649 if (bootverbose) 650 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 651 (error) ? "failed" : "success"); 652 if (!error) { 653 cyrix_timing(scp, devno, ATA_UDMA2); 654 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 655 return; 656 } 657 } 658 if (wdmamode >= 2 && apiomode >= 4) { 659 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 660 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 661 if (bootverbose) 662 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 663 (error) ? "failed" : "success"); 664 if (!error) { 665 cyrix_timing(scp, devno, ATA_WDMA2); 666 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 667 return; 668 } 669 } 670 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 671 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 672 ATA_WAIT_READY); 673 if (bootverbose) 674 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 675 (error) ? "failed" : "success", 676 ata_mode2str(ATA_PIO0 + apiomode)); 677 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 678 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 679 return; 680 681 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 682 if (udmamode >= 2) { 683 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 684 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_printf(scp, device, 687 "%s setting UDMA2 on ServerWorks chip\n", 688 (error) ? "failed" : "success"); 689 if (!error) { 690 u_int16_t reg56; 691 692 pci_write_config(parent, 0x54, 693 pci_read_config(parent, 0x54, 1) | 694 (0x01 << devno), 1); 695 reg56 = pci_read_config(parent, 0x56, 2); 696 reg56 &= ~(0xf << (devno * 4)); 697 reg56 |= (0x2 << (devno * 4)); 698 pci_write_config(parent, 0x56, reg56, 2); 699 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 700 return; 701 } 702 } 703 if (wdmamode >= 2 && apiomode >= 4) { 704 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 705 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 706 if (bootverbose) 707 ata_printf(scp, device, 708 "%s setting WDMA2 on ServerWorks chip\n", 709 (error) ? "failed" : "success"); 710 if (!error) { 711 int offset = (scp->channel * 2) + (device == ATA_MASTER); 712 int word44 = pci_read_config(parent, 0x44, 4); 713 714 pci_write_config(parent, 0x54, 715 pci_read_config(parent, 0x54, 1) & 716 ~(0x01 << devno), 1); 717 word44 &= ~(0xff << (offset << 8)); 718 word44 |= (0x20 << (offset << 8)); 719 pci_write_config(parent, 0x44, 0x20, 4); 720 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 721 return; 722 } 723 } 724 /* we could set PIO mode timings, but we assume the BIOS did that */ 725 break; 726 727 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 728 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
|
739 return; 740 } 741 } 742 if (udmamode >= 2) { 743 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 744 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 745 if (bootverbose) 746 ata_printf(scp, device, "%s setting %s on Promise chip\n", 747 (error) ? "failed" : "success", "UDMA2"); 748 if (!error) { 749 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 750 return; 751 } 752 } 753 if (wdmamode >= 2 && apiomode >= 4) { 754 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 755 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 756 if (bootverbose) 757 ata_printf(scp, device, "%s setting %s on Promise chip\n", 758 (error) ? "failed" : "success", "WDMA2"); 759 if (!error) { 760 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 761 return; 762 } 763 } 764 break; 765 766 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 767 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 768 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 769 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 770 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 771 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 772 if (bootverbose) 773 ata_printf(scp, device, 774 "%s setting UDMA5 on Promise chip\n", 775 (error) ? "failed" : "success"); 776 if (!error) { 777 promise_timing(scp, devno, ATA_UDMA5); 778 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 779 return; 780 } 781 } 782 /* FALLTHROUGH */ 783 784 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 785 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 786 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 787 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 788 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 789 if (bootverbose) 790 ata_printf(scp, device, 791 "%s setting UDMA4 on Promise chip\n", 792 (error) ? "failed" : "success"); 793 if (!error) { 794 promise_timing(scp, devno, ATA_UDMA4); 795 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 796 return; 797 } 798 } 799 /* FALLTHROUGH */ 800 801 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 802 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 803 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 804 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 805 if (bootverbose) 806 ata_printf(scp, device, 807 "%s setting UDMA2 on Promise chip\n", 808 (error) ? "failed" : "success"); 809 if (!error) { 810 promise_timing(scp, devno, ATA_UDMA2); 811 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 812 return; 813 } 814 } 815 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 816 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 817 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 818 if (bootverbose) 819 ata_printf(scp, device, 820 "%s setting WDMA2 on Promise chip\n", 821 (error) ? "failed" : "success"); 822 if (!error) { 823 promise_timing(scp, devno, ATA_WDMA2); 824 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 825 return; 826 } 827 } 828 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 829 ATA_PIO0 + apiomode, 830 ATA_C_F_SETXFER, ATA_WAIT_READY); 831 if (bootverbose) 832 ata_printf(scp, device, 833 "%s setting PIO%d on Promise chip\n", 834 (error) ? "failed" : "success", 835 (apiomode >= 0) ? apiomode : 0); 836 promise_timing(scp, devno, ATA_PIO0 + apiomode); 837 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 838 return; 839 840 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 841 if (!ATAPI_DEVICE(scp, device) && 842 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 843 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 844 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 845 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 846 if (bootverbose) 847 ata_printf(scp, device, 848 "%s setting UDMA5 on HighPoint chip\n", 849 (error) ? "failed" : "success"); 850 if (!error) { 851 hpt_timing(scp, devno, ATA_UDMA5); 852 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 853 return; 854 } 855 } 856 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 857 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 858 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 859 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 860 if (bootverbose) 861 ata_printf(scp, device, 862 "%s setting UDMA4 on HighPoint chip\n", 863 (error) ? "failed" : "success"); 864 if (!error) { 865 hpt_timing(scp, devno, ATA_UDMA4); 866 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 867 return; 868 } 869 } 870 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 871 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 872 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 873 if (bootverbose) 874 ata_printf(scp, device, 875 "%s setting UDMA2 on HighPoint chip\n", 876 (error) ? "failed" : "success"); 877 if (!error) { 878 hpt_timing(scp, devno, ATA_UDMA2); 879 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 880 return; 881 } 882 } 883 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 884 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 885 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 886 if (bootverbose) 887 ata_printf(scp, device, 888 "%s setting WDMA2 on HighPoint chip\n", 889 (error) ? "failed" : "success"); 890 if (!error) { 891 hpt_timing(scp, devno, ATA_WDMA2); 892 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 893 return; 894 } 895 } 896 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 897 ATA_PIO0 + apiomode, 898 ATA_C_F_SETXFER, ATA_WAIT_READY); 899 if (bootverbose) 900 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 901 (error) ? "failed" : "success", 902 (apiomode >= 0) ? apiomode : 0); 903 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 904 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 905 return; 906 907 default: /* unknown controller chip */ 908 /* better not try generic DMA on ATAPI devices it almost never works */ 909 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 910 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 911 break; 912 913 /* if controller says its setup for DMA take the easy way out */ 914 /* the downside is we dont know what DMA mode we are in */ 915 if ((udmamode >= 0 || wdmamode > 1) && 916 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 917 ((device==ATA_MASTER) ? 918 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 919 scp->mode[ATA_DEV(device)] = ATA_DMA; 920 return; 921 } 922 923 /* well, we have no support for this, but try anyways */ 924 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 925 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 926 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 927 if (bootverbose) 928 ata_printf(scp, device, 929 "%s setting WDMA2 on generic chip\n", 930 (error) ? "failed" : "success"); 931 if (!error) { 932 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 933 return; 934 } 935 } 936 } 937 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 938 ATA_C_F_SETXFER,ATA_WAIT_READY); 939 if (bootverbose) 940 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 941 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 942 if (!error) 943 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 944 else { 945 if (bootverbose) 946 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 947 scp->mode[ATA_DEV(device)] = ATA_PIO; 948 } 949} 950 951int 952ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 953 caddr_t data, int32_t count) 954{ 955 u_int32_t dma_count, dma_base; 956 int i = 0; 957 958 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 959 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 960 return -1; 961 } 962 963 if (!count) { 964 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 965 return -1; 966 } 967 968 dma_base = vtophys(data); 969 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 970 data += dma_count; 971 count -= dma_count; 972 973 while (count) { 974 dmatab[i].base = dma_base; 975 dmatab[i].count = (dma_count & 0xffff); 976 i++; 977 if (i >= ATA_DMA_ENTRIES) { 978 ata_printf(scp, device, "too many segments in DMA table\n"); 979 return -1; 980 } 981 dma_base = vtophys(data); 982 dma_count = min(count, PAGE_SIZE); 983 data += min(count, PAGE_SIZE); 984 count -= min(count, PAGE_SIZE); 985 } 986 dmatab[i].base = dma_base; 987 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 988 return 0; 989} 990 991void 992ata_dmastart(struct ata_softc *scp, int device, 993 struct ata_dmaentry *dmatab, int dir) 994{ 995 scp->flags |= ATA_DMA_ACTIVE; 996 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 997 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 998 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 999 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1000 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1001 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1002 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1003} 1004 1005int 1006ata_dmadone(struct ata_softc *scp) 1007{ 1008 int error; 1009 1010 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1011 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1012 scp->flags &= ~ATA_DMA_ACTIVE; 1013 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1014 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1015 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1016 return error & ATA_BMSTAT_MASK; 1017} 1018 1019int 1020ata_dmastatus(struct ata_softc *scp) 1021{ 1022 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1023} 1024 1025static void 1026cyrix_timing(struct ata_softc *scp, int devno, int mode) 1027{ 1028 u_int32_t reg20 = 0x0000e132; 1029 u_int32_t reg24 = 0x00017771; 1030 1031 switch (mode) { 1032 case ATA_PIO0: reg20 = 0x0000e132; break; 1033 case ATA_PIO1: reg20 = 0x00018121; break; 1034 case ATA_PIO2: reg20 = 0x00024020; break; 1035 case ATA_PIO3: reg20 = 0x00032010; break; 1036 case ATA_PIO4: reg20 = 0x00040010; break; 1037 case ATA_WDMA2: reg24 = 0x00002020; break; 1038 case ATA_UDMA2: reg24 = 0x00911030; break; 1039 } 1040 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1041 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1042} 1043 1044static void 1045promise_timing(struct ata_softc *scp, int devno, int mode) 1046{ 1047 u_int32_t timing = 0; 1048 struct promise_timing { 1049 u_int8_t pa:4; 1050 u_int8_t prefetch:1; 1051 u_int8_t iordy:1; 1052 u_int8_t errdy:1; 1053 u_int8_t syncin:1; 1054 u_int8_t pb:5; 1055 u_int8_t mb:3; 1056 u_int8_t mc:4; 1057 u_int8_t dmaw:1; 1058 u_int8_t dmar:1; 1059 u_int8_t iordyp:1; 1060 u_int8_t dmarqp:1; 1061 u_int8_t reserved:8; 1062 } *t = (struct promise_timing*)&timing; 1063 1064 t->iordy = 1; t->iordyp = 1; 1065 if (mode >= ATA_DMA) { 1066 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1067 } 1068 1069 switch (scp->chiptype) { 1070 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1071 switch (mode) { 1072 default: 1073 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1074 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1075 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1076 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1077 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1078 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1079 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1080 } 1081 break; 1082 1083 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1084 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1085 case 0x0d30105a: /* Promise OEM ATA 100 */ 1086 switch (mode) { 1087 default: 1088 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1089 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1090 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1091 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1092 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1093 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1094 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1095 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1096 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1097 } 1098 break; 1099 } 1100 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1101} 1102 1103static void 1104hpt_timing(struct ata_softc *scp, int devno, int mode) 1105{ 1106 device_t parent = device_get_parent(scp->dev); 1107 u_int32_t timing; 1108 1109 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1110 switch (mode) { 1111 case ATA_PIO0: timing = 0x06914e57; break; 1112 case ATA_PIO1: timing = 0x06914e43; break; 1113 case ATA_PIO2: timing = 0x06514e33; break; 1114 case ATA_PIO3: timing = 0x06514e22; break; 1115 case ATA_PIO4: timing = 0x06514e21; break; 1116 case ATA_WDMA2: timing = 0x26514e21; break; 1117 case ATA_UDMA2: timing = 0x16494e31; break; 1118 case ATA_UDMA4: timing = 0x16454e31; break; 1119 case ATA_UDMA5: timing = 0x16454e31; break; 1120 default: timing = 0x06514e57; 1121 } 1122 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1123 pci_write_config(parent, 0x5b, 0x22, 1); 1124 } 1125 else { /* HPT36[68] */ 1126 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1127 case 0x85: /* 25Mhz */ 1128 switch (mode) { 1129 case ATA_PIO0: timing = 0xc0d08585; break; 1130 case ATA_PIO1: timing = 0xc0d08572; break; 1131 case ATA_PIO2: timing = 0xc0ca8542; break; 1132 case ATA_PIO3: timing = 0xc0ca8532; break; 1133 case ATA_PIO4: timing = 0xc0ca8521; break; 1134 case ATA_WDMA2: timing = 0xa0ca8521; break; 1135 case ATA_UDMA2: timing = 0x90cf8521; break; 1136 case ATA_UDMA4: timing = 0x90c98521; break; 1137 default: timing = 0x01208585; 1138 } 1139 break; 1140 default: 1141 case 0xa7: /* 33MHz */ 1142 switch (mode) { 1143 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1144 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1145 case ATA_PIO2: timing = 0xc0d0a753; break; 1146 case ATA_PIO3: timing = 0xc0c8a742; break; 1147 case ATA_PIO4: timing = 0xc0c8a731; break; 1148 case ATA_WDMA2: timing = 0xa0c8a731; break; 1149 case ATA_UDMA2: timing = 0x90caa731; break; 1150 case ATA_UDMA4: timing = 0x90c9a731; break; 1151 default: timing = 0x0120a7a7; 1152 } 1153 break; 1154 case 0xd9: /* 40Mhz */ 1155 switch (mode) { 1156 case ATA_PIO0: timing = 0xc018d9d9; break; 1157 case ATA_PIO1: timing = 0xc010d9c7; break; 1158 case ATA_PIO2: timing = 0xc010d997; break; 1159 case ATA_PIO3: timing = 0xc010d974; break; 1160 case ATA_PIO4: timing = 0xc008d963; break; 1161 case ATA_WDMA2: timing = 0xa008d943; break; 1162 case ATA_UDMA2: timing = 0x900bd943; break; 1163 case ATA_UDMA4: timing = 0x900fd943; break; 1164 default: timing = 0x0120d9d9; 1165 } 1166 } 1167 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1168 } 1169}
| 741 return; 742 } 743 } 744 if (udmamode >= 2) { 745 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 746 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 747 if (bootverbose) 748 ata_printf(scp, device, "%s setting %s on Promise chip\n", 749 (error) ? "failed" : "success", "UDMA2"); 750 if (!error) { 751 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 752 return; 753 } 754 } 755 if (wdmamode >= 2 && apiomode >= 4) { 756 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 757 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 758 if (bootverbose) 759 ata_printf(scp, device, "%s setting %s on Promise chip\n", 760 (error) ? "failed" : "success", "WDMA2"); 761 if (!error) { 762 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 763 return; 764 } 765 } 766 break; 767 768 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 769 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 770 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 771 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 772 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 773 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 774 if (bootverbose) 775 ata_printf(scp, device, 776 "%s setting UDMA5 on Promise chip\n", 777 (error) ? "failed" : "success"); 778 if (!error) { 779 promise_timing(scp, devno, ATA_UDMA5); 780 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 781 return; 782 } 783 } 784 /* FALLTHROUGH */ 785 786 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 787 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 788 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 789 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 790 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting UDMA4 on Promise chip\n", 794 (error) ? "failed" : "success"); 795 if (!error) { 796 promise_timing(scp, devno, ATA_UDMA4); 797 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 798 return; 799 } 800 } 801 /* FALLTHROUGH */ 802 803 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 804 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 805 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 806 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 807 if (bootverbose) 808 ata_printf(scp, device, 809 "%s setting UDMA2 on Promise chip\n", 810 (error) ? "failed" : "success"); 811 if (!error) { 812 promise_timing(scp, devno, ATA_UDMA2); 813 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 814 return; 815 } 816 } 817 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 818 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 819 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 820 if (bootverbose) 821 ata_printf(scp, device, 822 "%s setting WDMA2 on Promise chip\n", 823 (error) ? "failed" : "success"); 824 if (!error) { 825 promise_timing(scp, devno, ATA_WDMA2); 826 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 827 return; 828 } 829 } 830 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 831 ATA_PIO0 + apiomode, 832 ATA_C_F_SETXFER, ATA_WAIT_READY); 833 if (bootverbose) 834 ata_printf(scp, device, 835 "%s setting PIO%d on Promise chip\n", 836 (error) ? "failed" : "success", 837 (apiomode >= 0) ? apiomode : 0); 838 promise_timing(scp, devno, ATA_PIO0 + apiomode); 839 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 840 return; 841 842 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 843 if (!ATAPI_DEVICE(scp, device) && 844 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 845 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 846 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 847 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 848 if (bootverbose) 849 ata_printf(scp, device, 850 "%s setting UDMA5 on HighPoint chip\n", 851 (error) ? "failed" : "success"); 852 if (!error) { 853 hpt_timing(scp, devno, ATA_UDMA5); 854 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 855 return; 856 } 857 } 858 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 859 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 860 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 861 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 862 if (bootverbose) 863 ata_printf(scp, device, 864 "%s setting UDMA4 on HighPoint chip\n", 865 (error) ? "failed" : "success"); 866 if (!error) { 867 hpt_timing(scp, devno, ATA_UDMA4); 868 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 869 return; 870 } 871 } 872 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 873 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 874 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 875 if (bootverbose) 876 ata_printf(scp, device, 877 "%s setting UDMA2 on HighPoint chip\n", 878 (error) ? "failed" : "success"); 879 if (!error) { 880 hpt_timing(scp, devno, ATA_UDMA2); 881 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 882 return; 883 } 884 } 885 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 886 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 887 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 888 if (bootverbose) 889 ata_printf(scp, device, 890 "%s setting WDMA2 on HighPoint chip\n", 891 (error) ? "failed" : "success"); 892 if (!error) { 893 hpt_timing(scp, devno, ATA_WDMA2); 894 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 895 return; 896 } 897 } 898 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 899 ATA_PIO0 + apiomode, 900 ATA_C_F_SETXFER, ATA_WAIT_READY); 901 if (bootverbose) 902 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 903 (error) ? "failed" : "success", 904 (apiomode >= 0) ? apiomode : 0); 905 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 906 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 907 return; 908 909 default: /* unknown controller chip */ 910 /* better not try generic DMA on ATAPI devices it almost never works */ 911 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 912 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 913 break; 914 915 /* if controller says its setup for DMA take the easy way out */ 916 /* the downside is we dont know what DMA mode we are in */ 917 if ((udmamode >= 0 || wdmamode > 1) && 918 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 919 ((device==ATA_MASTER) ? 920 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 921 scp->mode[ATA_DEV(device)] = ATA_DMA; 922 return; 923 } 924 925 /* well, we have no support for this, but try anyways */ 926 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 927 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 928 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 929 if (bootverbose) 930 ata_printf(scp, device, 931 "%s setting WDMA2 on generic chip\n", 932 (error) ? "failed" : "success"); 933 if (!error) { 934 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 935 return; 936 } 937 } 938 } 939 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 940 ATA_C_F_SETXFER,ATA_WAIT_READY); 941 if (bootverbose) 942 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 943 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 944 if (!error) 945 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 946 else { 947 if (bootverbose) 948 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 949 scp->mode[ATA_DEV(device)] = ATA_PIO; 950 } 951} 952 953int 954ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 955 caddr_t data, int32_t count) 956{ 957 u_int32_t dma_count, dma_base; 958 int i = 0; 959 960 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 961 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 962 return -1; 963 } 964 965 if (!count) { 966 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 967 return -1; 968 } 969 970 dma_base = vtophys(data); 971 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 972 data += dma_count; 973 count -= dma_count; 974 975 while (count) { 976 dmatab[i].base = dma_base; 977 dmatab[i].count = (dma_count & 0xffff); 978 i++; 979 if (i >= ATA_DMA_ENTRIES) { 980 ata_printf(scp, device, "too many segments in DMA table\n"); 981 return -1; 982 } 983 dma_base = vtophys(data); 984 dma_count = min(count, PAGE_SIZE); 985 data += min(count, PAGE_SIZE); 986 count -= min(count, PAGE_SIZE); 987 } 988 dmatab[i].base = dma_base; 989 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 990 return 0; 991} 992 993void 994ata_dmastart(struct ata_softc *scp, int device, 995 struct ata_dmaentry *dmatab, int dir) 996{ 997 scp->flags |= ATA_DMA_ACTIVE; 998 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 999 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1000 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1001 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1002 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1003 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1004 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1005} 1006 1007int 1008ata_dmadone(struct ata_softc *scp) 1009{ 1010 int error; 1011 1012 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1013 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1014 scp->flags &= ~ATA_DMA_ACTIVE; 1015 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1016 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1017 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1018 return error & ATA_BMSTAT_MASK; 1019} 1020 1021int 1022ata_dmastatus(struct ata_softc *scp) 1023{ 1024 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1025} 1026 1027static void 1028cyrix_timing(struct ata_softc *scp, int devno, int mode) 1029{ 1030 u_int32_t reg20 = 0x0000e132; 1031 u_int32_t reg24 = 0x00017771; 1032 1033 switch (mode) { 1034 case ATA_PIO0: reg20 = 0x0000e132; break; 1035 case ATA_PIO1: reg20 = 0x00018121; break; 1036 case ATA_PIO2: reg20 = 0x00024020; break; 1037 case ATA_PIO3: reg20 = 0x00032010; break; 1038 case ATA_PIO4: reg20 = 0x00040010; break; 1039 case ATA_WDMA2: reg24 = 0x00002020; break; 1040 case ATA_UDMA2: reg24 = 0x00911030; break; 1041 } 1042 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1043 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1044} 1045 1046static void 1047promise_timing(struct ata_softc *scp, int devno, int mode) 1048{ 1049 u_int32_t timing = 0; 1050 struct promise_timing { 1051 u_int8_t pa:4; 1052 u_int8_t prefetch:1; 1053 u_int8_t iordy:1; 1054 u_int8_t errdy:1; 1055 u_int8_t syncin:1; 1056 u_int8_t pb:5; 1057 u_int8_t mb:3; 1058 u_int8_t mc:4; 1059 u_int8_t dmaw:1; 1060 u_int8_t dmar:1; 1061 u_int8_t iordyp:1; 1062 u_int8_t dmarqp:1; 1063 u_int8_t reserved:8; 1064 } *t = (struct promise_timing*)&timing; 1065 1066 t->iordy = 1; t->iordyp = 1; 1067 if (mode >= ATA_DMA) { 1068 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1069 } 1070 1071 switch (scp->chiptype) { 1072 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1073 switch (mode) { 1074 default: 1075 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1076 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1077 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1078 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1079 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1080 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1081 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1082 } 1083 break; 1084 1085 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1086 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1087 case 0x0d30105a: /* Promise OEM ATA 100 */ 1088 switch (mode) { 1089 default: 1090 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1091 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1092 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1093 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1094 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1095 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1096 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1097 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1098 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1099 } 1100 break; 1101 } 1102 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1103} 1104 1105static void 1106hpt_timing(struct ata_softc *scp, int devno, int mode) 1107{ 1108 device_t parent = device_get_parent(scp->dev); 1109 u_int32_t timing; 1110 1111 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1112 switch (mode) { 1113 case ATA_PIO0: timing = 0x06914e57; break; 1114 case ATA_PIO1: timing = 0x06914e43; break; 1115 case ATA_PIO2: timing = 0x06514e33; break; 1116 case ATA_PIO3: timing = 0x06514e22; break; 1117 case ATA_PIO4: timing = 0x06514e21; break; 1118 case ATA_WDMA2: timing = 0x26514e21; break; 1119 case ATA_UDMA2: timing = 0x16494e31; break; 1120 case ATA_UDMA4: timing = 0x16454e31; break; 1121 case ATA_UDMA5: timing = 0x16454e31; break; 1122 default: timing = 0x06514e57; 1123 } 1124 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1125 pci_write_config(parent, 0x5b, 0x22, 1); 1126 } 1127 else { /* HPT36[68] */ 1128 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1129 case 0x85: /* 25Mhz */ 1130 switch (mode) { 1131 case ATA_PIO0: timing = 0xc0d08585; break; 1132 case ATA_PIO1: timing = 0xc0d08572; break; 1133 case ATA_PIO2: timing = 0xc0ca8542; break; 1134 case ATA_PIO3: timing = 0xc0ca8532; break; 1135 case ATA_PIO4: timing = 0xc0ca8521; break; 1136 case ATA_WDMA2: timing = 0xa0ca8521; break; 1137 case ATA_UDMA2: timing = 0x90cf8521; break; 1138 case ATA_UDMA4: timing = 0x90c98521; break; 1139 default: timing = 0x01208585; 1140 } 1141 break; 1142 default: 1143 case 0xa7: /* 33MHz */ 1144 switch (mode) { 1145 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1146 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1147 case ATA_PIO2: timing = 0xc0d0a753; break; 1148 case ATA_PIO3: timing = 0xc0c8a742; break; 1149 case ATA_PIO4: timing = 0xc0c8a731; break; 1150 case ATA_WDMA2: timing = 0xa0c8a731; break; 1151 case ATA_UDMA2: timing = 0x90caa731; break; 1152 case ATA_UDMA4: timing = 0x90c9a731; break; 1153 default: timing = 0x0120a7a7; 1154 } 1155 break; 1156 case 0xd9: /* 40Mhz */ 1157 switch (mode) { 1158 case ATA_PIO0: timing = 0xc018d9d9; break; 1159 case ATA_PIO1: timing = 0xc010d9c7; break; 1160 case ATA_PIO2: timing = 0xc010d997; break; 1161 case ATA_PIO3: timing = 0xc010d974; break; 1162 case ATA_PIO4: timing = 0xc008d963; break; 1163 case ATA_WDMA2: timing = 0xa008d943; break; 1164 case ATA_UDMA2: timing = 0x900bd943; break; 1165 case ATA_UDMA4: timing = 0x900fd943; break; 1166 default: timing = 0x0120d9d9; 1167 } 1168 } 1169 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1170 } 1171}
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