29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
48static void cyrix_timing(struct ata_softc *, int, int);
49static void promise_timing(struct ata_softc *, int, int);
50static void hpt_timing(struct ata_softc *, int, int);
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
57#define ATAPI_DEVICE(scp, device) \
58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
60
61
62void *
63ata_dmaalloc(struct ata_softc *scp, int device)
64{
65 void *dmatab;
66
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
72 dmatab = NULL;
73 }
74 }
75 return dmatab;
76}
77
78void
79ata_dmainit(struct ata_softc *scp, int device,
80 int apiomode, int wdmamode, int udmamode)
81{
82 device_t parent = device_get_parent(scp->dev);
83 int devno = (scp->channel << 1) + ATA_DEV(device);
84 int error;
85
86 /* set our most pessimistic default mode */
87 scp->mode[ATA_DEV(device)] = ATA_PIO;
88
89 if (!scp->r_bmio)
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
93 if (scp->channel == 1) {
94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_printf(scp, device, "simplex device, DMA on primary only\n");
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
104 scp->alignment = 0x1;
105
106 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
107 ata_printf(scp, device,
108 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
109 udmamode = 2;
110 }
111
112 switch (scp->chiptype) {
113
114 case 0x244a8086: /* Intel ICH2 mobile */
115 case 0x244b8086: /* Intel ICH2 */
116 if (udmamode >= 5) {
117 int32_t mask48, new48;
118 int16_t word54;
119
120 word54 = pci_read_config(parent, 0x54, 2);
121 if (word54 & (0x10 << devno)) {
122 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
123 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
124 if (bootverbose)
125 ata_printf(scp, device,
126 "%s setting UDMA5 on Intel chip\n",
127 (error) ? "failed" : "success");
128 if (!error) {
129 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
130 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
131 pci_write_config(parent, 0x48,
132 (pci_read_config(parent, 0x48, 4) &
133 ~mask48) | new48, 4);
134 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
135 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
136 return;
137 }
138 }
139 }
140 /* make sure eventual ATA100 mode from the BIOS is disabled */
141 pci_write_config(parent, 0x54,
142 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
143 /* FALLTHROUGH */
144
145 case 0x24118086: /* Intel ICH */
146 if (udmamode >= 4) {
147 int32_t mask48, new48;
148 int16_t word54;
149
150 word54 = pci_read_config(parent, 0x54, 2);
151 if (word54 & (0x10 << devno)) {
152 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
153 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
154 if (bootverbose)
155 ata_printf(scp, device,
156 "%s setting UDMA4 on Intel chip\n",
157 (error) ? "failed" : "success");
158 if (!error) {
159 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
160 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
161 pci_write_config(parent, 0x48,
162 (pci_read_config(parent, 0x48, 4) &
163 ~mask48) | new48, 4);
164 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
165 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
166 return;
167 }
168 }
169 }
170 /* make sure eventual ATA66 mode from the BIOS is disabled */
171 pci_write_config(parent, 0x54,
172 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
173 /* FALLTHROUGH */
174
175 case 0x71118086: /* Intel PIIX4 */
176 case 0x71998086: /* Intel PIIX4e */
177 case 0x24218086: /* Intel ICH0 */
178 if (udmamode >= 2) {
179 int32_t mask48, new48;
180
181 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
182 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
183 if (bootverbose)
184 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n",
185 (error) ? "failed" : "success");
186 if (!error) {
187 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
188 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
189 pci_write_config(parent, 0x48,
190 (pci_read_config(parent, 0x48, 4) &
191 ~mask48) | new48, 4);
192 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
193 return;
194 }
195 }
196 /* make sure eventual ATA33 mode from the BIOS is disabled */
197 pci_write_config(parent, 0x48,
198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
199 /* FALLTHROUGH */
200
201 case 0x70108086: /* Intel PIIX3 */
202 if (wdmamode >= 2 && apiomode >= 4) {
203 int32_t mask40, new40, mask44, new44;
204
205 /* if SITRE not set doit for both channels */
206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) {
207 new40 = pci_read_config(parent, 0x40, 4);
208 new44 = pci_read_config(parent, 0x44, 4);
209 if (!(new40 & 0x00004000)) {
210 new44 &= ~0x0000000f;
211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
212 }
213 if (!(new40 & 0x40000000)) {
214 new44 &= ~0x000000f0;
215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
216 }
217 new40 |= 0x40004000;
218 pci_write_config(parent, 0x40, new40, 4);
219 pci_write_config(parent, 0x44, new44, 4);
220 }
221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
223 if (bootverbose)
224 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
225 (error) ? "failed" : "success");
226 if (!error) {
227 if (device == ATA_MASTER) {
228 mask40 = 0x0000330f;
229 new40 = 0x00002307;
230 mask44 = 0;
231 new44 = 0;
232 }
233 else {
234 mask40 = 0x000000f0;
235 new40 = 0x00000070;
236 mask44 = 0x0000000f;
237 new44 = 0x0000000b;
238 }
239 if (scp->channel) {
240 mask40 <<= 16;
241 new40 <<= 16;
242 mask44 <<= 4;
243 new44 <<= 4;
244 }
245 pci_write_config(parent, 0x40,
246 (pci_read_config(parent, 0x40, 4) & ~mask40)|
247 new40, 4);
248 pci_write_config(parent, 0x44,
249 (pci_read_config(parent, 0x44, 4) & ~mask44)|
250 new44, 4);
251 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
252 return;
253 }
254 }
255 /* we could set PIO mode timings, but we assume the BIOS did that */
256 break;
257
258 case 0x12308086: /* Intel PIIX */
259 if (wdmamode >= 2 && apiomode >= 4) {
260 int32_t word40;
261
262 word40 = pci_read_config(parent, 0x40, 4);
263 word40 >>= scp->channel * 16;
264
265 /* Check for timing config usable for DMA on controller */
266 if (!((word40 & 0x3300) == 0x2300 &&
267 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
268 break;
269
270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
272 if (bootverbose)
273 ata_printf(scp, device,
274 "%s setting WDMA2 on Intel chip\n",
275 (error) ? "failed" : "success");
276 if (!error) {
277 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
278 return;
279 }
280 }
281 break;
282
283 case 0x522910b9: /* AcerLabs Aladdin IV/V */
284 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
285 if (pci_get_revid(parent) < 0xC2 &&
286 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
287 ata_printf(scp, device,
288 "Aladdin: two atapi devices on this channel, no DMA\n");
289 break;
290 }
291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) {
292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
294 if (bootverbose)
295 ata_printf(scp, device,
296 "%s setting UDMA5 on Acer chip\n",
297 (error) ? "failed" : "success");
298 if (!error) {
299 int32_t word54 = pci_read_config(parent, 0x54, 4);
300
301 pci_write_config(parent, 0x4b,
302 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
303 word54 &= ~(0x000f000f << (devno << 2));
304 word54 |= (0x000f0005 << (devno << 2));
305 pci_write_config(parent, 0x54, word54, 4);
306 pci_write_config(parent, 0x53,
307 pci_read_config(parent, 0x53, 1) | 0x03, 1);
308 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
309 return;
310 }
311 }
312 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) {
313 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
314 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
315 if (bootverbose)
316 ata_printf(scp, device,
317 "%s setting UDMA4 on Acer chip\n",
318 (error) ? "failed" : "success");
319 if (!error) {
320 int32_t word54 = pci_read_config(parent, 0x54, 4);
321
322 pci_write_config(parent, 0x4b,
323 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
324 word54 &= ~(0x000f000f << (devno << 2));
325 word54 |= (0x00080005 << (devno << 2));
326 pci_write_config(parent, 0x54, word54, 4);
327 pci_write_config(parent, 0x53,
328 pci_read_config(parent, 0x53, 1) | 0x03, 1);
329 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
330 return;
331 }
332 }
333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
336 if (bootverbose)
337 ata_printf(scp, device,
338 "%s setting UDMA2 on Acer chip\n",
339 (error) ? "failed" : "success");
340 if (!error) {
341 int32_t word54 = pci_read_config(parent, 0x54, 4);
342
343 word54 &= ~(0x000f000f << (devno << 2));
344 word54 |= (0x000a0005 << (devno << 2));
345 pci_write_config(parent, 0x54, word54, 4);
346 pci_write_config(parent, 0x53,
347 pci_read_config(parent, 0x53, 1) | 0x03, 1);
348 scp->flags |= ATA_ATAPI_DMA_RO;
349 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
350 return;
351 }
352 }
353
354 /* make sure eventual UDMA mode from the BIOS is disabled */
355 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
356 ~(0x0008 << (devno << 2)), 2);
357
358 if (wdmamode >= 2 && apiomode >= 4) {
359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
361 if (bootverbose)
362 ata_printf(scp, device,
363 "%s setting WDMA2 on Acer chip\n",
364 (error) ? "failed" : "success");
365 if (!error) {
366 pci_write_config(parent, 0x53,
367 pci_read_config(parent, 0x53, 1) | 0x03, 1);
368 scp->flags |= ATA_ATAPI_DMA_RO;
369 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
370 return;
371 }
372 }
373 pci_write_config(parent, 0x53,
374 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
375 /* we could set PIO mode timings, but we assume the BIOS did that */
376 break;
377
378 case 0x74111022: /* AMD 766 */
379 if (udmamode >= 5) {
380 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
381 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
382 if (bootverbose)
383 ata_printf(scp, device,
384 "%s setting UDMA5 on AMD chip\n",
385 (error) ? "failed" : "success");
386 if (!error) {
387 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
388 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
389 return;
390 }
391 }
392 /* FALLTHROUGH */
393
394 case 0x74091022: /* AMD 756 */
395 if (udmamode >= 4) {
396 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
397 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
398 if (bootverbose)
399 ata_printf(scp, device,
400 "%s setting UDMA4 on AMD chip\n",
401 (error) ? "failed" : "success");
402 if (!error) {
403 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
404 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
405 return;
406 }
407 }
408 goto via_82c586;
409
410 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
411 if (ata_find_dev(parent, 0x06861106, 0x40) ||
412 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */
413 if (udmamode >= 5) {
414 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
415 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
416 if (bootverbose)
417 ata_printf(scp, device,
418 "%s setting UDMA5 on VIA chip\n",
419 (error) ? "failed" : "success");
420 if (!error) {
421 pci_write_config(parent, 0x53 - devno, 0xf0, 1);
422 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
423 return;
424 }
425 }
426 if (udmamode >= 4) {
427 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
428 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
429 if (bootverbose)
430 ata_printf(scp, device,
431 "%s setting UDMA4 on VIA chip\n",
432 (error) ? "failed" : "success");
433 if (!error) {
434 pci_write_config(parent, 0x53 - devno, 0xf1, 1);
435 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
436 return;
437 }
438 }
439 if (udmamode >= 2) {
440 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
441 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
442 if (bootverbose)
443 ata_printf(scp, device,
444 "%s setting UDMA2 on VIA chip\n",
445 (error) ? "failed" : "success");
446 if (!error) {
447 pci_write_config(parent, 0x53 - devno, 0xf4, 1);
448 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
449 return;
450 }
451 }
452 }
453 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
454 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
455 if (udmamode >= 4) {
456 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
457 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
458 if (bootverbose)
459 ata_printf(scp, device,
460 "%s setting UDMA4 on VIA chip\n",
461 (error) ? "failed" : "success");
462 if (!error) {
463 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
464 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
465 return;
466 }
467 }
468 if (udmamode >= 2) {
469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
470 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
471 if (bootverbose)
472 ata_printf(scp, device,
473 "%s setting UDMA2 on VIA chip\n",
474 (error) ? "failed" : "success");
475 if (!error) {
476 pci_write_config(parent, 0x53 - devno, 0xea, 1);
477 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
478 return;
479 }
480 }
481 }
482 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
483 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
484via_82c586:
485 if (udmamode >= 2) {
486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
487 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
488 if (bootverbose)
489 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
490 (error) ? "failed" : "success",
491 ((scp->chiptype == 0x74091022) ||
492 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA");
493 if (!error) {
494 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
495 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
496 return;
497 }
498 }
499 }
500 if (wdmamode >= 2 && apiomode >= 4) {
501 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
502 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
503 if (bootverbose)
504 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
505 (error) ? "failed" : "success",
506 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
507 if (!error) {
508 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
509 pci_write_config(parent, 0x4b - devno, 0x31, 1);
510 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
511 return;
512 }
513 }
514 /* we could set PIO mode timings, but we assume the BIOS did that */
515 break;
516
517 case 0x55131039: /* SiS 5591 */
518 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
519 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
520 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
521 if (bootverbose)
522 ata_printf(scp, device,
523 "%s setting UDMA2 on SiS chip\n",
524 (error) ? "failed" : "success");
525 if (!error) {
526 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
527 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
528 return;
529 }
530 }
531 if (wdmamode >=2 && apiomode >= 4) {
532 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
533 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
534 if (bootverbose)
535 ata_printf(scp, device,
536 "%s setting WDMA2 on SiS chip\n",
537 (error) ? "failed" : "success");
538 if (!error) {
539 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
540 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
541 return;
542 }
543 }
544 /* we could set PIO mode timings, but we assume the BIOS did that */
545 break;
546
547 case 0x06491095: /* CMD 649 ATA100 controller */
548 if (udmamode >= 5) {
549 u_int8_t umode;
550
551 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
552 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 if (bootverbose)
554 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n",
555 (error) ? "failed" : "success");
556 if (!error) {
557 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
558 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
559 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
560 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
561 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
562 return;
563 }
564 }
565 /* FALLTHROUGH */
566
567 case 0x06481095: /* CMD 648 ATA66 controller */
568 if (udmamode >= 4) {
569 u_int8_t umode;
570
571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
573 if (bootverbose)
574 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n",
575 (error) ? "failed" : "success");
576 if (!error) {
577 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
578 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
579 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
580 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
581 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
582 return;
583 }
584 }
585 if (udmamode >= 2) {
586 u_int8_t umode;
587
588 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
589 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
590 if (bootverbose)
591 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n",
592 (error) ? "failed" : "success");
593 if (!error) {
594 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
595 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
596 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
597 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
598 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
599 return;
600 }
601 }
602 /* make sure eventual UDMA mode from the BIOS is disabled */
603 pci_write_config(parent, scp->channel ? 0x7b : 0x73,
604 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)&
605 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
606 /* FALLTHROUGH */
607
608 case 0x06461095: /* CMD 646 ATA controller */
609 if (wdmamode >= 2 && apiomode >= 4) {
610 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
611 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
612 if (bootverbose)
613 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n",
614 error ? "failed" : "success");
615 if (!error) {
616 int32_t offset = (devno < 3) ? (devno << 1) : 7;
617
618 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
619 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
620 return;
621 }
622 }
623 /* we could set PIO mode timings, but we assume the BIOS did that */
624 break;
625
626 case 0xc6931080: /* Cypress 82c693 ATA controller */
627 if (wdmamode >= 2 && apiomode >= 4) {
628 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
629 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
630 if (bootverbose)
631 ata_printf(scp, device,
632 "%s setting WDMA2 on Cypress chip\n",
633 error ? "failed" : "success");
634 if (!error) {
635 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2);
636 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
637 return;
638 }
639 }
640 /* we could set PIO mode timings, but we assume the BIOS did that */
641 break;
642
643 case 0x01021078: /* Cyrix 5530 ATA33 controller */
644 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
645 if (udmamode >= 2) {
646 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
647 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
648 if (bootverbose)
649 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
650 (error) ? "failed" : "success");
651 if (!error) {
652 cyrix_timing(scp, devno, ATA_UDMA2);
653 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
654 return;
655 }
656 }
657 if (wdmamode >= 2 && apiomode >= 4) {
658 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
659 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
660 if (bootverbose)
661 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
662 (error) ? "failed" : "success");
663 if (!error) {
664 cyrix_timing(scp, devno, ATA_WDMA2);
665 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
666 return;
667 }
668 }
669 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
670 ata_pio2mode(apiomode), ATA_C_F_SETXFER,
671 ATA_WAIT_READY);
672 if (bootverbose)
673 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
674 (error) ? "failed" : "success",
675 ata_mode2str(ata_pio2mode(apiomode)));
676 cyrix_timing(scp, devno, ata_pio2mode(apiomode));
677 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
678 return;
679
680 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
681 if (udmamode >= 2) {
682 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
683 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
684 if (bootverbose)
685 ata_printf(scp, device,
686 "%s setting UDMA2 on ServerWorks chip\n",
687 (error) ? "failed" : "success");
688 if (!error) {
689 u_int16_t reg56;
690
691 pci_write_config(parent, 0x54,
692 pci_read_config(parent, 0x54, 1) |
693 (0x01 << devno), 1);
694 reg56 = pci_read_config(parent, 0x56, 2);
695 reg56 &= ~(0xf << (devno * 4));
696 reg56 |= (0x2 << (devno * 4));
697 pci_write_config(parent, 0x56, reg56, 2);
698 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
699 return;
700 }
701 }
702 if (wdmamode >= 2 && apiomode >= 4) {
703 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
704 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
705 if (bootverbose)
706 ata_printf(scp, device,
707 "%s setting WDMA2 on ServerWorks chip\n",
708 (error) ? "failed" : "success");
709 if (!error) {
710 int offset = (scp->channel * 2) + (device == ATA_MASTER);
711 int word44 = pci_read_config(parent, 0x44, 4);
712
713 pci_write_config(parent, 0x54,
714 pci_read_config(parent, 0x54, 1) &
715 ~(0x01 << devno), 1);
716 word44 &= ~(0xff << (offset << 8));
717 word44 |= (0x20 << (offset << 8));
718 pci_write_config(parent, 0x44, 0x20, 4);
719 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
720 return;
721 }
722 }
723 /* we could set PIO mode timings, but we assume the BIOS did that */
724 break;
725
726 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
727 case 0x0d30105a: /* Promise OEM ATA100 controllers */
728 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
729 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
730 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 &&
731 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
732 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
733 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
734 if (bootverbose)
735 ata_printf(scp, device,
736 "%s setting UDMA5 on Promise chip\n",
737 (error) ? "failed" : "success");
738 if (!error) {
739 promise_timing(scp, devno, ATA_UDMA5);
740 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
741 return;
742 }
743 }
744 /* FALLTHROUGH */
745
746 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
747 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
748 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
749 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
750 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
751 if (bootverbose)
752 ata_printf(scp, device,
753 "%s setting UDMA4 on Promise chip\n",
754 (error) ? "failed" : "success");
755 if (!error) {
756 promise_timing(scp, devno, ATA_UDMA4);
757 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
758 return;
759 }
760 }
761 /* FALLTHROUGH */
762
763 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
764 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
765 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
766 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
767 if (bootverbose)
768 ata_printf(scp, device,
769 "%s setting UDMA2 on Promise chip\n",
770 (error) ? "failed" : "success");
771 if (!error) {
772 promise_timing(scp, devno, ATA_UDMA2);
773 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
774 return;
775 }
776 }
777 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
778 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
779 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
780 if (bootverbose)
781 ata_printf(scp, device,
782 "%s setting WDMA2 on Promise chip\n",
783 (error) ? "failed" : "success");
784 if (!error) {
785 promise_timing(scp, devno, ATA_WDMA2);
786 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
787 return;
788 }
789 }
790 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
791 ata_pio2mode(apiomode),
792 ATA_C_F_SETXFER, ATA_WAIT_READY);
793 if (bootverbose)
794 ata_printf(scp, device,
795 "%s setting PIO%d on Promise chip\n",
796 (error) ? "failed" : "success",
797 (apiomode >= 0) ? apiomode : 0);
798 promise_timing(scp, devno, ata_pio2mode(apiomode));
799 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
800 return;
801
802 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
803 if (!ATAPI_DEVICE(scp, device) &&
804 udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
805 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
806 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
807 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
808 if (bootverbose)
809 ata_printf(scp, device,
810 "%s setting UDMA5 on HighPoint chip\n",
811 (error) ? "failed" : "success");
812 if (!error) {
813 hpt_timing(scp, devno, ATA_UDMA5);
814 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
815 return;
816 }
817 }
818 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 &&
819 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
820 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
821 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
822 if (bootverbose)
823 ata_printf(scp, device,
824 "%s setting UDMA4 on HighPoint chip\n",
825 (error) ? "failed" : "success");
826 if (!error) {
827 hpt_timing(scp, devno, ATA_UDMA4);
828 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
829 return;
830 }
831 }
832 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
833 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
834 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
835 if (bootverbose)
836 ata_printf(scp, device,
837 "%s setting UDMA2 on HighPoint chip\n",
838 (error) ? "failed" : "success");
839 if (!error) {
840 hpt_timing(scp, devno, ATA_UDMA2);
841 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
842 return;
843 }
844 }
845 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
846 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
847 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
848 if (bootverbose)
849 ata_printf(scp, device,
850 "%s setting WDMA2 on HighPoint chip\n",
851 (error) ? "failed" : "success");
852 if (!error) {
853 hpt_timing(scp, devno, ATA_WDMA2);
854 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
855 return;
856 }
857 }
858 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
859 ata_pio2mode(apiomode),
860 ATA_C_F_SETXFER, ATA_WAIT_READY);
861 if (bootverbose)
862 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n",
863 (error) ? "failed" : "success",
864 (apiomode >= 0) ? apiomode : 0);
865 hpt_timing(scp, devno, ata_pio2mode(apiomode));
866 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
867 return;
868
869 default: /* unknown controller chip */
870 /* better not try generic DMA on ATAPI devices it almost never works */
871 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
872 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
873 break;
874
875 /* if controller says its setup for DMA take the easy way out */
876 /* the downside is we dont know what DMA mode we are in */
877 if ((udmamode >= 0 || wdmamode > 1) &&
878 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
879 ((device==ATA_MASTER) ?
880 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
881 scp->mode[ATA_DEV(device)] = ATA_DMA;
882 return;
883 }
884
885 /* well, we have no support for this, but try anyways */
886 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) {
887 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
888 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
889 if (bootverbose)
890 ata_printf(scp, device,
891 "%s setting WDMA2 on generic chip\n",
892 (error) ? "failed" : "success");
893 if (!error) {
894 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
895 return;
896 }
897 }
898 }
899 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
900 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
901 if (bootverbose)
902 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
903 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
904 if (!error)
905 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
906 else {
907 if (bootverbose)
908 ata_printf(scp, device, "using PIO mode set by BIOS\n");
909 scp->mode[ATA_DEV(device)] = ATA_PIO;
910 }
911}
912
913int
914ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
915 caddr_t data, int32_t count)
916{
917 u_int32_t dma_count, dma_base;
918 int i = 0;
919
920 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
921 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
922 return -1;
923 }
924
925 if (!count) {
926 ata_printf(scp, device, "zero length DMA transfer attempted\n");
927 return -1;
928 }
929
930 dma_base = vtophys(data);
931 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
932 data += dma_count;
933 count -= dma_count;
934
935 while (count) {
936 dmatab[i].base = dma_base;
937 dmatab[i].count = (dma_count & 0xffff);
938 i++;
939 if (i >= ATA_DMA_ENTRIES) {
940 ata_printf(scp, device, "too many segments in DMA table\n");
941 return -1;
942 }
943 dma_base = vtophys(data);
944 dma_count = min(count, PAGE_SIZE);
945 data += min(count, PAGE_SIZE);
946 count -= min(count, PAGE_SIZE);
947 }
948 dmatab[i].base = dma_base;
949 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
950 return 0;
951}
952
953void
954ata_dmastart(struct ata_softc *scp, int device,
955 struct ata_dmaentry *dmatab, int dir)
956{
957 scp->flags |= ATA_DMA_ACTIVE;
958 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
959 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
960 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
961 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) |
962 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
963 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
964 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
965}
966
967int
968ata_dmadone(struct ata_softc *scp)
969{
970 int error;
971
972 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
973 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
974 scp->flags &= ~ATA_DMA_ACTIVE;
975 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT);
976 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
977 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
978 return error & ATA_BMSTAT_MASK;
979}
980
981int
982ata_dmastatus(struct ata_softc *scp)
983{
984 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
985}
986
987static void
988cyrix_timing(struct ata_softc *scp, int devno, int mode)
989{
990 u_int32_t reg20 = 0x0000e132;
991 u_int32_t reg24 = 0x00017771;
992
993 switch (mode) {
994 case ATA_PIO0: reg20 = 0x0000e132; break;
995 case ATA_PIO1: reg20 = 0x00018121; break;
996 case ATA_PIO2: reg20 = 0x00024020; break;
997 case ATA_PIO3: reg20 = 0x00032010; break;
998 case ATA_PIO4: reg20 = 0x00040010; break;
999 case ATA_WDMA2: reg24 = 0x00002020; break;
1000 case ATA_UDMA2: reg24 = 0x00911030; break;
1001 }
1002 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20);
1003 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24);
1004}
1005
1006static void
1007promise_timing(struct ata_softc *scp, int devno, int mode)
1008{
1009 u_int32_t timing = 0;
1010 struct promise_timing {
1011 u_int8_t pa:4;
1012 u_int8_t prefetch:1;
1013 u_int8_t iordy:1;
1014 u_int8_t errdy:1;
1015 u_int8_t syncin:1;
1016 u_int8_t pb:5;
1017 u_int8_t mb:3;
1018 u_int8_t mc:4;
1019 u_int8_t dmaw:1;
1020 u_int8_t dmar:1;
1021 u_int8_t iordyp:1;
1022 u_int8_t dmarqp:1;
1023 u_int8_t reserved:8;
1024 } *t = (struct promise_timing*)&timing;
1025
1026 t->iordy = 1; t->iordyp = 1;
1027 if (mode >= ATA_DMA) {
1028 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1029 }
1030
1031 switch (scp->chiptype) {
1032 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1033 switch (mode) {
1034 default:
1035 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1036 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1037 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1038 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1039 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1040 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1041 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1042 }
1043 break;
1044
1045 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1046 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1047 case 0x0d30105a: /* Promise OEM ATA 100 */
1048 switch (mode) {
1049 default:
1050 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1051 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1052 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1053 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1054 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1055 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1056 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1057 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1058 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1059 }
1060 break;
1061
1062 case 0x4d68105a: /* Promise TX2 ATA 100 */
1063 case 0x6268105a: /* Promise TX2v2 ATA 100 */
1064 return;
1065 }
1066 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
1067}
1068
1069static void
1070hpt_timing(struct ata_softc *scp, int devno, int mode)
1071{
1072 device_t parent = device_get_parent(scp->dev);
1073 u_int32_t timing;
1074
1075 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1076 switch (mode) {
1077 case ATA_PIO0: timing = 0x06914e57; break;
1078 case ATA_PIO1: timing = 0x06914e43; break;
1079 case ATA_PIO2: timing = 0x06514e33; break;
1080 case ATA_PIO3: timing = 0x06514e22; break;
1081 case ATA_PIO4: timing = 0x06514e21; break;
1082 case ATA_WDMA2: timing = 0x26514e21; break;
1083 case ATA_UDMA2: timing = 0x16494e31; break;
1084 case ATA_UDMA4: timing = 0x16454e31; break;
1085 case ATA_UDMA5: timing = 0x16454e31; break;
1086 default: timing = 0x06514e57;
1087 }
1088 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1089 pci_write_config(parent, 0x5b, 0x22, 1);
1090 }
1091 else { /* HPT36[68] */
1092 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1093 case 0x85: /* 25Mhz */
1094 switch (mode) {
1095 case ATA_PIO0: timing = 0xc0d08585; break;
1096 case ATA_PIO1: timing = 0xc0d08572; break;
1097 case ATA_PIO2: timing = 0xc0ca8542; break;
1098 case ATA_PIO3: timing = 0xc0ca8532; break;
1099 case ATA_PIO4: timing = 0xc0ca8521; break;
1100 case ATA_WDMA2: timing = 0xa0ca8521; break;
1101 case ATA_UDMA2: timing = 0x90cf8521; break;
1102 case ATA_UDMA4: timing = 0x90c98521; break;
1103 default: timing = 0x01208585;
1104 }
1105 break;
1106 default:
1107 case 0xa7: /* 33MHz */
1108 switch (mode) {
1109 case ATA_PIO0: timing = 0xc0d0a7aa; break;
1110 case ATA_PIO1: timing = 0xc0d0a7a3; break;
1111 case ATA_PIO2: timing = 0xc0d0a753; break;
1112 case ATA_PIO3: timing = 0xc0c8a742; break;
1113 case ATA_PIO4: timing = 0xc0c8a731; break;
1114 case ATA_WDMA2: timing = 0xa0c8a731; break;
1115 case ATA_UDMA2: timing = 0x90caa731; break;
1116 case ATA_UDMA4: timing = 0x90c9a731; break;
1117 default: timing = 0x0120a7a7;
1118 }
1119 break;
1120 case 0xd9: /* 40Mhz */
1121 switch (mode) {
1122 case ATA_PIO0: timing = 0xc018d9d9; break;
1123 case ATA_PIO1: timing = 0xc010d9c7; break;
1124 case ATA_PIO2: timing = 0xc010d997; break;
1125 case ATA_PIO3: timing = 0xc010d974; break;
1126 case ATA_PIO4: timing = 0xc008d963; break;
1127 case ATA_WDMA2: timing = 0xa008d943; break;
1128 case ATA_UDMA2: timing = 0x900bd943; break;
1129 case ATA_UDMA4: timing = 0x900fd943; break;
1130 default: timing = 0x0120d9d9;
1131 }
1132 }
1133 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
1134 }
1135}
| 29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
48static void cyrix_timing(struct ata_softc *, int, int);
49static void promise_timing(struct ata_softc *, int, int);
50static void hpt_timing(struct ata_softc *, int, int);
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
57#define ATAPI_DEVICE(scp, device) \
58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
60
61
62void *
63ata_dmaalloc(struct ata_softc *scp, int device)
64{
65 void *dmatab;
66
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
72 dmatab = NULL;
73 }
74 }
75 return dmatab;
76}
77
78void
79ata_dmainit(struct ata_softc *scp, int device,
80 int apiomode, int wdmamode, int udmamode)
81{
82 device_t parent = device_get_parent(scp->dev);
83 int devno = (scp->channel << 1) + ATA_DEV(device);
84 int error;
85
86 /* set our most pessimistic default mode */
87 scp->mode[ATA_DEV(device)] = ATA_PIO;
88
89 if (!scp->r_bmio)
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
93 if (scp->channel == 1) {
94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_printf(scp, device, "simplex device, DMA on primary only\n");
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
104 scp->alignment = 0x1;
105
106 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
107 ata_printf(scp, device,
108 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
109 udmamode = 2;
110 }
111
112 switch (scp->chiptype) {
113
114 case 0x244a8086: /* Intel ICH2 mobile */
115 case 0x244b8086: /* Intel ICH2 */
116 if (udmamode >= 5) {
117 int32_t mask48, new48;
118 int16_t word54;
119
120 word54 = pci_read_config(parent, 0x54, 2);
121 if (word54 & (0x10 << devno)) {
122 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
123 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
124 if (bootverbose)
125 ata_printf(scp, device,
126 "%s setting UDMA5 on Intel chip\n",
127 (error) ? "failed" : "success");
128 if (!error) {
129 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
130 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
131 pci_write_config(parent, 0x48,
132 (pci_read_config(parent, 0x48, 4) &
133 ~mask48) | new48, 4);
134 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
135 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
136 return;
137 }
138 }
139 }
140 /* make sure eventual ATA100 mode from the BIOS is disabled */
141 pci_write_config(parent, 0x54,
142 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
143 /* FALLTHROUGH */
144
145 case 0x24118086: /* Intel ICH */
146 if (udmamode >= 4) {
147 int32_t mask48, new48;
148 int16_t word54;
149
150 word54 = pci_read_config(parent, 0x54, 2);
151 if (word54 & (0x10 << devno)) {
152 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
153 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
154 if (bootverbose)
155 ata_printf(scp, device,
156 "%s setting UDMA4 on Intel chip\n",
157 (error) ? "failed" : "success");
158 if (!error) {
159 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
160 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
161 pci_write_config(parent, 0x48,
162 (pci_read_config(parent, 0x48, 4) &
163 ~mask48) | new48, 4);
164 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
165 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
166 return;
167 }
168 }
169 }
170 /* make sure eventual ATA66 mode from the BIOS is disabled */
171 pci_write_config(parent, 0x54,
172 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
173 /* FALLTHROUGH */
174
175 case 0x71118086: /* Intel PIIX4 */
176 case 0x71998086: /* Intel PIIX4e */
177 case 0x24218086: /* Intel ICH0 */
178 if (udmamode >= 2) {
179 int32_t mask48, new48;
180
181 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
182 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
183 if (bootverbose)
184 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n",
185 (error) ? "failed" : "success");
186 if (!error) {
187 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
188 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
189 pci_write_config(parent, 0x48,
190 (pci_read_config(parent, 0x48, 4) &
191 ~mask48) | new48, 4);
192 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
193 return;
194 }
195 }
196 /* make sure eventual ATA33 mode from the BIOS is disabled */
197 pci_write_config(parent, 0x48,
198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
199 /* FALLTHROUGH */
200
201 case 0x70108086: /* Intel PIIX3 */
202 if (wdmamode >= 2 && apiomode >= 4) {
203 int32_t mask40, new40, mask44, new44;
204
205 /* if SITRE not set doit for both channels */
206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) {
207 new40 = pci_read_config(parent, 0x40, 4);
208 new44 = pci_read_config(parent, 0x44, 4);
209 if (!(new40 & 0x00004000)) {
210 new44 &= ~0x0000000f;
211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
212 }
213 if (!(new40 & 0x40000000)) {
214 new44 &= ~0x000000f0;
215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
216 }
217 new40 |= 0x40004000;
218 pci_write_config(parent, 0x40, new40, 4);
219 pci_write_config(parent, 0x44, new44, 4);
220 }
221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
223 if (bootverbose)
224 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
225 (error) ? "failed" : "success");
226 if (!error) {
227 if (device == ATA_MASTER) {
228 mask40 = 0x0000330f;
229 new40 = 0x00002307;
230 mask44 = 0;
231 new44 = 0;
232 }
233 else {
234 mask40 = 0x000000f0;
235 new40 = 0x00000070;
236 mask44 = 0x0000000f;
237 new44 = 0x0000000b;
238 }
239 if (scp->channel) {
240 mask40 <<= 16;
241 new40 <<= 16;
242 mask44 <<= 4;
243 new44 <<= 4;
244 }
245 pci_write_config(parent, 0x40,
246 (pci_read_config(parent, 0x40, 4) & ~mask40)|
247 new40, 4);
248 pci_write_config(parent, 0x44,
249 (pci_read_config(parent, 0x44, 4) & ~mask44)|
250 new44, 4);
251 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
252 return;
253 }
254 }
255 /* we could set PIO mode timings, but we assume the BIOS did that */
256 break;
257
258 case 0x12308086: /* Intel PIIX */
259 if (wdmamode >= 2 && apiomode >= 4) {
260 int32_t word40;
261
262 word40 = pci_read_config(parent, 0x40, 4);
263 word40 >>= scp->channel * 16;
264
265 /* Check for timing config usable for DMA on controller */
266 if (!((word40 & 0x3300) == 0x2300 &&
267 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
268 break;
269
270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
272 if (bootverbose)
273 ata_printf(scp, device,
274 "%s setting WDMA2 on Intel chip\n",
275 (error) ? "failed" : "success");
276 if (!error) {
277 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
278 return;
279 }
280 }
281 break;
282
283 case 0x522910b9: /* AcerLabs Aladdin IV/V */
284 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
285 if (pci_get_revid(parent) < 0xC2 &&
286 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
287 ata_printf(scp, device,
288 "Aladdin: two atapi devices on this channel, no DMA\n");
289 break;
290 }
291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) {
292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
294 if (bootverbose)
295 ata_printf(scp, device,
296 "%s setting UDMA5 on Acer chip\n",
297 (error) ? "failed" : "success");
298 if (!error) {
299 int32_t word54 = pci_read_config(parent, 0x54, 4);
300
301 pci_write_config(parent, 0x4b,
302 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
303 word54 &= ~(0x000f000f << (devno << 2));
304 word54 |= (0x000f0005 << (devno << 2));
305 pci_write_config(parent, 0x54, word54, 4);
306 pci_write_config(parent, 0x53,
307 pci_read_config(parent, 0x53, 1) | 0x03, 1);
308 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
309 return;
310 }
311 }
312 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) {
313 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
314 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
315 if (bootverbose)
316 ata_printf(scp, device,
317 "%s setting UDMA4 on Acer chip\n",
318 (error) ? "failed" : "success");
319 if (!error) {
320 int32_t word54 = pci_read_config(parent, 0x54, 4);
321
322 pci_write_config(parent, 0x4b,
323 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
324 word54 &= ~(0x000f000f << (devno << 2));
325 word54 |= (0x00080005 << (devno << 2));
326 pci_write_config(parent, 0x54, word54, 4);
327 pci_write_config(parent, 0x53,
328 pci_read_config(parent, 0x53, 1) | 0x03, 1);
329 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
330 return;
331 }
332 }
333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
336 if (bootverbose)
337 ata_printf(scp, device,
338 "%s setting UDMA2 on Acer chip\n",
339 (error) ? "failed" : "success");
340 if (!error) {
341 int32_t word54 = pci_read_config(parent, 0x54, 4);
342
343 word54 &= ~(0x000f000f << (devno << 2));
344 word54 |= (0x000a0005 << (devno << 2));
345 pci_write_config(parent, 0x54, word54, 4);
346 pci_write_config(parent, 0x53,
347 pci_read_config(parent, 0x53, 1) | 0x03, 1);
348 scp->flags |= ATA_ATAPI_DMA_RO;
349 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
350 return;
351 }
352 }
353
354 /* make sure eventual UDMA mode from the BIOS is disabled */
355 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
356 ~(0x0008 << (devno << 2)), 2);
357
358 if (wdmamode >= 2 && apiomode >= 4) {
359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
361 if (bootverbose)
362 ata_printf(scp, device,
363 "%s setting WDMA2 on Acer chip\n",
364 (error) ? "failed" : "success");
365 if (!error) {
366 pci_write_config(parent, 0x53,
367 pci_read_config(parent, 0x53, 1) | 0x03, 1);
368 scp->flags |= ATA_ATAPI_DMA_RO;
369 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
370 return;
371 }
372 }
373 pci_write_config(parent, 0x53,
374 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
375 /* we could set PIO mode timings, but we assume the BIOS did that */
376 break;
377
378 case 0x74111022: /* AMD 766 */
379 if (udmamode >= 5) {
380 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
381 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
382 if (bootverbose)
383 ata_printf(scp, device,
384 "%s setting UDMA5 on AMD chip\n",
385 (error) ? "failed" : "success");
386 if (!error) {
387 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
388 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
389 return;
390 }
391 }
392 /* FALLTHROUGH */
393
394 case 0x74091022: /* AMD 756 */
395 if (udmamode >= 4) {
396 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
397 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
398 if (bootverbose)
399 ata_printf(scp, device,
400 "%s setting UDMA4 on AMD chip\n",
401 (error) ? "failed" : "success");
402 if (!error) {
403 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
404 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
405 return;
406 }
407 }
408 goto via_82c586;
409
410 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
411 if (ata_find_dev(parent, 0x06861106, 0x40) ||
412 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */
413 if (udmamode >= 5) {
414 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
415 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
416 if (bootverbose)
417 ata_printf(scp, device,
418 "%s setting UDMA5 on VIA chip\n",
419 (error) ? "failed" : "success");
420 if (!error) {
421 pci_write_config(parent, 0x53 - devno, 0xf0, 1);
422 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
423 return;
424 }
425 }
426 if (udmamode >= 4) {
427 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
428 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
429 if (bootverbose)
430 ata_printf(scp, device,
431 "%s setting UDMA4 on VIA chip\n",
432 (error) ? "failed" : "success");
433 if (!error) {
434 pci_write_config(parent, 0x53 - devno, 0xf1, 1);
435 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
436 return;
437 }
438 }
439 if (udmamode >= 2) {
440 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
441 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
442 if (bootverbose)
443 ata_printf(scp, device,
444 "%s setting UDMA2 on VIA chip\n",
445 (error) ? "failed" : "success");
446 if (!error) {
447 pci_write_config(parent, 0x53 - devno, 0xf4, 1);
448 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
449 return;
450 }
451 }
452 }
453 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
454 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
455 if (udmamode >= 4) {
456 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
457 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
458 if (bootverbose)
459 ata_printf(scp, device,
460 "%s setting UDMA4 on VIA chip\n",
461 (error) ? "failed" : "success");
462 if (!error) {
463 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
464 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
465 return;
466 }
467 }
468 if (udmamode >= 2) {
469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
470 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
471 if (bootverbose)
472 ata_printf(scp, device,
473 "%s setting UDMA2 on VIA chip\n",
474 (error) ? "failed" : "success");
475 if (!error) {
476 pci_write_config(parent, 0x53 - devno, 0xea, 1);
477 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
478 return;
479 }
480 }
481 }
482 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
483 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
484via_82c586:
485 if (udmamode >= 2) {
486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
487 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
488 if (bootverbose)
489 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
490 (error) ? "failed" : "success",
491 ((scp->chiptype == 0x74091022) ||
492 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA");
493 if (!error) {
494 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
495 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
496 return;
497 }
498 }
499 }
500 if (wdmamode >= 2 && apiomode >= 4) {
501 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
502 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
503 if (bootverbose)
504 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
505 (error) ? "failed" : "success",
506 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
507 if (!error) {
508 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
509 pci_write_config(parent, 0x4b - devno, 0x31, 1);
510 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
511 return;
512 }
513 }
514 /* we could set PIO mode timings, but we assume the BIOS did that */
515 break;
516
517 case 0x55131039: /* SiS 5591 */
518 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
519 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
520 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
521 if (bootverbose)
522 ata_printf(scp, device,
523 "%s setting UDMA2 on SiS chip\n",
524 (error) ? "failed" : "success");
525 if (!error) {
526 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
527 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
528 return;
529 }
530 }
531 if (wdmamode >=2 && apiomode >= 4) {
532 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
533 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
534 if (bootverbose)
535 ata_printf(scp, device,
536 "%s setting WDMA2 on SiS chip\n",
537 (error) ? "failed" : "success");
538 if (!error) {
539 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
540 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
541 return;
542 }
543 }
544 /* we could set PIO mode timings, but we assume the BIOS did that */
545 break;
546
547 case 0x06491095: /* CMD 649 ATA100 controller */
548 if (udmamode >= 5) {
549 u_int8_t umode;
550
551 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
552 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 if (bootverbose)
554 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n",
555 (error) ? "failed" : "success");
556 if (!error) {
557 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
558 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
559 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
560 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
561 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
562 return;
563 }
564 }
565 /* FALLTHROUGH */
566
567 case 0x06481095: /* CMD 648 ATA66 controller */
568 if (udmamode >= 4) {
569 u_int8_t umode;
570
571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
573 if (bootverbose)
574 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n",
575 (error) ? "failed" : "success");
576 if (!error) {
577 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
578 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
579 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
580 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
581 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
582 return;
583 }
584 }
585 if (udmamode >= 2) {
586 u_int8_t umode;
587
588 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
589 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
590 if (bootverbose)
591 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n",
592 (error) ? "failed" : "success");
593 if (!error) {
594 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
595 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
596 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
597 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
598 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
599 return;
600 }
601 }
602 /* make sure eventual UDMA mode from the BIOS is disabled */
603 pci_write_config(parent, scp->channel ? 0x7b : 0x73,
604 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)&
605 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
606 /* FALLTHROUGH */
607
608 case 0x06461095: /* CMD 646 ATA controller */
609 if (wdmamode >= 2 && apiomode >= 4) {
610 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
611 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
612 if (bootverbose)
613 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n",
614 error ? "failed" : "success");
615 if (!error) {
616 int32_t offset = (devno < 3) ? (devno << 1) : 7;
617
618 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
619 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
620 return;
621 }
622 }
623 /* we could set PIO mode timings, but we assume the BIOS did that */
624 break;
625
626 case 0xc6931080: /* Cypress 82c693 ATA controller */
627 if (wdmamode >= 2 && apiomode >= 4) {
628 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
629 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
630 if (bootverbose)
631 ata_printf(scp, device,
632 "%s setting WDMA2 on Cypress chip\n",
633 error ? "failed" : "success");
634 if (!error) {
635 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2);
636 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
637 return;
638 }
639 }
640 /* we could set PIO mode timings, but we assume the BIOS did that */
641 break;
642
643 case 0x01021078: /* Cyrix 5530 ATA33 controller */
644 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
645 if (udmamode >= 2) {
646 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
647 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
648 if (bootverbose)
649 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
650 (error) ? "failed" : "success");
651 if (!error) {
652 cyrix_timing(scp, devno, ATA_UDMA2);
653 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
654 return;
655 }
656 }
657 if (wdmamode >= 2 && apiomode >= 4) {
658 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
659 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
660 if (bootverbose)
661 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
662 (error) ? "failed" : "success");
663 if (!error) {
664 cyrix_timing(scp, devno, ATA_WDMA2);
665 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
666 return;
667 }
668 }
669 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
670 ata_pio2mode(apiomode), ATA_C_F_SETXFER,
671 ATA_WAIT_READY);
672 if (bootverbose)
673 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
674 (error) ? "failed" : "success",
675 ata_mode2str(ata_pio2mode(apiomode)));
676 cyrix_timing(scp, devno, ata_pio2mode(apiomode));
677 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
678 return;
679
680 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
681 if (udmamode >= 2) {
682 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
683 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
684 if (bootverbose)
685 ata_printf(scp, device,
686 "%s setting UDMA2 on ServerWorks chip\n",
687 (error) ? "failed" : "success");
688 if (!error) {
689 u_int16_t reg56;
690
691 pci_write_config(parent, 0x54,
692 pci_read_config(parent, 0x54, 1) |
693 (0x01 << devno), 1);
694 reg56 = pci_read_config(parent, 0x56, 2);
695 reg56 &= ~(0xf << (devno * 4));
696 reg56 |= (0x2 << (devno * 4));
697 pci_write_config(parent, 0x56, reg56, 2);
698 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
699 return;
700 }
701 }
702 if (wdmamode >= 2 && apiomode >= 4) {
703 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
704 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
705 if (bootverbose)
706 ata_printf(scp, device,
707 "%s setting WDMA2 on ServerWorks chip\n",
708 (error) ? "failed" : "success");
709 if (!error) {
710 int offset = (scp->channel * 2) + (device == ATA_MASTER);
711 int word44 = pci_read_config(parent, 0x44, 4);
712
713 pci_write_config(parent, 0x54,
714 pci_read_config(parent, 0x54, 1) &
715 ~(0x01 << devno), 1);
716 word44 &= ~(0xff << (offset << 8));
717 word44 |= (0x20 << (offset << 8));
718 pci_write_config(parent, 0x44, 0x20, 4);
719 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
720 return;
721 }
722 }
723 /* we could set PIO mode timings, but we assume the BIOS did that */
724 break;
725
726 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
727 case 0x0d30105a: /* Promise OEM ATA100 controllers */
728 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
729 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */
730 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 &&
731 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
732 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
733 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
734 if (bootverbose)
735 ata_printf(scp, device,
736 "%s setting UDMA5 on Promise chip\n",
737 (error) ? "failed" : "success");
738 if (!error) {
739 promise_timing(scp, devno, ATA_UDMA5);
740 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
741 return;
742 }
743 }
744 /* FALLTHROUGH */
745
746 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
747 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
748 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
749 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
750 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
751 if (bootverbose)
752 ata_printf(scp, device,
753 "%s setting UDMA4 on Promise chip\n",
754 (error) ? "failed" : "success");
755 if (!error) {
756 promise_timing(scp, devno, ATA_UDMA4);
757 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
758 return;
759 }
760 }
761 /* FALLTHROUGH */
762
763 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
764 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
765 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
766 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
767 if (bootverbose)
768 ata_printf(scp, device,
769 "%s setting UDMA2 on Promise chip\n",
770 (error) ? "failed" : "success");
771 if (!error) {
772 promise_timing(scp, devno, ATA_UDMA2);
773 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
774 return;
775 }
776 }
777 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
778 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
779 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
780 if (bootverbose)
781 ata_printf(scp, device,
782 "%s setting WDMA2 on Promise chip\n",
783 (error) ? "failed" : "success");
784 if (!error) {
785 promise_timing(scp, devno, ATA_WDMA2);
786 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
787 return;
788 }
789 }
790 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
791 ata_pio2mode(apiomode),
792 ATA_C_F_SETXFER, ATA_WAIT_READY);
793 if (bootverbose)
794 ata_printf(scp, device,
795 "%s setting PIO%d on Promise chip\n",
796 (error) ? "failed" : "success",
797 (apiomode >= 0) ? apiomode : 0);
798 promise_timing(scp, devno, ata_pio2mode(apiomode));
799 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
800 return;
801
802 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
803 if (!ATAPI_DEVICE(scp, device) &&
804 udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
805 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
806 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
807 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
808 if (bootverbose)
809 ata_printf(scp, device,
810 "%s setting UDMA5 on HighPoint chip\n",
811 (error) ? "failed" : "success");
812 if (!error) {
813 hpt_timing(scp, devno, ATA_UDMA5);
814 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
815 return;
816 }
817 }
818 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 &&
819 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
820 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
821 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
822 if (bootverbose)
823 ata_printf(scp, device,
824 "%s setting UDMA4 on HighPoint chip\n",
825 (error) ? "failed" : "success");
826 if (!error) {
827 hpt_timing(scp, devno, ATA_UDMA4);
828 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
829 return;
830 }
831 }
832 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
833 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
834 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
835 if (bootverbose)
836 ata_printf(scp, device,
837 "%s setting UDMA2 on HighPoint chip\n",
838 (error) ? "failed" : "success");
839 if (!error) {
840 hpt_timing(scp, devno, ATA_UDMA2);
841 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
842 return;
843 }
844 }
845 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
846 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
847 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
848 if (bootverbose)
849 ata_printf(scp, device,
850 "%s setting WDMA2 on HighPoint chip\n",
851 (error) ? "failed" : "success");
852 if (!error) {
853 hpt_timing(scp, devno, ATA_WDMA2);
854 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
855 return;
856 }
857 }
858 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
859 ata_pio2mode(apiomode),
860 ATA_C_F_SETXFER, ATA_WAIT_READY);
861 if (bootverbose)
862 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n",
863 (error) ? "failed" : "success",
864 (apiomode >= 0) ? apiomode : 0);
865 hpt_timing(scp, devno, ata_pio2mode(apiomode));
866 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
867 return;
868
869 default: /* unknown controller chip */
870 /* better not try generic DMA on ATAPI devices it almost never works */
871 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
872 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
873 break;
874
875 /* if controller says its setup for DMA take the easy way out */
876 /* the downside is we dont know what DMA mode we are in */
877 if ((udmamode >= 0 || wdmamode > 1) &&
878 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
879 ((device==ATA_MASTER) ?
880 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
881 scp->mode[ATA_DEV(device)] = ATA_DMA;
882 return;
883 }
884
885 /* well, we have no support for this, but try anyways */
886 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) {
887 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
888 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
889 if (bootverbose)
890 ata_printf(scp, device,
891 "%s setting WDMA2 on generic chip\n",
892 (error) ? "failed" : "success");
893 if (!error) {
894 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
895 return;
896 }
897 }
898 }
899 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
900 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
901 if (bootverbose)
902 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
903 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
904 if (!error)
905 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
906 else {
907 if (bootverbose)
908 ata_printf(scp, device, "using PIO mode set by BIOS\n");
909 scp->mode[ATA_DEV(device)] = ATA_PIO;
910 }
911}
912
913int
914ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
915 caddr_t data, int32_t count)
916{
917 u_int32_t dma_count, dma_base;
918 int i = 0;
919
920 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
921 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
922 return -1;
923 }
924
925 if (!count) {
926 ata_printf(scp, device, "zero length DMA transfer attempted\n");
927 return -1;
928 }
929
930 dma_base = vtophys(data);
931 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
932 data += dma_count;
933 count -= dma_count;
934
935 while (count) {
936 dmatab[i].base = dma_base;
937 dmatab[i].count = (dma_count & 0xffff);
938 i++;
939 if (i >= ATA_DMA_ENTRIES) {
940 ata_printf(scp, device, "too many segments in DMA table\n");
941 return -1;
942 }
943 dma_base = vtophys(data);
944 dma_count = min(count, PAGE_SIZE);
945 data += min(count, PAGE_SIZE);
946 count -= min(count, PAGE_SIZE);
947 }
948 dmatab[i].base = dma_base;
949 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
950 return 0;
951}
952
953void
954ata_dmastart(struct ata_softc *scp, int device,
955 struct ata_dmaentry *dmatab, int dir)
956{
957 scp->flags |= ATA_DMA_ACTIVE;
958 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
959 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
960 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
961 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) |
962 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
963 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
964 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
965}
966
967int
968ata_dmadone(struct ata_softc *scp)
969{
970 int error;
971
972 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
973 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
974 scp->flags &= ~ATA_DMA_ACTIVE;
975 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT);
976 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
977 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
978 return error & ATA_BMSTAT_MASK;
979}
980
981int
982ata_dmastatus(struct ata_softc *scp)
983{
984 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
985}
986
987static void
988cyrix_timing(struct ata_softc *scp, int devno, int mode)
989{
990 u_int32_t reg20 = 0x0000e132;
991 u_int32_t reg24 = 0x00017771;
992
993 switch (mode) {
994 case ATA_PIO0: reg20 = 0x0000e132; break;
995 case ATA_PIO1: reg20 = 0x00018121; break;
996 case ATA_PIO2: reg20 = 0x00024020; break;
997 case ATA_PIO3: reg20 = 0x00032010; break;
998 case ATA_PIO4: reg20 = 0x00040010; break;
999 case ATA_WDMA2: reg24 = 0x00002020; break;
1000 case ATA_UDMA2: reg24 = 0x00911030; break;
1001 }
1002 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20);
1003 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24);
1004}
1005
1006static void
1007promise_timing(struct ata_softc *scp, int devno, int mode)
1008{
1009 u_int32_t timing = 0;
1010 struct promise_timing {
1011 u_int8_t pa:4;
1012 u_int8_t prefetch:1;
1013 u_int8_t iordy:1;
1014 u_int8_t errdy:1;
1015 u_int8_t syncin:1;
1016 u_int8_t pb:5;
1017 u_int8_t mb:3;
1018 u_int8_t mc:4;
1019 u_int8_t dmaw:1;
1020 u_int8_t dmar:1;
1021 u_int8_t iordyp:1;
1022 u_int8_t dmarqp:1;
1023 u_int8_t reserved:8;
1024 } *t = (struct promise_timing*)&timing;
1025
1026 t->iordy = 1; t->iordyp = 1;
1027 if (mode >= ATA_DMA) {
1028 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1029 }
1030
1031 switch (scp->chiptype) {
1032 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1033 switch (mode) {
1034 default:
1035 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1036 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1037 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1038 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1039 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1040 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1041 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1042 }
1043 break;
1044
1045 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1046 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1047 case 0x0d30105a: /* Promise OEM ATA 100 */
1048 switch (mode) {
1049 default:
1050 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1051 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1052 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1053 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1054 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1055 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1056 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1057 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1058 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1059 }
1060 break;
1061
1062 case 0x4d68105a: /* Promise TX2 ATA 100 */
1063 case 0x6268105a: /* Promise TX2v2 ATA 100 */
1064 return;
1065 }
1066 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
1067}
1068
1069static void
1070hpt_timing(struct ata_softc *scp, int devno, int mode)
1071{
1072 device_t parent = device_get_parent(scp->dev);
1073 u_int32_t timing;
1074
1075 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1076 switch (mode) {
1077 case ATA_PIO0: timing = 0x06914e57; break;
1078 case ATA_PIO1: timing = 0x06914e43; break;
1079 case ATA_PIO2: timing = 0x06514e33; break;
1080 case ATA_PIO3: timing = 0x06514e22; break;
1081 case ATA_PIO4: timing = 0x06514e21; break;
1082 case ATA_WDMA2: timing = 0x26514e21; break;
1083 case ATA_UDMA2: timing = 0x16494e31; break;
1084 case ATA_UDMA4: timing = 0x16454e31; break;
1085 case ATA_UDMA5: timing = 0x16454e31; break;
1086 default: timing = 0x06514e57;
1087 }
1088 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1089 pci_write_config(parent, 0x5b, 0x22, 1);
1090 }
1091 else { /* HPT36[68] */
1092 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1093 case 0x85: /* 25Mhz */
1094 switch (mode) {
1095 case ATA_PIO0: timing = 0xc0d08585; break;
1096 case ATA_PIO1: timing = 0xc0d08572; break;
1097 case ATA_PIO2: timing = 0xc0ca8542; break;
1098 case ATA_PIO3: timing = 0xc0ca8532; break;
1099 case ATA_PIO4: timing = 0xc0ca8521; break;
1100 case ATA_WDMA2: timing = 0xa0ca8521; break;
1101 case ATA_UDMA2: timing = 0x90cf8521; break;
1102 case ATA_UDMA4: timing = 0x90c98521; break;
1103 default: timing = 0x01208585;
1104 }
1105 break;
1106 default:
1107 case 0xa7: /* 33MHz */
1108 switch (mode) {
1109 case ATA_PIO0: timing = 0xc0d0a7aa; break;
1110 case ATA_PIO1: timing = 0xc0d0a7a3; break;
1111 case ATA_PIO2: timing = 0xc0d0a753; break;
1112 case ATA_PIO3: timing = 0xc0c8a742; break;
1113 case ATA_PIO4: timing = 0xc0c8a731; break;
1114 case ATA_WDMA2: timing = 0xa0c8a731; break;
1115 case ATA_UDMA2: timing = 0x90caa731; break;
1116 case ATA_UDMA4: timing = 0x90c9a731; break;
1117 default: timing = 0x0120a7a7;
1118 }
1119 break;
1120 case 0xd9: /* 40Mhz */
1121 switch (mode) {
1122 case ATA_PIO0: timing = 0xc018d9d9; break;
1123 case ATA_PIO1: timing = 0xc010d9c7; break;
1124 case ATA_PIO2: timing = 0xc010d997; break;
1125 case ATA_PIO3: timing = 0xc010d974; break;
1126 case ATA_PIO4: timing = 0xc008d963; break;
1127 case ATA_WDMA2: timing = 0xa008d943; break;
1128 case ATA_UDMA2: timing = 0x900bd943; break;
1129 case ATA_UDMA4: timing = 0x900fd943; break;
1130 default: timing = 0x0120d9d9;
1131 }
1132 }
1133 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
1134 }
1135}
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