367 (error) ? "failed" : "success"); 368 if (!error) { 369 pci_write_config(parent, 0x53, 370 pci_read_config(parent, 0x53, 1) | 0x03, 1); 371 scp->flags |= ATA_ATAPI_DMA_RO; 372 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 373 return; 374 } 375 } 376 pci_write_config(parent, 0x53, 377 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 378 /* we could set PIO mode timings, but we assume the BIOS did that */ 379 break; 380 381 case 0x74091022: /* AMD 756 */ 382 if (udmamode >= 4) { 383 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 384 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 385 if (bootverbose) 386 ata_printf(scp, device, 387 "%s setting UDMA4 on AMD chip\n", 388 (error) ? "failed" : "success"); 389 if (!error) { 390 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 391 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 392 return; 393 } 394 } 395 goto via_82c586; 396 397 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 398 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 399 if (udmamode >= 5) { 400 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 401 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 402 if (bootverbose) 403 ata_printf(scp, device, 404 "%s setting UDMA5 on VIA chip\n", 405 (error) ? "failed" : "success"); 406 if (!error) { 407 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 408 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 409 return; 410 } 411 } 412 if (udmamode >= 4) { 413 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 414 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 415 if (bootverbose) 416 ata_printf(scp, device, 417 "%s setting UDMA4 on VIA chip\n", 418 (error) ? "failed" : "success"); 419 if (!error) { 420 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 421 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 422 return; 423 } 424 } 425 if (udmamode >= 2) { 426 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 427 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 428 if (bootverbose) 429 ata_printf(scp, device, 430 "%s setting UDMA2 on VIA chip\n", 431 (error) ? "failed" : "success"); 432 if (!error) { 433 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 434 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 435 return; 436 } 437 } 438 } 439 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 440 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 441 if (udmamode >= 4) { 442 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 443 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 444 if (bootverbose) 445 ata_printf(scp, device, 446 "%s setting UDMA4 on VIA chip\n", 447 (error) ? "failed" : "success"); 448 if (!error) { 449 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 450 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 451 return; 452 } 453 } 454 if (udmamode >= 2) { 455 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 456 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 457 if (bootverbose) 458 ata_printf(scp, device, 459 "%s setting UDMA2 on VIA chip\n", 460 (error) ? "failed" : "success"); 461 if (!error) { 462 pci_write_config(parent, 0x53 - devno, 0xea, 1); 463 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 464 return; 465 } 466 } 467 } 468 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 469 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 470via_82c586: 471 if (udmamode >= 2) { 472 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 473 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 474 if (bootverbose) 475 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 476 (error) ? "failed" : "success", 477 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 478 if (!error) { 479 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 480 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 481 return; 482 } 483 } 484 } 485 if (wdmamode >= 2 && apiomode >= 4) { 486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 487 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 488 if (bootverbose) 489 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 490 (error) ? "failed" : "success", 491 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 492 if (!error) { 493 pci_write_config(parent, 0x53 - devno, 0x82, 1); 494 pci_write_config(parent, 0x4b - devno, 0x31, 1); 495 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 496 return; 497 } 498 } 499 /* we could set PIO mode timings, but we assume the BIOS did that */ 500 break; 501 502 case 0x55131039: /* SiS 5591 */ 503 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 504 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 505 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 506 if (bootverbose) 507 ata_printf(scp, device, 508 "%s setting UDMA2 on SiS chip\n", 509 (error) ? "failed" : "success"); 510 if (!error) { 511 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 512 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 513 return; 514 } 515 } 516 if (wdmamode >=2 && apiomode >= 4) { 517 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 518 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 519 if (bootverbose) 520 ata_printf(scp, device, 521 "%s setting WDMA2 on SiS chip\n", 522 (error) ? "failed" : "success"); 523 if (!error) { 524 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 525 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 526 return; 527 } 528 } 529 /* we could set PIO mode timings, but we assume the BIOS did that */ 530 break; 531 532 case 0x06491095: /* CMD 649 ATA100 controller */ 533 if (udmamode >= 5) { 534 u_int8_t umode; 535 536 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 537 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 538 if (bootverbose) 539 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 540 (error) ? "failed" : "success"); 541 if (!error) { 542 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 543 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 544 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 545 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 546 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 547 return; 548 } 549 } 550 /* FALLTHROUGH */ 551 552 case 0x06481095: /* CMD 648 ATA66 controller */ 553 if (udmamode >= 4) { 554 u_int8_t umode; 555 556 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 557 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 558 if (bootverbose) 559 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 560 (error) ? "failed" : "success"); 561 if (!error) { 562 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 563 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 564 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 565 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 566 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 567 return; 568 } 569 } 570 if (udmamode >= 2) { 571 u_int8_t umode; 572 573 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 574 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 575 if (bootverbose) 576 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 577 (error) ? "failed" : "success"); 578 if (!error) { 579 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 580 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 581 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 582 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 583 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 584 return; 585 } 586 } 587 /* make sure eventual UDMA mode from the BIOS is disabled */ 588 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 589 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 590 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 591 /* FALLTHROUGH */ 592 593 case 0x06461095: /* CMD 646 ATA controller */ 594 if (wdmamode >= 2 && apiomode >= 4) { 595 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 596 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 597 if (bootverbose) 598 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 599 error ? "failed" : "success"); 600 if (!error) { 601 int32_t offset = (devno < 3) ? (devno << 1) : 7; 602 603 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 604 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 605 return; 606 } 607 } 608 /* we could set PIO mode timings, but we assume the BIOS did that */ 609 break; 610 611 case 0xc6931080: /* Cypress 82c693 ATA controller */ 612 if (wdmamode >= 2 && apiomode >= 4) { 613 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 614 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 615 if (bootverbose) 616 ata_printf(scp, device, 617 "%s setting WDMA2 on Cypress chip\n", 618 error ? "failed" : "success"); 619 if (!error) { 620 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 621 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 622 return; 623 } 624 } 625 /* we could set PIO mode timings, but we assume the BIOS did that */ 626 break; 627 628 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 629 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 630 if (udmamode >= 2) { 631 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 632 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 633 if (bootverbose) 634 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 635 (error) ? "failed" : "success"); 636 if (!error) { 637 cyrix_timing(scp, devno, ATA_UDMA2); 638 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 639 return; 640 } 641 } 642 if (wdmamode >= 2 && apiomode >= 4) { 643 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 644 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 645 if (bootverbose) 646 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 647 (error) ? "failed" : "success"); 648 if (!error) { 649 cyrix_timing(scp, devno, ATA_WDMA2); 650 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 651 return; 652 } 653 } 654 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 655 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 656 ATA_WAIT_READY); 657 if (bootverbose) 658 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 659 (error) ? "failed" : "success", 660 ata_mode2str(ata_pio2mode(apiomode))); 661 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 662 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 663 return; 664 665 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 666 if (udmamode >= 2) { 667 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 668 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 669 if (bootverbose) 670 ata_printf(scp, device, 671 "%s setting UDMA2 on ServerWorks chip\n", 672 (error) ? "failed" : "success"); 673 if (!error) { 674 u_int16_t reg56; 675 676 pci_write_config(parent, 0x54, 677 pci_read_config(parent, 0x54, 1) | 678 (0x01 << devno), 1); 679 reg56 = pci_read_config(parent, 0x56, 2); 680 reg56 &= ~(0xf << (devno * 4)); 681 reg56 |= (0x2 << (devno * 4)); 682 pci_write_config(parent, 0x56, reg56, 2); 683 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 684 return; 685 } 686 } 687 if (wdmamode >= 2 && apiomode >= 4) { 688 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 689 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 690 if (bootverbose) 691 ata_printf(scp, device, 692 "%s setting WDMA2 on ServerWorks chip\n", 693 (error) ? "failed" : "success"); 694 if (!error) { 695 int offset = (scp->channel * 2) + (device == ATA_MASTER); 696 int word44 = pci_read_config(parent, 0x44, 4); 697 698 pci_write_config(parent, 0x54, 699 pci_read_config(parent, 0x54, 1) & 700 ~(0x01 << devno), 1); 701 word44 &= ~(0xff << (offset << 8)); 702 word44 |= (0x20 << (offset << 8)); 703 pci_write_config(parent, 0x44, 0x20, 4); 704 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 705 return; 706 } 707 } 708 /* we could set PIO mode timings, but we assume the BIOS did that */ 709 break; 710 711 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 712 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 713 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 714 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 715 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 716 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 717 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 718 break; 719 720 if (udmamode >= 5 && 721 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 722 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 723 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 724 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 725 if (bootverbose) 726 ata_printf(scp, device, 727 "%s setting UDMA5 on Promise chip\n", 728 (error) ? "failed" : "success"); 729 if (!error) { 730 promise_timing(scp, devno, ATA_UDMA5); 731 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 732 return; 733 } 734 } 735 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 736 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 737 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 738 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 739 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 740 if (bootverbose) 741 ata_printf(scp, device, 742 "%s setting UDMA4 on Promise chip\n", 743 (error) ? "failed" : "success"); 744 if (!error) { 745 promise_timing(scp, devno, ATA_UDMA4); 746 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 747 return; 748 } 749 } 750 if (udmamode >= 2) { 751 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 752 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 753 if (bootverbose) 754 ata_printf(scp, device, 755 "%s setting UDMA2 on Promise chip\n", 756 (error) ? "failed" : "success"); 757 if (!error) { 758 promise_timing(scp, devno, ATA_UDMA2); 759 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 760 return; 761 } 762 } 763 if (wdmamode >= 2 && apiomode >= 4) { 764 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 765 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 766 if (bootverbose) 767 ata_printf(scp, device, 768 "%s setting WDMA2 on Promise chip\n", 769 (error) ? "failed" : "success"); 770 if (!error) { 771 promise_timing(scp, devno, ATA_WDMA2); 772 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 773 return; 774 } 775 } 776 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 777 ata_pio2mode(apiomode), 778 ATA_C_F_SETXFER, ATA_WAIT_READY); 779 if (bootverbose) 780 ata_printf(scp, device, 781 "%s setting PIO%d on Promise chip\n", 782 (error) ? "failed" : "success", 783 (apiomode >= 0) ? apiomode : 0); 784 promise_timing(scp, devno, ata_pio2mode(apiomode)); 785 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 786 return; 787 788 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 789 /* no ATAPI devices for now */ 790 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 791 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 792 break; 793 794 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 795 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 796 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 797 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 798 if (bootverbose) 799 ata_printf(scp, device, 800 "%s setting UDMA5 on HighPoint chip\n", 801 (error) ? "failed" : "success"); 802 if (!error) { 803 hpt_timing(scp, devno, ATA_UDMA5); 804 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 805 return; 806 } 807 } 808 if (udmamode >=4 && 809 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 810 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 811 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 812 if (bootverbose) 813 ata_printf(scp, device, 814 "%s setting UDMA4 on HighPoint chip\n", 815 (error) ? "failed" : "success"); 816 if (!error) { 817 hpt_timing(scp, devno, ATA_UDMA4); 818 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 819 return; 820 } 821 } 822 if (udmamode >= 2) { 823 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 824 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 825 if (bootverbose) 826 ata_printf(scp, device, 827 "%s setting UDMA2 on HighPoint chip\n", 828 (error) ? "failed" : "success"); 829 if (!error) { 830 hpt_timing(scp, devno, ATA_UDMA2); 831 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 832 return; 833 } 834 } 835 if (wdmamode >= 2 && apiomode >= 4) { 836 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 837 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 838 if (bootverbose) 839 ata_printf(scp, device, 840 "%s setting WDMA2 on HighPoint chip\n", 841 (error) ? "failed" : "success"); 842 if (!error) { 843 hpt_timing(scp, devno, ATA_WDMA2); 844 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 845 return; 846 } 847 } 848 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 849 ata_pio2mode(apiomode), 850 ATA_C_F_SETXFER, ATA_WAIT_READY); 851 if (bootverbose) 852 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 853 (error) ? "failed" : "success", 854 (apiomode >= 0) ? apiomode : 0); 855 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 856 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 857 return; 858 859 default: /* unknown controller chip */ 860 /* better not try generic DMA on ATAPI devices it almost never works */ 861 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 862 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 863 break; 864 865 /* if controller says its setup for DMA take the easy way out */ 866 /* the downside is we dont know what DMA mode we are in */ 867 if ((udmamode >= 0 || wdmamode > 1) && 868 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 869 ((device==ATA_MASTER) ? 870 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 871 scp->mode[ATA_DEV(device)] = ATA_DMA; 872 return; 873 } 874 875 /* well, we have no support for this, but try anyways */ 876 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 877 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 878 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 879 if (bootverbose) 880 ata_printf(scp, device, 881 "%s setting WDMA2 on generic chip\n", 882 (error) ? "failed" : "success"); 883 if (!error) { 884 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 885 return; 886 } 887 } 888 } 889 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 890 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 891 if (bootverbose) 892 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 893 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 894 if (!error) 895 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 896 else { 897 if (bootverbose) 898 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 899 scp->mode[ATA_DEV(device)] = ATA_PIO; 900 } 901} 902 903int 904ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 905 caddr_t data, int32_t count) 906{ 907 u_int32_t dma_count, dma_base; 908 int i = 0; 909 910 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 911 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 912 return -1; 913 } 914 915 if (!count) { 916 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 917 return -1; 918 } 919 920 dma_base = vtophys(data); 921 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 922 data += dma_count; 923 count -= dma_count; 924 925 while (count) { 926 dmatab[i].base = dma_base; 927 dmatab[i].count = (dma_count & 0xffff); 928 i++; 929 if (i >= ATA_DMA_ENTRIES) { 930 ata_printf(scp, device, "too many segments in DMA table\n"); 931 return -1; 932 } 933 dma_base = vtophys(data); 934 dma_count = min(count, PAGE_SIZE); 935 data += min(count, PAGE_SIZE); 936 count -= min(count, PAGE_SIZE); 937 } 938 dmatab[i].base = dma_base; 939 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 940 return 0; 941} 942 943void 944ata_dmastart(struct ata_softc *scp, int device, 945 struct ata_dmaentry *dmatab, int dir) 946{ 947 scp->flags |= ATA_DMA_ACTIVE; 948 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 949 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 950 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 951 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 952 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 953 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 954 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 955} 956 957int 958ata_dmadone(struct ata_softc *scp) 959{ 960 int error; 961 962 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 963 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 964 scp->flags &= ~ATA_DMA_ACTIVE; 965 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 966 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 967 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 968 return error & ATA_BMSTAT_MASK; 969} 970 971int 972ata_dmastatus(struct ata_softc *scp) 973{ 974 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 975} 976 977static void 978cyrix_timing(struct ata_softc *scp, int devno, int mode) 979{ 980 u_int32_t reg20 = 0x0000e132; 981 u_int32_t reg24 = 0x00017771; 982 983 switch (mode) { 984 case ATA_PIO0: reg20 = 0x0000e132; break; 985 case ATA_PIO1: reg20 = 0x00018121; break; 986 case ATA_PIO2: reg20 = 0x00024020; break; 987 case ATA_PIO3: reg20 = 0x00032010; break; 988 case ATA_PIO4: reg20 = 0x00040010; break; 989 case ATA_WDMA2: reg24 = 0x00002020; break; 990 case ATA_UDMA2: reg24 = 0x00911030; break; 991 } 992 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 993 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 994} 995 996static void 997promise_timing(struct ata_softc *scp, int devno, int mode) 998{ 999 u_int32_t timing = 0; 1000 struct promise_timing { 1001 u_int8_t pa:4; 1002 u_int8_t prefetch:1; 1003 u_int8_t iordy:1; 1004 u_int8_t errdy:1; 1005 u_int8_t syncin:1; 1006 u_int8_t pb:5; 1007 u_int8_t mb:3; 1008 u_int8_t mc:4; 1009 u_int8_t dmaw:1; 1010 u_int8_t dmar:1; 1011 u_int8_t iordyp:1; 1012 u_int8_t dmarqp:1; 1013 u_int8_t reserved:8; 1014 } *t = (struct promise_timing*)&timing; 1015 1016 t->iordy = 1; t->iordyp = 1; 1017 if (mode >= ATA_DMA) { 1018 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1019 } 1020 1021 switch (scp->chiptype) { 1022 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1023 switch (mode) { 1024 default: 1025 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1026 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1027 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1028 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1029 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1030 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1031 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1032 } 1033 break; 1034 1035 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1036 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1037 case 0x0d30105a: /* Promise OEM ATA 100 */ 1038 switch (mode) { 1039 default: 1040 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1041 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1042 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1043 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1044 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1045 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1046 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1047 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1048 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1049 } 1050 break; 1051 } 1052 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1053} 1054 1055static void 1056hpt_timing(struct ata_softc *scp, int devno, int mode) 1057{ 1058 device_t parent = device_get_parent(scp->dev); 1059 u_int32_t timing; 1060 1061 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1062 switch (mode) { 1063 case ATA_PIO0: timing = 0x06914e57; break; 1064 case ATA_PIO1: timing = 0x06914e43; break; 1065 case ATA_PIO2: timing = 0x06514e33; break; 1066 case ATA_PIO3: timing = 0x06514e22; break; 1067 case ATA_PIO4: timing = 0x06514e21; break; 1068 case ATA_WDMA2: timing = 0x26514e21; break; 1069 case ATA_UDMA2: timing = 0x16494e31; break; 1070 case ATA_UDMA4: timing = 0x16454e31; break; 1071 case ATA_UDMA5: timing = 0x16454e31; break; 1072 default: timing = 0x06514e57; 1073 } 1074 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1075 pci_write_config(parent, 0x5b, 0x22, 1); 1076 } 1077 else { /* HPT36[68] */ 1078 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1079 case 0x85: /* 25Mhz */ 1080 switch (mode) { 1081 case ATA_PIO0: timing = 0xc0d08585; break; 1082 case ATA_PIO1: timing = 0xc0d08572; break; 1083 case ATA_PIO2: timing = 0xc0ca8542; break; 1084 case ATA_PIO3: timing = 0xc0ca8532; break; 1085 case ATA_PIO4: timing = 0xc0ca8521; break; 1086 case ATA_WDMA2: timing = 0xa0ca8521; break; 1087 case ATA_UDMA2: timing = 0x90cf8521; break; 1088 case ATA_UDMA4: timing = 0x90c98521; break; 1089 default: timing = 0x01208585; 1090 } 1091 break; 1092 default: 1093 case 0xa7: /* 33MHz */ 1094 switch (mode) { 1095 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1096 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1097 case ATA_PIO2: timing = 0xc0d0a753; break; 1098 case ATA_PIO3: timing = 0xc0c8a742; break; 1099 case ATA_PIO4: timing = 0xc0c8a731; break; 1100 case ATA_WDMA2: timing = 0xa0c8a731; break; 1101 case ATA_UDMA2: timing = 0x90caa731; break; 1102 case ATA_UDMA4: timing = 0x90c9a731; break; 1103 default: timing = 0x0120a7a7; 1104 } 1105 break; 1106 case 0xd9: /* 40Mhz */ 1107 switch (mode) { 1108 case ATA_PIO0: timing = 0xc018d9d9; break; 1109 case ATA_PIO1: timing = 0xc010d9c7; break; 1110 case ATA_PIO2: timing = 0xc010d997; break; 1111 case ATA_PIO3: timing = 0xc010d974; break; 1112 case ATA_PIO4: timing = 0xc008d963; break; 1113 case ATA_WDMA2: timing = 0xa008d943; break; 1114 case ATA_UDMA2: timing = 0x900bd943; break; 1115 case ATA_UDMA4: timing = 0x900fd943; break; 1116 default: timing = 0x0120d9d9; 1117 } 1118 } 1119 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1120 } 1121}
| 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53, 363 pci_read_config(parent, 0x53, 1) | 0x03, 1); 364 scp->flags |= ATA_ATAPI_DMA_RO; 365 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 366 return; 367 } 368 } 369 pci_write_config(parent, 0x53, 370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x74091022: /* AMD 756 */ 375 if (udmamode >= 4) { 376 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 377 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 378 if (bootverbose) 379 ata_printf(scp, device, 380 "%s setting UDMA4 on AMD chip\n", 381 (error) ? "failed" : "success"); 382 if (!error) { 383 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 384 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 385 return; 386 } 387 } 388 goto via_82c586; 389 390 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 391 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 392 if (udmamode >= 5) { 393 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 394 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 395 if (bootverbose) 396 ata_printf(scp, device, 397 "%s setting UDMA5 on VIA chip\n", 398 (error) ? "failed" : "success"); 399 if (!error) { 400 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 401 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 402 return; 403 } 404 } 405 if (udmamode >= 4) { 406 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 407 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 408 if (bootverbose) 409 ata_printf(scp, device, 410 "%s setting UDMA4 on VIA chip\n", 411 (error) ? "failed" : "success"); 412 if (!error) { 413 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 414 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 415 return; 416 } 417 } 418 if (udmamode >= 2) { 419 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 420 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 421 if (bootverbose) 422 ata_printf(scp, device, 423 "%s setting UDMA2 on VIA chip\n", 424 (error) ? "failed" : "success"); 425 if (!error) { 426 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 427 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 428 return; 429 } 430 } 431 } 432 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 433 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 434 if (udmamode >= 4) { 435 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 436 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 437 if (bootverbose) 438 ata_printf(scp, device, 439 "%s setting UDMA4 on VIA chip\n", 440 (error) ? "failed" : "success"); 441 if (!error) { 442 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 443 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 444 return; 445 } 446 } 447 if (udmamode >= 2) { 448 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 449 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 450 if (bootverbose) 451 ata_printf(scp, device, 452 "%s setting UDMA2 on VIA chip\n", 453 (error) ? "failed" : "success"); 454 if (!error) { 455 pci_write_config(parent, 0x53 - devno, 0xea, 1); 456 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 457 return; 458 } 459 } 460 } 461 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 462 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 463via_82c586: 464 if (udmamode >= 2) { 465 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 466 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 467 if (bootverbose) 468 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 469 (error) ? "failed" : "success", 470 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 471 if (!error) { 472 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 473 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 474 return; 475 } 476 } 477 } 478 if (wdmamode >= 2 && apiomode >= 4) { 479 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 480 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 483 (error) ? "failed" : "success", 484 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 485 if (!error) { 486 pci_write_config(parent, 0x53 - devno, 0x82, 1); 487 pci_write_config(parent, 0x4b - devno, 0x31, 1); 488 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 489 return; 490 } 491 } 492 /* we could set PIO mode timings, but we assume the BIOS did that */ 493 break; 494 495 case 0x55131039: /* SiS 5591 */ 496 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 497 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 498 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 499 if (bootverbose) 500 ata_printf(scp, device, 501 "%s setting UDMA2 on SiS chip\n", 502 (error) ? "failed" : "success"); 503 if (!error) { 504 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 505 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 506 return; 507 } 508 } 509 if (wdmamode >=2 && apiomode >= 4) { 510 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 511 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 512 if (bootverbose) 513 ata_printf(scp, device, 514 "%s setting WDMA2 on SiS chip\n", 515 (error) ? "failed" : "success"); 516 if (!error) { 517 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 518 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 519 return; 520 } 521 } 522 /* we could set PIO mode timings, but we assume the BIOS did that */ 523 break; 524 525 case 0x06491095: /* CMD 649 ATA100 controller */ 526 if (udmamode >= 5) { 527 u_int8_t umode; 528 529 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 530 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 531 if (bootverbose) 532 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 533 (error) ? "failed" : "success"); 534 if (!error) { 535 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 536 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 537 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 538 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 539 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 540 return; 541 } 542 } 543 /* FALLTHROUGH */ 544 545 case 0x06481095: /* CMD 648 ATA66 controller */ 546 if (udmamode >= 4) { 547 u_int8_t umode; 548 549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 550 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 551 if (bootverbose) 552 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 553 (error) ? "failed" : "success"); 554 if (!error) { 555 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 556 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 557 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 558 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 559 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 560 return; 561 } 562 } 563 if (udmamode >= 2) { 564 u_int8_t umode; 565 566 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 567 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 568 if (bootverbose) 569 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 570 (error) ? "failed" : "success"); 571 if (!error) { 572 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 573 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 574 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 575 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 576 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 577 return; 578 } 579 } 580 /* make sure eventual UDMA mode from the BIOS is disabled */ 581 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 582 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 583 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 584 /* FALLTHROUGH */ 585 586 case 0x06461095: /* CMD 646 ATA controller */ 587 if (wdmamode >= 2 && apiomode >= 4) { 588 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 589 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 590 if (bootverbose) 591 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 592 error ? "failed" : "success"); 593 if (!error) { 594 int32_t offset = (devno < 3) ? (devno << 1) : 7; 595 596 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 597 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 598 return; 599 } 600 } 601 /* we could set PIO mode timings, but we assume the BIOS did that */ 602 break; 603 604 case 0xc6931080: /* Cypress 82c693 ATA controller */ 605 if (wdmamode >= 2 && apiomode >= 4) { 606 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 607 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 608 if (bootverbose) 609 ata_printf(scp, device, 610 "%s setting WDMA2 on Cypress chip\n", 611 error ? "failed" : "success"); 612 if (!error) { 613 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 614 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 615 return; 616 } 617 } 618 /* we could set PIO mode timings, but we assume the BIOS did that */ 619 break; 620 621 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 622 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 623 if (udmamode >= 2) { 624 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 625 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 626 if (bootverbose) 627 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 628 (error) ? "failed" : "success"); 629 if (!error) { 630 cyrix_timing(scp, devno, ATA_UDMA2); 631 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 632 return; 633 } 634 } 635 if (wdmamode >= 2 && apiomode >= 4) { 636 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 637 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 638 if (bootverbose) 639 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 640 (error) ? "failed" : "success"); 641 if (!error) { 642 cyrix_timing(scp, devno, ATA_WDMA2); 643 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 644 return; 645 } 646 } 647 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 648 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 649 ATA_WAIT_READY); 650 if (bootverbose) 651 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 652 (error) ? "failed" : "success", 653 ata_mode2str(ata_pio2mode(apiomode))); 654 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 655 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 656 return; 657 658 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 659 if (udmamode >= 2) { 660 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 662 if (bootverbose) 663 ata_printf(scp, device, 664 "%s setting UDMA2 on ServerWorks chip\n", 665 (error) ? "failed" : "success"); 666 if (!error) { 667 u_int16_t reg56; 668 669 pci_write_config(parent, 0x54, 670 pci_read_config(parent, 0x54, 1) | 671 (0x01 << devno), 1); 672 reg56 = pci_read_config(parent, 0x56, 2); 673 reg56 &= ~(0xf << (devno * 4)); 674 reg56 |= (0x2 << (devno * 4)); 675 pci_write_config(parent, 0x56, reg56, 2); 676 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 677 return; 678 } 679 } 680 if (wdmamode >= 2 && apiomode >= 4) { 681 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 682 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 683 if (bootverbose) 684 ata_printf(scp, device, 685 "%s setting WDMA2 on ServerWorks chip\n", 686 (error) ? "failed" : "success"); 687 if (!error) { 688 int offset = (scp->channel * 2) + (device == ATA_MASTER); 689 int word44 = pci_read_config(parent, 0x44, 4); 690 691 pci_write_config(parent, 0x54, 692 pci_read_config(parent, 0x54, 1) & 693 ~(0x01 << devno), 1); 694 word44 &= ~(0xff << (offset << 8)); 695 word44 |= (0x20 << (offset << 8)); 696 pci_write_config(parent, 0x44, 0x20, 4); 697 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 698 return; 699 } 700 } 701 /* we could set PIO mode timings, but we assume the BIOS did that */ 702 break; 703 704 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 705 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 706 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 707 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 708 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 709 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 710 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 711 break; 712 713 if (udmamode >= 5 && 714 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 715 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 716 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 717 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 718 if (bootverbose) 719 ata_printf(scp, device, 720 "%s setting UDMA5 on Promise chip\n", 721 (error) ? "failed" : "success"); 722 if (!error) { 723 promise_timing(scp, devno, ATA_UDMA5); 724 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 725 return; 726 } 727 } 728 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 729 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 730 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 731 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 732 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 733 if (bootverbose) 734 ata_printf(scp, device, 735 "%s setting UDMA4 on Promise chip\n", 736 (error) ? "failed" : "success"); 737 if (!error) { 738 promise_timing(scp, devno, ATA_UDMA4); 739 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 740 return; 741 } 742 } 743 if (udmamode >= 2) { 744 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 745 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 746 if (bootverbose) 747 ata_printf(scp, device, 748 "%s setting UDMA2 on Promise chip\n", 749 (error) ? "failed" : "success"); 750 if (!error) { 751 promise_timing(scp, devno, ATA_UDMA2); 752 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 753 return; 754 } 755 } 756 if (wdmamode >= 2 && apiomode >= 4) { 757 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 758 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 759 if (bootverbose) 760 ata_printf(scp, device, 761 "%s setting WDMA2 on Promise chip\n", 762 (error) ? "failed" : "success"); 763 if (!error) { 764 promise_timing(scp, devno, ATA_WDMA2); 765 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 766 return; 767 } 768 } 769 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 770 ata_pio2mode(apiomode), 771 ATA_C_F_SETXFER, ATA_WAIT_READY); 772 if (bootverbose) 773 ata_printf(scp, device, 774 "%s setting PIO%d on Promise chip\n", 775 (error) ? "failed" : "success", 776 (apiomode >= 0) ? apiomode : 0); 777 promise_timing(scp, devno, ata_pio2mode(apiomode)); 778 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 779 return; 780 781 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 782 /* no ATAPI devices for now */ 783 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 784 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 785 break; 786 787 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 788 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 789 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 790 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting UDMA5 on HighPoint chip\n", 794 (error) ? "failed" : "success"); 795 if (!error) { 796 hpt_timing(scp, devno, ATA_UDMA5); 797 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 798 return; 799 } 800 } 801 if (udmamode >=4 && 802 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 803 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 804 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 805 if (bootverbose) 806 ata_printf(scp, device, 807 "%s setting UDMA4 on HighPoint chip\n", 808 (error) ? "failed" : "success"); 809 if (!error) { 810 hpt_timing(scp, devno, ATA_UDMA4); 811 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 812 return; 813 } 814 } 815 if (udmamode >= 2) { 816 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 817 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 818 if (bootverbose) 819 ata_printf(scp, device, 820 "%s setting UDMA2 on HighPoint chip\n", 821 (error) ? "failed" : "success"); 822 if (!error) { 823 hpt_timing(scp, devno, ATA_UDMA2); 824 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 825 return; 826 } 827 } 828 if (wdmamode >= 2 && apiomode >= 4) { 829 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 830 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 831 if (bootverbose) 832 ata_printf(scp, device, 833 "%s setting WDMA2 on HighPoint chip\n", 834 (error) ? "failed" : "success"); 835 if (!error) { 836 hpt_timing(scp, devno, ATA_WDMA2); 837 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 838 return; 839 } 840 } 841 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 842 ata_pio2mode(apiomode), 843 ATA_C_F_SETXFER, ATA_WAIT_READY); 844 if (bootverbose) 845 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 846 (error) ? "failed" : "success", 847 (apiomode >= 0) ? apiomode : 0); 848 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 849 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 850 return; 851 852 default: /* unknown controller chip */ 853 /* better not try generic DMA on ATAPI devices it almost never works */ 854 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 855 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 856 break; 857 858 /* if controller says its setup for DMA take the easy way out */ 859 /* the downside is we dont know what DMA mode we are in */ 860 if ((udmamode >= 0 || wdmamode > 1) && 861 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 862 ((device==ATA_MASTER) ? 863 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 864 scp->mode[ATA_DEV(device)] = ATA_DMA; 865 return; 866 } 867 868 /* well, we have no support for this, but try anyways */ 869 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 870 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 871 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 872 if (bootverbose) 873 ata_printf(scp, device, 874 "%s setting WDMA2 on generic chip\n", 875 (error) ? "failed" : "success"); 876 if (!error) { 877 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 878 return; 879 } 880 } 881 } 882 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 883 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 884 if (bootverbose) 885 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 886 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 887 if (!error) 888 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 889 else { 890 if (bootverbose) 891 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 892 scp->mode[ATA_DEV(device)] = ATA_PIO; 893 } 894} 895 896int 897ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 898 caddr_t data, int32_t count) 899{ 900 u_int32_t dma_count, dma_base; 901 int i = 0; 902 903 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 904 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 905 return -1; 906 } 907 908 if (!count) { 909 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 910 return -1; 911 } 912 913 dma_base = vtophys(data); 914 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 915 data += dma_count; 916 count -= dma_count; 917 918 while (count) { 919 dmatab[i].base = dma_base; 920 dmatab[i].count = (dma_count & 0xffff); 921 i++; 922 if (i >= ATA_DMA_ENTRIES) { 923 ata_printf(scp, device, "too many segments in DMA table\n"); 924 return -1; 925 } 926 dma_base = vtophys(data); 927 dma_count = min(count, PAGE_SIZE); 928 data += min(count, PAGE_SIZE); 929 count -= min(count, PAGE_SIZE); 930 } 931 dmatab[i].base = dma_base; 932 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 933 return 0; 934} 935 936void 937ata_dmastart(struct ata_softc *scp, int device, 938 struct ata_dmaentry *dmatab, int dir) 939{ 940 scp->flags |= ATA_DMA_ACTIVE; 941 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 942 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 943 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 944 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 945 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 946 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 947 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 948} 949 950int 951ata_dmadone(struct ata_softc *scp) 952{ 953 int error; 954 955 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 956 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 957 scp->flags &= ~ATA_DMA_ACTIVE; 958 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 959 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 960 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 961 return error & ATA_BMSTAT_MASK; 962} 963 964int 965ata_dmastatus(struct ata_softc *scp) 966{ 967 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 968} 969 970static void 971cyrix_timing(struct ata_softc *scp, int devno, int mode) 972{ 973 u_int32_t reg20 = 0x0000e132; 974 u_int32_t reg24 = 0x00017771; 975 976 switch (mode) { 977 case ATA_PIO0: reg20 = 0x0000e132; break; 978 case ATA_PIO1: reg20 = 0x00018121; break; 979 case ATA_PIO2: reg20 = 0x00024020; break; 980 case ATA_PIO3: reg20 = 0x00032010; break; 981 case ATA_PIO4: reg20 = 0x00040010; break; 982 case ATA_WDMA2: reg24 = 0x00002020; break; 983 case ATA_UDMA2: reg24 = 0x00911030; break; 984 } 985 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 986 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 987} 988 989static void 990promise_timing(struct ata_softc *scp, int devno, int mode) 991{ 992 u_int32_t timing = 0; 993 struct promise_timing { 994 u_int8_t pa:4; 995 u_int8_t prefetch:1; 996 u_int8_t iordy:1; 997 u_int8_t errdy:1; 998 u_int8_t syncin:1; 999 u_int8_t pb:5; 1000 u_int8_t mb:3; 1001 u_int8_t mc:4; 1002 u_int8_t dmaw:1; 1003 u_int8_t dmar:1; 1004 u_int8_t iordyp:1; 1005 u_int8_t dmarqp:1; 1006 u_int8_t reserved:8; 1007 } *t = (struct promise_timing*)&timing; 1008 1009 t->iordy = 1; t->iordyp = 1; 1010 if (mode >= ATA_DMA) { 1011 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1012 } 1013 1014 switch (scp->chiptype) { 1015 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1016 switch (mode) { 1017 default: 1018 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1019 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1020 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1021 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1022 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1023 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1024 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1025 } 1026 break; 1027 1028 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1029 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1030 case 0x0d30105a: /* Promise OEM ATA 100 */ 1031 switch (mode) { 1032 default: 1033 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1034 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1035 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1036 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1037 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1038 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1039 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1040 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1041 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1042 } 1043 break; 1044 } 1045 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1046} 1047 1048static void 1049hpt_timing(struct ata_softc *scp, int devno, int mode) 1050{ 1051 device_t parent = device_get_parent(scp->dev); 1052 u_int32_t timing; 1053 1054 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1055 switch (mode) { 1056 case ATA_PIO0: timing = 0x06914e57; break; 1057 case ATA_PIO1: timing = 0x06914e43; break; 1058 case ATA_PIO2: timing = 0x06514e33; break; 1059 case ATA_PIO3: timing = 0x06514e22; break; 1060 case ATA_PIO4: timing = 0x06514e21; break; 1061 case ATA_WDMA2: timing = 0x26514e21; break; 1062 case ATA_UDMA2: timing = 0x16494e31; break; 1063 case ATA_UDMA4: timing = 0x16454e31; break; 1064 case ATA_UDMA5: timing = 0x16454e31; break; 1065 default: timing = 0x06514e57; 1066 } 1067 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1068 pci_write_config(parent, 0x5b, 0x22, 1); 1069 } 1070 else { /* HPT36[68] */ 1071 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1072 case 0x85: /* 25Mhz */ 1073 switch (mode) { 1074 case ATA_PIO0: timing = 0xc0d08585; break; 1075 case ATA_PIO1: timing = 0xc0d08572; break; 1076 case ATA_PIO2: timing = 0xc0ca8542; break; 1077 case ATA_PIO3: timing = 0xc0ca8532; break; 1078 case ATA_PIO4: timing = 0xc0ca8521; break; 1079 case ATA_WDMA2: timing = 0xa0ca8521; break; 1080 case ATA_UDMA2: timing = 0x90cf8521; break; 1081 case ATA_UDMA4: timing = 0x90c98521; break; 1082 default: timing = 0x01208585; 1083 } 1084 break; 1085 default: 1086 case 0xa7: /* 33MHz */ 1087 switch (mode) { 1088 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1089 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1090 case ATA_PIO2: timing = 0xc0d0a753; break; 1091 case ATA_PIO3: timing = 0xc0c8a742; break; 1092 case ATA_PIO4: timing = 0xc0c8a731; break; 1093 case ATA_WDMA2: timing = 0xa0c8a731; break; 1094 case ATA_UDMA2: timing = 0x90caa731; break; 1095 case ATA_UDMA4: timing = 0x90c9a731; break; 1096 default: timing = 0x0120a7a7; 1097 } 1098 break; 1099 case 0xd9: /* 40Mhz */ 1100 switch (mode) { 1101 case ATA_PIO0: timing = 0xc018d9d9; break; 1102 case ATA_PIO1: timing = 0xc010d9c7; break; 1103 case ATA_PIO2: timing = 0xc010d997; break; 1104 case ATA_PIO3: timing = 0xc010d974; break; 1105 case ATA_PIO4: timing = 0xc008d963; break; 1106 case ATA_WDMA2: timing = 0xa008d943; break; 1107 case ATA_UDMA2: timing = 0x900bd943; break; 1108 case ATA_UDMA4: timing = 0x900fd943; break; 1109 default: timing = 0x0120d9d9; 1110 } 1111 } 1112 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1113 } 1114}
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