95 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 96 return; 97 } 98 } 99 100 /* DMA engine address alignment is usually 1 word (2 bytes) */ 101 scp->alignment = 0x1; 102 103 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 104 ata_printf(scp, device, 105 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 106 udmamode = 2; 107 } 108 109 switch (scp->chiptype) { 110 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on ICH2 chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on ICH%s chip\n", 153 (error) ? "failed" : "success", 154 (scp->chiptype == 0x244b8086) ? "2" : ""); 155 if (!error) { 156 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 157 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 158 pci_write_config(parent, 0x48, 159 (pci_read_config(parent, 0x48, 4) & 160 ~mask48) | new48, 4); 161 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 162 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 163 return; 164 } 165 } 166 } 167 /* make sure eventual ATA66 mode from the BIOS is disabled */ 168 pci_write_config(parent, 0x54, 169 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 170 /* FALLTHROUGH */ 171 172 case 0x71118086: /* Intel PIIX4 */ 173 case 0x71998086: /* Intel PIIX4e */ 174 case 0x24218086: /* Intel ICH0 */ 175 if (udmamode >= 2) { 176 int32_t mask48, new48; 177 178 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 180 if (bootverbose) 181 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 182 (error) ? "failed" : "success", 183 (scp->chiptype == 0x244b8086) ? "ICH2" : 184 (scp->chiptype == 0x24118086) ? "ICH" : 185 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 186 if (!error) { 187 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 188 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 189 pci_write_config(parent, 0x48, 190 (pci_read_config(parent, 0x48, 4) & 191 ~mask48) | new48, 4); 192 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 193 return; 194 } 195 } 196 /* make sure eventual ATA33 mode from the BIOS is disabled */ 197 pci_write_config(parent, 0x48, 198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 199 /* FALLTHROUGH */ 200 201 case 0x70108086: /* Intel PIIX3 */ 202 if (wdmamode >= 2 && apiomode >= 4) { 203 int32_t mask40, new40, mask44, new44; 204 205 /* if SITRE not set doit for both channels */ 206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 207 new40 = pci_read_config(parent, 0x40, 4); 208 new44 = pci_read_config(parent, 0x44, 4); 209 if (!(new40 & 0x00004000)) { 210 new44 &= ~0x0000000f; 211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 212 } 213 if (!(new40 & 0x40000000)) { 214 new44 &= ~0x000000f0; 215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 216 } 217 new40 |= 0x40004000; 218 pci_write_config(parent, 0x40, new40, 4); 219 pci_write_config(parent, 0x44, new44, 4); 220 } 221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 223 if (bootverbose) 224 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 225 (error) ? "failed" : "success", 226 (scp->chiptype == 0x244b8086) ? "ICH2" : 227 (scp->chiptype == 0x24118086) ? "ICH" : 228 (scp->chiptype == 0x24218086) ? "ICH0" : 229 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 230 if (!error) { 231 if (device == ATA_MASTER) { 232 mask40 = 0x0000330f; 233 new40 = 0x00002307; 234 mask44 = 0; 235 new44 = 0; 236 } 237 else { 238 mask40 = 0x000000f0; 239 new40 = 0x00000070; 240 mask44 = 0x0000000f; 241 new44 = 0x0000000b; 242 } 243 if (scp->channel) { 244 mask40 <<= 16; 245 new40 <<= 16; 246 mask44 <<= 4; 247 new44 <<= 4; 248 } 249 pci_write_config(parent, 0x40, 250 (pci_read_config(parent, 0x40, 4) & ~mask40)| 251 new40, 4); 252 pci_write_config(parent, 0x44, 253 (pci_read_config(parent, 0x44, 4) & ~mask44)| 254 new44, 4); 255 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 256 return; 257 } 258 } 259 /* we could set PIO mode timings, but we assume the BIOS did that */ 260 break; 261 262 case 0x12308086: /* Intel PIIX */ 263 if (wdmamode >= 2 && apiomode >= 4) { 264 int32_t word40; 265 266 word40 = pci_read_config(parent, 0x40, 4); 267 word40 >>= scp->channel * 16; 268 269 /* Check for timing config usable for DMA on controller */ 270 if (!((word40 & 0x3300) == 0x2300 && 271 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 272 break; 273 274 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 275 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 276 if (bootverbose) 277 ata_printf(scp, device, 278 "%s setting WDMA2 on PIIX chip\n", 279 (error) ? "failed" : "success"); 280 if (!error) { 281 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 282 return; 283 } 284 } 285 break; 286 287 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 288 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 289 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 290 ata_printf(scp, device, 291 "Aladdin: two atapi devices on this channel, no DMA\n"); 292 break; 293 } 294 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 298 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA2 on Aladdin chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000a0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->flags |= ATA_ATAPI_DMA_RO; 310 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 311 return; 312 } 313 } 314 315 /* make sure eventual UDMA mode from the BIOS is disabled */ 316 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 317 ~(0x0008 << (devno << 2)), 2); 318 319 if (wdmamode >= 2 && apiomode >= 4) { 320 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 321 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 322 if (bootverbose) 323 ata_printf(scp, device, 324 "%s setting WDMA2 on Aladdin chip\n", 325 (error) ? "failed" : "success"); 326 if (!error) { 327 pci_write_config(parent, 0x53, 328 pci_read_config(parent, 0x53, 1) | 0x03, 1); 329 scp->flags |= ATA_ATAPI_DMA_RO; 330 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 331 return; 332 } 333 } 334 pci_write_config(parent, 0x53, 335 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 336 /* we could set PIO mode timings, but we assume the BIOS did that */ 337 break; 338 339 case 0x74091022: /* AMD 756 */ 340 if (udmamode >= 4) { 341 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 342 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 343 if (bootverbose) 344 ata_printf(scp, device, 345 "%s setting UDMA4 on AMD chip\n", 346 (error) ? "failed" : "success"); 347 if (!error) { 348 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 349 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 350 return; 351 } 352 } 353 goto via_82c586; 354 355 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 356 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 357 if (udmamode >= 5) { 358 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 359 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 360 if (bootverbose) 361 ata_printf(scp, device, 362 "%s setting UDMA5 on VIA chip\n", 363 (error) ? "failed" : "success"); 364 if (!error) { 365 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 366 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 367 return; 368 } 369 } 370 if (udmamode >= 4) { 371 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 372 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 373 if (bootverbose) 374 ata_printf(scp, device, 375 "%s setting UDMA4 on VIA chip\n", 376 (error) ? "failed" : "success"); 377 if (!error) { 378 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 379 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 380 return; 381 } 382 } 383 if (udmamode >= 2) { 384 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 385 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 386 if (bootverbose) 387 ata_printf(scp, device, 388 "%s setting UDMA2 on VIA chip\n", 389 (error) ? "failed" : "success"); 390 if (!error) { 391 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 392 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 393 return; 394 } 395 } 396 } 397 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 398 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 399 if (udmamode >= 4) { 400 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 401 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 402 if (bootverbose) 403 ata_printf(scp, device, 404 "%s setting UDMA4 on VIA chip\n", 405 (error) ? "failed" : "success"); 406 if (!error) { 407 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 408 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 409 return; 410 } 411 } 412 if (udmamode >= 2) { 413 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 414 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 415 if (bootverbose) 416 ata_printf(scp, device, 417 "%s setting UDMA2 on VIA chip\n", 418 (error) ? "failed" : "success"); 419 if (!error) { 420 pci_write_config(parent, 0x53 - devno, 0xea, 1); 421 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 422 return; 423 } 424 } 425 } 426 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 427 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 428via_82c586: 429 if (udmamode >= 2) { 430 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 431 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 432 if (bootverbose) 433 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 434 (error) ? "failed" : "success", 435 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 436 if (!error) { 437 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 438 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 439 return; 440 } 441 } 442 } 443 if (wdmamode >= 2 && apiomode >= 4) { 444 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 445 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 446 if (bootverbose) 447 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 448 (error) ? "failed" : "success", 449 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 450 if (!error) { 451 pci_write_config(parent, 0x53 - devno, 0x82, 1); 452 pci_write_config(parent, 0x4b - devno, 0x31, 1); 453 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 454 return; 455 } 456 } 457 /* we could set PIO mode timings, but we assume the BIOS did that */ 458 break; 459 460 case 0x55131039: /* SiS 5591 */ 461 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 463 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 464 if (bootverbose) 465 ata_printf(scp, device, 466 "%s setting UDMA2 on SiS chip\n", 467 (error) ? "failed" : "success"); 468 if (!error) { 469 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 470 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 471 return; 472 } 473 } 474 if (wdmamode >=2 && apiomode >= 4) { 475 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 476 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 477 if (bootverbose) 478 ata_printf(scp, device, 479 "%s setting WDMA2 on SiS chip\n", 480 (error) ? "failed" : "success"); 481 if (!error) { 482 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 483 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 484 return; 485 } 486 } 487 /* we could set PIO mode timings, but we assume the BIOS did that */ 488 break; 489 490 case 0x06491095: /* CMD 649 ATA100 controller */ 491 if (udmamode >= 5) { 492 u_int8_t umode; 493 494 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 495 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 496 if (bootverbose) 497 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 498 (error) ? "failed" : "success"); 499 if (!error) { 500 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 501 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 502 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 503 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 504 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 505 return; 506 } 507 } 508 /* FALLTHROUGH */ 509 510 case 0x06481095: /* CMD 648 ATA66 controller */ 511 if (udmamode >= 4) { 512 u_int8_t umode; 513 514 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 515 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 516 if (bootverbose) 517 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 518 (error) ? "failed" : "success"); 519 if (!error) { 520 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 521 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 522 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 523 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 524 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 525 return; 526 } 527 } 528 if (udmamode >= 2) { 529 u_int8_t umode; 530 531 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 532 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 533 if (bootverbose) 534 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 535 (error) ? "failed" : "success"); 536 if (!error) { 537 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 538 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 539 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 540 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 541 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 542 return; 543 } 544 } 545 /* make sure eventual UDMA mode from the BIOS is disabled */ 546 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 547 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 548 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 549 /* FALLTHROUGH */ 550 551 case 0x06461095: /* CMD 646 ATA controller */ 552 if (wdmamode >= 2 && apiomode >= 4) { 553 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 554 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 555 if (bootverbose) 556 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 557 error ? "failed" : "success"); 558 if (!error) { 559 int32_t offset = (devno < 3) ? (devno << 1) : 7; 560 561 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 562 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 563 return; 564 } 565 } 566 /* we could set PIO mode timings, but we assume the BIOS did that */ 567 break; 568 569 case 0xc6931080: /* Cypress 82c693 ATA controller */ 570 if (wdmamode >= 2 && apiomode >= 4) { 571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 572 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 573 if (bootverbose) 574 ata_printf(scp, device, 575 "%s setting WDMA2 on Cypress chip\n", 576 error ? "failed" : "success"); 577 if (!error) { 578 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 579 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 580 return; 581 } 582 } 583 /* we could set PIO mode timings, but we assume the BIOS did that */ 584 break; 585 586 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 587 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 588 if (udmamode >= 2) { 589 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 590 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 593 (error) ? "failed" : "success"); 594 if (!error) { 595 cyrix_timing(scp, devno, ATA_UDMA2); 596 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 597 return; 598 } 599 } 600 if (wdmamode >= 2 && apiomode >= 4) { 601 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 602 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 603 if (bootverbose) 604 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 605 (error) ? "failed" : "success"); 606 if (!error) { 607 cyrix_timing(scp, devno, ATA_WDMA2); 608 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 609 return; 610 } 611 } 612 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 613 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 614 ATA_WAIT_READY); 615 if (bootverbose) 616 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 617 (error) ? "failed" : "success", 618 ata_mode2str(ata_pio2mode(apiomode))); 619 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 620 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 621 return; 622 623 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 624 if (udmamode >= 2) { 625 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 626 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 627 if (bootverbose) 628 ata_printf(scp, device, 629 "%s setting UDMA2 on ServerWorks chip\n", 630 (error) ? "failed" : "success"); 631 if (!error) { 632 u_int16_t reg56; 633 634 pci_write_config(parent, 0x54, 635 pci_read_config(parent, 0x54, 1) | 636 (0x01 << devno), 1); 637 reg56 = pci_read_config(parent, 0x56, 2); 638 reg56 &= ~(0xf << (devno * 4)); 639 reg56 |= (0x2 << (devno * 4)); 640 pci_write_config(parent, 0x56, reg56, 2); 641 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 642 return; 643 } 644 } 645 if (wdmamode >= 2 && apiomode >= 4) { 646 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 647 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 648 if (bootverbose) 649 ata_printf(scp, device, 650 "%s setting WDMA2 on ServerWorks chip\n", 651 (error) ? "failed" : "success"); 652 if (!error) { 653 int offset = (scp->channel * 2) + (device == ATA_MASTER); 654 int word44 = pci_read_config(parent, 0x44, 4); 655 656 pci_write_config(parent, 0x54, 657 pci_read_config(parent, 0x54, 1) & 658 ~(0x01 << devno), 1); 659 word44 &= ~(0xff << (offset << 8)); 660 word44 |= (0x20 << (offset << 8)); 661 pci_write_config(parent, 0x44, 0x20, 4); 662 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 663 return; 664 } 665 } 666 /* we could set PIO mode timings, but we assume the BIOS did that */ 667 break; 668 669 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 670 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 671 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 672 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 673 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 674 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 675 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 676 break; 677 678 if (udmamode >= 5 && 679 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 680 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 681 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 682 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 683 if (bootverbose) 684 ata_printf(scp, device, 685 "%s setting UDMA5 on Promise chip\n", 686 (error) ? "failed" : "success"); 687 if (!error) { 688 promise_timing(scp, devno, ATA_UDMA5); 689 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 690 return; 691 } 692 } 693 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 694 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 695 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 696 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 697 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 698 if (bootverbose) 699 ata_printf(scp, device, 700 "%s setting UDMA4 on Promise chip\n", 701 (error) ? "failed" : "success"); 702 if (!error) { 703 promise_timing(scp, devno, ATA_UDMA4); 704 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 705 return; 706 } 707 } 708 if (udmamode >= 2) { 709 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 710 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 711 if (bootverbose) 712 ata_printf(scp, device, 713 "%s setting UDMA2 on Promise chip\n", 714 (error) ? "failed" : "success"); 715 if (!error) { 716 promise_timing(scp, devno, ATA_UDMA2); 717 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 718 return; 719 } 720 } 721 if (wdmamode >= 2 && apiomode >= 4) { 722 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 723 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 724 if (bootverbose) 725 ata_printf(scp, device, 726 "%s setting WDMA2 on Promise chip\n", 727 (error) ? "failed" : "success"); 728 if (!error) { 729 promise_timing(scp, devno, ATA_WDMA2); 730 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 731 return; 732 } 733 } 734 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 735 ata_pio2mode(apiomode), 736 ATA_C_F_SETXFER, ATA_WAIT_READY); 737 if (bootverbose) 738 ata_printf(scp, device, 739 "%s setting PIO%d on Promise chip\n", 740 (error) ? "failed" : "success", 741 (apiomode >= 0) ? apiomode : 0); 742 promise_timing(scp, devno, ata_pio2mode(apiomode)); 743 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 744 return; 745 746 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 747 /* no ATAPI devices for now */ 748 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 749 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 750 break; 751 752 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 753 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 754 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 755 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 756 if (bootverbose) 757 ata_printf(scp, device, 758 "%s setting UDMA5 on HighPoint chip\n", 759 (error) ? "failed" : "success"); 760 if (!error) { 761 hpt_timing(scp, devno, ATA_UDMA5); 762 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 763 return; 764 } 765 } 766 if (udmamode >=4 && 767 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 768 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 769 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 770 if (bootverbose) 771 ata_printf(scp, device, 772 "%s setting UDMA4 on HighPoint chip\n", 773 (error) ? "failed" : "success"); 774 if (!error) { 775 hpt_timing(scp, devno, ATA_UDMA4); 776 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 777 return; 778 } 779 } 780 if (udmamode >= 2) { 781 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 782 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 783 if (bootverbose) 784 ata_printf(scp, device, 785 "%s setting UDMA2 on HighPoint chip\n", 786 (error) ? "failed" : "success"); 787 if (!error) { 788 hpt_timing(scp, devno, ATA_UDMA2); 789 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 790 return; 791 } 792 } 793 if (wdmamode >= 2 && apiomode >= 4) { 794 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 795 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 796 if (bootverbose) 797 ata_printf(scp, device, 798 "%s setting WDMA2 on HighPoint chip\n", 799 (error) ? "failed" : "success"); 800 if (!error) { 801 hpt_timing(scp, devno, ATA_WDMA2); 802 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 803 return; 804 } 805 } 806 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 807 ata_pio2mode(apiomode), 808 ATA_C_F_SETXFER, ATA_WAIT_READY); 809 if (bootverbose) 810 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 811 (error) ? "failed" : "success", 812 (apiomode >= 0) ? apiomode : 0); 813 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 814 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 815 return; 816 817 default: /* unknown controller chip */ 818 /* better not try generic DMA on ATAPI devices it almost never works */ 819 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 820 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 821 break; 822 823 /* if controller says its setup for DMA take the easy way out */ 824 /* the downside is we dont know what DMA mode we are in */ 825 if ((udmamode >= 0 || wdmamode > 1) &&
| 97 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 98 return; 99 } 100 } 101 102 /* DMA engine address alignment is usually 1 word (2 bytes) */ 103 scp->alignment = 0x1; 104 105 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 106 ata_printf(scp, device, 107 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 108 udmamode = 2; 109 } 110 111 switch (scp->chiptype) { 112 113 case 0x244b8086: /* Intel ICH2 */ 114 if (udmamode >= 5) { 115 int32_t mask48, new48; 116 int16_t word54; 117 118 word54 = pci_read_config(parent, 0x54, 2); 119 if (word54 & (0x10 << devno)) { 120 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 121 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 122 if (bootverbose) 123 ata_printf(scp, device, 124 "%s setting UDMA5 on ICH2 chip\n", 125 (error) ? "failed" : "success"); 126 if (!error) { 127 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 128 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 129 pci_write_config(parent, 0x48, 130 (pci_read_config(parent, 0x48, 4) & 131 ~mask48) | new48, 4); 132 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 133 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 134 return; 135 } 136 } 137 } 138 /* make sure eventual ATA100 mode from the BIOS is disabled */ 139 pci_write_config(parent, 0x54, 140 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 141 /* FALLTHROUGH */ 142 143 case 0x24118086: /* Intel ICH */ 144 if (udmamode >= 4) { 145 int32_t mask48, new48; 146 int16_t word54; 147 148 word54 = pci_read_config(parent, 0x54, 2); 149 if (word54 & (0x10 << devno)) { 150 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 151 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 152 if (bootverbose) 153 ata_printf(scp, device, 154 "%s setting UDMA4 on ICH%s chip\n", 155 (error) ? "failed" : "success", 156 (scp->chiptype == 0x244b8086) ? "2" : ""); 157 if (!error) { 158 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 159 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 160 pci_write_config(parent, 0x48, 161 (pci_read_config(parent, 0x48, 4) & 162 ~mask48) | new48, 4); 163 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 164 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 165 return; 166 } 167 } 168 } 169 /* make sure eventual ATA66 mode from the BIOS is disabled */ 170 pci_write_config(parent, 0x54, 171 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 172 /* FALLTHROUGH */ 173 174 case 0x71118086: /* Intel PIIX4 */ 175 case 0x71998086: /* Intel PIIX4e */ 176 case 0x24218086: /* Intel ICH0 */ 177 if (udmamode >= 2) { 178 int32_t mask48, new48; 179 180 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 181 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 182 if (bootverbose) 183 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 184 (error) ? "failed" : "success", 185 (scp->chiptype == 0x244b8086) ? "ICH2" : 186 (scp->chiptype == 0x24118086) ? "ICH" : 187 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 188 if (!error) { 189 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 190 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 191 pci_write_config(parent, 0x48, 192 (pci_read_config(parent, 0x48, 4) & 193 ~mask48) | new48, 4); 194 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 195 return; 196 } 197 } 198 /* make sure eventual ATA33 mode from the BIOS is disabled */ 199 pci_write_config(parent, 0x48, 200 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 201 /* FALLTHROUGH */ 202 203 case 0x70108086: /* Intel PIIX3 */ 204 if (wdmamode >= 2 && apiomode >= 4) { 205 int32_t mask40, new40, mask44, new44; 206 207 /* if SITRE not set doit for both channels */ 208 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 209 new40 = pci_read_config(parent, 0x40, 4); 210 new44 = pci_read_config(parent, 0x44, 4); 211 if (!(new40 & 0x00004000)) { 212 new44 &= ~0x0000000f; 213 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 214 } 215 if (!(new40 & 0x40000000)) { 216 new44 &= ~0x000000f0; 217 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 218 } 219 new40 |= 0x40004000; 220 pci_write_config(parent, 0x40, new40, 4); 221 pci_write_config(parent, 0x44, new44, 4); 222 } 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 227 (error) ? "failed" : "success", 228 (scp->chiptype == 0x244b8086) ? "ICH2" : 229 (scp->chiptype == 0x24118086) ? "ICH" : 230 (scp->chiptype == 0x24218086) ? "ICH0" : 231 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 232 if (!error) { 233 if (device == ATA_MASTER) { 234 mask40 = 0x0000330f; 235 new40 = 0x00002307; 236 mask44 = 0; 237 new44 = 0; 238 } 239 else { 240 mask40 = 0x000000f0; 241 new40 = 0x00000070; 242 mask44 = 0x0000000f; 243 new44 = 0x0000000b; 244 } 245 if (scp->channel) { 246 mask40 <<= 16; 247 new40 <<= 16; 248 mask44 <<= 4; 249 new44 <<= 4; 250 } 251 pci_write_config(parent, 0x40, 252 (pci_read_config(parent, 0x40, 4) & ~mask40)| 253 new40, 4); 254 pci_write_config(parent, 0x44, 255 (pci_read_config(parent, 0x44, 4) & ~mask44)| 256 new44, 4); 257 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 258 return; 259 } 260 } 261 /* we could set PIO mode timings, but we assume the BIOS did that */ 262 break; 263 264 case 0x12308086: /* Intel PIIX */ 265 if (wdmamode >= 2 && apiomode >= 4) { 266 int32_t word40; 267 268 word40 = pci_read_config(parent, 0x40, 4); 269 word40 >>= scp->channel * 16; 270 271 /* Check for timing config usable for DMA on controller */ 272 if (!((word40 & 0x3300) == 0x2300 && 273 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 274 break; 275 276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 277 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 278 if (bootverbose) 279 ata_printf(scp, device, 280 "%s setting WDMA2 on PIIX chip\n", 281 (error) ? "failed" : "success"); 282 if (!error) { 283 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 284 return; 285 } 286 } 287 break; 288 289 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 290 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 291 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 292 ata_printf(scp, device, 293 "Aladdin: two atapi devices on this channel, no DMA\n"); 294 break; 295 } 296 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 297 int32_t word54 = pci_read_config(parent, 0x54, 4); 298 299 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 300 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 301 if (bootverbose) 302 ata_printf(scp, device, 303 "%s setting UDMA2 on Aladdin chip\n", 304 (error) ? "failed" : "success"); 305 if (!error) { 306 word54 &= ~(0x000f000f << (devno << 2)); 307 word54 |= (0x000a0005 << (devno << 2)); 308 pci_write_config(parent, 0x54, word54, 4); 309 pci_write_config(parent, 0x53, 310 pci_read_config(parent, 0x53, 1) | 0x03, 1); 311 scp->flags |= ATA_ATAPI_DMA_RO; 312 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 313 return; 314 } 315 } 316 317 /* make sure eventual UDMA mode from the BIOS is disabled */ 318 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 319 ~(0x0008 << (devno << 2)), 2); 320 321 if (wdmamode >= 2 && apiomode >= 4) { 322 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 323 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 324 if (bootverbose) 325 ata_printf(scp, device, 326 "%s setting WDMA2 on Aladdin chip\n", 327 (error) ? "failed" : "success"); 328 if (!error) { 329 pci_write_config(parent, 0x53, 330 pci_read_config(parent, 0x53, 1) | 0x03, 1); 331 scp->flags |= ATA_ATAPI_DMA_RO; 332 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 333 return; 334 } 335 } 336 pci_write_config(parent, 0x53, 337 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 338 /* we could set PIO mode timings, but we assume the BIOS did that */ 339 break; 340 341 case 0x74091022: /* AMD 756 */ 342 if (udmamode >= 4) { 343 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 344 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 345 if (bootverbose) 346 ata_printf(scp, device, 347 "%s setting UDMA4 on AMD chip\n", 348 (error) ? "failed" : "success"); 349 if (!error) { 350 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 351 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 352 return; 353 } 354 } 355 goto via_82c586; 356 357 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 358 if (ata_find_dev(parent, 0x06861106, 0x40)) { /* 82C686b */ 359 if (udmamode >= 5) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 361 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting UDMA5 on VIA chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 368 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 369 return; 370 } 371 } 372 if (udmamode >= 4) { 373 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 374 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 375 if (bootverbose) 376 ata_printf(scp, device, 377 "%s setting UDMA4 on VIA chip\n", 378 (error) ? "failed" : "success"); 379 if (!error) { 380 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 381 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 382 return; 383 } 384 } 385 if (udmamode >= 2) { 386 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 387 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 388 if (bootverbose) 389 ata_printf(scp, device, 390 "%s setting UDMA2 on VIA chip\n", 391 (error) ? "failed" : "success"); 392 if (!error) { 393 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 394 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 395 return; 396 } 397 } 398 } 399 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 400 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 401 if (udmamode >= 4) { 402 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 403 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 404 if (bootverbose) 405 ata_printf(scp, device, 406 "%s setting UDMA4 on VIA chip\n", 407 (error) ? "failed" : "success"); 408 if (!error) { 409 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 410 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 411 return; 412 } 413 } 414 if (udmamode >= 2) { 415 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 416 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 417 if (bootverbose) 418 ata_printf(scp, device, 419 "%s setting UDMA2 on VIA chip\n", 420 (error) ? "failed" : "success"); 421 if (!error) { 422 pci_write_config(parent, 0x53 - devno, 0xea, 1); 423 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 424 return; 425 } 426 } 427 } 428 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 429 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 430via_82c586: 431 if (udmamode >= 2) { 432 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 433 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 434 if (bootverbose) 435 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 436 (error) ? "failed" : "success", 437 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 438 if (!error) { 439 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 440 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 441 return; 442 } 443 } 444 } 445 if (wdmamode >= 2 && apiomode >= 4) { 446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 447 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 448 if (bootverbose) 449 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 450 (error) ? "failed" : "success", 451 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 452 if (!error) { 453 pci_write_config(parent, 0x53 - devno, 0x82, 1); 454 pci_write_config(parent, 0x4b - devno, 0x31, 1); 455 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 456 return; 457 } 458 } 459 /* we could set PIO mode timings, but we assume the BIOS did that */ 460 break; 461 462 case 0x55131039: /* SiS 5591 */ 463 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 464 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 465 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 466 if (bootverbose) 467 ata_printf(scp, device, 468 "%s setting UDMA2 on SiS chip\n", 469 (error) ? "failed" : "success"); 470 if (!error) { 471 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 472 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 473 return; 474 } 475 } 476 if (wdmamode >=2 && apiomode >= 4) { 477 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 478 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 479 if (bootverbose) 480 ata_printf(scp, device, 481 "%s setting WDMA2 on SiS chip\n", 482 (error) ? "failed" : "success"); 483 if (!error) { 484 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 485 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 486 return; 487 } 488 } 489 /* we could set PIO mode timings, but we assume the BIOS did that */ 490 break; 491 492 case 0x06491095: /* CMD 649 ATA100 controller */ 493 if (udmamode >= 5) { 494 u_int8_t umode; 495 496 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 497 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 498 if (bootverbose) 499 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 500 (error) ? "failed" : "success"); 501 if (!error) { 502 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 503 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 504 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 505 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 506 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 507 return; 508 } 509 } 510 /* FALLTHROUGH */ 511 512 case 0x06481095: /* CMD 648 ATA66 controller */ 513 if (udmamode >= 4) { 514 u_int8_t umode; 515 516 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 517 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 518 if (bootverbose) 519 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 520 (error) ? "failed" : "success"); 521 if (!error) { 522 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 523 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 524 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 525 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 526 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 527 return; 528 } 529 } 530 if (udmamode >= 2) { 531 u_int8_t umode; 532 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 534 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 537 (error) ? "failed" : "success"); 538 if (!error) { 539 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 540 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 541 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 542 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 543 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 544 return; 545 } 546 } 547 /* make sure eventual UDMA mode from the BIOS is disabled */ 548 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 549 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 550 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 551 /* FALLTHROUGH */ 552 553 case 0x06461095: /* CMD 646 ATA controller */ 554 if (wdmamode >= 2 && apiomode >= 4) { 555 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 556 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 557 if (bootverbose) 558 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 559 error ? "failed" : "success"); 560 if (!error) { 561 int32_t offset = (devno < 3) ? (devno << 1) : 7; 562 563 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 564 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 565 return; 566 } 567 } 568 /* we could set PIO mode timings, but we assume the BIOS did that */ 569 break; 570 571 case 0xc6931080: /* Cypress 82c693 ATA controller */ 572 if (wdmamode >= 2 && apiomode >= 4) { 573 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 574 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 575 if (bootverbose) 576 ata_printf(scp, device, 577 "%s setting WDMA2 on Cypress chip\n", 578 error ? "failed" : "success"); 579 if (!error) { 580 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 581 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 582 return; 583 } 584 } 585 /* we could set PIO mode timings, but we assume the BIOS did that */ 586 break; 587 588 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 589 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 590 if (udmamode >= 2) { 591 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 592 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 593 if (bootverbose) 594 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 595 (error) ? "failed" : "success"); 596 if (!error) { 597 cyrix_timing(scp, devno, ATA_UDMA2); 598 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 599 return; 600 } 601 } 602 if (wdmamode >= 2 && apiomode >= 4) { 603 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 604 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 605 if (bootverbose) 606 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 607 (error) ? "failed" : "success"); 608 if (!error) { 609 cyrix_timing(scp, devno, ATA_WDMA2); 610 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 611 return; 612 } 613 } 614 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 615 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 616 ATA_WAIT_READY); 617 if (bootverbose) 618 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 619 (error) ? "failed" : "success", 620 ata_mode2str(ata_pio2mode(apiomode))); 621 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 622 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 623 return; 624 625 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 626 if (udmamode >= 2) { 627 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 628 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 629 if (bootverbose) 630 ata_printf(scp, device, 631 "%s setting UDMA2 on ServerWorks chip\n", 632 (error) ? "failed" : "success"); 633 if (!error) { 634 u_int16_t reg56; 635 636 pci_write_config(parent, 0x54, 637 pci_read_config(parent, 0x54, 1) | 638 (0x01 << devno), 1); 639 reg56 = pci_read_config(parent, 0x56, 2); 640 reg56 &= ~(0xf << (devno * 4)); 641 reg56 |= (0x2 << (devno * 4)); 642 pci_write_config(parent, 0x56, reg56, 2); 643 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 644 return; 645 } 646 } 647 if (wdmamode >= 2 && apiomode >= 4) { 648 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 649 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 650 if (bootverbose) 651 ata_printf(scp, device, 652 "%s setting WDMA2 on ServerWorks chip\n", 653 (error) ? "failed" : "success"); 654 if (!error) { 655 int offset = (scp->channel * 2) + (device == ATA_MASTER); 656 int word44 = pci_read_config(parent, 0x44, 4); 657 658 pci_write_config(parent, 0x54, 659 pci_read_config(parent, 0x54, 1) & 660 ~(0x01 << devno), 1); 661 word44 &= ~(0xff << (offset << 8)); 662 word44 |= (0x20 << (offset << 8)); 663 pci_write_config(parent, 0x44, 0x20, 4); 664 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 665 return; 666 } 667 } 668 /* we could set PIO mode timings, but we assume the BIOS did that */ 669 break; 670 671 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 672 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 673 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 674 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 675 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 676 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 677 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 678 break; 679 680 if (udmamode >= 5 && 681 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 682 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 683 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 684 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_printf(scp, device, 687 "%s setting UDMA5 on Promise chip\n", 688 (error) ? "failed" : "success"); 689 if (!error) { 690 promise_timing(scp, devno, ATA_UDMA5); 691 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 692 return; 693 } 694 } 695 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 696 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 697 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 698 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 699 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 700 if (bootverbose) 701 ata_printf(scp, device, 702 "%s setting UDMA4 on Promise chip\n", 703 (error) ? "failed" : "success"); 704 if (!error) { 705 promise_timing(scp, devno, ATA_UDMA4); 706 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 707 return; 708 } 709 } 710 if (udmamode >= 2) { 711 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 712 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 713 if (bootverbose) 714 ata_printf(scp, device, 715 "%s setting UDMA2 on Promise chip\n", 716 (error) ? "failed" : "success"); 717 if (!error) { 718 promise_timing(scp, devno, ATA_UDMA2); 719 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 720 return; 721 } 722 } 723 if (wdmamode >= 2 && apiomode >= 4) { 724 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 725 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 726 if (bootverbose) 727 ata_printf(scp, device, 728 "%s setting WDMA2 on Promise chip\n", 729 (error) ? "failed" : "success"); 730 if (!error) { 731 promise_timing(scp, devno, ATA_WDMA2); 732 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 733 return; 734 } 735 } 736 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 737 ata_pio2mode(apiomode), 738 ATA_C_F_SETXFER, ATA_WAIT_READY); 739 if (bootverbose) 740 ata_printf(scp, device, 741 "%s setting PIO%d on Promise chip\n", 742 (error) ? "failed" : "success", 743 (apiomode >= 0) ? apiomode : 0); 744 promise_timing(scp, devno, ata_pio2mode(apiomode)); 745 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 746 return; 747 748 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 749 /* no ATAPI devices for now */ 750 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 751 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 752 break; 753 754 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 755 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 756 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 757 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 758 if (bootverbose) 759 ata_printf(scp, device, 760 "%s setting UDMA5 on HighPoint chip\n", 761 (error) ? "failed" : "success"); 762 if (!error) { 763 hpt_timing(scp, devno, ATA_UDMA5); 764 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 765 return; 766 } 767 } 768 if (udmamode >=4 && 769 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 770 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 771 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 772 if (bootverbose) 773 ata_printf(scp, device, 774 "%s setting UDMA4 on HighPoint chip\n", 775 (error) ? "failed" : "success"); 776 if (!error) { 777 hpt_timing(scp, devno, ATA_UDMA4); 778 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 779 return; 780 } 781 } 782 if (udmamode >= 2) { 783 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 784 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 785 if (bootverbose) 786 ata_printf(scp, device, 787 "%s setting UDMA2 on HighPoint chip\n", 788 (error) ? "failed" : "success"); 789 if (!error) { 790 hpt_timing(scp, devno, ATA_UDMA2); 791 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 792 return; 793 } 794 } 795 if (wdmamode >= 2 && apiomode >= 4) { 796 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 797 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 798 if (bootverbose) 799 ata_printf(scp, device, 800 "%s setting WDMA2 on HighPoint chip\n", 801 (error) ? "failed" : "success"); 802 if (!error) { 803 hpt_timing(scp, devno, ATA_WDMA2); 804 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 805 return; 806 } 807 } 808 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 809 ata_pio2mode(apiomode), 810 ATA_C_F_SETXFER, ATA_WAIT_READY); 811 if (bootverbose) 812 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 813 (error) ? "failed" : "success", 814 (apiomode >= 0) ? apiomode : 0); 815 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 816 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 817 return; 818 819 default: /* unknown controller chip */ 820 /* better not try generic DMA on ATAPI devices it almost never works */ 821 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 822 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 823 break; 824 825 /* if controller says its setup for DMA take the easy way out */ 826 /* the downside is we dont know what DMA mode we are in */ 827 if ((udmamode >= 0 || wdmamode > 1) &&
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