47
48#if NPCI > 0
49
50/* prototypes */
51static void cyrix_timing(struct ata_softc *, int, int);
52static void promise_timing(struct ata_softc *, int, int);
53static void hpt_timing(struct ata_softc *, int, int);
54
55/* misc defines */
56#ifdef __alpha__
57#undef vtophys
58#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59#endif
60
61void *
62ata_dmaalloc(struct ata_softc *scp, int device)
63{
64 void *dmatab;
65
66 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
67 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
68 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
69 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
70 free(dmatab, M_DEVBUF);
71 dmatab = NULL;
72 }
73 }
74 return dmatab;
75}
76
77void
78ata_dmainit(struct ata_softc *scp, int device,
79 int apiomode, int wdmamode, int udmamode)
80{
81 device_t parent = device_get_parent(scp->dev);
82 int devno = (scp->unit << 1) + ATA_DEV(device);
83 int error;
84
85 /* set our most pessimistic default mode */
86 scp->mode[ATA_DEV(device)] = ATA_PIO;
87
88 if (!scp->bmaddr)
89 return;
90
91 /* if simplex controller, only allow DMA on primary channel */
92 if (scp->unit == 1) {
93 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
94 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
95 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
96 ata_printf(scp, device, "simplex device, DMA on primary only\n");
97 return;
98 }
99 }
100
101 /* DMA engine address alignment is usually 1 word (2 bytes) */
102 scp->alignment = 0x1;
103
104 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
105 ata_printf(scp, device,
106 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
107 udmamode = 2;
108 }
109
110 switch (scp->chiptype) {
111
112 case 0x244b8086: /* Intel ICH2 */
113 if (udmamode >= 5) {
114 int32_t mask48, new48;
115 int16_t word54;
116
117 word54 = pci_read_config(parent, 0x54, 2);
118 if (word54 & (0x10 << devno)) {
119 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
120 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
121 if (bootverbose)
122 ata_printf(scp, device,
123 "%s setting UDMA5 on ICH2 chip\n",
124 (error) ? "failed" : "success");
125 if (!error) {
126 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
127 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
128 pci_write_config(parent, 0x48,
129 (pci_read_config(parent, 0x48, 4) &
130 ~mask48) | new48, 4);
131 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
132 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
133 return;
134 }
135 }
136 }
137 /* make sure eventual ATA100 mode from the BIOS is disabled */
138 pci_write_config(parent, 0x54,
139 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
140 /* FALLTHROUGH */
141
142 case 0x24118086: /* Intel ICH */
143 if (udmamode >= 4) {
144 int32_t mask48, new48;
145 int16_t word54;
146
147 word54 = pci_read_config(parent, 0x54, 2);
148 if (word54 & (0x10 << devno)) {
149 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
150 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
151 if (bootverbose)
152 ata_printf(scp, device,
153 "%s setting UDMA4 on ICH%s chip\n",
154 (error) ? "failed" : "success",
155 (scp->chiptype == 0x244b8086) ? "2" : "");
156 if (!error) {
157 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
158 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
159 pci_write_config(parent, 0x48,
160 (pci_read_config(parent, 0x48, 4) &
161 ~mask48) | new48, 4);
162 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
163 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
164 return;
165 }
166 }
167 }
168 /* make sure eventual ATA66 mode from the BIOS is disabled */
169 pci_write_config(parent, 0x54,
170 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
171 /* FALLTHROUGH */
172
173 case 0x71118086: /* Intel PIIX4 */
174 case 0x71998086: /* Intel PIIX4e */
175 case 0x24218086: /* Intel ICH0 */
176 if (udmamode >= 2) {
177 int32_t mask48, new48;
178
179 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
180 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
181 if (bootverbose)
182 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
183 (error) ? "failed" : "success",
184 (scp->chiptype == 0x244b8086) ? "ICH2" :
185 (scp->chiptype == 0x24118086) ? "ICH" :
186 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
187 if (!error) {
188 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
189 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
190 pci_write_config(parent, 0x48,
191 (pci_read_config(parent, 0x48, 4) &
192 ~mask48) | new48, 4);
193 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
194 return;
195 }
196 }
197 /* make sure eventual ATA33 mode from the BIOS is disabled */
198 pci_write_config(parent, 0x48,
199 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
200 /* FALLTHROUGH */
201
202 case 0x70108086: /* Intel PIIX3 */
203 if (wdmamode >= 2 && apiomode >= 4) {
204 int32_t mask40, new40, mask44, new44;
205
206 /* if SITRE not set doit for both channels */
207 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
208 new40 = pci_read_config(parent, 0x40, 4);
209 new44 = pci_read_config(parent, 0x44, 4);
210 if (!(new40 & 0x00004000)) {
211 new44 &= ~0x0000000f;
212 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
213 }
214 if (!(new40 & 0x40000000)) {
215 new44 &= ~0x000000f0;
216 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
217 }
218 new40 |= 0x40004000;
219 pci_write_config(parent, 0x40, new40, 4);
220 pci_write_config(parent, 0x44, new44, 4);
221 }
222 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
223 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
224 if (bootverbose)
225 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
226 (error) ? "failed" : "success",
227 (scp->chiptype == 0x244b8086) ? "ICH2" :
228 (scp->chiptype == 0x24118086) ? "ICH" :
229 (scp->chiptype == 0x24218086) ? "ICH0" :
230 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4");
231 if (!error) {
232 if (device == ATA_MASTER) {
233 mask40 = 0x0000330f;
234 new40 = 0x00002307;
235 mask44 = 0;
236 new44 = 0;
237 }
238 else {
239 mask40 = 0x000000f0;
240 new40 = 0x00000070;
241 mask44 = 0x0000000f;
242 new44 = 0x0000000b;
243 }
244 if (scp->unit) {
245 mask40 <<= 16;
246 new40 <<= 16;
247 mask44 <<= 4;
248 new44 <<= 4;
249 }
250 pci_write_config(parent, 0x40,
251 (pci_read_config(parent, 0x40, 4) & ~mask40)|
252 new40, 4);
253 pci_write_config(parent, 0x44,
254 (pci_read_config(parent, 0x44, 4) & ~mask44)|
255 new44, 4);
256 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
257 return;
258 }
259 }
260 /* we could set PIO mode timings, but we assume the BIOS did that */
261 break;
262
263 case 0x12308086: /* Intel PIIX */
264 if (wdmamode >= 2 && apiomode >= 4) {
265 int32_t word40;
266
267 word40 = pci_read_config(parent, 0x40, 4);
268 word40 >>= scp->unit * 16;
269
270 /* Check for timing config usable for DMA on controller */
271 if (!((word40 & 0x3300) == 0x2300 &&
272 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
273 break;
274
275 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
276 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
277 if (bootverbose)
278 ata_printf(scp, device,
279 "%s setting WDMA2 on PIIX chip\n",
280 (error) ? "failed" : "success");
281 if (!error) {
282 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
283 return;
284 }
285 }
286 break;
287
288 case 0x522910b9: /* AcerLabs Aladdin IV/V */
289 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
290 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
291 ata_printf(scp, device,
292 "Aladdin: two atapi devices on this channel, no DMA\n");
293 break;
294 }
295 if (udmamode >= 2 && pci_read_config(parent, 0x08, 1) > 0x20) {
296 int32_t word54 = pci_read_config(parent, 0x54, 4);
297
298 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
299 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
300 if (bootverbose)
301 ata_printf(scp, device,
302 "%s setting UDMA2 on Aladdin chip\n",
303 (error) ? "failed" : "success");
304 if (!error) {
305 word54 &= ~(0x000f000f << (devno << 2));
306 word54 |= (0x000a0005 << (devno << 2));
307 pci_write_config(parent, 0x54, word54, 4);
308 pci_write_config(parent, 0x53,
309 pci_read_config(parent, 0x53, 1) | 0x03, 1);
310 scp->flags |= ATA_ATAPI_DMA_RO;
311 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
312 return;
313 }
314 }
315 if (wdmamode >= 2 && apiomode >= 4) {
316 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
317 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
318 if (bootverbose)
319 ata_printf(scp, device,
320 "%s setting WDMA2 on Aladdin chip\n",
321 (error) ? "failed" : "success");
322 if (!error) {
323 pci_write_config(parent, 0x53,
324 pci_read_config(parent, 0x53, 1) | 0x03, 1);
325 scp->flags |= ATA_ATAPI_DMA_RO;
326 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
327 return;
328 }
329 }
330 pci_write_config(parent, 0x53,
331 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
332 /* we could set PIO mode timings, but we assume the BIOS did that */
333 break;
334
335 case 0x74091022: /* AMD 756 */
336 if (udmamode >= 4) {
337 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
338 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
339 if (bootverbose)
340 ata_printf(scp, device,
341 "%s setting UDMA4 on AMD chip\n",
342 (error) ? "failed" : "success");
343 if (!error) {
344 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
345 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
346 return;
347 }
348 }
349 goto via_82c586;
350
351 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
352 if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
353 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
354
355 if (udmamode >= 4) {
356 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
357 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 if (bootverbose)
359 ata_printf(scp, device,
360 "%s setting UDMA4 on VIA chip\n",
361 (error) ? "failed" : "success");
362 if (!error) {
363 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
364 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
365 return;
366 }
367 }
368 if (udmamode >= 2) {
369 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
370 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
371 if (bootverbose)
372 ata_printf(scp, device,
373 "%s setting UDMA2 on VIA chip\n",
374 (error) ? "failed" : "success");
375 if (!error) {
376 pci_write_config(parent, 0x53 - devno, 0xea, 1);
377 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
378 return;
379 }
380 }
381 }
382 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
383 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */
384via_82c586:
385 if (udmamode >= 2) {
386 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
387 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
388 if (bootverbose)
389 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
390 (error) ? "failed" : "success",
391 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
392 if (!error) {
393 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
394 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
395 return;
396 }
397 }
398 }
399 if (wdmamode >= 2 && apiomode >= 4) {
400 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
401 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
402 if (bootverbose)
403 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
404 (error) ? "failed" : "success",
405 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
406 if (!error) {
407 pci_write_config(parent, 0x53 - devno, 0x82, 1);
408 pci_write_config(parent, 0x4b - devno, 0x31, 1);
409 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
410 return;
411 }
412 }
413 /* we could set PIO mode timings, but we assume the BIOS did that */
414 break;
415
416 case 0x55131039: /* SiS 5591 */
417 if (udmamode >= 2) {
418 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
419 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
420 if (bootverbose)
421 ata_printf(scp, device,
422 "%s setting UDMA2 on SiS chip\n",
423 (error) ? "failed" : "success");
424 if (!error) {
425 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
426 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
427 return;
428 }
429 }
430 if (wdmamode >=2 && apiomode >= 4) {
431 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
432 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
433 if (bootverbose)
434 ata_printf(scp, device,
435 "%s setting WDMA2 on SiS chip\n",
436 (error) ? "failed" : "success");
437 if (!error) {
438 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
439 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
440 return;
441 }
442 }
443 /* we could set PIO mode timings, but we assume the BIOS did that */
444 break;
445
446 case 0x06461095: /* CMD 646 ATA controller */
447 if (wdmamode >= 2 && apiomode >= 4) {
448 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
449 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
450 if (bootverbose)
451 ata_printf(scp, device,
452 "%s setting WDMA2 on CMD646 chip\n",
453 error ? "failed" : "success");
454 if (!error) {
455 int32_t offset = (devno < 3) ? (devno << 1) : 7;
456
457 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
458 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
459 return;
460 }
461 }
462 /* we could set PIO mode timings, but we assume the BIOS did that */
463 break;
464
465 case 0xc6931080: /* Cypress 82c693 ATA controller */
466 if (wdmamode >= 2 && apiomode >= 4) {
467 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
468 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
469 if (bootverbose)
470 ata_printf(scp, device,
471 "%s setting WDMA2 on Cypress chip\n",
472 error ? "failed" : "success");
473 if (!error) {
474 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2);
475 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
476 return;
477 }
478 }
479 /* we could set PIO mode timings, but we assume the BIOS did that */
480 break;
481
482 case 0x01021078:
483 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
484 if (udmamode >= 2) {
485 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
486 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
487 if (bootverbose)
488 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
489 (error) ? "failed" : "success");
490 if (!error) {
491 cyrix_timing(scp, devno, ATA_UDMA2);
492 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
493 return;
494 }
495 }
496 if (wdmamode >= 2 && apiomode >= 4) {
497 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
498 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
499 if (bootverbose)
500 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
501 (error) ? "failed" : "success");
502 if (!error) {
503 cyrix_timing(scp, devno, ATA_WDMA2);
504 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
505 return;
506 }
507 }
508 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
509 ata_pio2mode(apiomode), ATA_C_F_SETXFER,
510 ATA_WAIT_READY);
511 if (bootverbose)
512 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
513 (error) ? "failed" : "success",
514 ata_mode2str(ata_pio2mode(apiomode)));
515 cyrix_timing(scp, devno, ata_pio2mode(apiomode));
516 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
517 return;
518
519 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
520 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
521 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
522 case 0x0d30105a: /* Promise OEM ATA100 controllers */
523 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
524 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
525 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
526 break;
527
528 if (udmamode >=5 &&
529 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) &&
530 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
531 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
532 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
533 if (bootverbose)
534 ata_printf(scp, device,
535 "%s setting UDMA5 on Promise chip\n",
536 (error) ? "failed" : "success");
537 if (!error) {
538 promise_timing(scp, devno, ATA_UDMA5);
539 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
540 return;
541 }
542 }
543 if (udmamode >=4 && (scp->chiptype == 0x4d38105a ||
544 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) &&
545 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
546 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
547 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
548 if (bootverbose)
549 ata_printf(scp, device,
550 "%s setting UDMA4 on Promise chip\n",
551 (error) ? "failed" : "success");
552 if (!error) {
553 promise_timing(scp, devno, ATA_UDMA4);
554 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
555 return;
556 }
557 }
558 if (udmamode >= 2) {
559 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
560 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
561 if (bootverbose)
562 ata_printf(scp, device,
563 "%s setting UDMA2 on Promise chip\n",
564 (error) ? "failed" : "success");
565 if (!error) {
566 promise_timing(scp, devno, ATA_UDMA2);
567 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
568 return;
569 }
570 }
571 if (wdmamode >= 2 && apiomode >= 4) {
572 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
573 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
574 if (bootverbose)
575 ata_printf(scp, device,
576 "%s setting WDMA2 on Promise chip\n",
577 (error) ? "failed" : "success");
578 if (!error) {
579 promise_timing(scp, devno, ATA_WDMA2);
580 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
581 return;
582 }
583 }
584 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
585 ata_pio2mode(apiomode),
586 ATA_C_F_SETXFER, ATA_WAIT_READY);
587 if (bootverbose)
588 ata_printf(scp, device,
589 "%s setting PIO%d on Promise chip\n",
590 (error) ? "failed" : "success",
591 (apiomode >= 0) ? apiomode : 0);
592 promise_timing(scp, devno, ata_pio2mode(apiomode));
593 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
594 return;
595
596 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
597 /* no ATAPI devices for now */
598 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
599 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
600 break;
601
602 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
603 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
604 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
605 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
606 if (bootverbose)
607 ata_printf(scp, device,
608 "%s setting UDMA5 on HPT370 chip\n",
609 (error) ? "failed" : "success");
610 if (!error) {
611 hpt_timing(scp, devno, ATA_UDMA5);
612 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
613 return;
614 }
615 }
616
617 if (udmamode >=4 &&
618 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
619 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
620 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
621 if (bootverbose)
622 ata_printf(scp, device,
623 "%s setting UDMA4 on HPT366 chip\n",
624 (error) ? "failed" : "success");
625 if (!error) {
626 hpt_timing(scp, devno, ATA_UDMA4);
627 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
628 return;
629 }
630 }
631 if (udmamode >= 2) {
632 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
633 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
634 if (bootverbose)
635 ata_printf(scp, device,
636 "%s setting UDMA2 on HPT366 chip\n",
637 (error) ? "failed" : "success");
638 if (!error) {
639 hpt_timing(scp, devno, ATA_UDMA2);
640 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
641 return;
642 }
643 }
644 if (wdmamode >= 2 && apiomode >= 4) {
645 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
646 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
647 if (bootverbose)
648 ata_printf(scp, device,
649 "%s setting WDMA2 on HPT366 chip\n",
650 (error) ? "failed" : "success");
651 if (!error) {
652 hpt_timing(scp, devno, ATA_WDMA2);
653 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
654 return;
655 }
656 }
657 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
658 ata_pio2mode(apiomode),
659 ATA_C_F_SETXFER, ATA_WAIT_READY);
660 if (bootverbose)
661 ata_printf(scp, device, "%s setting PIO%d on HPT366 chip\n",
662 (error) ? "failed" : "success",
663 (apiomode >= 0) ? apiomode : 0);
664 hpt_timing(scp, devno, ata_pio2mode(apiomode));
665 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
666 return;
667
668 default: /* unknown controller chip */
669 /* better not try generic DMA on ATAPI devices it almost never works */
670 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
671 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
672 break;
673
674 /* if controller says its setup for DMA take the easy way out */
675 /* the downside is we dont know what DMA mode we are in */
676 if ((udmamode >= 0 || wdmamode > 1) &&
677 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
678 ((device==ATA_MASTER) ?
679 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
680 scp->mode[ATA_DEV(device)] = ATA_DMA;
681 return;
682 }
683
684 /* well, we have no support for this, but try anyways */
685 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
686 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
687 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
688 if (bootverbose)
689 ata_printf(scp, device,
690 "%s setting WDMA2 on generic chip\n",
691 (error) ? "failed" : "success");
692 if (!error) {
693 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
694 return;
695 }
696 }
697 }
698 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
699 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
700 if (bootverbose)
701 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
702 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
703 if (!error)
704 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
705 else {
706 if (bootverbose)
707 ata_printf(scp, device, "using PIO mode set by BIOS\n");
708 scp->mode[ATA_DEV(device)] = ATA_PIO;
709 }
710}
711
712int
713ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
714 caddr_t data, int32_t count)
715{
716 u_int32_t dma_count, dma_base;
717 int i = 0;
718
719 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
720 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
721 return -1;
722 }
723
724 if (!count) {
725 ata_printf(scp, device, "zero length DMA transfer attempted\n");
726 return -1;
727 }
728
729 dma_base = vtophys(data);
730 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
731 data += dma_count;
732 count -= dma_count;
733
734 while (count) {
735 dmatab[i].base = dma_base;
736 dmatab[i].count = (dma_count & 0xffff);
737 i++;
738 if (i >= ATA_DMA_ENTRIES) {
739 ata_printf(scp, device, "too many segments in DMA table\n");
740 return -1;
741 }
742 dma_base = vtophys(data);
743 dma_count = min(count, PAGE_SIZE);
744 data += min(count, PAGE_SIZE);
745 count -= min(count, PAGE_SIZE);
746 }
747 dmatab[i].base = dma_base;
748 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
749 return 0;
750}
751
752void
753ata_dmastart(struct ata_softc *scp, int device,
754 struct ata_dmaentry *dmatab, int dir)
755{
756 scp->flags |= ATA_DMA_ACTIVE;
757 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
758 outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
759 outb(scp->bmaddr + ATA_BMSTAT_PORT,
760 (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
761 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
762 outb(scp->bmaddr + ATA_BMCMD_PORT,
763 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
764}
765
766int
767ata_dmadone(struct ata_softc *scp)
768{
769 outb(scp->bmaddr + ATA_BMCMD_PORT,
770 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
771 scp->flags &= ~ATA_DMA_ACTIVE;
772 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
773}
774
775int
776ata_dmastatus(struct ata_softc *scp)
777{
778 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
779}
780
781static void
782cyrix_timing(struct ata_softc *scp, int devno, int mode)
783{
784 u_int32_t reg20 = 0x0000e132;
785 u_int32_t reg24 = 0x00017771;
786
787 switch (mode) {
788 case ATA_PIO0: reg20 = 0x0000e132; break;
789 case ATA_PIO1: reg20 = 0x00018121; break;
790 case ATA_PIO2: reg20 = 0x00024020; break;
791 case ATA_PIO3: reg20 = 0x00032010; break;
792 case ATA_PIO4: reg20 = 0x00040010; break;
793 case ATA_WDMA2: reg24 = 0x00002020; break;
794 case ATA_UDMA2: reg24 = 0x00911030; break;
795 }
796 outl(scp->bmaddr + (devno * 8) + 0x20, reg20);
797 outl(scp->bmaddr + (devno * 8) + 0x24, reg24);
798}
799
800static void
801promise_timing(struct ata_softc *scp, int devno, int mode)
802{
803 u_int32_t timing = 0;
804 struct promise_timing {
805 u_int8_t pa:4;
806 u_int8_t prefetch:1;
807 u_int8_t iordy:1;
808 u_int8_t errdy:1;
809 u_int8_t syncin:1;
810 u_int8_t pb:5;
811 u_int8_t mb:3;
812 u_int8_t mc:4;
813 u_int8_t dmaw:1;
814 u_int8_t dmar:1;
815 u_int8_t iordyp:1;
816 u_int8_t dmarqp:1;
817 u_int8_t reserved:8;
818 } *t = (struct promise_timing*)&timing;
819
820 t->iordy = 1; t->iordyp = 1;
821 if (mode >= ATA_DMA) {
822 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
823 }
824
825 switch (scp->chiptype) {
826 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
827 switch (mode) {
828 default:
829 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
830 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
831 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
832 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
833 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
834 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
835 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
836 }
837 break;
838
839 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
840 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
841 case 0x0d30105a: /* Promise OEM ATA 100 */
842 switch (mode) {
843 default:
844 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
845 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
846 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
847 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
848 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
849 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
850 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
851 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
852 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
853 }
854 break;
855 }
856 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
857}
858
859static void
860hpt_timing(struct ata_softc *scp, int devno, int mode)
861{
862 device_t parent = device_get_parent(scp->dev);
863 u_int32_t timing;
864
865 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
866 switch (mode) {
867 case ATA_PIO0: timing = 0x06914e57; break;
868 case ATA_PIO1: timing = 0x06914e43; break;
869 case ATA_PIO2: timing = 0x06514e33; break;
870 case ATA_PIO3: timing = 0x06514e22; break;
871 case ATA_PIO4: timing = 0x06514e21; break;
872 case ATA_WDMA2: timing = 0x26514e21; break;
873 case ATA_UDMA2: timing = 0x16494e31; break;
874 case ATA_UDMA4: timing = 0x16454e31; break;
875 case ATA_UDMA5: timing = 0x16454e31; break;
876 default: timing = 0x06514e57;
877 }
878 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
879 pci_write_config(parent, 0x5b, 0x22, 1);
880 }
881 else { /* HPT36[68] */
882 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
883 case 0x85: /* 25Mhz */
884 switch (mode) {
885 case ATA_PIO0: timing = 0xc0d08585; break;
886 case ATA_PIO1: timing = 0xc0d08572; break;
887 case ATA_PIO2: timing = 0xc0ca8542; break;
888 case ATA_PIO3: timing = 0xc0ca8532; break;
889 case ATA_PIO4: timing = 0xc0ca8521; break;
890 case ATA_WDMA2: timing = 0xa0ca8521; break;
891 case ATA_UDMA2: timing = 0x90cf8521; break;
892 case ATA_UDMA4: timing = 0x90c98521; break;
893 default: timing = 0x01208585;
894 }
895 break;
896 default:
897 case 0xa7: /* 33MHz */
898 switch (mode) {
899 case ATA_PIO0: timing = 0xc0d0a7aa; break;
900 case ATA_PIO1: timing = 0xc0d0a7a3; break;
901 case ATA_PIO2: timing = 0xc0d0a753; break;
902 case ATA_PIO3: timing = 0xc0c8a742; break;
903 case ATA_PIO4: timing = 0xc0c8a731; break;
904 case ATA_WDMA2: timing = 0xa0c8a731; break;
905 case ATA_UDMA2: timing = 0x90caa731; break;
906 case ATA_UDMA4: timing = 0x90c9a731; break;
907 default: timing = 0x0120a7a7;
908 }
909 break;
910 case 0xd9: /* 40Mhz */
911 switch (mode) {
912 case ATA_PIO0: timing = 0xc018d9d9; break;
913 case ATA_PIO1: timing = 0xc010d9c7; break;
914 case ATA_PIO2: timing = 0xc010d997; break;
915 case ATA_PIO3: timing = 0xc010d974; break;
916 case ATA_PIO4: timing = 0xc008d963; break;
917 case ATA_WDMA2: timing = 0xa008d943; break;
918 case ATA_UDMA2: timing = 0x900bd943; break;
919 case ATA_UDMA4: timing = 0x900fd943; break;
920 default: timing = 0x0120d9d9;
921 }
922 }
923 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
924 }
925}
926
927#else /* NPCI > 0 */
928
929void
930ata_dmainit(struct ata_softc *scp, int device,
931 int piomode, int wdmamode, int udmamode)
932{
933}
934
935int
936ata_dmasetup(struct ata_softc *scp, int device,
937 int8_t *data, int32_t count, int flags)
938{
939 return -1;
940}
941
942void
943ata_dmastart(struct ata_softc *scp)
944{
945}
946
947int
948ata_dmadone(struct ata_softc *scp)
949{
950 return -1;
951}
952
953int
954ata_dmastatus(struct ata_softc *scp)
955{
956 return -1;
957}
958
959#endif /* NPCI > 0 */
| 46
47#if NPCI > 0
48
49/* prototypes */
50static void cyrix_timing(struct ata_softc *, int, int);
51static void promise_timing(struct ata_softc *, int, int);
52static void hpt_timing(struct ata_softc *, int, int);
53
54/* misc defines */
55#ifdef __alpha__
56#undef vtophys
57#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
58#endif
59
60void *
61ata_dmaalloc(struct ata_softc *scp, int device)
62{
63 void *dmatab;
64
65 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
66 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
67 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
68 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
69 free(dmatab, M_DEVBUF);
70 dmatab = NULL;
71 }
72 }
73 return dmatab;
74}
75
76void
77ata_dmainit(struct ata_softc *scp, int device,
78 int apiomode, int wdmamode, int udmamode)
79{
80 device_t parent = device_get_parent(scp->dev);
81 int devno = (scp->unit << 1) + ATA_DEV(device);
82 int error;
83
84 /* set our most pessimistic default mode */
85 scp->mode[ATA_DEV(device)] = ATA_PIO;
86
87 if (!scp->bmaddr)
88 return;
89
90 /* if simplex controller, only allow DMA on primary channel */
91 if (scp->unit == 1) {
92 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
93 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
94 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
95 ata_printf(scp, device, "simplex device, DMA on primary only\n");
96 return;
97 }
98 }
99
100 /* DMA engine address alignment is usually 1 word (2 bytes) */
101 scp->alignment = 0x1;
102
103 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) {
104 ata_printf(scp, device,
105 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
106 udmamode = 2;
107 }
108
109 switch (scp->chiptype) {
110
111 case 0x244b8086: /* Intel ICH2 */
112 if (udmamode >= 5) {
113 int32_t mask48, new48;
114 int16_t word54;
115
116 word54 = pci_read_config(parent, 0x54, 2);
117 if (word54 & (0x10 << devno)) {
118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
120 if (bootverbose)
121 ata_printf(scp, device,
122 "%s setting UDMA5 on ICH2 chip\n",
123 (error) ? "failed" : "success");
124 if (!error) {
125 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
126 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
127 pci_write_config(parent, 0x48,
128 (pci_read_config(parent, 0x48, 4) &
129 ~mask48) | new48, 4);
130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
131 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
132 return;
133 }
134 }
135 }
136 /* make sure eventual ATA100 mode from the BIOS is disabled */
137 pci_write_config(parent, 0x54,
138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
139 /* FALLTHROUGH */
140
141 case 0x24118086: /* Intel ICH */
142 if (udmamode >= 4) {
143 int32_t mask48, new48;
144 int16_t word54;
145
146 word54 = pci_read_config(parent, 0x54, 2);
147 if (word54 & (0x10 << devno)) {
148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
150 if (bootverbose)
151 ata_printf(scp, device,
152 "%s setting UDMA4 on ICH%s chip\n",
153 (error) ? "failed" : "success",
154 (scp->chiptype == 0x244b8086) ? "2" : "");
155 if (!error) {
156 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
157 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
158 pci_write_config(parent, 0x48,
159 (pci_read_config(parent, 0x48, 4) &
160 ~mask48) | new48, 4);
161 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
162 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
163 return;
164 }
165 }
166 }
167 /* make sure eventual ATA66 mode from the BIOS is disabled */
168 pci_write_config(parent, 0x54,
169 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
170 /* FALLTHROUGH */
171
172 case 0x71118086: /* Intel PIIX4 */
173 case 0x71998086: /* Intel PIIX4e */
174 case 0x24218086: /* Intel ICH0 */
175 if (udmamode >= 2) {
176 int32_t mask48, new48;
177
178 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
180 if (bootverbose)
181 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
182 (error) ? "failed" : "success",
183 (scp->chiptype == 0x244b8086) ? "ICH2" :
184 (scp->chiptype == 0x24118086) ? "ICH" :
185 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
186 if (!error) {
187 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
188 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
189 pci_write_config(parent, 0x48,
190 (pci_read_config(parent, 0x48, 4) &
191 ~mask48) | new48, 4);
192 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
193 return;
194 }
195 }
196 /* make sure eventual ATA33 mode from the BIOS is disabled */
197 pci_write_config(parent, 0x48,
198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
199 /* FALLTHROUGH */
200
201 case 0x70108086: /* Intel PIIX3 */
202 if (wdmamode >= 2 && apiomode >= 4) {
203 int32_t mask40, new40, mask44, new44;
204
205 /* if SITRE not set doit for both channels */
206 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
207 new40 = pci_read_config(parent, 0x40, 4);
208 new44 = pci_read_config(parent, 0x44, 4);
209 if (!(new40 & 0x00004000)) {
210 new44 &= ~0x0000000f;
211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
212 }
213 if (!(new40 & 0x40000000)) {
214 new44 &= ~0x000000f0;
215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
216 }
217 new40 |= 0x40004000;
218 pci_write_config(parent, 0x40, new40, 4);
219 pci_write_config(parent, 0x44, new44, 4);
220 }
221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
223 if (bootverbose)
224 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
225 (error) ? "failed" : "success",
226 (scp->chiptype == 0x244b8086) ? "ICH2" :
227 (scp->chiptype == 0x24118086) ? "ICH" :
228 (scp->chiptype == 0x24218086) ? "ICH0" :
229 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4");
230 if (!error) {
231 if (device == ATA_MASTER) {
232 mask40 = 0x0000330f;
233 new40 = 0x00002307;
234 mask44 = 0;
235 new44 = 0;
236 }
237 else {
238 mask40 = 0x000000f0;
239 new40 = 0x00000070;
240 mask44 = 0x0000000f;
241 new44 = 0x0000000b;
242 }
243 if (scp->unit) {
244 mask40 <<= 16;
245 new40 <<= 16;
246 mask44 <<= 4;
247 new44 <<= 4;
248 }
249 pci_write_config(parent, 0x40,
250 (pci_read_config(parent, 0x40, 4) & ~mask40)|
251 new40, 4);
252 pci_write_config(parent, 0x44,
253 (pci_read_config(parent, 0x44, 4) & ~mask44)|
254 new44, 4);
255 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
256 return;
257 }
258 }
259 /* we could set PIO mode timings, but we assume the BIOS did that */
260 break;
261
262 case 0x12308086: /* Intel PIIX */
263 if (wdmamode >= 2 && apiomode >= 4) {
264 int32_t word40;
265
266 word40 = pci_read_config(parent, 0x40, 4);
267 word40 >>= scp->unit * 16;
268
269 /* Check for timing config usable for DMA on controller */
270 if (!((word40 & 0x3300) == 0x2300 &&
271 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
272 break;
273
274 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
275 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
276 if (bootverbose)
277 ata_printf(scp, device,
278 "%s setting WDMA2 on PIIX chip\n",
279 (error) ? "failed" : "success");
280 if (!error) {
281 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
282 return;
283 }
284 }
285 break;
286
287 case 0x522910b9: /* AcerLabs Aladdin IV/V */
288 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
289 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
290 ata_printf(scp, device,
291 "Aladdin: two atapi devices on this channel, no DMA\n");
292 break;
293 }
294 if (udmamode >= 2 && pci_read_config(parent, 0x08, 1) > 0x20) {
295 int32_t word54 = pci_read_config(parent, 0x54, 4);
296
297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
298 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
299 if (bootverbose)
300 ata_printf(scp, device,
301 "%s setting UDMA2 on Aladdin chip\n",
302 (error) ? "failed" : "success");
303 if (!error) {
304 word54 &= ~(0x000f000f << (devno << 2));
305 word54 |= (0x000a0005 << (devno << 2));
306 pci_write_config(parent, 0x54, word54, 4);
307 pci_write_config(parent, 0x53,
308 pci_read_config(parent, 0x53, 1) | 0x03, 1);
309 scp->flags |= ATA_ATAPI_DMA_RO;
310 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
311 return;
312 }
313 }
314 if (wdmamode >= 2 && apiomode >= 4) {
315 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
316 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
317 if (bootverbose)
318 ata_printf(scp, device,
319 "%s setting WDMA2 on Aladdin chip\n",
320 (error) ? "failed" : "success");
321 if (!error) {
322 pci_write_config(parent, 0x53,
323 pci_read_config(parent, 0x53, 1) | 0x03, 1);
324 scp->flags |= ATA_ATAPI_DMA_RO;
325 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
326 return;
327 }
328 }
329 pci_write_config(parent, 0x53,
330 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
331 /* we could set PIO mode timings, but we assume the BIOS did that */
332 break;
333
334 case 0x74091022: /* AMD 756 */
335 if (udmamode >= 4) {
336 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
337 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
338 if (bootverbose)
339 ata_printf(scp, device,
340 "%s setting UDMA4 on AMD chip\n",
341 (error) ? "failed" : "success");
342 if (!error) {
343 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
344 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
345 return;
346 }
347 }
348 goto via_82c586;
349
350 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */
351 if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */
352 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
353
354 if (udmamode >= 4) {
355 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
356 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
357 if (bootverbose)
358 ata_printf(scp, device,
359 "%s setting UDMA4 on VIA chip\n",
360 (error) ? "failed" : "success");
361 if (!error) {
362 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
363 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
364 return;
365 }
366 }
367 if (udmamode >= 2) {
368 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
369 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
370 if (bootverbose)
371 ata_printf(scp, device,
372 "%s setting UDMA2 on VIA chip\n",
373 (error) ? "failed" : "success");
374 if (!error) {
375 pci_write_config(parent, 0x53 - devno, 0xea, 1);
376 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
377 return;
378 }
379 }
380 }
381 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
382 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */
383via_82c586:
384 if (udmamode >= 2) {
385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
386 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
387 if (bootverbose)
388 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n",
389 (error) ? "failed" : "success",
390 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
391 if (!error) {
392 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
393 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
394 return;
395 }
396 }
397 }
398 if (wdmamode >= 2 && apiomode >= 4) {
399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
401 if (bootverbose)
402 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
403 (error) ? "failed" : "success",
404 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
405 if (!error) {
406 pci_write_config(parent, 0x53 - devno, 0x82, 1);
407 pci_write_config(parent, 0x4b - devno, 0x31, 1);
408 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
409 return;
410 }
411 }
412 /* we could set PIO mode timings, but we assume the BIOS did that */
413 break;
414
415 case 0x55131039: /* SiS 5591 */
416 if (udmamode >= 2) {
417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
418 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
419 if (bootverbose)
420 ata_printf(scp, device,
421 "%s setting UDMA2 on SiS chip\n",
422 (error) ? "failed" : "success");
423 if (!error) {
424 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
425 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
426 return;
427 }
428 }
429 if (wdmamode >=2 && apiomode >= 4) {
430 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
431 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
432 if (bootverbose)
433 ata_printf(scp, device,
434 "%s setting WDMA2 on SiS chip\n",
435 (error) ? "failed" : "success");
436 if (!error) {
437 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
438 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
439 return;
440 }
441 }
442 /* we could set PIO mode timings, but we assume the BIOS did that */
443 break;
444
445 case 0x06461095: /* CMD 646 ATA controller */
446 if (wdmamode >= 2 && apiomode >= 4) {
447 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
448 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
449 if (bootverbose)
450 ata_printf(scp, device,
451 "%s setting WDMA2 on CMD646 chip\n",
452 error ? "failed" : "success");
453 if (!error) {
454 int32_t offset = (devno < 3) ? (devno << 1) : 7;
455
456 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
457 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
458 return;
459 }
460 }
461 /* we could set PIO mode timings, but we assume the BIOS did that */
462 break;
463
464 case 0xc6931080: /* Cypress 82c693 ATA controller */
465 if (wdmamode >= 2 && apiomode >= 4) {
466 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
467 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
468 if (bootverbose)
469 ata_printf(scp, device,
470 "%s setting WDMA2 on Cypress chip\n",
471 error ? "failed" : "success");
472 if (!error) {
473 pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2);
474 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
475 return;
476 }
477 }
478 /* we could set PIO mode timings, but we assume the BIOS did that */
479 break;
480
481 case 0x01021078:
482 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
483 if (udmamode >= 2) {
484 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
485 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
486 if (bootverbose)
487 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
488 (error) ? "failed" : "success");
489 if (!error) {
490 cyrix_timing(scp, devno, ATA_UDMA2);
491 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
492 return;
493 }
494 }
495 if (wdmamode >= 2 && apiomode >= 4) {
496 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
497 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
498 if (bootverbose)
499 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
500 (error) ? "failed" : "success");
501 if (!error) {
502 cyrix_timing(scp, devno, ATA_WDMA2);
503 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
504 return;
505 }
506 }
507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
508 ata_pio2mode(apiomode), ATA_C_F_SETXFER,
509 ATA_WAIT_READY);
510 if (bootverbose)
511 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
512 (error) ? "failed" : "success",
513 ata_mode2str(ata_pio2mode(apiomode)));
514 cyrix_timing(scp, devno, ata_pio2mode(apiomode));
515 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
516 return;
517
518 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
519 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
520 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
521 case 0x0d30105a: /* Promise OEM ATA100 controllers */
522 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
523 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
524 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
525 break;
526
527 if (udmamode >=5 &&
528 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) &&
529 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
530 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
531 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
532 if (bootverbose)
533 ata_printf(scp, device,
534 "%s setting UDMA5 on Promise chip\n",
535 (error) ? "failed" : "success");
536 if (!error) {
537 promise_timing(scp, devno, ATA_UDMA5);
538 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
539 return;
540 }
541 }
542 if (udmamode >=4 && (scp->chiptype == 0x4d38105a ||
543 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) &&
544 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
545 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
546 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
547 if (bootverbose)
548 ata_printf(scp, device,
549 "%s setting UDMA4 on Promise chip\n",
550 (error) ? "failed" : "success");
551 if (!error) {
552 promise_timing(scp, devno, ATA_UDMA4);
553 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
554 return;
555 }
556 }
557 if (udmamode >= 2) {
558 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
559 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
560 if (bootverbose)
561 ata_printf(scp, device,
562 "%s setting UDMA2 on Promise chip\n",
563 (error) ? "failed" : "success");
564 if (!error) {
565 promise_timing(scp, devno, ATA_UDMA2);
566 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
567 return;
568 }
569 }
570 if (wdmamode >= 2 && apiomode >= 4) {
571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
572 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
573 if (bootverbose)
574 ata_printf(scp, device,
575 "%s setting WDMA2 on Promise chip\n",
576 (error) ? "failed" : "success");
577 if (!error) {
578 promise_timing(scp, devno, ATA_WDMA2);
579 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
580 return;
581 }
582 }
583 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
584 ata_pio2mode(apiomode),
585 ATA_C_F_SETXFER, ATA_WAIT_READY);
586 if (bootverbose)
587 ata_printf(scp, device,
588 "%s setting PIO%d on Promise chip\n",
589 (error) ? "failed" : "success",
590 (apiomode >= 0) ? apiomode : 0);
591 promise_timing(scp, devno, ata_pio2mode(apiomode));
592 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
593 return;
594
595 case 0x00041103: /* HighPoint HPT366/368/370 controllers */
596 /* no ATAPI devices for now */
597 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
598 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
599 break;
600
601 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 &&
602 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
603 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
604 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
605 if (bootverbose)
606 ata_printf(scp, device,
607 "%s setting UDMA5 on HPT370 chip\n",
608 (error) ? "failed" : "success");
609 if (!error) {
610 hpt_timing(scp, devno, ATA_UDMA5);
611 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
612 return;
613 }
614 }
615
616 if (udmamode >=4 &&
617 !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) {
618 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
619 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
620 if (bootverbose)
621 ata_printf(scp, device,
622 "%s setting UDMA4 on HPT366 chip\n",
623 (error) ? "failed" : "success");
624 if (!error) {
625 hpt_timing(scp, devno, ATA_UDMA4);
626 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
627 return;
628 }
629 }
630 if (udmamode >= 2) {
631 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
632 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
633 if (bootverbose)
634 ata_printf(scp, device,
635 "%s setting UDMA2 on HPT366 chip\n",
636 (error) ? "failed" : "success");
637 if (!error) {
638 hpt_timing(scp, devno, ATA_UDMA2);
639 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
640 return;
641 }
642 }
643 if (wdmamode >= 2 && apiomode >= 4) {
644 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
645 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
646 if (bootverbose)
647 ata_printf(scp, device,
648 "%s setting WDMA2 on HPT366 chip\n",
649 (error) ? "failed" : "success");
650 if (!error) {
651 hpt_timing(scp, devno, ATA_WDMA2);
652 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
653 return;
654 }
655 }
656 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
657 ata_pio2mode(apiomode),
658 ATA_C_F_SETXFER, ATA_WAIT_READY);
659 if (bootverbose)
660 ata_printf(scp, device, "%s setting PIO%d on HPT366 chip\n",
661 (error) ? "failed" : "success",
662 (apiomode >= 0) ? apiomode : 0);
663 hpt_timing(scp, devno, ata_pio2mode(apiomode));
664 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
665 return;
666
667 default: /* unknown controller chip */
668 /* better not try generic DMA on ATAPI devices it almost never works */
669 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
670 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
671 break;
672
673 /* if controller says its setup for DMA take the easy way out */
674 /* the downside is we dont know what DMA mode we are in */
675 if ((udmamode >= 0 || wdmamode > 1) &&
676 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
677 ((device==ATA_MASTER) ?
678 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
679 scp->mode[ATA_DEV(device)] = ATA_DMA;
680 return;
681 }
682
683 /* well, we have no support for this, but try anyways */
684 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
685 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
686 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
687 if (bootverbose)
688 ata_printf(scp, device,
689 "%s setting WDMA2 on generic chip\n",
690 (error) ? "failed" : "success");
691 if (!error) {
692 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
693 return;
694 }
695 }
696 }
697 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
698 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
699 if (bootverbose)
700 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
701 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
702 if (!error)
703 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
704 else {
705 if (bootverbose)
706 ata_printf(scp, device, "using PIO mode set by BIOS\n");
707 scp->mode[ATA_DEV(device)] = ATA_PIO;
708 }
709}
710
711int
712ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
713 caddr_t data, int32_t count)
714{
715 u_int32_t dma_count, dma_base;
716 int i = 0;
717
718 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
719 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
720 return -1;
721 }
722
723 if (!count) {
724 ata_printf(scp, device, "zero length DMA transfer attempted\n");
725 return -1;
726 }
727
728 dma_base = vtophys(data);
729 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
730 data += dma_count;
731 count -= dma_count;
732
733 while (count) {
734 dmatab[i].base = dma_base;
735 dmatab[i].count = (dma_count & 0xffff);
736 i++;
737 if (i >= ATA_DMA_ENTRIES) {
738 ata_printf(scp, device, "too many segments in DMA table\n");
739 return -1;
740 }
741 dma_base = vtophys(data);
742 dma_count = min(count, PAGE_SIZE);
743 data += min(count, PAGE_SIZE);
744 count -= min(count, PAGE_SIZE);
745 }
746 dmatab[i].base = dma_base;
747 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
748 return 0;
749}
750
751void
752ata_dmastart(struct ata_softc *scp, int device,
753 struct ata_dmaentry *dmatab, int dir)
754{
755 scp->flags |= ATA_DMA_ACTIVE;
756 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
757 outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
758 outb(scp->bmaddr + ATA_BMSTAT_PORT,
759 (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
760 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
761 outb(scp->bmaddr + ATA_BMCMD_PORT,
762 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
763}
764
765int
766ata_dmadone(struct ata_softc *scp)
767{
768 outb(scp->bmaddr + ATA_BMCMD_PORT,
769 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
770 scp->flags &= ~ATA_DMA_ACTIVE;
771 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
772}
773
774int
775ata_dmastatus(struct ata_softc *scp)
776{
777 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
778}
779
780static void
781cyrix_timing(struct ata_softc *scp, int devno, int mode)
782{
783 u_int32_t reg20 = 0x0000e132;
784 u_int32_t reg24 = 0x00017771;
785
786 switch (mode) {
787 case ATA_PIO0: reg20 = 0x0000e132; break;
788 case ATA_PIO1: reg20 = 0x00018121; break;
789 case ATA_PIO2: reg20 = 0x00024020; break;
790 case ATA_PIO3: reg20 = 0x00032010; break;
791 case ATA_PIO4: reg20 = 0x00040010; break;
792 case ATA_WDMA2: reg24 = 0x00002020; break;
793 case ATA_UDMA2: reg24 = 0x00911030; break;
794 }
795 outl(scp->bmaddr + (devno * 8) + 0x20, reg20);
796 outl(scp->bmaddr + (devno * 8) + 0x24, reg24);
797}
798
799static void
800promise_timing(struct ata_softc *scp, int devno, int mode)
801{
802 u_int32_t timing = 0;
803 struct promise_timing {
804 u_int8_t pa:4;
805 u_int8_t prefetch:1;
806 u_int8_t iordy:1;
807 u_int8_t errdy:1;
808 u_int8_t syncin:1;
809 u_int8_t pb:5;
810 u_int8_t mb:3;
811 u_int8_t mc:4;
812 u_int8_t dmaw:1;
813 u_int8_t dmar:1;
814 u_int8_t iordyp:1;
815 u_int8_t dmarqp:1;
816 u_int8_t reserved:8;
817 } *t = (struct promise_timing*)&timing;
818
819 t->iordy = 1; t->iordyp = 1;
820 if (mode >= ATA_DMA) {
821 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
822 }
823
824 switch (scp->chiptype) {
825 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
826 switch (mode) {
827 default:
828 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
829 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
830 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
831 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
832 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
833 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
834 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
835 }
836 break;
837
838 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
839 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
840 case 0x0d30105a: /* Promise OEM ATA 100 */
841 switch (mode) {
842 default:
843 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
844 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
845 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
846 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
847 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
848 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
849 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
850 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
851 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
852 }
853 break;
854 }
855 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
856}
857
858static void
859hpt_timing(struct ata_softc *scp, int devno, int mode)
860{
861 device_t parent = device_get_parent(scp->dev);
862 u_int32_t timing;
863
864 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
865 switch (mode) {
866 case ATA_PIO0: timing = 0x06914e57; break;
867 case ATA_PIO1: timing = 0x06914e43; break;
868 case ATA_PIO2: timing = 0x06514e33; break;
869 case ATA_PIO3: timing = 0x06514e22; break;
870 case ATA_PIO4: timing = 0x06514e21; break;
871 case ATA_WDMA2: timing = 0x26514e21; break;
872 case ATA_UDMA2: timing = 0x16494e31; break;
873 case ATA_UDMA4: timing = 0x16454e31; break;
874 case ATA_UDMA5: timing = 0x16454e31; break;
875 default: timing = 0x06514e57;
876 }
877 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
878 pci_write_config(parent, 0x5b, 0x22, 1);
879 }
880 else { /* HPT36[68] */
881 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
882 case 0x85: /* 25Mhz */
883 switch (mode) {
884 case ATA_PIO0: timing = 0xc0d08585; break;
885 case ATA_PIO1: timing = 0xc0d08572; break;
886 case ATA_PIO2: timing = 0xc0ca8542; break;
887 case ATA_PIO3: timing = 0xc0ca8532; break;
888 case ATA_PIO4: timing = 0xc0ca8521; break;
889 case ATA_WDMA2: timing = 0xa0ca8521; break;
890 case ATA_UDMA2: timing = 0x90cf8521; break;
891 case ATA_UDMA4: timing = 0x90c98521; break;
892 default: timing = 0x01208585;
893 }
894 break;
895 default:
896 case 0xa7: /* 33MHz */
897 switch (mode) {
898 case ATA_PIO0: timing = 0xc0d0a7aa; break;
899 case ATA_PIO1: timing = 0xc0d0a7a3; break;
900 case ATA_PIO2: timing = 0xc0d0a753; break;
901 case ATA_PIO3: timing = 0xc0c8a742; break;
902 case ATA_PIO4: timing = 0xc0c8a731; break;
903 case ATA_WDMA2: timing = 0xa0c8a731; break;
904 case ATA_UDMA2: timing = 0x90caa731; break;
905 case ATA_UDMA4: timing = 0x90c9a731; break;
906 default: timing = 0x0120a7a7;
907 }
908 break;
909 case 0xd9: /* 40Mhz */
910 switch (mode) {
911 case ATA_PIO0: timing = 0xc018d9d9; break;
912 case ATA_PIO1: timing = 0xc010d9c7; break;
913 case ATA_PIO2: timing = 0xc010d997; break;
914 case ATA_PIO3: timing = 0xc010d974; break;
915 case ATA_PIO4: timing = 0xc008d963; break;
916 case ATA_WDMA2: timing = 0xa008d943; break;
917 case ATA_UDMA2: timing = 0x900bd943; break;
918 case ATA_UDMA4: timing = 0x900fd943; break;
919 default: timing = 0x0120d9d9;
920 }
921 }
922 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4);
923 }
924}
925
926#else /* NPCI > 0 */
927
928void
929ata_dmainit(struct ata_softc *scp, int device,
930 int piomode, int wdmamode, int udmamode)
931{
932}
933
934int
935ata_dmasetup(struct ata_softc *scp, int device,
936 int8_t *data, int32_t count, int flags)
937{
938 return -1;
939}
940
941void
942ata_dmastart(struct ata_softc *scp)
943{
944}
945
946int
947ata_dmadone(struct ata_softc *scp)
948{
949 return -1;
950}
951
952int
953ata_dmastatus(struct ata_softc *scp)
954{
955 return -1;
956}
957
958#endif /* NPCI > 0 */
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