102 case 0x24218086: /* Intel ICH0 */
103 if (udmamode >= 2) {
104 int32_t mask48, new48;
105
106 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
107 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
108 if (bootverbose)
109 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
110 (error) ? "failed" : "success",
111 (scp->chiptype == 0x24118086) ? "ICH" :
112 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
113 if (!error) {
114 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
115 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
116 pci_write_config(parent, 0x48,
117 (pci_read_config(parent, 0x48, 4) &
118 ~mask48) | new48, 4);
119 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
120 return;
121 }
122 }
123 /* FALLTHROUGH */
124
125 case 0x70108086: /* Intel PIIX3 */
126 if (wdmamode >= 2 && apiomode >= 4) {
127 int32_t mask40, new40, mask44, new44;
128
129 /* if SITRE not set doit for both channels */
130 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
131 new40 = pci_read_config(parent, 0x40, 4);
132 new44 = pci_read_config(parent, 0x44, 4);
133 if (!(new40 & 0x00004000)) {
134 new44 &= ~0x0000000f;
135 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
136 }
137 if (!(new40 & 0x40000000)) {
138 new44 &= ~0x000000f0;
139 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
140 }
141 new40 |= 0x40004000;
142 pci_write_config(parent, 0x40, new40, 4);
143 pci_write_config(parent, 0x44, new44, 4);
144 }
145 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
146 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
147 if (bootverbose)
148 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
149 (error) ? "failed" : "success",
150 (scp->chiptype == 0x70108086) ? "PIIX3" :
151 (scp->chiptype == 0x24118086) ? "ICH" :
152 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
153 if (!error) {
154 if (device == ATA_MASTER) {
155 mask40 = 0x0000330f;
156 new40 = 0x00002307;
157 mask44 = 0;
158 new44 = 0;
159 }
160 else {
161 mask40 = 0x000000f0;
162 new40 = 0x00000070;
163 mask44 = 0x0000000f;
164 new44 = 0x0000000b;
165 }
166 if (scp->unit) {
167 mask40 <<= 16;
168 new40 <<= 16;
169 mask44 <<= 4;
170 new44 <<= 4;
171 }
172 pci_write_config(parent, 0x40,
173 (pci_read_config(parent, 0x40, 4) & ~mask40)|
174 new40, 4);
175 pci_write_config(parent, 0x44,
176 (pci_read_config(parent, 0x44, 4) & ~mask44)|
177 new44, 4);
178 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
179 return;
180 }
181 }
182 /* we could set PIO mode timings, but we assume the BIOS did that */
183 break;
184
185 case 0x12308086: /* Intel PIIX */
186 if (wdmamode >= 2 && apiomode >= 4) {
187 int32_t word40;
188
189 word40 = pci_read_config(parent, 0x40, 4);
190 word40 >>= scp->unit * 16;
191
192 /* Check for timing config usable for DMA on controller */
193 if (!((word40 & 0x3300) == 0x2300 &&
194 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
195 break;
196
197 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
198 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
199 if (bootverbose)
200 ata_printf(scp, device,
201 "%s setting up WDMA2 mode on PIIX chip\n",
202 (error) ? "failed" : "success");
203 if (!error) {
204 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
205 return;
206 }
207 }
208 break;
209
210 case 0x522910b9: /* AcerLabs Aladdin IV/V */
211 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
212 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
213 ata_printf(scp, device,
214 "Aladdin: two atapi devices on this channel, no DMA\n");
215 break;
216 }
217 if (udmamode >= 2) {
218 int32_t word54 = pci_read_config(parent, 0x54, 4);
219
220 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
221 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
222 if (bootverbose)
223 ata_printf(scp, device,
224 "%s setting up UDMA2 mode on Aladdin chip\n",
225 (error) ? "failed" : "success");
226 if (!error) {
227 word54 |= 0x5555;
228 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
229 pci_write_config(parent, 0x54, word54, 4);
230 pci_write_config(parent, 0x53,
231 pci_read_config(parent, 0x53, 1) | 0x03, 1);
232 scp->flags |= ATA_ATAPI_DMA_RO;
233 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
234 return;
235 }
236 }
237 if (wdmamode >= 2 && apiomode >= 4) {
238 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
239 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
240 if (bootverbose)
241 ata_printf(scp, device,
242 "%s setting up WDMA2 mode on Aladdin chip\n",
243 (error) ? "failed" : "success");
244 if (!error) {
245 pci_write_config(parent, 0x53,
246 pci_read_config(parent, 0x53, 1) | 0x03, 1);
247 scp->flags |= ATA_ATAPI_DMA_RO;
248 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
249 return;
250 }
251 }
252 /* we could set PIO mode timings, but we assume the BIOS did that */
253 break;
254
255 case 0x06861106: /* VIA 82C686 */
256 if (udmamode >= 4) {
257 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
259 if (bootverbose)
260 ata_printf(scp, device,
261 "%s setting up UDMA4 mode on VIA chip\n",
262 (error) ? "failed" : "success");
263 if (!error) {
264 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
265 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
266 return;
267 }
268 }
269 if (udmamode >= 2) {
270 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
271 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
272 if (bootverbose)
273 ata_printf(scp, device,
274 "%s setting up UDMA2 mode on VIA chip\n",
275 (error) ? "failed" : "success");
276 if (!error) {
277 pci_write_config(parent, 0x53 - devno, 0xea, 1);
278 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
279 return;
280 }
281 }
282 goto via_generic;
283
284 case 0x74091022: /* AMD 756 */
285 if (udmamode >= 4) {
286 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
287 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
288 if (bootverbose)
289 ata_printf(scp, device,
290 "%s setting up UDMA4 mode on AMD chip\n",
291 (error) ? "failed" : "success");
292 if (!error) {
293 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
294 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
295 return;
296 }
297 }
298 /* FALLTHROUGH */
299
300 case 0x05961106: /* VIA 82C596 */
301 case 0x05861106: /* VIA 82C586 */
302
303 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
304 if ((udmamode >= 2 && scp->chiptype == 0x05861106 &&
305 pci_read_config(scp->dev, 0x08, 1) >= 0x01) ||
306 (udmamode >= 2 && scp->chiptype == 0x05961106) ||
307 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
308 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
309 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
310 if (bootverbose)
311 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
312 (error) ? "failed" : "success",
313 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
314 if (!error) {
315 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
316 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
317 return;
318 }
319 }
320 /* FALLTHROUGH */
321
322 case 0x05711106: /* VIA 82C571 */
323via_generic:
324 if (wdmamode >= 2 && apiomode >= 4) {
325 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
326 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
327 if (bootverbose)
328 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
329 (error) ? "failed" : "success",
330 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
331 if (!error) {
332 pci_write_config(parent, 0x53 - devno, 0x82, 1);
333 pci_write_config(parent, 0x4b - devno, 0x31, 1);
334 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
335 return;
336 }
337 }
338 /* we could set PIO mode timings, but we assume the BIOS did that */
339 break;
340
341 case 0x55131039: /* SiS 5591 */
342 if (udmamode >= 2) {
343 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
344 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
345 if (bootverbose)
346 ata_printf(scp, device,
347 "%s setting up UDMA2 mode on SiS chip\n",
348 (error) ? "failed" : "success");
349 if (!error) {
350 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
351 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
352 return;
353 }
354 }
355 if (wdmamode >=2 && apiomode >= 4) {
356 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 if (bootverbose)
359 ata_printf(scp, device,
360 "%s setting up WDMA2 mode on SiS chip\n",
361 (error) ? "failed" : "success");
362 if (!error) {
363 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
364 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
365 return;
366 }
367 }
368 /* we could set PIO mode timings, but we assume the BIOS did that */
369 break;
370
371 case 0x06461095: /* CMD 646 ATA controller */
372 if (wdmamode >= 2 && apiomode >= 4) {
373 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
374 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
375 if (bootverbose)
376 ata_printf(scp, device,
377 "%s setting up WDMA2 mode on CMD646 chip\n",
378 error ? "failed" : "success");
379 if (!error) {
380 int32_t offset = (devno < 3) ? (devno << 1) : 7;
381
382 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
383 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
384 return;
385 }
386 }
387 /* we could set PIO mode timings, but we assume the BIOS did that */
388 break;
389
390 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
391 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
392 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
393 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
394 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
395 break;
396
397 if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
398 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
400 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
401 if (bootverbose)
402 ata_printf(scp, device,
403 "%s setting up UDMA4 mode on Promise chip\n",
404 (error) ? "failed" : "success");
405 if (!error) {
406 promise_timing(scp, devno, ATA_UDMA4);
407 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
408 return;
409 }
410 }
411 if (udmamode >= 2) {
412 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
413 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
414 if (bootverbose)
415 ata_printf(scp, device,
416 "%s setting up UDMA2 mode on Promise chip\n",
417 (error) ? "failed" : "success");
418 if (!error) {
419 promise_timing(scp, devno, ATA_UDMA2);
420 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
421 return;
422 }
423 }
424 if (wdmamode >= 2 && apiomode >= 4) {
425 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
426 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
427 if (bootverbose)
428 ata_printf(scp, device,
429 "%s setting up WDMA2 mode on Promise chip\n",
430 (error) ? "failed" : "success");
431 if (!error) {
432 promise_timing(scp, devno, ATA_WDMA2);
433 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
434 return;
435 }
436 }
437 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
438 ata_pio2mode(apiomode),
439 ATA_C_F_SETXFER, ATA_WAIT_READY);
440 if (bootverbose)
441 ata_printf(scp, device,
442 "%s setting up PIO%d mode on Promise chip\n",
443 (error) ? "failed" : "success",
444 (apiomode >= 0) ? apiomode : 0);
445 promise_timing(scp, devno, ata_pio2mode(apiomode));
446 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
447 return;
448
449 case 0x00041103: /* HighPoint HPT366 controller */
450 /* no ATAPI devices for now */
451 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
452 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
453 break;
454
455 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) {
456 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
457 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
458 if (bootverbose)
459 ata_printf(scp, device,
460 "%s setting up UDMA4 mode on HPT366 chip\n",
461 (error) ? "failed" : "success");
462 if (!error) {
463 hpt366_timing(scp, devno, ATA_UDMA4);
464 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
465 return;
466 }
467 }
468 if (udmamode >= 2) {
469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
470 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
471 if (bootverbose)
472 ata_printf(scp, device,
473 "%s setting up UDMA2 mode on HPT366 chip\n",
474 (error) ? "failed" : "success");
475 if (!error) {
476 hpt366_timing(scp, devno, ATA_UDMA2);
477 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
478 return;
479 }
480 }
481 if (wdmamode >= 2 && apiomode >= 4) {
482 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
483 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
484 if (bootverbose)
485 ata_printf(scp, device,
486 "%s setting up WDMA2 mode on HPT366 chip\n",
487 (error) ? "failed" : "success");
488 if (!error) {
489 hpt366_timing(scp, devno, ATA_WDMA2);
490 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
491 return;
492 }
493 }
494 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
495 ata_pio2mode(apiomode),
496 ATA_C_F_SETXFER, ATA_WAIT_READY);
497 if (bootverbose)
498 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
499 (error) ? "failed" : "success",
500 (apiomode >= 0) ? apiomode : 0);
501 hpt366_timing(scp, devno, ata_pio2mode(apiomode));
502 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
503 return;
504
505 default: /* unknown controller chip */
506 /* better not try generic DMA on ATAPI devices it almost never works */
507 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
508 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
509 break;
510
511 /* if controller says its setup for DMA take the easy way out */
512 /* the downside is we dont know what DMA mode we are in */
513 if ((udmamode >= 0 || wdmamode > 1) &&
514 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
515 ((device==ATA_MASTER) ?
516 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
517 scp->mode[ATA_DEV(device)] = ATA_DMA;
518 return;
519 }
520
521 /* well, we have no support for this, but try anyways */
522 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
523 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
524 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
525 if (bootverbose)
526 ata_printf(scp, device,
527 "%s setting up WDMA2 mode on generic chip\n",
528 (error) ? "failed" : "success");
529 if (!error) {
530 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
531 return;
532 }
533 }
534 }
535 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
536 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
537 if (bootverbose)
538 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
539 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
540 if (!error)
541 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
542 else
543 if (bootverbose)
544 ata_printf(scp, device, "using PIO mode set by BIOS\n");
545}
546
547int32_t
548ata_dmasetup(struct ata_softc *scp, int32_t device,
549 int8_t *data, int32_t count, int32_t flags)
550{
551 struct ata_dmaentry *dmatab;
552 u_int32_t dma_count, dma_base;
553 int32_t i = 0;
554
555 if (((uintptr_t)data & 1) || (count & 1))
556 return -1;
557
558 if (!count) {
559 ata_printf(scp, device, "zero length DMA transfer attempted\n");
560 return -1;
561 }
562
563 dmatab = scp->dmatab[ATA_DEV(device)];
564 dma_base = vtophys(data);
565 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
566 data += dma_count;
567 count -= dma_count;
568
569 while (count) {
570 dmatab[i].base = dma_base;
571 dmatab[i].count = (dma_count & 0xffff);
572 i++;
573 if (i >= ATA_DMA_ENTRIES) {
574 ata_printf(scp, device, "too many segments in DMA table\n");
575 return -1;
576 }
577 dma_base = vtophys(data);
578 dma_count = min(count, PAGE_SIZE);
579 data += min(count, PAGE_SIZE);
580 count -= min(count, PAGE_SIZE);
581 }
582 dmatab[i].base = dma_base;
583 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
584 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
585 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
586 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
587 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
588 return 0;
589}
590
591void
592ata_dmastart(struct ata_softc *scp)
593{
594 scp->flags |= ATA_DMA_ACTIVE;
595 outb(scp->bmaddr + ATA_BMCMD_PORT,
596 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
597}
598
599int32_t
600ata_dmadone(struct ata_softc *scp)
601{
602 outb(scp->bmaddr + ATA_BMCMD_PORT,
603 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
604 scp->flags &= ~ATA_DMA_ACTIVE;
605 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
606}
607
608int32_t
609ata_dmastatus(struct ata_softc *scp)
610{
611 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
612}
613
614static void
615promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
616{
617 u_int32_t timing = 0;
618 struct promise_timing {
619 u_int8_t pa:4;
620 u_int8_t prefetch:1;
621 u_int8_t iordy:1;
622 u_int8_t errdy:1;
623 u_int8_t syncin:1;
624 u_int8_t pb:5;
625 u_int8_t mb:3;
626 u_int8_t mc:4;
627 u_int8_t dmaw:1;
628 u_int8_t dmar:1;
629 u_int8_t iordyp:1;
630 u_int8_t dmarqp:1;
631 u_int8_t reserved:8;
632 } *t = (struct promise_timing*)&timing;
633
634 t->iordy = 1; t->iordyp = 1;
635 if (mode >= ATA_DMA) {
636 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
637 }
638
639 switch (scp->chiptype) {
640 case 0x4d33105a: /* Promise 33's */
641 switch (mode) {
642 default:
643 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
644 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
645 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
646 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
647 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
648 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
649 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
650 }
651 break;
652
653 case 0x4d38105a: /* Promise 66's */
654 switch (mode) {
655 default:
656 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
657 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
658 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
659 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
660 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
661 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
662 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
663 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
664 }
665 break;
666 }
667 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
668}
669
670static void
671hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
672{
673 device_t parent = device_get_parent(scp->dev);
674 u_int32_t timing;
675
676 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
677 case 0x85: /* 25Mhz */
678 switch (mode) {
679 case ATA_PIO0: timing = 0xc0d08585; break;
680 case ATA_PIO1: timing = 0xc0d08572; break;
681 case ATA_PIO2: timing = 0xc0ca8542; break;
682 case ATA_PIO3: timing = 0xc0ca8532; break;
683 case ATA_PIO4: timing = 0xc0ca8521; break;
684 case ATA_WDMA2: timing = 0xa0ca8521; break;
685 case ATA_UDMA2: timing = 0x90cf8521; break;
686 case ATA_UDMA4: timing = 0x90c98521; break;
687 default: timing = 0x01208585;
688 }
689 break;
690 default:
691 case 0xa7: /* 33MHz */
692 switch (mode) {
693 case ATA_PIO0: timing = 0xc0d0a7aa; break;
694 case ATA_PIO1: timing = 0xc0d0a7a3; break;
695 case ATA_PIO2: timing = 0xc0d0a753; break;
696 case ATA_PIO3: timing = 0xc0c8a742; break;
697 case ATA_PIO4: timing = 0xc0c8a731; break;
698 case ATA_WDMA2: timing = 0xa0c8a731; break;
699 case ATA_UDMA2: timing = 0x90caa731; break;
700 case ATA_UDMA4: timing = 0x90c9a731; break;
701 default: timing = 0x0120a7a7;
702 }
703 break;
704 case 0xd9: /* 40Mhz */
705 switch (mode) {
706 case ATA_PIO0: timing = 0xc018d9d9; break;
707 case ATA_PIO1: timing = 0xc010d9c7; break;
708 case ATA_PIO2: timing = 0xc010d997; break;
709 case ATA_PIO3: timing = 0xc010d974; break;
710 case ATA_PIO4: timing = 0xc008d963; break;
711 case ATA_WDMA2: timing = 0xa008d943; break;
712 case ATA_UDMA2: timing = 0x900bd943; break;
713 case ATA_UDMA4: timing = 0x900fd943; break;
714 default: timing = 0x0120d9d9;
715 }
716 }
717 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4);
718}
719
720#else /* NPCI > 0 */
721
722void
723ata_dmainit(struct ata_softc *scp, int32_t device,
724 int32_t piomode, int32_t wdmamode, int32_t udmamode)
725{
726}
727
728int32_t
729ata_dmasetup(struct ata_softc *scp, int32_t device,
730 int8_t *data, int32_t count, int32_t flags)
731{
732 return -1;
733}
734
735void
736ata_dmastart(struct ata_softc *scp)
737{
738}
739
740int32_t
741ata_dmadone(struct ata_softc *scp)
742{
743 return -1;
744}
745
746int32_t
747ata_dmastatus(struct ata_softc *scp)
748{
749 return -1;
750}
751
752#endif /* NPCI > 0 */
| 128 case 0x24218086: /* Intel ICH0 */
129 if (udmamode >= 2) {
130 int32_t mask48, new48;
131
132 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
133 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
134 if (bootverbose)
135 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
136 (error) ? "failed" : "success",
137 (scp->chiptype == 0x24118086) ? "ICH" :
138 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
139 if (!error) {
140 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
141 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
142 pci_write_config(parent, 0x48,
143 (pci_read_config(parent, 0x48, 4) &
144 ~mask48) | new48, 4);
145 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
146 return;
147 }
148 }
149 /* FALLTHROUGH */
150
151 case 0x70108086: /* Intel PIIX3 */
152 if (wdmamode >= 2 && apiomode >= 4) {
153 int32_t mask40, new40, mask44, new44;
154
155 /* if SITRE not set doit for both channels */
156 if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){
157 new40 = pci_read_config(parent, 0x40, 4);
158 new44 = pci_read_config(parent, 0x44, 4);
159 if (!(new40 & 0x00004000)) {
160 new44 &= ~0x0000000f;
161 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
162 }
163 if (!(new40 & 0x40000000)) {
164 new44 &= ~0x000000f0;
165 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
166 }
167 new40 |= 0x40004000;
168 pci_write_config(parent, 0x40, new40, 4);
169 pci_write_config(parent, 0x44, new44, 4);
170 }
171 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
172 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
173 if (bootverbose)
174 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
175 (error) ? "failed" : "success",
176 (scp->chiptype == 0x70108086) ? "PIIX3" :
177 (scp->chiptype == 0x24118086) ? "ICH" :
178 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
179 if (!error) {
180 if (device == ATA_MASTER) {
181 mask40 = 0x0000330f;
182 new40 = 0x00002307;
183 mask44 = 0;
184 new44 = 0;
185 }
186 else {
187 mask40 = 0x000000f0;
188 new40 = 0x00000070;
189 mask44 = 0x0000000f;
190 new44 = 0x0000000b;
191 }
192 if (scp->unit) {
193 mask40 <<= 16;
194 new40 <<= 16;
195 mask44 <<= 4;
196 new44 <<= 4;
197 }
198 pci_write_config(parent, 0x40,
199 (pci_read_config(parent, 0x40, 4) & ~mask40)|
200 new40, 4);
201 pci_write_config(parent, 0x44,
202 (pci_read_config(parent, 0x44, 4) & ~mask44)|
203 new44, 4);
204 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
205 return;
206 }
207 }
208 /* we could set PIO mode timings, but we assume the BIOS did that */
209 break;
210
211 case 0x12308086: /* Intel PIIX */
212 if (wdmamode >= 2 && apiomode >= 4) {
213 int32_t word40;
214
215 word40 = pci_read_config(parent, 0x40, 4);
216 word40 >>= scp->unit * 16;
217
218 /* Check for timing config usable for DMA on controller */
219 if (!((word40 & 0x3300) == 0x2300 &&
220 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
221 break;
222
223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
225 if (bootverbose)
226 ata_printf(scp, device,
227 "%s setting up WDMA2 mode on PIIX chip\n",
228 (error) ? "failed" : "success");
229 if (!error) {
230 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
231 return;
232 }
233 }
234 break;
235
236 case 0x522910b9: /* AcerLabs Aladdin IV/V */
237 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
238 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
239 ata_printf(scp, device,
240 "Aladdin: two atapi devices on this channel, no DMA\n");
241 break;
242 }
243 if (udmamode >= 2) {
244 int32_t word54 = pci_read_config(parent, 0x54, 4);
245
246 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
247 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
248 if (bootverbose)
249 ata_printf(scp, device,
250 "%s setting up UDMA2 mode on Aladdin chip\n",
251 (error) ? "failed" : "success");
252 if (!error) {
253 word54 |= 0x5555;
254 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
255 pci_write_config(parent, 0x54, word54, 4);
256 pci_write_config(parent, 0x53,
257 pci_read_config(parent, 0x53, 1) | 0x03, 1);
258 scp->flags |= ATA_ATAPI_DMA_RO;
259 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
260 return;
261 }
262 }
263 if (wdmamode >= 2 && apiomode >= 4) {
264 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
265 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
266 if (bootverbose)
267 ata_printf(scp, device,
268 "%s setting up WDMA2 mode on Aladdin chip\n",
269 (error) ? "failed" : "success");
270 if (!error) {
271 pci_write_config(parent, 0x53,
272 pci_read_config(parent, 0x53, 1) | 0x03, 1);
273 scp->flags |= ATA_ATAPI_DMA_RO;
274 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
275 return;
276 }
277 }
278 /* we could set PIO mode timings, but we assume the BIOS did that */
279 break;
280
281 case 0x06861106: /* VIA 82C686 */
282 if (udmamode >= 4) {
283 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
284 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
285 if (bootverbose)
286 ata_printf(scp, device,
287 "%s setting up UDMA4 mode on VIA chip\n",
288 (error) ? "failed" : "success");
289 if (!error) {
290 pci_write_config(parent, 0x53 - devno, 0xe8, 1);
291 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
292 return;
293 }
294 }
295 if (udmamode >= 2) {
296 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
297 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
298 if (bootverbose)
299 ata_printf(scp, device,
300 "%s setting up UDMA2 mode on VIA chip\n",
301 (error) ? "failed" : "success");
302 if (!error) {
303 pci_write_config(parent, 0x53 - devno, 0xea, 1);
304 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
305 return;
306 }
307 }
308 goto via_generic;
309
310 case 0x74091022: /* AMD 756 */
311 if (udmamode >= 4) {
312 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
313 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
314 if (bootverbose)
315 ata_printf(scp, device,
316 "%s setting up UDMA4 mode on AMD chip\n",
317 (error) ? "failed" : "success");
318 if (!error) {
319 pci_write_config(parent, 0x53 - devno, 0xc3, 1);
320 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
321 return;
322 }
323 }
324 /* FALLTHROUGH */
325
326 case 0x05961106: /* VIA 82C596 */
327 case 0x05861106: /* VIA 82C586 */
328
329 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
330 if ((udmamode >= 2 && scp->chiptype == 0x05861106 &&
331 pci_read_config(scp->dev, 0x08, 1) >= 0x01) ||
332 (udmamode >= 2 && scp->chiptype == 0x05961106) ||
333 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
336 if (bootverbose)
337 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
338 (error) ? "failed" : "success",
339 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
340 if (!error) {
341 pci_write_config(parent, 0x53 - devno, 0xc0, 1);
342 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
343 return;
344 }
345 }
346 /* FALLTHROUGH */
347
348 case 0x05711106: /* VIA 82C571 */
349via_generic:
350 if (wdmamode >= 2 && apiomode >= 4) {
351 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
352 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
353 if (bootverbose)
354 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
355 (error) ? "failed" : "success",
356 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
357 if (!error) {
358 pci_write_config(parent, 0x53 - devno, 0x82, 1);
359 pci_write_config(parent, 0x4b - devno, 0x31, 1);
360 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
361 return;
362 }
363 }
364 /* we could set PIO mode timings, but we assume the BIOS did that */
365 break;
366
367 case 0x55131039: /* SiS 5591 */
368 if (udmamode >= 2) {
369 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
370 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
371 if (bootverbose)
372 ata_printf(scp, device,
373 "%s setting up UDMA2 mode on SiS chip\n",
374 (error) ? "failed" : "success");
375 if (!error) {
376 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
377 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
378 return;
379 }
380 }
381 if (wdmamode >=2 && apiomode >= 4) {
382 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
383 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
384 if (bootverbose)
385 ata_printf(scp, device,
386 "%s setting up WDMA2 mode on SiS chip\n",
387 (error) ? "failed" : "success");
388 if (!error) {
389 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
390 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
391 return;
392 }
393 }
394 /* we could set PIO mode timings, but we assume the BIOS did that */
395 break;
396
397 case 0x06461095: /* CMD 646 ATA controller */
398 if (wdmamode >= 2 && apiomode >= 4) {
399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
401 if (bootverbose)
402 ata_printf(scp, device,
403 "%s setting up WDMA2 mode on CMD646 chip\n",
404 error ? "failed" : "success");
405 if (!error) {
406 int32_t offset = (devno < 3) ? (devno << 1) : 7;
407
408 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
409 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
410 return;
411 }
412 }
413 /* we could set PIO mode timings, but we assume the BIOS did that */
414 break;
415
416 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
417 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
418 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
419 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
420 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
421 break;
422
423 if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
424 !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
425 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
426 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
427 if (bootverbose)
428 ata_printf(scp, device,
429 "%s setting up UDMA4 mode on Promise chip\n",
430 (error) ? "failed" : "success");
431 if (!error) {
432 promise_timing(scp, devno, ATA_UDMA4);
433 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
434 return;
435 }
436 }
437 if (udmamode >= 2) {
438 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
439 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
440 if (bootverbose)
441 ata_printf(scp, device,
442 "%s setting up UDMA2 mode on Promise chip\n",
443 (error) ? "failed" : "success");
444 if (!error) {
445 promise_timing(scp, devno, ATA_UDMA2);
446 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
447 return;
448 }
449 }
450 if (wdmamode >= 2 && apiomode >= 4) {
451 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
452 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
453 if (bootverbose)
454 ata_printf(scp, device,
455 "%s setting up WDMA2 mode on Promise chip\n",
456 (error) ? "failed" : "success");
457 if (!error) {
458 promise_timing(scp, devno, ATA_WDMA2);
459 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
460 return;
461 }
462 }
463 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
464 ata_pio2mode(apiomode),
465 ATA_C_F_SETXFER, ATA_WAIT_READY);
466 if (bootverbose)
467 ata_printf(scp, device,
468 "%s setting up PIO%d mode on Promise chip\n",
469 (error) ? "failed" : "success",
470 (apiomode >= 0) ? apiomode : 0);
471 promise_timing(scp, devno, ata_pio2mode(apiomode));
472 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
473 return;
474
475 case 0x00041103: /* HighPoint HPT366 controller */
476 /* no ATAPI devices for now */
477 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
478 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
479 break;
480
481 if (udmamode >=4 && !(pci_read_config(parent, 0x5a, 1) & 0x2)) {
482 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
483 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
484 if (bootverbose)
485 ata_printf(scp, device,
486 "%s setting up UDMA4 mode on HPT366 chip\n",
487 (error) ? "failed" : "success");
488 if (!error) {
489 hpt366_timing(scp, devno, ATA_UDMA4);
490 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
491 return;
492 }
493 }
494 if (udmamode >= 2) {
495 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
496 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
497 if (bootverbose)
498 ata_printf(scp, device,
499 "%s setting up UDMA2 mode on HPT366 chip\n",
500 (error) ? "failed" : "success");
501 if (!error) {
502 hpt366_timing(scp, devno, ATA_UDMA2);
503 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
504 return;
505 }
506 }
507 if (wdmamode >= 2 && apiomode >= 4) {
508 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
509 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
510 if (bootverbose)
511 ata_printf(scp, device,
512 "%s setting up WDMA2 mode on HPT366 chip\n",
513 (error) ? "failed" : "success");
514 if (!error) {
515 hpt366_timing(scp, devno, ATA_WDMA2);
516 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
517 return;
518 }
519 }
520 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
521 ata_pio2mode(apiomode),
522 ATA_C_F_SETXFER, ATA_WAIT_READY);
523 if (bootverbose)
524 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
525 (error) ? "failed" : "success",
526 (apiomode >= 0) ? apiomode : 0);
527 hpt366_timing(scp, devno, ata_pio2mode(apiomode));
528 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
529 return;
530
531 default: /* unknown controller chip */
532 /* better not try generic DMA on ATAPI devices it almost never works */
533 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
534 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
535 break;
536
537 /* if controller says its setup for DMA take the easy way out */
538 /* the downside is we dont know what DMA mode we are in */
539 if ((udmamode >= 0 || wdmamode > 1) &&
540 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
541 ((device==ATA_MASTER) ?
542 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
543 scp->mode[ATA_DEV(device)] = ATA_DMA;
544 return;
545 }
546
547 /* well, we have no support for this, but try anyways */
548 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
549 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
550 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
551 if (bootverbose)
552 ata_printf(scp, device,
553 "%s setting up WDMA2 mode on generic chip\n",
554 (error) ? "failed" : "success");
555 if (!error) {
556 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
557 return;
558 }
559 }
560 }
561 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
562 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
563 if (bootverbose)
564 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
565 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
566 if (!error)
567 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
568 else
569 if (bootverbose)
570 ata_printf(scp, device, "using PIO mode set by BIOS\n");
571}
572
573int32_t
574ata_dmasetup(struct ata_softc *scp, int32_t device,
575 int8_t *data, int32_t count, int32_t flags)
576{
577 struct ata_dmaentry *dmatab;
578 u_int32_t dma_count, dma_base;
579 int32_t i = 0;
580
581 if (((uintptr_t)data & 1) || (count & 1))
582 return -1;
583
584 if (!count) {
585 ata_printf(scp, device, "zero length DMA transfer attempted\n");
586 return -1;
587 }
588
589 dmatab = scp->dmatab[ATA_DEV(device)];
590 dma_base = vtophys(data);
591 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
592 data += dma_count;
593 count -= dma_count;
594
595 while (count) {
596 dmatab[i].base = dma_base;
597 dmatab[i].count = (dma_count & 0xffff);
598 i++;
599 if (i >= ATA_DMA_ENTRIES) {
600 ata_printf(scp, device, "too many segments in DMA table\n");
601 return -1;
602 }
603 dma_base = vtophys(data);
604 dma_count = min(count, PAGE_SIZE);
605 data += min(count, PAGE_SIZE);
606 count -= min(count, PAGE_SIZE);
607 }
608 dmatab[i].base = dma_base;
609 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
610 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
611 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
612 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
613 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
614 return 0;
615}
616
617void
618ata_dmastart(struct ata_softc *scp)
619{
620 scp->flags |= ATA_DMA_ACTIVE;
621 outb(scp->bmaddr + ATA_BMCMD_PORT,
622 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
623}
624
625int32_t
626ata_dmadone(struct ata_softc *scp)
627{
628 outb(scp->bmaddr + ATA_BMCMD_PORT,
629 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
630 scp->flags &= ~ATA_DMA_ACTIVE;
631 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
632}
633
634int32_t
635ata_dmastatus(struct ata_softc *scp)
636{
637 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
638}
639
640static void
641promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
642{
643 u_int32_t timing = 0;
644 struct promise_timing {
645 u_int8_t pa:4;
646 u_int8_t prefetch:1;
647 u_int8_t iordy:1;
648 u_int8_t errdy:1;
649 u_int8_t syncin:1;
650 u_int8_t pb:5;
651 u_int8_t mb:3;
652 u_int8_t mc:4;
653 u_int8_t dmaw:1;
654 u_int8_t dmar:1;
655 u_int8_t iordyp:1;
656 u_int8_t dmarqp:1;
657 u_int8_t reserved:8;
658 } *t = (struct promise_timing*)&timing;
659
660 t->iordy = 1; t->iordyp = 1;
661 if (mode >= ATA_DMA) {
662 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
663 }
664
665 switch (scp->chiptype) {
666 case 0x4d33105a: /* Promise 33's */
667 switch (mode) {
668 default:
669 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
670 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
671 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
672 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
673 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
674 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
675 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
676 }
677 break;
678
679 case 0x4d38105a: /* Promise 66's */
680 switch (mode) {
681 default:
682 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
683 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
684 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
685 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
686 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
687 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
688 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
689 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
690 }
691 break;
692 }
693 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
694}
695
696static void
697hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
698{
699 device_t parent = device_get_parent(scp->dev);
700 u_int32_t timing;
701
702 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
703 case 0x85: /* 25Mhz */
704 switch (mode) {
705 case ATA_PIO0: timing = 0xc0d08585; break;
706 case ATA_PIO1: timing = 0xc0d08572; break;
707 case ATA_PIO2: timing = 0xc0ca8542; break;
708 case ATA_PIO3: timing = 0xc0ca8532; break;
709 case ATA_PIO4: timing = 0xc0ca8521; break;
710 case ATA_WDMA2: timing = 0xa0ca8521; break;
711 case ATA_UDMA2: timing = 0x90cf8521; break;
712 case ATA_UDMA4: timing = 0x90c98521; break;
713 default: timing = 0x01208585;
714 }
715 break;
716 default:
717 case 0xa7: /* 33MHz */
718 switch (mode) {
719 case ATA_PIO0: timing = 0xc0d0a7aa; break;
720 case ATA_PIO1: timing = 0xc0d0a7a3; break;
721 case ATA_PIO2: timing = 0xc0d0a753; break;
722 case ATA_PIO3: timing = 0xc0c8a742; break;
723 case ATA_PIO4: timing = 0xc0c8a731; break;
724 case ATA_WDMA2: timing = 0xa0c8a731; break;
725 case ATA_UDMA2: timing = 0x90caa731; break;
726 case ATA_UDMA4: timing = 0x90c9a731; break;
727 default: timing = 0x0120a7a7;
728 }
729 break;
730 case 0xd9: /* 40Mhz */
731 switch (mode) {
732 case ATA_PIO0: timing = 0xc018d9d9; break;
733 case ATA_PIO1: timing = 0xc010d9c7; break;
734 case ATA_PIO2: timing = 0xc010d997; break;
735 case ATA_PIO3: timing = 0xc010d974; break;
736 case ATA_PIO4: timing = 0xc008d963; break;
737 case ATA_WDMA2: timing = 0xa008d943; break;
738 case ATA_UDMA2: timing = 0x900bd943; break;
739 case ATA_UDMA4: timing = 0x900fd943; break;
740 default: timing = 0x0120d9d9;
741 }
742 }
743 pci_write_config(parent, 0x40 + (devno << 2) , (timing & ~0x80000000), 4);
744}
745
746#else /* NPCI > 0 */
747
748void
749ata_dmainit(struct ata_softc *scp, int32_t device,
750 int32_t piomode, int32_t wdmamode, int32_t udmamode)
751{
752}
753
754int32_t
755ata_dmasetup(struct ata_softc *scp, int32_t device,
756 int8_t *data, int32_t count, int32_t flags)
757{
758 return -1;
759}
760
761void
762ata_dmastart(struct ata_softc *scp)
763{
764}
765
766int32_t
767ata_dmadone(struct ata_softc *scp)
768{
769 return -1;
770}
771
772int32_t
773ata_dmastatus(struct ata_softc *scp)
774{
775 return -1;
776}
777
778#endif /* NPCI > 0 */
|