1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 56686 2000-01-27 19:00:51Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 56744 2000-01-28 13:35:43Z sos $
|
29 */
30
31#include "pci.h"
32#include "apm.h"
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/buf.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#if NPCI > 0
43#include <pci/pcivar.h>
44#endif
45#if NAPM > 0
46#include <machine/apm_bios.h>
47#endif
48#include <dev/ata/ata-all.h>
49#include <dev/ata/ata-disk.h>
50
51/* prototypes */
52static void promise_timing(struct ata_softc *, int32_t, int32_t);
53static void hpt366_timing(struct ata_softc *, int32_t, int32_t);
54
55/* misc defines */
56#ifdef __alpha__
57#undef vtophys
58#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59#endif
60
61#if NPCI > 0
62
| 29 */
30
31#include "pci.h"
32#include "apm.h"
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/buf.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#if NPCI > 0
43#include <pci/pcivar.h>
44#endif
45#if NAPM > 0
46#include <machine/apm_bios.h>
47#endif
48#include <dev/ata/ata-all.h>
49#include <dev/ata/ata-disk.h>
50
51/* prototypes */
52static void promise_timing(struct ata_softc *, int32_t, int32_t);
53static void hpt366_timing(struct ata_softc *, int32_t, int32_t);
54
55/* misc defines */
56#ifdef __alpha__
57#undef vtophys
58#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59#endif
60
61#if NPCI > 0
62
|
63int32_t
| 63void
|
64ata_dmainit(struct ata_softc *scp, int32_t device,
65 int32_t apiomode, int32_t wdmamode, int32_t udmamode)
66{
67 int32_t devno = (scp->unit << 1) + ATA_DEV(device);
68 int32_t error;
69
| 64ata_dmainit(struct ata_softc *scp, int32_t device,
65 int32_t apiomode, int32_t wdmamode, int32_t udmamode)
66{
67 int32_t devno = (scp->unit << 1) + ATA_DEV(device);
68 int32_t error;
69
|
| 70 /* set our most pessimistic default mode */
71 scp->mode[ATA_DEV(device)] = ATA_PIO;
72
|
70 if (!scp->bmaddr)
| 73 if (!scp->bmaddr)
|
71 return -1;
| 74 return;
|
72
73 /* if simplex controller, only allow DMA on primary channel */
74 if (scp->unit == 1) {
75 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
76 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
77 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
78 ata_printf(scp, device, "simplex device, DMA on primary only\n");
| 75
76 /* if simplex controller, only allow DMA on primary channel */
77 if (scp->unit == 1) {
78 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) &
79 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
80 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
81 ata_printf(scp, device, "simplex device, DMA on primary only\n");
|
79 return -1;
| 82 return;
|
80 }
81 }
82
83 if (!scp->dmatab[ATA_DEV(device)]) {
84 void *dmatab;
85
86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT)))
| 83 }
84 }
85
86 if (!scp->dmatab[ATA_DEV(device)]) {
87 void *dmatab;
88
89 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT)))
|
87 return -1;
| 90 return;
|
88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
90 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
91 free(dmatab, M_DEVBUF);
| 91 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
92 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
93 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
94 free(dmatab, M_DEVBUF);
|
92 return -1;
| 95 return;
|
93 }
94 scp->dmatab[ATA_DEV(device)] = dmatab;
95 }
96
97 switch (scp->chiptype) {
98
99 case 0x71118086: /* Intel PIIX4 */
100 case 0x71998086: /* Intel PIIX4e */
101 case 0x24118086: /* Intel ICH */
102 case 0x24218086: /* Intel ICH0 */
103 if (udmamode >= 2) {
104 int32_t mask48, new48;
105
106 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
107 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
108 if (bootverbose)
109 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
110 (error) ? "failed" : "success",
111 (scp->chiptype == 0x24118086) ? "ICH" :
112 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
113 if (!error) {
114 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
115 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
116 pci_write_config(scp->dev, 0x48,
117 (pci_read_config(scp->dev, 0x48, 4) &
118 ~mask48) | new48, 4);
119 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 96 }
97 scp->dmatab[ATA_DEV(device)] = dmatab;
98 }
99
100 switch (scp->chiptype) {
101
102 case 0x71118086: /* Intel PIIX4 */
103 case 0x71998086: /* Intel PIIX4e */
104 case 0x24118086: /* Intel ICH */
105 case 0x24218086: /* Intel ICH0 */
106 if (udmamode >= 2) {
107 int32_t mask48, new48;
108
109 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
110 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
111 if (bootverbose)
112 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
113 (error) ? "failed" : "success",
114 (scp->chiptype == 0x24118086) ? "ICH" :
115 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
116 if (!error) {
117 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
118 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
119 pci_write_config(scp->dev, 0x48,
120 (pci_read_config(scp->dev, 0x48, 4) &
121 ~mask48) | new48, 4);
122 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
120 return 0;
| 123 return;
|
121 }
122 }
123 /* FALLTHROUGH */
124
125 case 0x70108086: /* Intel PIIX3 */
126 if (wdmamode >= 2 && apiomode >= 4) {
127 int32_t mask40, new40, mask44, new44;
128
129 /* if SITRE not set doit for both channels */
130 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){
131 new40 = pci_read_config(scp->dev, 0x40, 4);
132 new44 = pci_read_config(scp->dev, 0x44, 4);
133 if (!(new40 & 0x00004000)) {
134 new44 &= ~0x0000000f;
135 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
136 }
137 if (!(new40 & 0x40000000)) {
138 new44 &= ~0x000000f0;
139 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
140 }
141 new40 |= 0x40004000;
142 pci_write_config(scp->dev, 0x40, new40, 4);
143 pci_write_config(scp->dev, 0x44, new44, 4);
144 }
145 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
146 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
147 if (bootverbose)
148 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
149 (error) ? "failed" : "success",
150 (scp->chiptype == 0x70108086) ? "PIIX3" :
151 (scp->chiptype == 0x24118086) ? "ICH" :
152 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
153 if (!error) {
154 if (device == ATA_MASTER) {
155 mask40 = 0x0000330f;
156 new40 = 0x00002307;
157 mask44 = 0;
158 new44 = 0;
159 }
160 else {
161 mask40 = 0x000000f0;
162 new40 = 0x00000070;
163 mask44 = 0x0000000f;
164 new44 = 0x0000000b;
165 }
166 if (scp->unit) {
167 mask40 <<= 16;
168 new40 <<= 16;
169 mask44 <<= 4;
170 new44 <<= 4;
171 }
172 pci_write_config(scp->dev, 0x40,
173 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)|
174 new40, 4);
175 pci_write_config(scp->dev, 0x44,
176 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)|
177 new44, 4);
178 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 124 }
125 }
126 /* FALLTHROUGH */
127
128 case 0x70108086: /* Intel PIIX3 */
129 if (wdmamode >= 2 && apiomode >= 4) {
130 int32_t mask40, new40, mask44, new44;
131
132 /* if SITRE not set doit for both channels */
133 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){
134 new40 = pci_read_config(scp->dev, 0x40, 4);
135 new44 = pci_read_config(scp->dev, 0x44, 4);
136 if (!(new40 & 0x00004000)) {
137 new44 &= ~0x0000000f;
138 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
139 }
140 if (!(new40 & 0x40000000)) {
141 new44 &= ~0x000000f0;
142 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
143 }
144 new40 |= 0x40004000;
145 pci_write_config(scp->dev, 0x40, new40, 4);
146 pci_write_config(scp->dev, 0x44, new44, 4);
147 }
148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
149 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
150 if (bootverbose)
151 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
152 (error) ? "failed" : "success",
153 (scp->chiptype == 0x70108086) ? "PIIX3" :
154 (scp->chiptype == 0x24118086) ? "ICH" :
155 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
156 if (!error) {
157 if (device == ATA_MASTER) {
158 mask40 = 0x0000330f;
159 new40 = 0x00002307;
160 mask44 = 0;
161 new44 = 0;
162 }
163 else {
164 mask40 = 0x000000f0;
165 new40 = 0x00000070;
166 mask44 = 0x0000000f;
167 new44 = 0x0000000b;
168 }
169 if (scp->unit) {
170 mask40 <<= 16;
171 new40 <<= 16;
172 mask44 <<= 4;
173 new44 <<= 4;
174 }
175 pci_write_config(scp->dev, 0x40,
176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)|
177 new40, 4);
178 pci_write_config(scp->dev, 0x44,
179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)|
180 new44, 4);
181 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
179 return 0;
| 182 return;
|
180 }
181 }
182 /* we could set PIO mode timings, but we assume the BIOS did that */
183 break;
184
185 case 0x12308086: /* Intel PIIX */
186 if (wdmamode >= 2 && apiomode >= 4) {
187 int32_t word40;
188
189 word40 = pci_read_config(scp->dev, 0x40, 4);
190 word40 >>= scp->unit * 16;
191
192 /* Check for timing config usable for DMA on controller */
193 if (!((word40 & 0x3300) == 0x2300 &&
194 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
195 break;
196
197 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
198 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
199 if (bootverbose)
200 ata_printf(scp, device,
201 "%s setting up WDMA2 mode on PIIX chip\n",
202 (error) ? "failed" : "success");
203 if (!error) {
204 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 183 }
184 }
185 /* we could set PIO mode timings, but we assume the BIOS did that */
186 break;
187
188 case 0x12308086: /* Intel PIIX */
189 if (wdmamode >= 2 && apiomode >= 4) {
190 int32_t word40;
191
192 word40 = pci_read_config(scp->dev, 0x40, 4);
193 word40 >>= scp->unit * 16;
194
195 /* Check for timing config usable for DMA on controller */
196 if (!((word40 & 0x3300) == 0x2300 &&
197 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
198 break;
199
200 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
201 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
202 if (bootverbose)
203 ata_printf(scp, device,
204 "%s setting up WDMA2 mode on PIIX chip\n",
205 (error) ? "failed" : "success");
206 if (!error) {
207 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
205 return 0;
| 208 return;
|
206 }
207 }
208 break;
209
210 case 0x522910b9: /* AcerLabs Aladdin IV/V */
211 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
212 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
213 ata_printf(scp, device,
214 "Aladdin: two atapi devices on this channel, no DMA\n");
215 break;
216 }
217 if (udmamode >= 2) {
218 int32_t word54 = pci_read_config(scp->dev, 0x54, 4);
219
220 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
221 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
222 if (bootverbose)
223 ata_printf(scp, device,
224 "%s setting up UDMA2 mode on Aladdin chip\n",
225 (error) ? "failed" : "success");
226 if (!error) {
227 word54 |= 0x5555;
228 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
229 pci_write_config(scp->dev, 0x54, word54, 4);
230 pci_write_config(scp->dev, 0x53,
231 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
232 scp->flags |= ATA_ATAPI_DMA_RO;
233 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 209 }
210 }
211 break;
212
213 case 0x522910b9: /* AcerLabs Aladdin IV/V */
214 /* the Aladdin doesn't support ATAPI DMA on both master & slave */
215 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
216 ata_printf(scp, device,
217 "Aladdin: two atapi devices on this channel, no DMA\n");
218 break;
219 }
220 if (udmamode >= 2) {
221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4);
222
223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
225 if (bootverbose)
226 ata_printf(scp, device,
227 "%s setting up UDMA2 mode on Aladdin chip\n",
228 (error) ? "failed" : "success");
229 if (!error) {
230 word54 |= 0x5555;
231 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2)));
232 pci_write_config(scp->dev, 0x54, word54, 4);
233 pci_write_config(scp->dev, 0x53,
234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
235 scp->flags |= ATA_ATAPI_DMA_RO;
236 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
234 return 0;
| 237 return;
|
235 }
236 }
237 if (wdmamode >= 2 && apiomode >= 4) {
238 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
239 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
240 if (bootverbose)
241 ata_printf(scp, device,
242 "%s setting up WDMA2 mode on Aladdin chip\n",
243 (error) ? "failed" : "success");
244 if (!error) {
245 pci_write_config(scp->dev, 0x53,
246 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
247 scp->flags |= ATA_ATAPI_DMA_RO;
248 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 238 }
239 }
240 if (wdmamode >= 2 && apiomode >= 4) {
241 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
243 if (bootverbose)
244 ata_printf(scp, device,
245 "%s setting up WDMA2 mode on Aladdin chip\n",
246 (error) ? "failed" : "success");
247 if (!error) {
248 pci_write_config(scp->dev, 0x53,
249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1);
250 scp->flags |= ATA_ATAPI_DMA_RO;
251 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
249 return 0;
| 252 return;
|
250 }
251 }
252 /* we could set PIO mode timings, but we assume the BIOS did that */
253 break;
254
255 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */
256 case 0x74091022: /* AMD 756 */
257 /* UDMA modes on 82C686 */
258 if (ata_find_dev(scp->dev, 0x06861106)) {
259 if (udmamode >= 4) {
260 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
261 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
262 if (bootverbose)
263 ata_printf(scp, device,
264 "%s setting up UDMA4 mode on VIA chip\n",
265 (error) ? "failed" : "success");
266 if (!error) {
267 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1);
268 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
| 253 }
254 }
255 /* we could set PIO mode timings, but we assume the BIOS did that */
256 break;
257
258 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */
259 case 0x74091022: /* AMD 756 */
260 /* UDMA modes on 82C686 */
261 if (ata_find_dev(scp->dev, 0x06861106)) {
262 if (udmamode >= 4) {
263 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
264 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
265 if (bootverbose)
266 ata_printf(scp, device,
267 "%s setting up UDMA4 mode on VIA chip\n",
268 (error) ? "failed" : "success");
269 if (!error) {
270 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1);
271 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
|
269 return 0;
| 272 return;
|
270 }
271 }
272 if (udmamode >= 2) {
273 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
274 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
275 if (bootverbose)
276 ata_printf(scp, device,
277 "%s setting up UDMA2 mode on VIA chip\n",
278 (error) ? "failed" : "success");
279 if (!error) {
280 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1);
281 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 273 }
274 }
275 if (udmamode >= 2) {
276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
277 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
278 if (bootverbose)
279 ata_printf(scp, device,
280 "%s setting up UDMA2 mode on VIA chip\n",
281 (error) ? "failed" : "success");
282 if (!error) {
283 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1);
284 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
282 return 0;
| 285 return;
|
283 }
284 }
285 }
286
287 /* UDMA4 mode on AMD 756 */
288 if (udmamode >= 4 && scp->chiptype == 0x74091022) {
289 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
290 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
291 if (bootverbose)
292 ata_printf(scp, device,
293 "%s setting up UDMA4 mode on AMD chip\n",
294 (error) ? "failed" : "success");
295 if (!error) {
296 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1);
297 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
| 286 }
287 }
288 }
289
290 /* UDMA4 mode on AMD 756 */
291 if (udmamode >= 4 && scp->chiptype == 0x74091022) {
292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
293 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
294 if (bootverbose)
295 ata_printf(scp, device,
296 "%s setting up UDMA4 mode on AMD chip\n",
297 (error) ? "failed" : "success");
298 if (!error) {
299 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1);
300 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
|
298 return 0;
| 301 return;
|
299 }
300 }
301
302 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
303 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) &&
304 pci_read_config(scp->dev, 0x08, 1) >= 0x01) ||
305 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) ||
306 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
307 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
308 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
309 if (bootverbose)
310 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
311 (error) ? "failed" : "success",
312 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
313 if (!error) {
314 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1);
315 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 302 }
303 }
304
305 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
306 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) &&
307 pci_read_config(scp->dev, 0x08, 1) >= 0x01) ||
308 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) ||
309 (udmamode >= 2 && scp->chiptype == 0x74091022)) {
310 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
311 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
312 if (bootverbose)
313 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n",
314 (error) ? "failed" : "success",
315 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
316 if (!error) {
317 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1);
318 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
316 return 0;
| 319 return;
|
317 }
318 }
319 if (wdmamode >= 2 && apiomode >= 4) {
320 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
321 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
322 if (bootverbose)
323 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
324 (error) ? "failed" : "success",
325 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
326 if (!error) {
327 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1);
328 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1);
329 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 320 }
321 }
322 if (wdmamode >= 2 && apiomode >= 4) {
323 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
324 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
325 if (bootverbose)
326 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n",
327 (error) ? "failed" : "success",
328 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
329 if (!error) {
330 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1);
331 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1);
332 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
330 return 0;
| 333 return;
|
331 }
332 }
333 /* we could set PIO mode timings, but we assume the BIOS did that */
334 break;
335
336 case 0x55131039: /* SiS 5591 */
337 if (udmamode >= 2) {
338 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
339 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
340 if (bootverbose)
341 ata_printf(scp, device,
342 "%s setting up UDMA2 mode on SiS chip\n",
343 (error) ? "failed" : "success");
344 if (!error) {
345 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2);
346 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 334 }
335 }
336 /* we could set PIO mode timings, but we assume the BIOS did that */
337 break;
338
339 case 0x55131039: /* SiS 5591 */
340 if (udmamode >= 2) {
341 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
342 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
343 if (bootverbose)
344 ata_printf(scp, device,
345 "%s setting up UDMA2 mode on SiS chip\n",
346 (error) ? "failed" : "success");
347 if (!error) {
348 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2);
349 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
347 return 0;
| 350 return;
|
348 }
349 }
350 if (wdmamode >=2 && apiomode >= 4) {
351 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
352 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
353 if (bootverbose)
354 ata_printf(scp, device,
355 "%s setting up WDMA2 mode on SiS chip\n",
356 (error) ? "failed" : "success");
357 if (!error) {
358 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2);
359 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 351 }
352 }
353 if (wdmamode >=2 && apiomode >= 4) {
354 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
355 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
356 if (bootverbose)
357 ata_printf(scp, device,
358 "%s setting up WDMA2 mode on SiS chip\n",
359 (error) ? "failed" : "success");
360 if (!error) {
361 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2);
362 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
360 return 0;
| 363 return;
|
361 }
362 }
363 /* we could set PIO mode timings, but we assume the BIOS did that */
364 break;
365
366 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
367 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
368 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
369 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
370 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
371 break;
372
373 if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
374 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
375 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
376 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
377 if (bootverbose)
378 ata_printf(scp, device,
379 "%s setting up UDMA4 mode on Promise chip\n",
380 (error) ? "failed" : "success");
381 if (!error) {
382 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2);
383 promise_timing(scp, devno, ATA_UDMA4);
384 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
| 364 }
365 }
366 /* we could set PIO mode timings, but we assume the BIOS did that */
367 break;
368
369 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */
370 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */
371 /* the Promise can only do DMA on ATA disks not on ATAPI devices */
372 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
373 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
374 break;
375
376 if (udmamode >=4 && scp->chiptype == 0x4d38105a &&
377 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) {
378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
379 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
380 if (bootverbose)
381 ata_printf(scp, device,
382 "%s setting up UDMA4 mode on Promise chip\n",
383 (error) ? "failed" : "success");
384 if (!error) {
385 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2);
386 promise_timing(scp, devno, ATA_UDMA4);
387 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
|
385 return 0;
| 388 return;
|
386 }
387 }
388 if (udmamode >= 2) {
389 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
390 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
391 if (bootverbose)
392 ata_printf(scp, device,
393 "%s setting up UDMA2 mode on Promise chip\n",
394 (error) ? "failed" : "success");
395 if (!error) {
396 promise_timing(scp, devno, ATA_UDMA2);
397 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 389 }
390 }
391 if (udmamode >= 2) {
392 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
393 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
394 if (bootverbose)
395 ata_printf(scp, device,
396 "%s setting up UDMA2 mode on Promise chip\n",
397 (error) ? "failed" : "success");
398 if (!error) {
399 promise_timing(scp, devno, ATA_UDMA2);
400 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
398 return 0;
| 401 return;
|
399 }
400 }
401 if (wdmamode >= 2 && apiomode >= 4) {
402 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
403 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
404 if (bootverbose)
405 ata_printf(scp, device,
406 "%s setting up WDMA2 mode on Promise chip\n",
407 (error) ? "failed" : "success");
408 if (!error) {
409 promise_timing(scp, devno, ATA_WDMA2);
410 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 402 }
403 }
404 if (wdmamode >= 2 && apiomode >= 4) {
405 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
406 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
407 if (bootverbose)
408 ata_printf(scp, device,
409 "%s setting up WDMA2 mode on Promise chip\n",
410 (error) ? "failed" : "success");
411 if (!error) {
412 promise_timing(scp, devno, ATA_WDMA2);
413 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
411 return 0;
| 414 return;
|
412 }
413 }
414 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
415 ata_pio2mode(apiomode),
416 ATA_C_F_SETXFER, ATA_WAIT_READY);
417 if (bootverbose)
418 ata_printf(scp, device,
419 "%s setting up PIO%d mode on Promise chip\n",
420 (error) ? "failed" : "success",
421 (apiomode >= 0) ? apiomode : 0);
422 promise_timing(scp, devno, ata_pio2mode(apiomode));
423 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
| 415 }
416 }
417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
418 ata_pio2mode(apiomode),
419 ATA_C_F_SETXFER, ATA_WAIT_READY);
420 if (bootverbose)
421 ata_printf(scp, device,
422 "%s setting up PIO%d mode on Promise chip\n",
423 (error) ? "failed" : "success",
424 (apiomode >= 0) ? apiomode : 0);
425 promise_timing(scp, devno, ata_pio2mode(apiomode));
426 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
|
424 return -1;
| 427 return;
|
425
426 case 0x00041103: /* HighPoint HPT366 controller */
427 /* no ATAPI devices for now */
428 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
429 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
430 break;
431
432 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) {
433 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
434 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
435 if (bootverbose)
436 ata_printf(scp, device,
437 "%s setting up UDMA4 mode on HPT366 chip\n",
438 (error) ? "failed" : "success");
439 if (!error) {
440 hpt366_timing(scp, devno, ATA_UDMA4);
441 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
| 428
429 case 0x00041103: /* HighPoint HPT366 controller */
430 /* no ATAPI devices for now */
431 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
432 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
433 break;
434
435 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) {
436 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
437 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
438 if (bootverbose)
439 ata_printf(scp, device,
440 "%s setting up UDMA4 mode on HPT366 chip\n",
441 (error) ? "failed" : "success");
442 if (!error) {
443 hpt366_timing(scp, devno, ATA_UDMA4);
444 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
|
442 return 0;
| 445 return;
|
443 }
444 }
445 if (udmamode >= 2) {
446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
447 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
448 if (bootverbose)
449 ata_printf(scp, device,
450 "%s setting up UDMA2 mode on HPT366 chip\n",
451 (error) ? "failed" : "success");
452 if (!error) {
453 hpt366_timing(scp, devno, ATA_UDMA2);
454 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
| 446 }
447 }
448 if (udmamode >= 2) {
449 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
450 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
451 if (bootverbose)
452 ata_printf(scp, device,
453 "%s setting up UDMA2 mode on HPT366 chip\n",
454 (error) ? "failed" : "success");
455 if (!error) {
456 hpt366_timing(scp, devno, ATA_UDMA2);
457 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
|
455 return 0;
| 458 return;
|
456 }
457 }
458 if (wdmamode >= 2 && apiomode >= 4) {
459 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
460 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
461 if (bootverbose)
462 ata_printf(scp, device,
463 "%s setting up WDMA2 mode on HPT366 chip\n",
464 (error) ? "failed" : "success");
465 if (!error) {
466 hpt366_timing(scp, devno, ATA_WDMA2);
467 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 459 }
460 }
461 if (wdmamode >= 2 && apiomode >= 4) {
462 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
463 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
464 if (bootverbose)
465 ata_printf(scp, device,
466 "%s setting up WDMA2 mode on HPT366 chip\n",
467 (error) ? "failed" : "success");
468 if (!error) {
469 hpt366_timing(scp, devno, ATA_WDMA2);
470 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
468 return 0;
| 471 return;
|
469 }
470 }
471 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
472 ata_pio2mode(apiomode),
473 ATA_C_F_SETXFER, ATA_WAIT_READY);
474 if (bootverbose)
475 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
476 (error) ? "failed" : "success",
477 (apiomode >= 0) ? apiomode : 0);
478 hpt366_timing(scp, devno, ata_pio2mode(apiomode));
479 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
| 472 }
473 }
474 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
475 ata_pio2mode(apiomode),
476 ATA_C_F_SETXFER, ATA_WAIT_READY);
477 if (bootverbose)
478 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n",
479 (error) ? "failed" : "success",
480 (apiomode >= 0) ? apiomode : 0);
481 hpt366_timing(scp, devno, ata_pio2mode(apiomode));
482 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
|
480 return -1;
| 483 return;
|
481
482 default: /* unknown controller chip */
483 /* better not try generic DMA on ATAPI devices it almost never works */
484 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
485 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
486 break;
487
| 484
485 default: /* unknown controller chip */
486 /* better not try generic DMA on ATAPI devices it almost never works */
487 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
488 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
489 break;
490
|
| 491 /* if controller says its setup for DMA take the easy way out */
492 /* the downside is we dont know what DMA mode we are in */
493 if ((udmamode >= 0 || wdmamode > 1) &&
494 (inb(scp->bmaddr + ATA_BMSTAT_PORT) &
495 ((device==ATA_MASTER) ?
496 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
497 scp->mode[ATA_DEV(device)] = ATA_DMA;
498 return;
499 }
500
|
488 /* well, we have no support for this, but try anyways */
489 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
490 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
491 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
492 if (bootverbose)
493 ata_printf(scp, device,
494 "%s setting up WDMA2 mode on generic chip\n",
495 (error) ? "failed" : "success");
496 if (!error) {
497 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
| 501 /* well, we have no support for this, but try anyways */
502 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) {
503 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
504 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
505 if (bootverbose)
506 ata_printf(scp, device,
507 "%s setting up WDMA2 mode on generic chip\n",
508 (error) ? "failed" : "success");
509 if (!error) {
510 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
|
498 return 0;
| 511 return;
|
499 }
500 }
501 }
| 512 }
513 }
514 }
|
502 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
503 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY);
| |
504 if (bootverbose)
| 515 if (bootverbose)
|
505 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n",
506 (error) ? "failed" : "success",(apiomode>=0) ? apiomode : 0);
507 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode);
508 return -1;
| 516 ata_printf(scp, device, "using PIO mode set by BIOS\n");
|
509}
510
511int32_t
512ata_dmasetup(struct ata_softc *scp, int32_t device,
513 int8_t *data, int32_t count, int32_t flags)
514{
515 struct ata_dmaentry *dmatab;
516 u_int32_t dma_count, dma_base;
517 int32_t i = 0;
518
519 if (((uintptr_t)data & 1) || (count & 1))
520 return -1;
521
522 if (!count) {
523 ata_printf(scp, device, "zero length DMA transfer attempted\n");
524 return -1;
525 }
526
527 dmatab = scp->dmatab[ATA_DEV(device)];
528 dma_base = vtophys(data);
529 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
530 data += dma_count;
531 count -= dma_count;
532
533 while (count) {
534 dmatab[i].base = dma_base;
535 dmatab[i].count = (dma_count & 0xffff);
536 i++;
537 if (i >= ATA_DMA_ENTRIES) {
538 ata_printf(scp, device, "too many segments in DMA table\n");
539 return -1;
540 }
541 dma_base = vtophys(data);
542 dma_count = min(count, PAGE_SIZE);
543 data += min(count, PAGE_SIZE);
544 count -= min(count, PAGE_SIZE);
545 }
546 dmatab[i].base = dma_base;
547 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
548 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
549 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
550 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
551 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
552 return 0;
553}
554
555void
556ata_dmastart(struct ata_softc *scp)
557{
558 scp->flags |= ATA_DMA_ACTIVE;
559 outb(scp->bmaddr + ATA_BMCMD_PORT,
560 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
561}
562
563int32_t
564ata_dmadone(struct ata_softc *scp)
565{
566 outb(scp->bmaddr + ATA_BMCMD_PORT,
567 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
568 scp->flags &= ~ATA_DMA_ACTIVE;
569 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
570}
571
572int32_t
573ata_dmastatus(struct ata_softc *scp)
574{
575 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
576}
577
578static void
579promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
580{
581 u_int32_t timing;
582 switch (mode) {
583 default:
584 case ATA_PIO0: timing = 0x004ff329; break;
585 case ATA_PIO1: timing = 0x004fec25; break;
586 case ATA_PIO2: timing = 0x004fe823; break;
587 case ATA_PIO3: timing = 0x004fe622; break;
588 case ATA_PIO4: timing = 0x004fe421; break;
589 case ATA_WDMA2: timing = 0x004367f3; break;
590 case ATA_UDMA2: timing = 0x004127f3; break;
591 case ATA_UDMA4: timing = 0x004127f3; break;
592 }
593 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4);
594}
595
596static void
597hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
598{
599 u_int32_t timing;
600
601 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) {
602 case 0x85: /* 25Mhz */
603 switch (mode) {
604 case ATA_PIO0: timing = 0xc0d08585; break;
605 case ATA_PIO1: timing = 0xc0d08572; break;
606 case ATA_PIO2: timing = 0xc0ca8542; break;
607 case ATA_PIO3: timing = 0xc0ca8532; break;
608 case ATA_PIO4: timing = 0xc0ca8521; break;
609 case ATA_WDMA2: timing = 0xa0ca8521; break;
610 case ATA_UDMA2: timing = 0x90cf8521; break;
611 case ATA_UDMA4: timing = 0x90c98521; break;
612 default: timing = 0x01208585;
613 }
614 break;
615 default:
616 case 0xa7: /* 33MHz */
617 switch (mode) {
618 case ATA_PIO0: timing = 0xc0d0a7aa; break;
619 case ATA_PIO1: timing = 0xc0d0a7a3; break;
620 case ATA_PIO2: timing = 0xc0d0a753; break;
621 case ATA_PIO3: timing = 0xc0c8a742; break;
622 case ATA_PIO4: timing = 0xc0c8a731; break;
623 case ATA_WDMA2: timing = 0xa0c8a731; break;
624 case ATA_UDMA2: timing = 0x90caa731; break;
625 case ATA_UDMA4: timing = 0x90c9a731; break;
626 default: timing = 0x0120a7a7;
627 }
628 break;
629 case 0xd9: /* 40Mhz */
630 switch (mode) {
631 case ATA_PIO0: timing = 0xc018d9d9; break;
632 case ATA_PIO1: timing = 0xc010d9c7; break;
633 case ATA_PIO2: timing = 0xc010d997; break;
634 case ATA_PIO3: timing = 0xc010d974; break;
635 case ATA_PIO4: timing = 0xc008d963; break;
636 case ATA_WDMA2: timing = 0xa008d943; break;
637 case ATA_UDMA2: timing = 0x900bd943; break;
638 case ATA_UDMA4: timing = 0x900fd943; break;
639 default: timing = 0x0120d9d9;
640 }
641 }
642 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4);
643}
644
645#else /* NPCI > 0 */
646
647int32_t
648ata_dmainit(struct ata_softc *scp, int32_t device,
649 int32_t piomode, int32_t wdmamode, int32_t udmamode)
650{
651 return -1;
652}
653
654int32_t
655ata_dmasetup(struct ata_softc *scp, int32_t device,
656 int8_t *data, int32_t count, int32_t flags)
657{
658 return -1;
659}
660
661void
662ata_dmastart(struct ata_softc *scp)
663{
664}
665
666int32_t
667ata_dmadone(struct ata_softc *scp)
668{
669 return -1;
670}
671
672int32_t
673ata_dmastatus(struct ata_softc *scp)
674{
675 return -1;
676}
677
678#endif /* NPCI > 0 */
| 517}
518
519int32_t
520ata_dmasetup(struct ata_softc *scp, int32_t device,
521 int8_t *data, int32_t count, int32_t flags)
522{
523 struct ata_dmaentry *dmatab;
524 u_int32_t dma_count, dma_base;
525 int32_t i = 0;
526
527 if (((uintptr_t)data & 1) || (count & 1))
528 return -1;
529
530 if (!count) {
531 ata_printf(scp, device, "zero length DMA transfer attempted\n");
532 return -1;
533 }
534
535 dmatab = scp->dmatab[ATA_DEV(device)];
536 dma_base = vtophys(data);
537 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
538 data += dma_count;
539 count -= dma_count;
540
541 while (count) {
542 dmatab[i].base = dma_base;
543 dmatab[i].count = (dma_count & 0xffff);
544 i++;
545 if (i >= ATA_DMA_ENTRIES) {
546 ata_printf(scp, device, "too many segments in DMA table\n");
547 return -1;
548 }
549 dma_base = vtophys(data);
550 dma_count = min(count, PAGE_SIZE);
551 data += min(count, PAGE_SIZE);
552 count -= min(count, PAGE_SIZE);
553 }
554 dmatab[i].base = dma_base;
555 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
556 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab));
557 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0);
558 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) |
559 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
560 return 0;
561}
562
563void
564ata_dmastart(struct ata_softc *scp)
565{
566 scp->flags |= ATA_DMA_ACTIVE;
567 outb(scp->bmaddr + ATA_BMCMD_PORT,
568 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
569}
570
571int32_t
572ata_dmadone(struct ata_softc *scp)
573{
574 outb(scp->bmaddr + ATA_BMCMD_PORT,
575 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
576 scp->flags &= ~ATA_DMA_ACTIVE;
577 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
578}
579
580int32_t
581ata_dmastatus(struct ata_softc *scp)
582{
583 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
584}
585
586static void
587promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
588{
589 u_int32_t timing;
590 switch (mode) {
591 default:
592 case ATA_PIO0: timing = 0x004ff329; break;
593 case ATA_PIO1: timing = 0x004fec25; break;
594 case ATA_PIO2: timing = 0x004fe823; break;
595 case ATA_PIO3: timing = 0x004fe622; break;
596 case ATA_PIO4: timing = 0x004fe421; break;
597 case ATA_WDMA2: timing = 0x004367f3; break;
598 case ATA_UDMA2: timing = 0x004127f3; break;
599 case ATA_UDMA4: timing = 0x004127f3; break;
600 }
601 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4);
602}
603
604static void
605hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode)
606{
607 u_int32_t timing;
608
609 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) {
610 case 0x85: /* 25Mhz */
611 switch (mode) {
612 case ATA_PIO0: timing = 0xc0d08585; break;
613 case ATA_PIO1: timing = 0xc0d08572; break;
614 case ATA_PIO2: timing = 0xc0ca8542; break;
615 case ATA_PIO3: timing = 0xc0ca8532; break;
616 case ATA_PIO4: timing = 0xc0ca8521; break;
617 case ATA_WDMA2: timing = 0xa0ca8521; break;
618 case ATA_UDMA2: timing = 0x90cf8521; break;
619 case ATA_UDMA4: timing = 0x90c98521; break;
620 default: timing = 0x01208585;
621 }
622 break;
623 default:
624 case 0xa7: /* 33MHz */
625 switch (mode) {
626 case ATA_PIO0: timing = 0xc0d0a7aa; break;
627 case ATA_PIO1: timing = 0xc0d0a7a3; break;
628 case ATA_PIO2: timing = 0xc0d0a753; break;
629 case ATA_PIO3: timing = 0xc0c8a742; break;
630 case ATA_PIO4: timing = 0xc0c8a731; break;
631 case ATA_WDMA2: timing = 0xa0c8a731; break;
632 case ATA_UDMA2: timing = 0x90caa731; break;
633 case ATA_UDMA4: timing = 0x90c9a731; break;
634 default: timing = 0x0120a7a7;
635 }
636 break;
637 case 0xd9: /* 40Mhz */
638 switch (mode) {
639 case ATA_PIO0: timing = 0xc018d9d9; break;
640 case ATA_PIO1: timing = 0xc010d9c7; break;
641 case ATA_PIO2: timing = 0xc010d997; break;
642 case ATA_PIO3: timing = 0xc010d974; break;
643 case ATA_PIO4: timing = 0xc008d963; break;
644 case ATA_WDMA2: timing = 0xa008d943; break;
645 case ATA_UDMA2: timing = 0x900bd943; break;
646 case ATA_UDMA4: timing = 0x900fd943; break;
647 default: timing = 0x0120d9d9;
648 }
649 }
650 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4);
651}
652
653#else /* NPCI > 0 */
654
655int32_t
656ata_dmainit(struct ata_softc *scp, int32_t device,
657 int32_t piomode, int32_t wdmamode, int32_t udmamode)
658{
659 return -1;
660}
661
662int32_t
663ata_dmasetup(struct ata_softc *scp, int32_t device,
664 int8_t *data, int32_t count, int32_t flags)
665{
666 return -1;
667}
668
669void
670ata_dmastart(struct ata_softc *scp)
671{
672}
673
674int32_t
675ata_dmadone(struct ata_softc *scp)
676{
677 return -1;
678}
679
680int32_t
681ata_dmastatus(struct ata_softc *scp)
682{
683 return -1;
684}
685
686#endif /* NPCI > 0 */
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