1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
| 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 55333 2000-01-03 10:26:59Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 56138 2000-01-17 02:04:19Z sos $
|
29 */ 30 31#include "pci.h" 32#include "apm.h" 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/buf.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <vm/vm.h> 41#include <vm/pmap.h> 42#if NPCI > 0 43#include <pci/pcivar.h> 44#endif 45#if NAPM > 0 46#include <machine/apm_bios.h> 47#endif 48#include <dev/ata/ata-all.h> 49#include <dev/ata/ata-disk.h> 50 51/* prototypes */ 52static void promise_timing(struct ata_softc *, int32_t, int32_t); 53static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 54 55/* misc defines */ 56#define MIN(a,b) ((a)>(b)?(b):(a)) 57#ifdef __alpha__ 58#undef vtophys 59#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 60#endif 61 62#if NPCI > 0 63 64int32_t 65ata_dmainit(struct ata_softc *scp, int32_t device, 66 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 67{ 68 int32_t devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 69 int32_t error; 70 void *dmatab; 71 72 if (!scp->bmaddr) 73 return -1; 74 75 /* if simplex controller, only allow DMA on primary channel */ 76 if (scp->unit == 1) { 77 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 78 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 79 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 80 printf("ata%d: simplex device, DMA on primary channel only\n", 81 scp->lun); 82 return -1; 83 } 84 } 85 86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87 return -1; 88 89 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 90 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 91 printf("ata%d-%s: dmatab crosses page boundary, no DMA\n", 92 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 93 free(dmatab, M_DEVBUF); 94 return -1; 95 } 96 scp->dmatab[(device == ATA_MASTER) ? 0 : 1] = dmatab; 97 98 switch (scp->chiptype) { 99 100 case 0x71118086: /* Intel PIIX4 */
| 29 */ 30 31#include "pci.h" 32#include "apm.h" 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/buf.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <vm/vm.h> 41#include <vm/pmap.h> 42#if NPCI > 0 43#include <pci/pcivar.h> 44#endif 45#if NAPM > 0 46#include <machine/apm_bios.h> 47#endif 48#include <dev/ata/ata-all.h> 49#include <dev/ata/ata-disk.h> 50 51/* prototypes */ 52static void promise_timing(struct ata_softc *, int32_t, int32_t); 53static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 54 55/* misc defines */ 56#define MIN(a,b) ((a)>(b)?(b):(a)) 57#ifdef __alpha__ 58#undef vtophys 59#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 60#endif 61 62#if NPCI > 0 63 64int32_t 65ata_dmainit(struct ata_softc *scp, int32_t device, 66 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 67{ 68 int32_t devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 69 int32_t error; 70 void *dmatab; 71 72 if (!scp->bmaddr) 73 return -1; 74 75 /* if simplex controller, only allow DMA on primary channel */ 76 if (scp->unit == 1) { 77 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 78 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 79 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 80 printf("ata%d: simplex device, DMA on primary channel only\n", 81 scp->lun); 82 return -1; 83 } 84 } 85 86 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87 return -1; 88 89 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 90 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 91 printf("ata%d-%s: dmatab crosses page boundary, no DMA\n", 92 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 93 free(dmatab, M_DEVBUF); 94 return -1; 95 } 96 scp->dmatab[(device == ATA_MASTER) ? 0 : 1] = dmatab; 97 98 switch (scp->chiptype) { 99 100 case 0x71118086: /* Intel PIIX4 */
|
101 case 0x71998086: /* Intel PIIX4 */
| 101 case 0x71998086: /* Intel PIIX4e */ 102 case 0x24118086: /* Intel ICH */ 103 case 0x24218086: /* Intel ICH0 */
|
102 if (udmamode >= 2) { 103 int32_t mask48, new48; 104 105 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 106 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 107 if (bootverbose)
| 104 if (udmamode >= 2) { 105 int32_t mask48, new48; 106 107 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 108 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 109 if (bootverbose)
|
108 printf("ata%d-%s: %s setting up UDMA2 mode on PIIX4 chip\n",
| 110 printf("ata%d-%s: %s setting up UDMA2 mode on %s chip\n",
|
109 scp->lun, (device == ATA_MASTER) ? "master" : "slave",
| 111 scp->lun, (device == ATA_MASTER) ? "master" : "slave",
|
110 (error) ? "failed" : "success");
| 112 (error) ? "failed" : "success", 113 (scp->chiptype == 0x24118086) ? "ICH" : 114 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
|
111 if (!error) { 112 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 113 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 114 pci_write_config(scp->dev, 0x48, 115 (pci_read_config(scp->dev, 0x48, 4) & 116 ~mask48) | new48, 4); 117 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 118 return 0; 119 } 120 } 121 /* FALLTHROUGH */ 122 123 case 0x70108086: /* Intel PIIX3 */ 124 if (wdmamode >= 2 && apiomode >= 4) { 125 int32_t mask40, new40, mask44, new44; 126 127 /* if SITRE not set doit for both channels */ 128 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 129 new40 = pci_read_config(scp->dev, 0x40, 4); 130 new44 = pci_read_config(scp->dev, 0x44, 4); 131 if (!(new40 & 0x00004000)) { 132 new44 &= ~0x0000000f; 133 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 134 } 135 if (!(new40 & 0x40000000)) { 136 new44 &= ~0x000000f0; 137 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 138 } 139 new40 |= 0x40004000; 140 pci_write_config(scp->dev, 0x40, new40, 4); 141 pci_write_config(scp->dev, 0x44, new44, 4); 142 } 143 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 144 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 145 if (bootverbose)
| 115 if (!error) { 116 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 117 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 118 pci_write_config(scp->dev, 0x48, 119 (pci_read_config(scp->dev, 0x48, 4) & 120 ~mask48) | new48, 4); 121 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 122 return 0; 123 } 124 } 125 /* FALLTHROUGH */ 126 127 case 0x70108086: /* Intel PIIX3 */ 128 if (wdmamode >= 2 && apiomode >= 4) { 129 int32_t mask40, new40, mask44, new44; 130 131 /* if SITRE not set doit for both channels */ 132 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 133 new40 = pci_read_config(scp->dev, 0x40, 4); 134 new44 = pci_read_config(scp->dev, 0x44, 4); 135 if (!(new40 & 0x00004000)) { 136 new44 &= ~0x0000000f; 137 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 138 } 139 if (!(new40 & 0x40000000)) { 140 new44 &= ~0x000000f0; 141 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 142 } 143 new40 |= 0x40004000; 144 pci_write_config(scp->dev, 0x40, new40, 4); 145 pci_write_config(scp->dev, 0x44, new44, 4); 146 } 147 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 148 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 149 if (bootverbose)
|
146 printf("ata%d-%s: %s setting up WDMA2 mode on PIIX%s chip\n",
| 150 printf("ata%d-%s: %s setting up WDMA2 mode on %s chip\n",
|
147 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 148 (error) ? "failed" : "success",
| 151 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 152 (error) ? "failed" : "success",
|
149 (scp->chiptype == 0x70108086) ? "3" : "4");
| 153 (scp->chiptype == 0x70108086) ? "PIIX3" : 154 (scp->chiptype == 0x24118086) ? "ICH" : 155 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4");
|
150 if (!error) { 151 if (device == ATA_MASTER) { 152 mask40 = 0x0000330f; 153 new40 = 0x00002307; 154 mask44 = 0; 155 new44 = 0; 156 } 157 else { 158 mask40 = 0x000000f0; 159 new40 = 0x00000070; 160 mask44 = 0x0000000f; 161 new44 = 0x0000000b; 162 } 163 if (scp->unit) { 164 mask40 <<= 16; 165 new40 <<= 16; 166 mask44 <<= 4; 167 new44 <<= 4; 168 } 169 pci_write_config(scp->dev, 0x40, 170 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 171 new40, 4); 172 pci_write_config(scp->dev, 0x44, 173 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 174 new44, 4); 175 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 176 return 0; 177 } 178 } 179 /* we could set PIO mode timings, but we assume the BIOS did that */ 180 break; 181 182 case 0x12308086: /* Intel PIIX */ 183 if (wdmamode >= 2 && apiomode >= 4) { 184 int32_t word40; 185 186 word40 = pci_read_config(scp->dev, 0x40, 4); 187 word40 >>= scp->unit * 16; 188 189 /* Check for timing config usable for DMA on controller */ 190 if (!((word40 & 0x3300) == 0x2300 && 191 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 192 break; 193 194 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 195 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 196 if (bootverbose) 197 printf("ata%d-%s: %s setting up WDMA2 mode on PIIX chip\n", 198 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 199 (error) ? "failed" : "success"); 200 if (!error) { 201 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 202 return 0; 203 } 204 } 205 break; 206 207 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 208 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 209 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 210 printf("ata%d: Aladdin: two atapi devices on this channel, " 211 "DMA disabled\n", scp->lun); 212 break; 213 } 214 if (udmamode >= 2) { 215 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 216 217 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 218 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 219 if (bootverbose) 220 printf("ata%d-%s: %s setting up UDMA2 mode on Aladdin chip\n", 221 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 222 (error) ? "failed" : "success"); 223 if (!error) { 224 word54 |= 0x5555; 225 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 226 pci_write_config(scp->dev, 0x54, word54, 4); 227 pci_write_config(scp->dev, 0x53, 228 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 229 scp->flags |= ATA_ATAPI_DMA_RO; 230 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 231 return 0; 232 } 233 } 234 if (wdmamode >= 2 && apiomode >= 4) { 235 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 236 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 237 if (bootverbose) 238 printf("ata%d-%s: %s setting up WDMA2 mode on Aladdin chip\n", 239 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 240 (error) ? "failed" : "success"); 241 if (!error) { 242 pci_write_config(scp->dev, 0x53, 243 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 244 scp->flags |= ATA_ATAPI_DMA_RO; 245 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 246 return 0; 247 } 248 } 249 /* we could set PIO mode timings, but we assume the BIOS did that */ 250 break; 251 252 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */ 253 case 0x74091022: /* AMD 756 */
| 156 if (!error) { 157 if (device == ATA_MASTER) { 158 mask40 = 0x0000330f; 159 new40 = 0x00002307; 160 mask44 = 0; 161 new44 = 0; 162 } 163 else { 164 mask40 = 0x000000f0; 165 new40 = 0x00000070; 166 mask44 = 0x0000000f; 167 new44 = 0x0000000b; 168 } 169 if (scp->unit) { 170 mask40 <<= 16; 171 new40 <<= 16; 172 mask44 <<= 4; 173 new44 <<= 4; 174 } 175 pci_write_config(scp->dev, 0x40, 176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 177 new40, 4); 178 pci_write_config(scp->dev, 0x44, 179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 180 new44, 4); 181 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 182 return 0; 183 } 184 } 185 /* we could set PIO mode timings, but we assume the BIOS did that */ 186 break; 187 188 case 0x12308086: /* Intel PIIX */ 189 if (wdmamode >= 2 && apiomode >= 4) { 190 int32_t word40; 191 192 word40 = pci_read_config(scp->dev, 0x40, 4); 193 word40 >>= scp->unit * 16; 194 195 /* Check for timing config usable for DMA on controller */ 196 if (!((word40 & 0x3300) == 0x2300 && 197 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 198 break; 199 200 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 201 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 202 if (bootverbose) 203 printf("ata%d-%s: %s setting up WDMA2 mode on PIIX chip\n", 204 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 205 (error) ? "failed" : "success"); 206 if (!error) { 207 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 208 return 0; 209 } 210 } 211 break; 212 213 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 214 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 215 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 216 printf("ata%d: Aladdin: two atapi devices on this channel, " 217 "DMA disabled\n", scp->lun); 218 break; 219 } 220 if (udmamode >= 2) { 221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 printf("ata%d-%s: %s setting up UDMA2 mode on Aladdin chip\n", 227 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 word54 |= 0x5555; 231 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 232 pci_write_config(scp->dev, 0x54, word54, 4); 233 pci_write_config(scp->dev, 0x53, 234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 235 scp->flags |= ATA_ATAPI_DMA_RO; 236 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 237 return 0; 238 } 239 } 240 if (wdmamode >= 2 && apiomode >= 4) { 241 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 243 if (bootverbose) 244 printf("ata%d-%s: %s setting up WDMA2 mode on Aladdin chip\n", 245 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 246 (error) ? "failed" : "success"); 247 if (!error) { 248 pci_write_config(scp->dev, 0x53, 249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 250 scp->flags |= ATA_ATAPI_DMA_RO; 251 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 252 return 0; 253 } 254 } 255 /* we could set PIO mode timings, but we assume the BIOS did that */ 256 break; 257 258 case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */ 259 case 0x74091022: /* AMD 756 */
|
254 /* UDMA4 mode only on 82C686 and AMD 756 */ 255 if ((udmamode >= 4 && ata_find_dev(scp->dev, 0x06861106)) || 256 (udmamode >= 4 && scp->chiptype == 0x74091022)) { 257 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 260 /* UDMA modes on 82C686 */ 261 if (ata_find_dev(scp->dev, 0x06861106)) { 262 if (udmamode >= 4) { 263 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
| 264 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
| 265 if (bootverbose) 266 printf("ata%d-%s: %s setting up UDMA4 mode on VIA chip\n", 267 scp->lun, (device == ATA_MASTER) ? "master":"slave", 268 (error) ? "failed" : "success"); 269 if (!error) { 270 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1); 271 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 272 return 0; 273 } 274 } 275 if (udmamode >= 2) { 276 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 277 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 278 if (bootverbose) 279 printf("ata%d-%s: %s setting up UDMA2 mode on VIA chip\n", 280 scp->lun, (device == ATA_MASTER) ? "master":"slave", 281 (error) ? "failed" : "success"); 282 if (!error) { 283 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1); 284 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 285 return 0; 286 } 287 } 288 } 289 290 /* UDMA4 mode on AMD 756 */ 291 if (udmamode >= 4 && scp->chiptype == 0x74091022) { 292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 293 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
259 if (bootverbose)
| 294 if (bootverbose)
|
260 printf("ata%d-%s: %s setting up UDMA4 mode on %s chip\n",
| 295 printf("ata%d-%s: %s setting up UDMA4 mode on AMD chip\n",
|
261 scp->lun, (device == ATA_MASTER) ? "master":"slave",
| 296 scp->lun, (device == ATA_MASTER) ? "master":"slave",
|
262 (error) ? "failed" : "success", 263 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
| 297 (error) ? "failed" : "success");
|
264 if (!error) { 265 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 266 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 267 return 0; 268 } 269 } 270
| 298 if (!error) { 299 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 300 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 301 return 0; 302 } 303 } 304
|
271 /* UDMA2 mode only on 82C586 > rev1, 82C596, 82C686, AMD 756 */
| 305 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */
|
272 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) && 273 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 274 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) ||
| 306 if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) && 307 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 308 (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) ||
|
275 (udmamode >= 2 && ata_find_dev(scp->dev, 0x06861106)) ||
| |
276 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 277 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 278 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 279 if (bootverbose) 280 printf("ata%d-%s: %s setting up UDMA2 mode on %s chip\n", 281 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 282 (error) ? "failed" : "success", 283 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 284 if (!error) { 285 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 286 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 287 return 0; 288 } 289 } 290 if (wdmamode >= 2 && apiomode >= 4) {
| 309 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 310 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 311 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 312 if (bootverbose) 313 printf("ata%d-%s: %s setting up UDMA2 mode on %s chip\n", 314 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 315 (error) ? "failed" : "success", 316 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 317 if (!error) { 318 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 319 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 320 return 0; 321 } 322 } 323 if (wdmamode >= 2 && apiomode >= 4) {
|
291 /* set WDMA2 mode timing */
| |
292 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 293 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 printf("ata%d-%s: %s setting up WDMA2 mode on %s chip\n", 296 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 297 (error) ? "failed" : "success", 298 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 299 if (!error) { 300 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 301 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 302 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 303 return 0; 304 } 305 } 306 /* we could set PIO mode timings, but we assume the BIOS did that */ 307 break; 308 309 case 0x55131039: /* SiS 5591 */ 310 if (udmamode >= 2) { 311 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 312 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 313 if (bootverbose) 314 printf("ata%d-%s: %s setting up UDMA2 mode on SiS chip\n", 315 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 316 (error) ? "failed" : "success"); 317 if (!error) { 318 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 319 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 320 return 0; 321 } 322 } 323 if (wdmamode >=2 && apiomode >= 4) { 324 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 325 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 326 if (bootverbose) 327 printf("ata%d-%s: %s setting up WDMA2 mode on SiS chip\n", 328 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 329 (error) ? "failed" : "success"); 330 if (!error) { 331 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 332 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 333 return 0; 334 } 335 } 336 /* we could set PIO mode timings, but we assume the BIOS did that */ 337 break; 338 339 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 340 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 341 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 342 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 343 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 344 break; 345 346 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 347 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 348 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 349 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 350 if (bootverbose) 351 printf("ata%d-%s: %s setting up UDMA4 mode on Promise chip\n", 352 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 353 (error) ? "failed" : "success"); 354 if (!error) { 355 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2); 356 promise_timing(scp, devno, ATA_UDMA4); 357 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 358 return 0; 359 } 360 } 361 if (udmamode >= 2) { 362 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 363 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 364 if (bootverbose) 365 printf("ata%d-%s: %s setting up UDMA2 mode on Promise chip\n", 366 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 367 (error) ? "failed" : "success"); 368 if (!error) { 369 promise_timing(scp, devno, ATA_UDMA2); 370 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 371 return 0; 372 } 373 } 374 if (wdmamode >= 2 && apiomode >= 4) { 375 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 376 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 377 if (bootverbose) 378 printf("ata%d-%s: %s setting up WDMA2 mode on Promise chip\n", 379 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 380 (error) ? "failed" : "success"); 381 if (!error) { 382 promise_timing(scp, devno, ATA_WDMA2); 383 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 384 return 0; 385 } 386 } 387 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 388 ata_pio2mode(apiomode), 389 ATA_C_F_SETXFER, ATA_WAIT_READY); 390 if (bootverbose) 391 printf("ata%d-%s: %s setting up PIO%d mode on Promise chip\n", 392 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 393 (error) ? "failed" : "success", 394 (apiomode >= 0) ? apiomode : 0); 395 if (!error) { 396 promise_timing(scp, devno, ata_pio2mode(apiomode)); 397 return 0; 398 } 399 break; 400 401 case 0x00041103: /* HighPoint HPT366 controller */ 402 /* no ATAPI devices for now */ 403 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 404 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 405 break; 406 407 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 408 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 409 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 410 if (bootverbose) 411 printf("ata%d-%s: %s setting up UDMA4 mode on HPT366 chip\n", 412 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 413 (error) ? "failed" : "success"); 414 if (!error) { 415 hpt366_timing(scp, devno, ATA_UDMA4); 416 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 417 return 0; 418 } 419 } 420 if (udmamode >= 2) { 421 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 422 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 423 if (bootverbose) 424 printf("ata%d-%s: %s setting up UDMA2 mode on HPT366 chip\n", 425 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 426 (error) ? "failed" : "success"); 427 if (!error) { 428 hpt366_timing(scp, devno, ATA_UDMA2); 429 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 430 return 0; 431 } 432 } 433 if (wdmamode >= 2 && apiomode >= 4) { 434 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 435 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 436 if (bootverbose) 437 printf("ata%d-%s: %s setting up WDMA2 mode on HPT366 chip\n", 438 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 439 (error) ? "failed" : "success"); 440 if (!error) { 441 hpt366_timing(scp, devno, ATA_WDMA2); 442 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 443 return 0; 444 } 445 } 446 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 447 ata_pio2mode(apiomode), 448 ATA_C_F_SETXFER, ATA_WAIT_READY); 449 if (bootverbose) 450 printf("ata%d-%s: %s setting up PIO%d mode on HPT366 chip\n", 451 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 452 (error) ? "failed" : "success", 453 (apiomode >= 0) ? apiomode : 0); 454 if (!error) { 455 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 456 return 0; 457 } 458 break; 459 460 default: /* unknown controller chip */ 461 /* better not try generic DMA on ATAPI devices it almost never works */ 462 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 463 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 464 break; 465 466 /* well, we have no support for this, but try anyways */ 467 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 468#if MAYBE_NOT 469 && (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 470 ((device == ATA_MASTER) ? 471 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 472#endif 473 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 474 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 475 if (bootverbose) 476 printf("ata%d-%s: %s setting up WDMA2 mode on generic chip\n", 477 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 478 (error) ? "failed" : "success"); 479 if (!error) { 480 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 481 return 0; 482 } 483 } 484 } 485 free(dmatab, M_DEVBUF); 486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 487 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 488 if (bootverbose) 489 printf("ata%d-%s: %s setting up PIO%d mode on generic chip\n", 490 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 491 (error) ? "failed" : "success", (apiomode >= 0) ? apiomode : 0); 492 if (!error) 493 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ata_pio2mode(apiomode); 494 return -1; 495} 496 497int32_t 498ata_dmasetup(struct ata_softc *scp, int32_t device, 499 int8_t *data, int32_t count, int32_t flags) 500{ 501 struct ata_dmaentry *dmatab; 502 u_int32_t dma_count, dma_base; 503 int32_t i = 0; 504 505 if (((uintptr_t)data & 1) || (count & 1)) 506 return -1; 507 508 if (!count) { 509 printf("ata%d-%s: zero length DMA transfer attempted\n", 510 scp->lun, ((device == ATA_MASTER) ? "master" : "slave")); 511 return -1; 512 } 513 514 dmatab = scp->dmatab[(device == ATA_MASTER) ? 0 : 1]; 515 dma_base = vtophys(data); 516 dma_count = MIN(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 517 data += dma_count; 518 count -= dma_count; 519 520 while (count) { 521 dmatab[i].base = dma_base; 522 dmatab[i].count = (dma_count & 0xffff); 523 i++; 524 if (i >= ATA_DMA_ENTRIES) { 525 printf("ata%d-%s: too many segments in DMA table\n", 526 scp->lun, (device ? "slave" : "master")); 527 return -1; 528 } 529 dma_base = vtophys(data); 530 dma_count = MIN(count, PAGE_SIZE); 531 data += MIN(count, PAGE_SIZE); 532 count -= MIN(count, PAGE_SIZE); 533 } 534 dmatab[i].base = dma_base; 535 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 536 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 537 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 538 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 539 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 540 return 0; 541} 542 543void 544ata_dmastart(struct ata_softc *scp) 545{ 546 scp->flags |= ATA_DMA_ACTIVE; 547 outb(scp->bmaddr + ATA_BMCMD_PORT, 548 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 549} 550 551int32_t 552ata_dmadone(struct ata_softc *scp) 553{ 554 outb(scp->bmaddr + ATA_BMCMD_PORT, 555 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 556 scp->flags &= ~ATA_DMA_ACTIVE; 557 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 558} 559 560int32_t 561ata_dmastatus(struct ata_softc *scp) 562{ 563 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 564} 565 566static void 567promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 568{ 569 u_int32_t timing; 570 switch (mode) { 571 default: 572 case ATA_PIO0: timing = 0x004ff329; break; 573 case ATA_PIO1: timing = 0x004fec25; break; 574 case ATA_PIO2: timing = 0x004fe823; break; 575 case ATA_PIO3: timing = 0x004fe622; break; 576 case ATA_PIO4: timing = 0x004fe421; break; 577 case ATA_WDMA2: timing = 0x004367f3; break; 578 case ATA_UDMA2: timing = 0x004127f3; break; 579 case ATA_UDMA4: timing = 0x004127f3; break; 580 } 581 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 582} 583 584static void 585hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 586{ 587 u_int32_t timing; 588 589 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 590 case 0x85: /* 25Mhz */ 591 switch (mode) { 592 case ATA_PIO0: timing = 0xc0d08585; break; 593 case ATA_PIO1: timing = 0xc0d08572; break; 594 case ATA_PIO2: timing = 0xc0ca8542; break; 595 case ATA_PIO3: timing = 0xc0ca8532; break; 596 case ATA_PIO4: timing = 0xc0ca8521; break; 597 case ATA_WDMA2: timing = 0xa0ca8521; break; 598 case ATA_UDMA2: timing = 0x90cf8521; break; 599 case ATA_UDMA4: timing = 0x90c98521; break; 600 default: timing = 0x01208585; 601 } 602 break; 603 default: 604 case 0xa7: /* 33MHz */ 605 switch (mode) { 606 case ATA_PIO0: timing = 0xc0d0a7aa; break; 607 case ATA_PIO1: timing = 0xc0d0a7a3; break; 608 case ATA_PIO2: timing = 0xc0d0a753; break; 609 case ATA_PIO3: timing = 0xc0c8a742; break; 610 case ATA_PIO4: timing = 0xc0c8a731; break; 611 case ATA_WDMA2: timing = 0xa0c8a731; break; 612 case ATA_UDMA2: timing = 0x90caa731; break; 613 case ATA_UDMA4: timing = 0x90c9a731; break; 614 default: timing = 0x0120a7a7; 615 } 616 break; 617 case 0xd9: /* 40Mhz */ 618 switch (mode) { 619 case ATA_PIO0: timing = 0xc018d9d9; break; 620 case ATA_PIO1: timing = 0xc010d9c7; break; 621 case ATA_PIO2: timing = 0xc010d997; break; 622 case ATA_PIO3: timing = 0xc010d974; break; 623 case ATA_PIO4: timing = 0xc008d963; break; 624 case ATA_WDMA2: timing = 0xa008d943; break; 625 case ATA_UDMA2: timing = 0x900bd943; break; 626 case ATA_UDMA4: timing = 0x900fd943; break; 627 default: timing = 0x0120d9d9; 628 } 629 } 630 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4); 631} 632 633#else /* NPCI > 0 */ 634 635int32_t 636ata_dmainit(struct ata_softc *scp, int32_t device, 637 int32_t piomode, int32_t wdmamode, int32_t udmamode) 638{ 639 return -1; 640} 641 642int32_t 643ata_dmasetup(struct ata_softc *scp, int32_t device, 644 int8_t *data, int32_t count, int32_t flags) 645{ 646 return -1; 647} 648 649void 650ata_dmastart(struct ata_softc *scp) 651{ 652} 653 654int32_t 655ata_dmadone(struct ata_softc *scp) 656{ 657 return -1; 658} 659 660int32_t 661ata_dmastatus(struct ata_softc *scp) 662{ 663 return -1; 664} 665 666#endif /* NPCI > 0 */
| 324 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 325 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 326 if (bootverbose) 327 printf("ata%d-%s: %s setting up WDMA2 mode on %s chip\n", 328 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 329 (error) ? "failed" : "success", 330 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 331 if (!error) { 332 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 333 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 334 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 335 return 0; 336 } 337 } 338 /* we could set PIO mode timings, but we assume the BIOS did that */ 339 break; 340 341 case 0x55131039: /* SiS 5591 */ 342 if (udmamode >= 2) { 343 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 344 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 345 if (bootverbose) 346 printf("ata%d-%s: %s setting up UDMA2 mode on SiS chip\n", 347 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 348 (error) ? "failed" : "success"); 349 if (!error) { 350 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 351 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 352 return 0; 353 } 354 } 355 if (wdmamode >=2 && apiomode >= 4) { 356 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 358 if (bootverbose) 359 printf("ata%d-%s: %s setting up WDMA2 mode on SiS chip\n", 360 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 361 (error) ? "failed" : "success"); 362 if (!error) { 363 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 364 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 365 return 0; 366 } 367 } 368 /* we could set PIO mode timings, but we assume the BIOS did that */ 369 break; 370 371 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 372 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 373 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 374 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 375 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 376 break; 377 378 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 379 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 380 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 381 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 382 if (bootverbose) 383 printf("ata%d-%s: %s setting up UDMA4 mode on Promise chip\n", 384 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 385 (error) ? "failed" : "success"); 386 if (!error) { 387 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2); 388 promise_timing(scp, devno, ATA_UDMA4); 389 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 390 return 0; 391 } 392 } 393 if (udmamode >= 2) { 394 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 395 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 396 if (bootverbose) 397 printf("ata%d-%s: %s setting up UDMA2 mode on Promise chip\n", 398 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 399 (error) ? "failed" : "success"); 400 if (!error) { 401 promise_timing(scp, devno, ATA_UDMA2); 402 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 403 return 0; 404 } 405 } 406 if (wdmamode >= 2 && apiomode >= 4) { 407 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 408 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 409 if (bootverbose) 410 printf("ata%d-%s: %s setting up WDMA2 mode on Promise chip\n", 411 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 412 (error) ? "failed" : "success"); 413 if (!error) { 414 promise_timing(scp, devno, ATA_WDMA2); 415 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 416 return 0; 417 } 418 } 419 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 420 ata_pio2mode(apiomode), 421 ATA_C_F_SETXFER, ATA_WAIT_READY); 422 if (bootverbose) 423 printf("ata%d-%s: %s setting up PIO%d mode on Promise chip\n", 424 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 425 (error) ? "failed" : "success", 426 (apiomode >= 0) ? apiomode : 0); 427 if (!error) { 428 promise_timing(scp, devno, ata_pio2mode(apiomode)); 429 return 0; 430 } 431 break; 432 433 case 0x00041103: /* HighPoint HPT366 controller */ 434 /* no ATAPI devices for now */ 435 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 436 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 437 break; 438 439 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 440 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 441 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 442 if (bootverbose) 443 printf("ata%d-%s: %s setting up UDMA4 mode on HPT366 chip\n", 444 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 445 (error) ? "failed" : "success"); 446 if (!error) { 447 hpt366_timing(scp, devno, ATA_UDMA4); 448 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA4; 449 return 0; 450 } 451 } 452 if (udmamode >= 2) { 453 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 454 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 455 if (bootverbose) 456 printf("ata%d-%s: %s setting up UDMA2 mode on HPT366 chip\n", 457 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 458 (error) ? "failed" : "success"); 459 if (!error) { 460 hpt366_timing(scp, devno, ATA_UDMA2); 461 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_UDMA2; 462 return 0; 463 } 464 } 465 if (wdmamode >= 2 && apiomode >= 4) { 466 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 467 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 468 if (bootverbose) 469 printf("ata%d-%s: %s setting up WDMA2 mode on HPT366 chip\n", 470 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 471 (error) ? "failed" : "success"); 472 if (!error) { 473 hpt366_timing(scp, devno, ATA_WDMA2); 474 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 475 return 0; 476 } 477 } 478 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 479 ata_pio2mode(apiomode), 480 ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 printf("ata%d-%s: %s setting up PIO%d mode on HPT366 chip\n", 483 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 484 (error) ? "failed" : "success", 485 (apiomode >= 0) ? apiomode : 0); 486 if (!error) { 487 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 488 return 0; 489 } 490 break; 491 492 default: /* unknown controller chip */ 493 /* better not try generic DMA on ATAPI devices it almost never works */ 494 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 495 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 496 break; 497 498 /* well, we have no support for this, but try anyways */ 499 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 500#if MAYBE_NOT 501 && (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 502 ((device == ATA_MASTER) ? 503 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 504#endif 505 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 506 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 507 if (bootverbose) 508 printf("ata%d-%s: %s setting up WDMA2 mode on generic chip\n", 509 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 510 (error) ? "failed" : "success"); 511 if (!error) { 512 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_WDMA2; 513 return 0; 514 } 515 } 516 } 517 free(dmatab, M_DEVBUF); 518 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 519 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 520 if (bootverbose) 521 printf("ata%d-%s: %s setting up PIO%d mode on generic chip\n", 522 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 523 (error) ? "failed" : "success", (apiomode >= 0) ? apiomode : 0); 524 if (!error) 525 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ata_pio2mode(apiomode); 526 return -1; 527} 528 529int32_t 530ata_dmasetup(struct ata_softc *scp, int32_t device, 531 int8_t *data, int32_t count, int32_t flags) 532{ 533 struct ata_dmaentry *dmatab; 534 u_int32_t dma_count, dma_base; 535 int32_t i = 0; 536 537 if (((uintptr_t)data & 1) || (count & 1)) 538 return -1; 539 540 if (!count) { 541 printf("ata%d-%s: zero length DMA transfer attempted\n", 542 scp->lun, ((device == ATA_MASTER) ? "master" : "slave")); 543 return -1; 544 } 545 546 dmatab = scp->dmatab[(device == ATA_MASTER) ? 0 : 1]; 547 dma_base = vtophys(data); 548 dma_count = MIN(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 549 data += dma_count; 550 count -= dma_count; 551 552 while (count) { 553 dmatab[i].base = dma_base; 554 dmatab[i].count = (dma_count & 0xffff); 555 i++; 556 if (i >= ATA_DMA_ENTRIES) { 557 printf("ata%d-%s: too many segments in DMA table\n", 558 scp->lun, (device ? "slave" : "master")); 559 return -1; 560 } 561 dma_base = vtophys(data); 562 dma_count = MIN(count, PAGE_SIZE); 563 data += MIN(count, PAGE_SIZE); 564 count -= MIN(count, PAGE_SIZE); 565 } 566 dmatab[i].base = dma_base; 567 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 568 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 569 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 570 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 571 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 572 return 0; 573} 574 575void 576ata_dmastart(struct ata_softc *scp) 577{ 578 scp->flags |= ATA_DMA_ACTIVE; 579 outb(scp->bmaddr + ATA_BMCMD_PORT, 580 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 581} 582 583int32_t 584ata_dmadone(struct ata_softc *scp) 585{ 586 outb(scp->bmaddr + ATA_BMCMD_PORT, 587 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 588 scp->flags &= ~ATA_DMA_ACTIVE; 589 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 590} 591 592int32_t 593ata_dmastatus(struct ata_softc *scp) 594{ 595 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 596} 597 598static void 599promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 600{ 601 u_int32_t timing; 602 switch (mode) { 603 default: 604 case ATA_PIO0: timing = 0x004ff329; break; 605 case ATA_PIO1: timing = 0x004fec25; break; 606 case ATA_PIO2: timing = 0x004fe823; break; 607 case ATA_PIO3: timing = 0x004fe622; break; 608 case ATA_PIO4: timing = 0x004fe421; break; 609 case ATA_WDMA2: timing = 0x004367f3; break; 610 case ATA_UDMA2: timing = 0x004127f3; break; 611 case ATA_UDMA4: timing = 0x004127f3; break; 612 } 613 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 614} 615 616static void 617hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 618{ 619 u_int32_t timing; 620 621 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 622 case 0x85: /* 25Mhz */ 623 switch (mode) { 624 case ATA_PIO0: timing = 0xc0d08585; break; 625 case ATA_PIO1: timing = 0xc0d08572; break; 626 case ATA_PIO2: timing = 0xc0ca8542; break; 627 case ATA_PIO3: timing = 0xc0ca8532; break; 628 case ATA_PIO4: timing = 0xc0ca8521; break; 629 case ATA_WDMA2: timing = 0xa0ca8521; break; 630 case ATA_UDMA2: timing = 0x90cf8521; break; 631 case ATA_UDMA4: timing = 0x90c98521; break; 632 default: timing = 0x01208585; 633 } 634 break; 635 default: 636 case 0xa7: /* 33MHz */ 637 switch (mode) { 638 case ATA_PIO0: timing = 0xc0d0a7aa; break; 639 case ATA_PIO1: timing = 0xc0d0a7a3; break; 640 case ATA_PIO2: timing = 0xc0d0a753; break; 641 case ATA_PIO3: timing = 0xc0c8a742; break; 642 case ATA_PIO4: timing = 0xc0c8a731; break; 643 case ATA_WDMA2: timing = 0xa0c8a731; break; 644 case ATA_UDMA2: timing = 0x90caa731; break; 645 case ATA_UDMA4: timing = 0x90c9a731; break; 646 default: timing = 0x0120a7a7; 647 } 648 break; 649 case 0xd9: /* 40Mhz */ 650 switch (mode) { 651 case ATA_PIO0: timing = 0xc018d9d9; break; 652 case ATA_PIO1: timing = 0xc010d9c7; break; 653 case ATA_PIO2: timing = 0xc010d997; break; 654 case ATA_PIO3: timing = 0xc010d974; break; 655 case ATA_PIO4: timing = 0xc008d963; break; 656 case ATA_WDMA2: timing = 0xa008d943; break; 657 case ATA_UDMA2: timing = 0x900bd943; break; 658 case ATA_UDMA4: timing = 0x900fd943; break; 659 default: timing = 0x0120d9d9; 660 } 661 } 662 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4); 663} 664 665#else /* NPCI > 0 */ 666 667int32_t 668ata_dmainit(struct ata_softc *scp, int32_t device, 669 int32_t piomode, int32_t wdmamode, int32_t udmamode) 670{ 671 return -1; 672} 673 674int32_t 675ata_dmasetup(struct ata_softc *scp, int32_t device, 676 int8_t *data, int32_t count, int32_t flags) 677{ 678 return -1; 679} 680 681void 682ata_dmastart(struct ata_softc *scp) 683{ 684} 685 686int32_t 687ata_dmadone(struct ata_softc *scp) 688{ 689 return -1; 690} 691 692int32_t 693ata_dmastatus(struct ata_softc *scp) 694{ 695 return -1; 696} 697 698#endif /* NPCI > 0 */
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