1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
| 1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 52918 1999-11-06 16:50:21Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 53029 1999-11-08 21:36:00Z sos $
|
29 */ 30 31#include "pci.h" 32#include "apm.h" 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/buf.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#if NPCI > 0 41#include <pci/pcivar.h> 42#endif 43#if NAPM > 0 44#include <machine/apm_bios.h> 45#endif 46#include <dev/ata/ata-all.h> 47 48/* prototypes */ 49static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 50 51/* misc defines */ 52#define MIN(a,b) ((a)>(b)?(b):(a)) 53#ifdef __alpha__ 54#undef vtophys 55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56#endif 57 58#if NPCI > 0 59 60int32_t 61ata_dmainit(struct ata_softc *scp, int32_t device, 62 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 63{ 64 int32_t type, devno, error; 65 void *dmatab; 66 67 if (!scp->bmaddr) 68 return -1; 69#ifdef ATA_DMADEBUG 70 printf("ata%d: dmainit: ioaddr=0x%x altioaddr=0x%x, bmaddr=0x%x\n", 71 scp->lun, scp->ioaddr, scp->altioaddr, scp->bmaddr); 72#endif 73 74 /* if simplex controller, only allow DMA on primary channel */ 75 if (scp->unit == 1) { 76 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 77 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 78 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 79 printf("ata%d: simplex device, DMA on primary channel only\n", 80 scp->lun); 81 return -1; 82 } 83 } 84 85 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 86 return -1; 87 88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90 printf("ata_dmainit: dmatab crosses page boundary, no DMA\n"); 91 free(dmatab, M_DEVBUF); 92 return -1; 93 } 94 scp->dmatab[(device == ATA_MASTER) ? 0 : 1] = dmatab; 95 96 switch (type = pci_get_devid(scp->dev)) { 97 98 case 0x71118086: /* Intel PIIX4 */ 99 if (udmamode >= 2) { 100 int32_t mask48, new48; 101 102 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 29 */ 30 31#include "pci.h" 32#include "apm.h" 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/buf.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#if NPCI > 0 41#include <pci/pcivar.h> 42#endif 43#if NAPM > 0 44#include <machine/apm_bios.h> 45#endif 46#include <dev/ata/ata-all.h> 47 48/* prototypes */ 49static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 50 51/* misc defines */ 52#define MIN(a,b) ((a)>(b)?(b):(a)) 53#ifdef __alpha__ 54#undef vtophys 55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56#endif 57 58#if NPCI > 0 59 60int32_t 61ata_dmainit(struct ata_softc *scp, int32_t device, 62 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 63{ 64 int32_t type, devno, error; 65 void *dmatab; 66 67 if (!scp->bmaddr) 68 return -1; 69#ifdef ATA_DMADEBUG 70 printf("ata%d: dmainit: ioaddr=0x%x altioaddr=0x%x, bmaddr=0x%x\n", 71 scp->lun, scp->ioaddr, scp->altioaddr, scp->bmaddr); 72#endif 73 74 /* if simplex controller, only allow DMA on primary channel */ 75 if (scp->unit == 1) { 76 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 77 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 78 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 79 printf("ata%d: simplex device, DMA on primary channel only\n", 80 scp->lun); 81 return -1; 82 } 83 } 84 85 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 86 return -1; 87 88 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90 printf("ata_dmainit: dmatab crosses page boundary, no DMA\n"); 91 free(dmatab, M_DEVBUF); 92 return -1; 93 } 94 scp->dmatab[(device == ATA_MASTER) ? 0 : 1] = dmatab; 95 96 switch (type = pci_get_devid(scp->dev)) { 97 98 case 0x71118086: /* Intel PIIX4 */ 99 if (udmamode >= 2) { 100 int32_t mask48, new48; 101 102 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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103 ATA_UDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 103 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
|
104 if (bootverbose) 105 printf("ata%d: %s: %s setting up UDMA2 mode on PIIX4 chip\n", 106 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 107 (error) ? "failed" : "success"); 108 if (error) 109 break; 110 devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 111 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 112 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 113 pci_write_config(scp->dev, 0x48, 114 (pci_read_config(scp->dev, 0x48, 4) & 115 ~mask48) | new48, 4); 116 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 117 return 0; 118 } 119 /* FALLTHROUGH */ 120 121 case 0x70108086: /* Intel PIIX3 */ 122 if (wdmamode >= 2 && apiomode >= 4) { 123 int32_t mask40, new40, mask44, new44; 124 125 /* if SITRE not set doit for both channels */ 126 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 127 new40 = pci_read_config(scp->dev, 0x40, 4); 128 new44 = pci_read_config(scp->dev, 0x44, 4); 129 if (!(new40 & 0x00004000)) { 130 new44 &= ~0x0000000f; 131 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 132 } 133 if (!(new40 & 0x40000000)) { 134 new44 &= ~0x000000f0; 135 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 136 } 137 new40 |= 0x40004000; 138 pci_write_config(scp->dev, 0x40, new40, 4); 139 pci_write_config(scp->dev, 0x44, new44, 4); 140 } 141 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 104 if (bootverbose) 105 printf("ata%d: %s: %s setting up UDMA2 mode on PIIX4 chip\n", 106 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 107 (error) ? "failed" : "success"); 108 if (error) 109 break; 110 devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 111 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 112 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 113 pci_write_config(scp->dev, 0x48, 114 (pci_read_config(scp->dev, 0x48, 4) & 115 ~mask48) | new48, 4); 116 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 117 return 0; 118 } 119 /* FALLTHROUGH */ 120 121 case 0x70108086: /* Intel PIIX3 */ 122 if (wdmamode >= 2 && apiomode >= 4) { 123 int32_t mask40, new40, mask44, new44; 124 125 /* if SITRE not set doit for both channels */ 126 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 127 new40 = pci_read_config(scp->dev, 0x40, 4); 128 new44 = pci_read_config(scp->dev, 0x44, 4); 129 if (!(new40 & 0x00004000)) { 130 new44 &= ~0x0000000f; 131 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 132 } 133 if (!(new40 & 0x40000000)) { 134 new44 &= ~0x000000f0; 135 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 136 } 137 new40 |= 0x40004000; 138 pci_write_config(scp->dev, 0x40, new40, 4); 139 pci_write_config(scp->dev, 0x44, new44, 4); 140 } 141 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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142 ATA_WDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 142 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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143 if (bootverbose) 144 printf("ata%d: %s: %s setting up WDMA2 mode on PIIX4 chip\n", 145 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 146 (error) ? "failed" : "success"); 147 if (error) 148 break; 149 if (device == ATA_MASTER) { 150 mask40 = 0x0000330f; 151 new40 = 0x00002307; 152 mask44 = 0; 153 new44 = 0; 154 } else { 155 mask40 = 0x000000f0; 156 new40 = 0x00000070; 157 mask44 = 0x0000000f; 158 new44 = 0x0000000b; 159 } 160 if (scp->unit) { 161 mask40 <<= 16; 162 new40 <<= 16; 163 mask44 <<= 4; 164 new44 <<= 4; 165 } 166 pci_write_config(scp->dev, 0x40, 167 (pci_read_config(scp->dev, 0x40, 4) & ~mask40) | 168 new40, 4); 169 pci_write_config(scp->dev, 0x44, 170 (pci_read_config(scp->dev, 0x44, 4) & ~mask44) | 171 new44, 4); 172 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 173 return 0; 174 } 175 break; 176 177 case 0x12308086: /* Intel PIIX */ 178 /* probably not worth the trouble */ 179 break; 180 181 case 0x522910b9: /* AcerLabs Aladdin IV/V */
| 143 if (bootverbose) 144 printf("ata%d: %s: %s setting up WDMA2 mode on PIIX4 chip\n", 145 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 146 (error) ? "failed" : "success"); 147 if (error) 148 break; 149 if (device == ATA_MASTER) { 150 mask40 = 0x0000330f; 151 new40 = 0x00002307; 152 mask44 = 0; 153 new44 = 0; 154 } else { 155 mask40 = 0x000000f0; 156 new40 = 0x00000070; 157 mask44 = 0x0000000f; 158 new44 = 0x0000000b; 159 } 160 if (scp->unit) { 161 mask40 <<= 16; 162 new40 <<= 16; 163 mask44 <<= 4; 164 new44 <<= 4; 165 } 166 pci_write_config(scp->dev, 0x40, 167 (pci_read_config(scp->dev, 0x40, 4) & ~mask40) | 168 new40, 4); 169 pci_write_config(scp->dev, 0x44, 170 (pci_read_config(scp->dev, 0x44, 4) & ~mask44) | 171 new44, 4); 172 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 173 return 0; 174 } 175 break; 176 177 case 0x12308086: /* Intel PIIX */ 178 /* probably not worth the trouble */ 179 break; 180 181 case 0x522910b9: /* AcerLabs Aladdin IV/V */
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182 /* the Aladdin has to be setup specially for ATAPI devices */ 183 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 184 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) { 185 int8_t word53 = pci_read_config(scp->dev, 0x53, 1); 186 187 /* set atapi fifo, this should always work */ 188 pci_write_config(scp->dev, 0x53, (word53 & ~0x01) | 0x02, 1); 189 190 /* if both master & slave are atapi devices dont allow DMA */ 191 if (scp->devices & ATA_ATAPI_MASTER && 192 scp->devices & ATA_ATAPI_SLAVE) { 193 printf("ata%d: Aladdin: two atapi devices on this channel, " 194 "DMA disabled\n", scp->lun); 195 break; 196 } 197 /* if needed set atapi fifo & dma */ 198 if ((udmamode >=2) || (wdmamode >= 2 && apiomode >= 4)) { 199 pci_write_config(scp->dev, 0x53, word53 | 0x03, 1); 200 scp->flags |= ATA_ATAPI_DMA_RO; 201 if (device == ATA_MASTER) 202 outb(scp->bmaddr + ATA_BMSTAT_PORT, 203 inb(scp->bmaddr + ATA_BMSTAT_PORT) | 204 ATA_BMSTAT_DMA_MASTER); 205 else 206 outb(scp->bmaddr + ATA_BMSTAT_PORT, 207 inb(scp->bmaddr + ATA_BMSTAT_PORT) | 208 ATA_BMSTAT_DMA_SLAVE); 209 }
| 182 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 183 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 184 printf("ata%d: Aladdin: two atapi devices on this channel, " 185 "DMA disabled\n", scp->lun); 186 break;
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210 } 211 if (udmamode >=2) { 212 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 213 214 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 187 } 188 if (udmamode >=2) { 189 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 190 191 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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215 ATA_UDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 192 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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216 if (bootverbose) 217 printf("ata%d: %s: %s setting up UDMA2 mode on Aladdin chip\n", 218 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 219 (error) ? "failed" : "success"); 220 if (error) 221 break; 222 word54 |= 0x5555; 223 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 224 pci_write_config(scp->dev, 0x54, word54, 4);
| 193 if (bootverbose) 194 printf("ata%d: %s: %s setting up UDMA2 mode on Aladdin chip\n", 195 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 196 (error) ? "failed" : "success"); 197 if (error) 198 break; 199 word54 |= 0x5555; 200 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 201 pci_write_config(scp->dev, 0x54, word54, 4);
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| 202 pci_write_config(scp->dev, 0x53, 203 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 204 scp->flags |= ATA_ATAPI_DMA_RO;
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225 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 226 return 0; 227 228 } 229 else if (wdmamode >= 2 && apiomode >= 4) { 230 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 205 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 206 return 0; 207 208 } 209 else if (wdmamode >= 2 && apiomode >= 4) { 210 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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231 ATA_WDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 211 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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232 if (bootverbose) 233 printf("ata%d: %s: %s setting up WDMA2 mode on Aladdin chip\n", 234 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 235 (error) ? "failed" : "success"); 236 if (error) 237 break;
| 212 if (bootverbose) 213 printf("ata%d: %s: %s setting up WDMA2 mode on Aladdin chip\n", 214 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 215 (error) ? "failed" : "success"); 216 if (error) 217 break;
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| 218 pci_write_config(scp->dev, 0x53, 219 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 220 scp->flags |= ATA_ATAPI_DMA_RO;
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238 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 239 return 0; 240 } 241 break; 242 243 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 244 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 245 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 246 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 247 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 248 break; 249 250 devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 251 if (udmamode >=4 && type == 0x4d38105a && 252 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 253 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 221 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 222 return 0; 223 } 224 break; 225 226 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 227 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 228 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 229 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 230 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 231 break; 232 233 devno = (scp->unit << 1) + ((device == ATA_MASTER) ? 0 : 1); 234 if (udmamode >=4 && type == 0x4d38105a && 235 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 236 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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254 ATA_UDMA4, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 237 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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255 if (bootverbose) 256 printf("ata%d: %s: %s setting up UDMA4 mode on Promise chip\n", 257 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 258 (error) ? "failed" : "success"); 259 if (error) 260 break; 261 outb(scp->bmaddr + 0x11, inl(scp->bmaddr + 0x11) | scp->unit ? 8:2); 262 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004127f3, 4); 263 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA4; 264 return 0; 265 } 266 if (udmamode >=2) { 267 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 238 if (bootverbose) 239 printf("ata%d: %s: %s setting up UDMA4 mode on Promise chip\n", 240 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 241 (error) ? "failed" : "success"); 242 if (error) 243 break; 244 outb(scp->bmaddr + 0x11, inl(scp->bmaddr + 0x11) | scp->unit ? 8:2); 245 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004127f3, 4); 246 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA4; 247 return 0; 248 } 249 if (udmamode >=2) { 250 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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268 ATA_UDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 251 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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269 if (bootverbose) 270 printf("ata%d: %s: %s setting up UDMA2 mode on Promise chip\n", 271 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 272 (error) ? "failed" : "success"); 273 if (error) 274 break; 275 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004127f3, 4); 276 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 277 return 0; 278 } 279 else if (wdmamode >= 2 && apiomode >= 4) { 280 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 252 if (bootverbose) 253 printf("ata%d: %s: %s setting up UDMA2 mode on Promise chip\n", 254 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 255 (error) ? "failed" : "success"); 256 if (error) 257 break; 258 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004127f3, 4); 259 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 260 return 0; 261 } 262 else if (wdmamode >= 2 && apiomode >= 4) { 263 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
|
281 ATA_WDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 264 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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282 if (bootverbose) 283 printf("ata%d: %s: %s setting up WDMA2 mode on Promise chip\n", 284 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 285 (error) ? "failed" : "success"); 286 if (error) 287 break; 288 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004367f3, 4); 289 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 290 return 0; 291 } 292 else { 293 if (bootverbose) 294 printf("ata%d: %s: setting PIO mode on Promise chip\n", 295 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 296 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004fe924, 4); 297 } 298 break; 299 300 case 0x00041103: /* HighPoint HPT366 IDE controller */ 301 /* punt on ATAPI devices for now */ 302 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 303 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 304 break; 305 306 devno = (device == ATA_MASTER) ? 0 : 1; 307 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 308 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 265 if (bootverbose) 266 printf("ata%d: %s: %s setting up WDMA2 mode on Promise chip\n", 267 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 268 (error) ? "failed" : "success"); 269 if (error) 270 break; 271 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004367f3, 4); 272 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 273 return 0; 274 } 275 else { 276 if (bootverbose) 277 printf("ata%d: %s: setting PIO mode on Promise chip\n", 278 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 279 pci_write_config(scp->dev, 0x60 + (devno << 2), 0x004fe924, 4); 280 } 281 break; 282 283 case 0x00041103: /* HighPoint HPT366 IDE controller */ 284 /* punt on ATAPI devices for now */ 285 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 286 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 287 break; 288 289 devno = (device == ATA_MASTER) ? 0 : 1; 290 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 291 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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309 ATA_UDMA4, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 292 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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310 if (bootverbose) 311 printf("ata%d: %s: %s setting up UDMA4 mode on HPT366 chip\n", 312 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 313 (error) ? "failed" : "success"); 314 if (error) 315 break; 316 hpt366_timing(scp, device, ATA_MODE_UDMA4); 317 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA4; 318 return 0; 319 } 320 if (udmamode >=3 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 321 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 293 if (bootverbose) 294 printf("ata%d: %s: %s setting up UDMA4 mode on HPT366 chip\n", 295 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 296 (error) ? "failed" : "success"); 297 if (error) 298 break; 299 hpt366_timing(scp, device, ATA_MODE_UDMA4); 300 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA4; 301 return 0; 302 } 303 if (udmamode >=3 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 304 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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322 ATA_UDMA3, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 305 ATA_UDMA3, ATA_C_F_SETXFER, ATA_WAIT_READY);
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323 if (bootverbose) 324 printf("ata%d: %s: %s setting up UDMA3 mode on HPT366 chip\n", 325 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 326 (error) ? "failed" : "success"); 327 if (error) 328 break; 329 hpt366_timing(scp, device, ATA_MODE_UDMA3); 330 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA3; 331 return 0; 332 } 333 if (udmamode >=2) { 334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 306 if (bootverbose) 307 printf("ata%d: %s: %s setting up UDMA3 mode on HPT366 chip\n", 308 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 309 (error) ? "failed" : "success"); 310 if (error) 311 break; 312 hpt366_timing(scp, device, ATA_MODE_UDMA3); 313 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA3; 314 return 0; 315 } 316 if (udmamode >=2) { 317 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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335 ATA_UDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 318 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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336 if (bootverbose) 337 printf("ata%d: %s: %s setting up UDMA2 mode on HPT366 chip\n", 338 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 339 (error) ? "failed" : "success"); 340 if (error) 341 break; 342 hpt366_timing(scp, device, ATA_MODE_UDMA2); 343 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 344 return 0; 345 } 346 else if (wdmamode >= 2 && apiomode >= 4) { 347 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 319 if (bootverbose) 320 printf("ata%d: %s: %s setting up UDMA2 mode on HPT366 chip\n", 321 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 322 (error) ? "failed" : "success"); 323 if (error) 324 break; 325 hpt366_timing(scp, device, ATA_MODE_UDMA2); 326 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_UDMA2; 327 return 0; 328 } 329 else if (wdmamode >= 2 && apiomode >= 4) { 330 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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348 ATA_WDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 331 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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349 if (bootverbose) 350 printf("ata%d: %s: %s setting up WDMA2 mode on HPT366 chip\n", 351 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 352 (error) ? "failed" : "success"); 353 if (error) 354 break; 355 hpt366_timing(scp, device, ATA_MODE_WDMA2); 356 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 357 return 0; 358 } 359 else { 360 if (bootverbose) 361 printf("ata%d: %s: setting PIO mode on HPT366 chip\n", 362 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 363 hpt366_timing(scp, device, ATA_MODE_PIO); 364 } 365 break; 366 367 default: /* unknown controller chip */ 368 /* better not try generic DMA on ATAPI devices it almost never works */ 369 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 370 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 371 break; 372 373 /* well, we have no support for this, but try anyways */ 374 if (((wdmamode >= 2 && apiomode >= 4) || udmamode >= 2) && 375 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 376 ((device == ATA_MASTER) ? 377 ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
| 332 if (bootverbose) 333 printf("ata%d: %s: %s setting up WDMA2 mode on HPT366 chip\n", 334 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 335 (error) ? "failed" : "success"); 336 if (error) 337 break; 338 hpt366_timing(scp, device, ATA_MODE_WDMA2); 339 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 340 return 0; 341 } 342 else { 343 if (bootverbose) 344 printf("ata%d: %s: setting PIO mode on HPT366 chip\n", 345 scp->lun, (device == ATA_MASTER) ? "master" : "slave"); 346 hpt366_timing(scp, device, ATA_MODE_PIO); 347 } 348 break; 349 350 default: /* unknown controller chip */ 351 /* better not try generic DMA on ATAPI devices it almost never works */ 352 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 353 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 354 break; 355 356 /* well, we have no support for this, but try anyways */ 357 if (((wdmamode >= 2 && apiomode >= 4) || udmamode >= 2) && 358 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 359 ((device == ATA_MASTER) ? 360 ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 361 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
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379 ATA_WDMA2, ATA_C_FEA_SETXFER, ATA_WAIT_READY);
| 362 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
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380 if (bootverbose) 381 printf("ata%d: %s: %s setting up WDMA2 mode on generic chip\n", 382 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 383 (error) ? "failed" : "success"); 384 if (error) 385 break; 386 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 387 return 0; 388 } 389 } 390 free(dmatab, M_DEVBUF); 391 return -1; 392} 393 394int32_t 395ata_dmasetup(struct ata_softc *scp, int32_t device, 396 int8_t *data, int32_t count, int32_t flags) 397{ 398 struct ata_dmaentry *dmatab; 399 u_int32_t dma_count, dma_base; 400 int32_t i = 0; 401 402#ifdef ATA_DMADEBUG 403 printf("ata%d: dmasetup\n", scp->lun); 404#endif 405 if (((uintptr_t)data & 1) || (count & 1)) 406 return -1; 407 408 if (!count) { 409#ifdef ATA_DMADEBUG 410 printf("ata%d: zero length DMA transfer attempt on %s\n", 411 scp->lun, ((device == ATA_MASTER) ? "master" : "slave")); 412#endif 413 return -1; 414 } 415 416 dmatab = scp->dmatab[(device == ATA_MASTER) ? 0 : 1]; 417 dma_base = vtophys(data); 418 dma_count = MIN(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 419 data += dma_count; 420 count -= dma_count; 421 422 while (count) { 423 dmatab[i].base = dma_base; 424 dmatab[i].count = (dma_count & 0xffff); 425 i++; 426 if (i >= ATA_DMA_ENTRIES) { 427 printf("ata%d: too many segments in DMA table for %s\n", 428 scp->lun, (device ? "slave" : "master")); 429 return -1; 430 } 431 dma_base = vtophys(data); 432 dma_count = MIN(count, PAGE_SIZE); 433 data += MIN(count, PAGE_SIZE); 434 count -= MIN(count, PAGE_SIZE); 435 } 436#ifdef ATA_DMADEBUG 437 printf("ata_dmasetup: base=%08x count%08x\n", dma_base, dma_count); 438#endif 439 dmatab[i].base = dma_base; 440 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 441 442 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 443#ifdef ATA_DMADEBUG 444 printf("dmatab=%08x %08x\n", 445 vtophys(dmatab), inl(scp->bmaddr+ATA_BMDTP_PORT)); 446#endif 447 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 448 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 449 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 450 return 0; 451} 452 453void 454ata_dmastart(struct ata_softc *scp) 455{ 456#ifdef ATA_DMADEBUG 457 printf("ata%d: dmastart\n", scp->lun); 458#endif 459 scp->flags |= ATA_DMA_ACTIVE; 460 outb(scp->bmaddr + ATA_BMCMD_PORT, 461 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 462} 463 464int32_t 465ata_dmadone(struct ata_softc *scp) 466{ 467#ifdef ATA_DMADEBUG 468 printf("ata%d: dmadone\n", scp->lun); 469#endif 470 outb(scp->bmaddr + ATA_BMCMD_PORT, 471 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 472 scp->flags &= ~ATA_DMA_ACTIVE; 473 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 474} 475 476int32_t 477ata_dmastatus(struct ata_softc *scp) 478{ 479#ifdef ATA_DMADEBUG 480 printf("ata%d: dmastatus\n", scp->lun); 481#endif 482 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 483} 484 485static void 486hpt366_timing(struct ata_softc *scp, int32_t device, int32_t mode) 487{ 488 u_int32_t timing; 489 490 switch (pci_read_config(scp->dev, (device == ATA_MASTER) ? 0x41 : 0x45, 1)){ 491 case 0x85: /* 25Mhz */ 492 switch (mode) { 493 case ATA_MODE_PIO: timing = 0xc0ca8521; break; 494 case ATA_MODE_WDMA2: timing = 0xa0ca8521; break; 495 case ATA_MODE_UDMA2: 496 case ATA_MODE_UDMA3: timing = 0x90cf8521; break; 497 case ATA_MODE_UDMA4: timing = 0x90c98521; break; 498 default: timing = 0x01208585; 499 } 500 break; 501 default: 502 case 0xa7: /* 33MHz */ 503 switch (mode) { 504 case ATA_MODE_PIO: timing = 0xc0c8a731; break; 505 case ATA_MODE_WDMA2: timing = 0xa0c8a731; break; 506 case ATA_MODE_UDMA2: timing = 0x90caa731; break; 507 case ATA_MODE_UDMA3: timing = 0x90cfa731; break; 508 case ATA_MODE_UDMA4: timing = 0x90c9a731; break; 509 default: timing = 0x0120a7a7; 510 } 511 break; 512 case 0xd9: /* 40Mhz */ 513 switch (mode) { 514 case ATA_MODE_PIO: timing = 0xc008d963; break; 515 case ATA_MODE_WDMA2: timing = 0xa008d943; break; 516 case ATA_MODE_UDMA2: timing = 0x900bd943; break; 517 case ATA_MODE_UDMA3: timing = 0x900ad943; break; 518 case ATA_MODE_UDMA4: timing = 0x900fd943; break; 519 default: timing = 0x0120d9d9; 520 } 521 } 522 pci_write_config(scp->dev, 0x40 + (device==ATA_MASTER ? 0 : 4), timing, 4); 523} 524 525#else /* NPCI > 0 */ 526 527int32_t 528ata_dmainit(struct ata_softc *scp, int32_t device, 529 int32_t piomode, int32_t wdmamode, int32_t udmamode) 530{ 531 return -1; 532} 533 534int32_t 535ata_dmasetup(struct ata_softc *scp, int32_t device, 536 int8_t *data, int32_t count, int32_t flags) 537{ 538 return -1; 539} 540 541void 542ata_dmastart(struct ata_softc *scp) 543{ 544} 545 546int32_t 547ata_dmadone(struct ata_softc *scp) 548{ 549 return -1; 550} 551 552int32_t 553ata_dmastatus(struct ata_softc *scp) 554{ 555 return -1; 556} 557 558#endif /* NPCI > 0 */
| 363 if (bootverbose) 364 printf("ata%d: %s: %s setting up WDMA2 mode on generic chip\n", 365 scp->lun, (device == ATA_MASTER) ? "master" : "slave", 366 (error) ? "failed" : "success"); 367 if (error) 368 break; 369 scp->mode[(device == ATA_MASTER) ? 0 : 1] = ATA_MODE_WDMA2; 370 return 0; 371 } 372 } 373 free(dmatab, M_DEVBUF); 374 return -1; 375} 376 377int32_t 378ata_dmasetup(struct ata_softc *scp, int32_t device, 379 int8_t *data, int32_t count, int32_t flags) 380{ 381 struct ata_dmaentry *dmatab; 382 u_int32_t dma_count, dma_base; 383 int32_t i = 0; 384 385#ifdef ATA_DMADEBUG 386 printf("ata%d: dmasetup\n", scp->lun); 387#endif 388 if (((uintptr_t)data & 1) || (count & 1)) 389 return -1; 390 391 if (!count) { 392#ifdef ATA_DMADEBUG 393 printf("ata%d: zero length DMA transfer attempt on %s\n", 394 scp->lun, ((device == ATA_MASTER) ? "master" : "slave")); 395#endif 396 return -1; 397 } 398 399 dmatab = scp->dmatab[(device == ATA_MASTER) ? 0 : 1]; 400 dma_base = vtophys(data); 401 dma_count = MIN(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 402 data += dma_count; 403 count -= dma_count; 404 405 while (count) { 406 dmatab[i].base = dma_base; 407 dmatab[i].count = (dma_count & 0xffff); 408 i++; 409 if (i >= ATA_DMA_ENTRIES) { 410 printf("ata%d: too many segments in DMA table for %s\n", 411 scp->lun, (device ? "slave" : "master")); 412 return -1; 413 } 414 dma_base = vtophys(data); 415 dma_count = MIN(count, PAGE_SIZE); 416 data += MIN(count, PAGE_SIZE); 417 count -= MIN(count, PAGE_SIZE); 418 } 419#ifdef ATA_DMADEBUG 420 printf("ata_dmasetup: base=%08x count%08x\n", dma_base, dma_count); 421#endif 422 dmatab[i].base = dma_base; 423 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 424 425 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 426#ifdef ATA_DMADEBUG 427 printf("dmatab=%08x %08x\n", 428 vtophys(dmatab), inl(scp->bmaddr+ATA_BMDTP_PORT)); 429#endif 430 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 431 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 432 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 433 return 0; 434} 435 436void 437ata_dmastart(struct ata_softc *scp) 438{ 439#ifdef ATA_DMADEBUG 440 printf("ata%d: dmastart\n", scp->lun); 441#endif 442 scp->flags |= ATA_DMA_ACTIVE; 443 outb(scp->bmaddr + ATA_BMCMD_PORT, 444 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 445} 446 447int32_t 448ata_dmadone(struct ata_softc *scp) 449{ 450#ifdef ATA_DMADEBUG 451 printf("ata%d: dmadone\n", scp->lun); 452#endif 453 outb(scp->bmaddr + ATA_BMCMD_PORT, 454 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 455 scp->flags &= ~ATA_DMA_ACTIVE; 456 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 457} 458 459int32_t 460ata_dmastatus(struct ata_softc *scp) 461{ 462#ifdef ATA_DMADEBUG 463 printf("ata%d: dmastatus\n", scp->lun); 464#endif 465 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 466} 467 468static void 469hpt366_timing(struct ata_softc *scp, int32_t device, int32_t mode) 470{ 471 u_int32_t timing; 472 473 switch (pci_read_config(scp->dev, (device == ATA_MASTER) ? 0x41 : 0x45, 1)){ 474 case 0x85: /* 25Mhz */ 475 switch (mode) { 476 case ATA_MODE_PIO: timing = 0xc0ca8521; break; 477 case ATA_MODE_WDMA2: timing = 0xa0ca8521; break; 478 case ATA_MODE_UDMA2: 479 case ATA_MODE_UDMA3: timing = 0x90cf8521; break; 480 case ATA_MODE_UDMA4: timing = 0x90c98521; break; 481 default: timing = 0x01208585; 482 } 483 break; 484 default: 485 case 0xa7: /* 33MHz */ 486 switch (mode) { 487 case ATA_MODE_PIO: timing = 0xc0c8a731; break; 488 case ATA_MODE_WDMA2: timing = 0xa0c8a731; break; 489 case ATA_MODE_UDMA2: timing = 0x90caa731; break; 490 case ATA_MODE_UDMA3: timing = 0x90cfa731; break; 491 case ATA_MODE_UDMA4: timing = 0x90c9a731; break; 492 default: timing = 0x0120a7a7; 493 } 494 break; 495 case 0xd9: /* 40Mhz */ 496 switch (mode) { 497 case ATA_MODE_PIO: timing = 0xc008d963; break; 498 case ATA_MODE_WDMA2: timing = 0xa008d943; break; 499 case ATA_MODE_UDMA2: timing = 0x900bd943; break; 500 case ATA_MODE_UDMA3: timing = 0x900ad943; break; 501 case ATA_MODE_UDMA4: timing = 0x900fd943; break; 502 default: timing = 0x0120d9d9; 503 } 504 } 505 pci_write_config(scp->dev, 0x40 + (device==ATA_MASTER ? 0 : 4), timing, 4); 506} 507 508#else /* NPCI > 0 */ 509 510int32_t 511ata_dmainit(struct ata_softc *scp, int32_t device, 512 int32_t piomode, int32_t wdmamode, int32_t udmamode) 513{ 514 return -1; 515} 516 517int32_t 518ata_dmasetup(struct ata_softc *scp, int32_t device, 519 int8_t *data, int32_t count, int32_t flags) 520{ 521 return -1; 522} 523 524void 525ata_dmastart(struct ata_softc *scp) 526{ 527} 528 529int32_t 530ata_dmadone(struct ata_softc *scp) 531{ 532 return -1; 533} 534 535int32_t 536ata_dmastatus(struct ata_softc *scp) 537{ 538 return -1; 539} 540 541#endif /* NPCI > 0 */
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