| ata-all.h (74250) | ata-all.h (74302) |
|---|---|
| 1/*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 74250 2001-03-14 12:05:44Z sos $ | 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 74302 2001-03-15 15:36:25Z sos $ |
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 107 unchanged lines hidden (view full) --- 144#define ATA_BMDTP_PORT 0x04 145 146/* structure for holding DMA address data */ 147struct ata_dmaentry { 148 u_int32_t base; 149 u_int32_t count; 150}; 151 | 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ --- 107 unchanged lines hidden (view full) --- 144#define ATA_BMDTP_PORT 0x04 145 146/* structure for holding DMA address data */ 147struct ata_dmaentry { 148 u_int32_t base; 149 u_int32_t count; 150}; 151 |
| 152/* ATA/ATAPI device parameter information */ 153struct ata_params { 154 u_int8_t cmdsize :2; /* packet command size */ 155#define ATAPI_PSIZE_12 0 /* 12 bytes */ 156#define ATAPI_PSIZE_16 1 /* 16 bytes */ 157 158 u_int8_t :3; 159 u_int8_t drqtype :2; /* DRQ type */ 160#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 161#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 162#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 163 164 u_int8_t removable :1; /* device is removable */ 165 u_int8_t device_type :5; /* device type */ 166#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 167#define ATAPI_TYPE_TAPE 1 /* streaming tape */ 168#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 169#define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 170 171 u_int8_t :1; 172 u_int8_t proto :2; /* command protocol */ 173#define ATAPI_PROTO_ATAPI 2 174 175 u_int16_t cylinders; /* number of cylinders */ 176 u_int16_t reserved2; 177 u_int16_t heads; /* # heads */ 178 u_int16_t unfbytespertrk; /* # unformatted bytes/track */ 179 u_int16_t unfbytes; /* # unformatted bytes/sector */ 180 u_int16_t sectors; /* # sectors/track */ 181 u_int16_t vendorunique0[3]; 182 u_int8_t serial[20]; /* serial number */ 183 u_int16_t buffertype; /* buffer type */ 184#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 185#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 186#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 187 188 u_int16_t buffersize; /* buf size, 512-byte units */ 189 u_int16_t necc; /* ecc bytes appended */ 190 u_int8_t revision[8]; /* firmware revision */ 191 u_int8_t model[40]; /* model name */ 192 u_int8_t nsecperint; /* sectors per interrupt */ 193 u_int8_t vendorunique1; 194 u_int16_t usedmovsd; /* double word read/write? */ 195 196 u_int8_t vendorcap; /* vendor capabilities */ 197 u_int8_t dmaflag :1; /* DMA supported - always 1 */ 198 u_int8_t lbaflag :1; /* LBA supported - always 1 */ 199 u_int8_t iordydis :1; /* IORDY may be disabled */ 200 u_int8_t iordyflag :1; /* IORDY supported */ 201 u_int8_t softreset :1; /* needs softreset when busy */ 202 u_int8_t stdby_ovlap :1; /* standby/overlap supported */ 203 u_int8_t queueing :1; /* supports queuing overlap */ 204 u_int8_t idmaflag :1; /* interleaved DMA supported */ 205 u_int16_t capvalidate; /* validation for above */ 206 207 u_int8_t vendorunique3; 208 u_int8_t opiomode; /* PIO modes 0-2 */ 209 u_int8_t vendorunique4; 210 u_int8_t odmamode; /* old DMA modes, not ATA-3 */ 211 212 u_int16_t atavalid; /* fields valid */ 213#define ATA_FLAG_54_58 1 /* words 54-58 valid */ 214#define ATA_FLAG_64_70 2 /* words 64-70 valid */ 215#define ATA_FLAG_88 4 /* word 88 valid */ 216 217 u_int16_t currcyls; 218 u_int16_t currheads; 219 u_int16_t currsectors; 220 u_int16_t currsize0; 221 u_int16_t currsize1; 222 u_int8_t currmultsect; 223 u_int8_t multsectvalid; 224 u_int32_t lbasize; 225 226 u_int16_t sdmamodes; /* singleword DMA modes */ 227 u_int16_t wdmamodes; /* multiword DMA modes */ 228 u_int16_t apiomodes; /* advanced PIO modes */ 229 230 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 231 u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 232 u_int16_t pioblind; /* min. PIO cycle w/o flow */ 233 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 234 235 u_int16_t reserved69; 236 u_int16_t reserved70; 237 u_int16_t rlsovlap; /* rel time (us) for overlap */ 238 u_int16_t rlsservice; /* rel time (us) for service */ 239 u_int16_t reserved73; 240 u_int16_t reserved74; 241 u_int16_t queuelen:5; 242 u_int16_t :11; 243 u_int16_t reserved76; 244 u_int16_t reserved77; 245 u_int16_t reserved78; 246 u_int16_t reserved79; 247 u_int16_t versmajor; 248 u_int16_t versminor; 249 u_int16_t featsupp1; /* 82 */ 250 u_int16_t supmicrocode:1; 251 u_int16_t supqueued:1; 252 u_int16_t supcfa:1; 253 u_int16_t supapm:1; 254 u_int16_t suprmsn:1; 255 u_int16_t :11; 256 u_int16_t featsupp3; /* 84 */ 257 u_int16_t featenab1; /* 85 */ 258 u_int16_t enabmicrocode:1; 259 u_int16_t enabqueued:1; 260 u_int16_t enabcfa:1; 261 u_int16_t enabapm:1; 262 u_int16_t enabrmsn:1; 263 u_int16_t :11; 264 u_int16_t featenab3; /* 87 */ 265 u_int16_t udmamodes; /* UltraDMA modes */ 266 u_int16_t erasetime; 267 u_int16_t enherasetime; 268 u_int16_t apmlevel; 269 u_int16_t masterpasswdrev; 270 u_int16_t masterhwres :8; 271 u_int16_t slavehwres :5; 272 u_int16_t cblid :1; 273 u_int16_t reserved93_1415 :2; 274 u_int16_t reserved94[32]; 275 u_int16_t rmvstat; 276 u_int16_t securstat; 277 u_int16_t reserved129[30]; 278 u_int16_t cfapwrmode; 279 u_int16_t reserved161[84]; 280 u_int16_t integrity; 281}; 282 | |
| 283/* structure describing an ATA device */ 284struct ata_softc { 285 struct device *dev; /* device handle */ 286 int channel; /* channel on this controller */ 287 struct resource *r_io; /* io addr resource handle */ 288 struct resource *r_altio; /* altio addr resource handle */ 289 struct resource *r_bmio; /* bmio addr resource handle */ 290 struct resource *r_irq; /* interrupt of this channel */ 291 void *ih; /* interrupt handle */ 292 int (*intr_func)(struct ata_softc *); /* interrupt function */ 293 u_int32_t chiptype; /* pciid of controller chip */ 294 u_int32_t alignment; /* dma engine min alignment */ | 152/* structure describing an ATA device */ 153struct ata_softc { 154 struct device *dev; /* device handle */ 155 int channel; /* channel on this controller */ 156 struct resource *r_io; /* io addr resource handle */ 157 struct resource *r_altio; /* altio addr resource handle */ 158 struct resource *r_bmio; /* bmio addr resource handle */ 159 struct resource *r_irq; /* interrupt of this channel */ 160 void *ih; /* interrupt handle */ 161 int (*intr_func)(struct ata_softc *); /* interrupt function */ 162 u_int32_t chiptype; /* pciid of controller chip */ 163 u_int32_t alignment; /* dma engine min alignment */ |
| 164 char *dev_name[2]; /* name of device */ |
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| 295 struct ata_params *dev_param[2]; /* ptr to devices params */ 296 void *dev_softc[2]; /* ptr to devices softc's */ 297 int mode[2]; /* transfer mode for devices */ | 165 struct ata_params *dev_param[2]; /* ptr to devices params */ 166 void *dev_softc[2]; /* ptr to devices softc's */ 167 int mode[2]; /* transfer mode for devices */ |
| 298#define ATA_PIO 0x00 299#define ATA_PIO0 0x08 300#define ATA_PIO1 0x09 301#define ATA_PIO2 0x0a 302#define ATA_PIO3 0x0b 303#define ATA_PIO4 0x0c 304#define ATA_DMA 0x10 305#define ATA_WDMA2 0x22 306#define ATA_UDMA2 0x42 307#define ATA_UDMA4 0x44 308#define ATA_UDMA5 0x45 309 | |
| 310 int flags; /* controller flags */ 311#define ATA_DMA_ACTIVE 0x01 312#define ATA_ATAPI_DMA_RO 0x02 313#define ATA_USE_16BIT 0x04 314#define ATA_NO_SLAVE 0x08 315#define ATA_QUEUED 0x10 316 317 int devices; /* what is present */ --- 29 unchanged lines hidden (view full) --- 347int ata_resume(device_t); 348 349void ata_start(struct ata_softc *); 350void ata_reset(struct ata_softc *); 351int ata_reinit(struct ata_softc *); 352int ata_wait(struct ata_softc *, int, u_int8_t); 353int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int); 354int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4); | 168 int flags; /* controller flags */ 169#define ATA_DMA_ACTIVE 0x01 170#define ATA_ATAPI_DMA_RO 0x02 171#define ATA_USE_16BIT 0x04 172#define ATA_NO_SLAVE 0x08 173#define ATA_QUEUED 0x10 174 175 int devices; /* what is present */ --- 29 unchanged lines hidden (view full) --- 205int ata_resume(device_t); 206 207void ata_start(struct ata_softc *); 208void ata_reset(struct ata_softc *); 209int ata_reinit(struct ata_softc *); 210int ata_wait(struct ata_softc *, int, u_int8_t); 211int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int); 212int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4); |
| 213void ata_set_name(struct ata_softc *, int, char *); 214void ata_free_name(struct ata_softc *, int); |
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| 355int ata_get_lun(u_int32_t *); 356int ata_test_lun(u_int32_t *, int); 357void ata_free_lun(u_int32_t *, int); 358char *ata_mode2str(int); 359int ata_pio2mode(int); 360int ata_pmode(struct ata_params *); 361int ata_wmode(struct ata_params *); 362int ata_umode(struct ata_params *); --- 44 unchanged lines hidden --- | 215int ata_get_lun(u_int32_t *); 216int ata_test_lun(u_int32_t *, int); 217void ata_free_lun(u_int32_t *, int); 218char *ata_mode2str(int); 219int ata_pio2mode(int); 220int ata_pmode(struct ata_params *); 221int ata_wmode(struct ata_params *); 222int ata_umode(struct ata_params *); --- 44 unchanged lines hidden --- |