| ata-all.h (44566) | ata-all.h (45095) |
|---|---|
| 1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 1998,1999 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $Id: ata-all.h,v 1.3 1999/03/05 09:43:30 sos Exp $ | 28 * $Id: ata-all.h,v 1.4 1999/03/07 21:49:14 sos Exp $ |
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ | 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ |
| 34#define ATA_PRECOMP 0x01 /* (W) precompensation */ 35#define ATA_COUNT 0x02 /* sector count */ | 34#define ATA_FEATURE 0x01 /* (W) feature register */ 35#define ATA_F_DMA 0x01 /* enable DMA */ 36#define ATA_F_OVL 0x02 /* enable overlap */ 37 38#define ATA_COUNT 0x02 /* (W) sector count */ 39#define ATA_IREASON 0x02 /* (R) interrupt reason */ |
| 36#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 37#define ATA_I_IN 0x02 /* read (1) | write (0) */ 38#define ATA_I_RELEASE 0x04 /* released bus (1) */ | 40#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 41#define ATA_I_IN 0x02 /* read (1) | write (0) */ 42#define ATA_I_RELEASE 0x04 /* released bus (1) */ |
| 43#define ATA_I_TAGMASK 0xf8 /* tag mask */ |
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| 39 40#define ATA_SECTOR 0x03 /* sector # */ 41#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 42#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 43#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ | 44 45#define ATA_SECTOR 0x03 /* sector # */ 46#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 47#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 48#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ |
| 49#define ATA_D_LBA 0x40 /* use LBA adressing */ |
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| 44#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45 46#define ATA_CMD 0x07 /* command register */ 47#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 48#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 49#define ATA_C_READ 0x20 /* read command */ 50#define ATA_C_WRITE 0x30 /* write command */ 51#define ATA_C_READ_MULTI 0xc4 /* read multi command */ 52#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */ 53#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ | 50#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 51 52#define ATA_CMD 0x07 /* command register */ 53#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 54#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 55#define ATA_C_READ 0x20 /* read command */ 56#define ATA_C_WRITE 0x30 /* write command */ 57#define ATA_C_READ_MULTI 0xc4 /* read multi command */ 58#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */ 59#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ |
| 54#define ATA_C_PACKET_CMD 0xa0 /* set multi size command */ | 60#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 61#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 62#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 63#define ATA_C_SETFEATURES 0xef /* features command */ 64#define ATA_C_FEA_SETXFER 0x03 /* set transfer mode */ |
| 55 56#define ATA_STATUS 0x07 /* status register */ 57#define ATA_S_ERROR 0x01 /* error */ 58#define ATA_S_INDEX 0x02 /* index */ 59#define ATA_S_CORR 0x04 /* data corrected */ 60#define ATA_S_DRQ 0x08 /* data request */ | 65 66#define ATA_STATUS 0x07 /* status register */ 67#define ATA_S_ERROR 0x01 /* error */ 68#define ATA_S_INDEX 0x02 /* index */ 69#define ATA_S_CORR 0x04 /* data corrected */ 70#define ATA_S_DRQ 0x08 /* data request */ |
| 61#define ATA_S_DSC 0x10 /* drive Seek Completed */ | 71#define ATA_S_DSC 0x10 /* drive seek completed */ 72#define ATA_S_SERV 0x10 /* drive needs service */ |
| 62#define ATA_S_DWF 0x20 /* drive write fault */ | 73#define ATA_S_DWF 0x20 /* drive write fault */ |
| 74#define ATA_S_DMRD 0x20 /* DMA ready */ |
|
| 63#define ATA_S_DRDY 0x40 /* drive ready */ 64#define ATA_S_BSY 0x80 /* busy */ 65 66#define ATA_ALTPORT 0x206 /* alternate Status register */ 67#define ATA_A_IDS 0x02 /* disable interrupts */ 68#define ATA_A_RESET 0x04 /* RESET controller */ 69#define ATA_A_4BIT 0x08 /* 4 head bits */ 70 | 75#define ATA_S_DRDY 0x40 /* drive ready */ 76#define ATA_S_BSY 0x80 /* busy */ 77 78#define ATA_ALTPORT 0x206 /* alternate Status register */ 79#define ATA_A_IDS 0x02 /* disable interrupts */ 80#define ATA_A_RESET 0x04 /* RESET controller */ 81#define ATA_A_4BIT 0x08 /* 4 head bits */ 82 |
| 71/* Misc defines */ | 83/* misc defines */ |
| 72#define ATA_MASTER 0x00 73#define ATA_SLAVE 0x10 74#define ATA_IOSIZE 0x08 75#define ATA_OP_FINISHED 0x00 76#define ATA_OP_CONTINUES 0x01 77 | 84#define ATA_MASTER 0x00 85#define ATA_SLAVE 0x10 86#define ATA_IOSIZE 0x08 87#define ATA_OP_FINISHED 0x00 88#define ATA_OP_CONTINUES 0x01 89 |
| 78/* Devices types */ | 90/* devices types */ |
| 79#define ATA_ATA_MASTER 0x01 80#define ATA_ATA_SLAVE 0x02 81#define ATA_ATAPI_MASTER 0x04 82#define ATA_ATAPI_SLAVE 0x08 83 | 91#define ATA_ATA_MASTER 0x01 92#define ATA_ATA_SLAVE 0x02 93#define ATA_ATAPI_MASTER 0x04 94#define ATA_ATAPI_SLAVE 0x08 95 |
| 84/* Structure describing an ATA device */ | 96/* busmaster DMA related defines */ 97#define ATA_BM_OFFSET1 0x08 98#define ATA_DMA_ENTRIES 256 99#define ATA_DMA_EOT 0x80000000 100 101#define ATA_BMCMD_PORT 0x00 102#define ATA_BMCMD_START_STOP 0x01 103#define ATA_BMCMD_WRITE_READ 0x08 104 105#define ATA_BMSTAT_PORT 0x02 106#define ATA_BMSTAT_MASK 0x07 107#define ATA_BMSTAT_ACTIVE 0x01 108#define ATA_BMSTAT_ERROR 0x02 109#define ATA_BMSTAT_INTERRUPT 0x04 110#define ATA_BMSTAT_DMA_MASTER 0x20 111#define ATA_BMSTAT_DMA_SLAVE 0x40 112 113#define ATA_BMDTP_PORT 0x04 114 115#define ATA_WDMA2 0x22 116#define ATA_UDMA2 0x42 117 118/* structure for holding DMA address data */ 119struct ata_dmaentry { 120 u_int32_t base; 121 u_int32_t count; 122}; 123 124/* structure describing an ATA device */ |
| 85struct ata_softc { | 125struct ata_softc { |
| 86 u_int32_t unit; /* this instance's number */ 87 u_int32_t ioaddr; /* port addr */ 88 u_int32_t altioaddr; /* alternate port addr */ 89 void *dmacookie; /* handle for DMA services */ | 126 int32_t unit; /* unit on this controller */ 127 int32_t lun; /* logical unit # */ 128 pcici_t tag; /* PCI tag for this device */ 129 int32_t ioaddr; /* port addr */ 130 int32_t altioaddr; /* alternate port addr */ 131 int32_t bmaddr; /* bus master DMA port */ 132 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ |
| 90 int32_t flags; /* controller flags */ | 133 int32_t flags; /* controller flags */ |
| 91#define ATA_F_SLAVE_ONLY 0x0001 92 | |
| 93 int32_t devices; /* what is present */ 94 u_int8_t status; /* last controller status */ 95 u_int8_t error; /* last controller error */ 96 int32_t active; /* active processing request */ 97#define ATA_IDLE 0x0 98#define ATA_IMMEDIATE 0x0 99#define ATA_WAIT_INTR 0x1 100#define ATA_IGNORE_INTR 0x2 --- 5 unchanged lines hidden (view full) --- 106}; 107 108#define MAXATA 8 109 110extern struct ata_softc *atadevices[]; 111 112/* public prototypes */ 113void ata_start(struct ata_softc *); | 134 int32_t devices; /* what is present */ 135 u_int8_t status; /* last controller status */ 136 u_int8_t error; /* last controller error */ 137 int32_t active; /* active processing request */ 138#define ATA_IDLE 0x0 139#define ATA_IMMEDIATE 0x0 140#define ATA_WAIT_INTR 0x1 141#define ATA_IGNORE_INTR 0x2 --- 5 unchanged lines hidden (view full) --- 147}; 148 149#define MAXATA 8 150 151extern struct ata_softc *atadevices[]; 152 153/* public prototypes */ 154void ata_start(struct ata_softc *); |
| 114int32_t ata_wait(struct ata_softc *, u_int8_t); 115int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); | 155int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 156int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 157int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 158int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); 159void ata_dmastart(struct ata_softc *, int32_t); 160int32_t ata_dmastatus(struct ata_softc *, int32_t); 161int32_t ata_dmadone(struct ata_softc *, int32_t); |
| 116void bswap(int8_t *, int32_t); 117void btrim(int8_t *, int32_t); 118void bpack(int8_t *, int8_t *, int32_t); 119 | 162void bswap(int8_t *, int32_t); 163void btrim(int8_t *, int32_t); 164void bpack(int8_t *, int8_t *, int32_t); 165 |