28c28
< * $FreeBSD: head/sys/dev/ata/ata-all.h 64307 2000-08-06 19:51:58Z sos $
---
> * $FreeBSD: head/sys/dev/ata/ata-all.h 66070 2000-09-19 11:08:39Z sos $
60a61,63
> #define ATA_C_NOP 0x00 /* NOP command */
> #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
> #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
65a69
> #define ATA_C_SERVICE 0xa2 /* service command */
68a73
> #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
70a76
> #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
74d79
< #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
75a81,84
> #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
> #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
> #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
> #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89,90c98,99
< #define ATA_ALTPORT 0x206 /* alternate status register */
< #define ATA_ALTPORT_PCCARD 0x8 /* ditto on PCCARD devices */
---
> #define ATA_ALTSTAT 0x02 /* alternate status register */
> #define ATA_ALTCTRL 0X02 /* alternate device control */
95c104,105
< #define ATA_ALTIOSIZE 0x01
---
> #define ATA_ALTPORT 0x204 /* alternate registers offset */
> #define ATA_ALTIOSIZE 0x01 /* alternate registers size */
104c114
< #define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
---
> #define ATA_PARAM(scp, unit) (scp->dev_param[ATA_DEV(unit)])
106d115
<
159c168
< int16_t reserved2;
---
> u_int16_t reserved2;
161,162c170,171
< int16_t unfbytespertrk; /* # unformatted bytes/track */
< int16_t unfbytes; /* # unformatted bytes/sector */
---
> u_int16_t unfbytespertrk; /* # unformatted bytes/track */
> u_int16_t unfbytes; /* # unformatted bytes/sector */
164,166c173,175
< int16_t vendorunique0[3];
< int8_t serial[20]; /* serial number */
< int16_t buffertype; /* buffer type */
---
> u_int16_t vendorunique0[3];
> u_int8_t serial[20]; /* serial number */
> u_int16_t buffertype; /* buffer type */
171,177c180,186
< int16_t buffersize; /* buf size, 512-byte units */
< int16_t necc; /* ecc bytes appended */
< int8_t revision[8]; /* firmware revision */
< int8_t model[40]; /* model name */
< int8_t nsecperint; /* sectors per interrupt */
< int8_t vendorunique1;
< int16_t usedmovsd; /* double word read/write? */
---
> u_int16_t buffersize; /* buf size, 512-byte units */
> u_int16_t necc; /* ecc bytes appended */
> u_int8_t revision[8]; /* firmware revision */
> u_int8_t model[40]; /* model name */
> u_int8_t nsecperint; /* sectors per interrupt */
> u_int8_t vendorunique1;
> u_int16_t usedmovsd; /* double word read/write? */
186c195
< u_int8_t queuing :1; /* supports queuing overlap */
---
> u_int8_t queueing :1; /* supports queuing overlap */
188c197
< int16_t capvalidate; /* validation for above */
---
> u_int16_t capvalidate; /* validation for above */
190,193c199,202
< int8_t vendorunique3;
< int8_t opiomode; /* PIO modes 0-2 */
< int8_t vendorunique4;
< int8_t odmamode; /* old DMA modes, not ATA-3 */
---
> u_int8_t vendorunique3;
> u_int8_t opiomode; /* PIO modes 0-2 */
> u_int8_t vendorunique4;
> u_int8_t odmamode; /* old DMA modes, not ATA-3 */
195c204
< int16_t atavalid; /* fields valid */
---
> u_int16_t atavalid; /* fields valid */
200,207c209,216
< int16_t currcyls;
< int16_t currheads;
< int16_t currsectors;
< int16_t currsize0;
< int16_t currsize1;
< int8_t currmultsect;
< int8_t multsectvalid;
< int32_t lbasize;
---
> u_int16_t currcyls;
> u_int16_t currheads;
> u_int16_t currsectors;
> u_int16_t currsize0;
> u_int16_t currsize1;
> u_int8_t currmultsect;
> u_int8_t multsectvalid;
> u_int32_t lbasize;
209,211c218,220
< int16_t sdmamodes; /* singleword DMA modes */
< int16_t wdmamodes; /* multiword DMA modes */
< int16_t apiomodes; /* advanced PIO modes */
---
> u_int16_t sdmamodes; /* singleword DMA modes */
> u_int16_t wdmamodes; /* multiword DMA modes */
> u_int16_t apiomodes; /* advanced PIO modes */
218,219c227,228
< int16_t reserved69;
< int16_t reserved70;
---
> u_int16_t reserved69;
> u_int16_t reserved70;
222,241c231,261
< int16_t reserved73;
< int16_t reserved74;
< int16_t queuelen;
< int16_t reserved76;
< int16_t reserved77;
< int16_t reserved78;
< int16_t reserved79;
< int16_t versmajor;
< int16_t versminor;
< int16_t featsupp1;
< int16_t featsupp2;
< int16_t featsupp3;
< int16_t featenab1;
< int16_t featenab2;
< int16_t featenab3;
< int16_t udmamodes; /* UltraDMA modes */
< int16_t erasetime;
< int16_t enherasetime;
< int16_t apmlevel;
< int16_t masterpasswdrev;
---
> u_int16_t reserved73;
> u_int16_t reserved74;
> u_int16_t queuelen:5;
> u_int16_t :11;
> u_int16_t reserved76;
> u_int16_t reserved77;
> u_int16_t reserved78;
> u_int16_t reserved79;
> u_int16_t versmajor;
> u_int16_t versminor;
> u_int16_t featsupp1; /* 82 */
> u_int16_t supmicrocode:1;
> u_int16_t supqueued:1;
> u_int16_t supcfa:1;
> u_int16_t supapm:1;
> u_int16_t suprmsn:1;
> u_int16_t :11;
> u_int16_t featsupp3; /* 84 */
> u_int16_t featenab1; /* 85 */
> u_int16_t enabmicrocode:1;
> u_int16_t enabqueued:1;
> u_int16_t enabcfa:1;
> u_int16_t enabapm:1;
> u_int16_t enabrmsn:1;
> u_int16_t :11;
> u_int16_t featenab3; /* 87 */
> u_int16_t udmamodes; /* UltraDMA modes */
> u_int16_t erasetime;
> u_int16_t enherasetime;
> u_int16_t apmlevel;
> u_int16_t masterpasswdrev;
246,252c266,272
< int16_t reserved94[32];
< int16_t rmvstat;
< int16_t securstat;
< int16_t reserved129[30];
< int16_t cfapwrmode;
< int16_t reserved161[84];
< int16_t integrity;
---
> u_int16_t reserved94[32];
> u_int16_t rmvstat;
> u_int16_t securstat;
> u_int16_t reserved129[30];
> u_int16_t cfapwrmode;
> u_int16_t reserved161[84];
> u_int16_t integrity;
258c278
< int32_t unit; /* unit on this controller */
---
> int unit; /* unit on this controller */
264,267c284,288
< int32_t ioaddr; /* physical port addr */
< int32_t altioaddr; /* physical alt port addr */
< int32_t bmaddr; /* physical bus master port */
< int32_t chiptype; /* pciid of controller chip */
---
> u_int32_t ioaddr; /* physical port addr */
> u_int32_t altioaddr; /* physical alt port addr */
> u_int32_t bmaddr; /* physical bus master port */
> u_int32_t chiptype; /* pciid of controller chip */
> u_int32_t alignment; /* dma engine min alignment */
270,271c291
< struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
< int32_t mode[2]; /* transfer mode for devices */
---
> int mode[2]; /* transfer mode for devices */
284c304
< int32_t flags; /* controller flags */
---
> int flags; /* controller flags */
288a309
> #define ATA_QUEUED 0x10
290c311
< int32_t devices; /* what is present */
---
> int devices; /* what is present */
298c319
< int32_t active; /* active processing request */
---
> int active; /* active processing request */
318,322c339,343
< void ata_reset(struct ata_softc *, int32_t *);
< int32_t ata_reinit(struct ata_softc *);
< int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
< int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
< int ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
---
> void ata_reset(struct ata_softc *, int *);
> int ata_reinit(struct ata_softc *);
> int ata_wait(struct ata_softc *, int, u_int8_t);
> int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
> int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
325,326c346,347
< int8_t *ata_mode2str(int32_t);
< int8_t ata_pio2mode(int32_t);
---
> char *ata_mode2str(int);
> int ata_pio2mode(int);
331c352
< int32_t ata_find_dev(device_t, int32_t, int32_t);
---
> int ata_find_dev(device_t, u_int32_t, u_int32_t);
334,338c355,360
< void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
< int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
< void ata_dmastart(struct ata_softc *);
< int32_t ata_dmastatus(struct ata_softc *);
< int32_t ata_dmadone(struct ata_softc *);
---
> void *ata_dmaalloc(struct ata_softc *, int);
> void ata_dmainit(struct ata_softc *, int, int, int, int);
> int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
> void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
> int ata_dmastatus(struct ata_softc *);
> int ata_dmadone(struct ata_softc *);
< * $FreeBSD: head/sys/dev/ata/ata-all.h 64307 2000-08-06 19:51:58Z sos $
---
> * $FreeBSD: head/sys/dev/ata/ata-all.h 66070 2000-09-19 11:08:39Z sos $
60a61,63
> #define ATA_C_NOP 0x00 /* NOP command */
> #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
> #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
65a69
> #define ATA_C_SERVICE 0xa2 /* service command */
68a73
> #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
70a76
> #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
74d79
< #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
75a81,84
> #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
> #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
> #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
> #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89,90c98,99
< #define ATA_ALTPORT 0x206 /* alternate status register */
< #define ATA_ALTPORT_PCCARD 0x8 /* ditto on PCCARD devices */
---
> #define ATA_ALTSTAT 0x02 /* alternate status register */
> #define ATA_ALTCTRL 0X02 /* alternate device control */
95c104,105
< #define ATA_ALTIOSIZE 0x01
---
> #define ATA_ALTPORT 0x204 /* alternate registers offset */
> #define ATA_ALTIOSIZE 0x01 /* alternate registers size */
104c114
< #define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
---
> #define ATA_PARAM(scp, unit) (scp->dev_param[ATA_DEV(unit)])
106d115
<
159c168
< int16_t reserved2;
---
> u_int16_t reserved2;
161,162c170,171
< int16_t unfbytespertrk; /* # unformatted bytes/track */
< int16_t unfbytes; /* # unformatted bytes/sector */
---
> u_int16_t unfbytespertrk; /* # unformatted bytes/track */
> u_int16_t unfbytes; /* # unformatted bytes/sector */
164,166c173,175
< int16_t vendorunique0[3];
< int8_t serial[20]; /* serial number */
< int16_t buffertype; /* buffer type */
---
> u_int16_t vendorunique0[3];
> u_int8_t serial[20]; /* serial number */
> u_int16_t buffertype; /* buffer type */
171,177c180,186
< int16_t buffersize; /* buf size, 512-byte units */
< int16_t necc; /* ecc bytes appended */
< int8_t revision[8]; /* firmware revision */
< int8_t model[40]; /* model name */
< int8_t nsecperint; /* sectors per interrupt */
< int8_t vendorunique1;
< int16_t usedmovsd; /* double word read/write? */
---
> u_int16_t buffersize; /* buf size, 512-byte units */
> u_int16_t necc; /* ecc bytes appended */
> u_int8_t revision[8]; /* firmware revision */
> u_int8_t model[40]; /* model name */
> u_int8_t nsecperint; /* sectors per interrupt */
> u_int8_t vendorunique1;
> u_int16_t usedmovsd; /* double word read/write? */
186c195
< u_int8_t queuing :1; /* supports queuing overlap */
---
> u_int8_t queueing :1; /* supports queuing overlap */
188c197
< int16_t capvalidate; /* validation for above */
---
> u_int16_t capvalidate; /* validation for above */
190,193c199,202
< int8_t vendorunique3;
< int8_t opiomode; /* PIO modes 0-2 */
< int8_t vendorunique4;
< int8_t odmamode; /* old DMA modes, not ATA-3 */
---
> u_int8_t vendorunique3;
> u_int8_t opiomode; /* PIO modes 0-2 */
> u_int8_t vendorunique4;
> u_int8_t odmamode; /* old DMA modes, not ATA-3 */
195c204
< int16_t atavalid; /* fields valid */
---
> u_int16_t atavalid; /* fields valid */
200,207c209,216
< int16_t currcyls;
< int16_t currheads;
< int16_t currsectors;
< int16_t currsize0;
< int16_t currsize1;
< int8_t currmultsect;
< int8_t multsectvalid;
< int32_t lbasize;
---
> u_int16_t currcyls;
> u_int16_t currheads;
> u_int16_t currsectors;
> u_int16_t currsize0;
> u_int16_t currsize1;
> u_int8_t currmultsect;
> u_int8_t multsectvalid;
> u_int32_t lbasize;
209,211c218,220
< int16_t sdmamodes; /* singleword DMA modes */
< int16_t wdmamodes; /* multiword DMA modes */
< int16_t apiomodes; /* advanced PIO modes */
---
> u_int16_t sdmamodes; /* singleword DMA modes */
> u_int16_t wdmamodes; /* multiword DMA modes */
> u_int16_t apiomodes; /* advanced PIO modes */
218,219c227,228
< int16_t reserved69;
< int16_t reserved70;
---
> u_int16_t reserved69;
> u_int16_t reserved70;
222,241c231,261
< int16_t reserved73;
< int16_t reserved74;
< int16_t queuelen;
< int16_t reserved76;
< int16_t reserved77;
< int16_t reserved78;
< int16_t reserved79;
< int16_t versmajor;
< int16_t versminor;
< int16_t featsupp1;
< int16_t featsupp2;
< int16_t featsupp3;
< int16_t featenab1;
< int16_t featenab2;
< int16_t featenab3;
< int16_t udmamodes; /* UltraDMA modes */
< int16_t erasetime;
< int16_t enherasetime;
< int16_t apmlevel;
< int16_t masterpasswdrev;
---
> u_int16_t reserved73;
> u_int16_t reserved74;
> u_int16_t queuelen:5;
> u_int16_t :11;
> u_int16_t reserved76;
> u_int16_t reserved77;
> u_int16_t reserved78;
> u_int16_t reserved79;
> u_int16_t versmajor;
> u_int16_t versminor;
> u_int16_t featsupp1; /* 82 */
> u_int16_t supmicrocode:1;
> u_int16_t supqueued:1;
> u_int16_t supcfa:1;
> u_int16_t supapm:1;
> u_int16_t suprmsn:1;
> u_int16_t :11;
> u_int16_t featsupp3; /* 84 */
> u_int16_t featenab1; /* 85 */
> u_int16_t enabmicrocode:1;
> u_int16_t enabqueued:1;
> u_int16_t enabcfa:1;
> u_int16_t enabapm:1;
> u_int16_t enabrmsn:1;
> u_int16_t :11;
> u_int16_t featenab3; /* 87 */
> u_int16_t udmamodes; /* UltraDMA modes */
> u_int16_t erasetime;
> u_int16_t enherasetime;
> u_int16_t apmlevel;
> u_int16_t masterpasswdrev;
246,252c266,272
< int16_t reserved94[32];
< int16_t rmvstat;
< int16_t securstat;
< int16_t reserved129[30];
< int16_t cfapwrmode;
< int16_t reserved161[84];
< int16_t integrity;
---
> u_int16_t reserved94[32];
> u_int16_t rmvstat;
> u_int16_t securstat;
> u_int16_t reserved129[30];
> u_int16_t cfapwrmode;
> u_int16_t reserved161[84];
> u_int16_t integrity;
258c278
< int32_t unit; /* unit on this controller */
---
> int unit; /* unit on this controller */
264,267c284,288
< int32_t ioaddr; /* physical port addr */
< int32_t altioaddr; /* physical alt port addr */
< int32_t bmaddr; /* physical bus master port */
< int32_t chiptype; /* pciid of controller chip */
---
> u_int32_t ioaddr; /* physical port addr */
> u_int32_t altioaddr; /* physical alt port addr */
> u_int32_t bmaddr; /* physical bus master port */
> u_int32_t chiptype; /* pciid of controller chip */
> u_int32_t alignment; /* dma engine min alignment */
270,271c291
< struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
< int32_t mode[2]; /* transfer mode for devices */
---
> int mode[2]; /* transfer mode for devices */
284c304
< int32_t flags; /* controller flags */
---
> int flags; /* controller flags */
288a309
> #define ATA_QUEUED 0x10
290c311
< int32_t devices; /* what is present */
---
> int devices; /* what is present */
298c319
< int32_t active; /* active processing request */
---
> int active; /* active processing request */
318,322c339,343
< void ata_reset(struct ata_softc *, int32_t *);
< int32_t ata_reinit(struct ata_softc *);
< int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
< int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
< int ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
---
> void ata_reset(struct ata_softc *, int *);
> int ata_reinit(struct ata_softc *);
> int ata_wait(struct ata_softc *, int, u_int8_t);
> int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
> int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
325,326c346,347
< int8_t *ata_mode2str(int32_t);
< int8_t ata_pio2mode(int32_t);
---
> char *ata_mode2str(int);
> int ata_pio2mode(int);
331c352
< int32_t ata_find_dev(device_t, int32_t, int32_t);
---
> int ata_find_dev(device_t, u_int32_t, u_int32_t);
334,338c355,360
< void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
< int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
< void ata_dmastart(struct ata_softc *);
< int32_t ata_dmastatus(struct ata_softc *);
< int32_t ata_dmadone(struct ata_softc *);
---
> void *ata_dmaalloc(struct ata_softc *, int);
> void ata_dmainit(struct ata_softc *, int, int, int, int);
> int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
> void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
> int ata_dmastatus(struct ata_softc *);
> int ata_dmadone(struct ata_softc *);