1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
77#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
78#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
79#define ATA_C_SETFEATURES 0xef /* features command */
80#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
81#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
82#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
83#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
84#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
85#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
86#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
87#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
88#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89
90#define ATA_STATUS 0x07 /* status register */
91#define ATA_S_ERROR 0x01 /* error */
92#define ATA_S_INDEX 0x02 /* index */
93#define ATA_S_CORR 0x04 /* data corrected */
94#define ATA_S_DRQ 0x08 /* data request */
95#define ATA_S_DSC 0x10 /* drive seek completed */
96#define ATA_S_SERVICE 0x10 /* drive needs service */
97#define ATA_S_DWF 0x20 /* drive write fault */
98#define ATA_S_DMA 0x20 /* DMA ready */
99#define ATA_S_READY 0x40 /* drive ready */
100#define ATA_S_BUSY 0x80 /* busy */
101
102#define ATA_ALTSTAT 0x00 /* alternate status register */
103#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
104#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
105#define ATA_A_IDS 0x02 /* disable interrupts */
106#define ATA_A_RESET 0x04 /* RESET controller */
107#define ATA_A_4BIT 0x08 /* 4 head bits */
108
109/* misc defines */
110#define ATA_PRIMARY 0x1f0
111#define ATA_SECONDARY 0x170
112#define ATA_MASTER 0x00
113#define ATA_SLAVE 0x10
114#define ATA_IOSIZE 0x08
115#define ATA_ALTIOSIZE 0x01
116#define ATA_BMIOSIZE 0x08
117#define ATA_OP_FINISHED 0x00
118#define ATA_OP_CONTINUES 0x01
119#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
120#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
121
122#define ATA_IOADDR_RID 0
123#define ATA_ALTADDR_RID 1
124#define ATA_BMADDR_RID 2
125#define ATA_IRQ_RID 0
126
127/* busmaster DMA related defines */
128#define ATA_DMA_ENTRIES 256
129#define ATA_DMA_EOT 0x80000000
130
131#define ATA_BMCMD_PORT 0x00
132#define ATA_BMCMD_START_STOP 0x01
133#define ATA_BMCMD_WRITE_READ 0x08
134
135#define ATA_BMSTAT_PORT 0x02
136#define ATA_BMSTAT_ACTIVE 0x01
137#define ATA_BMSTAT_ERROR 0x02
138#define ATA_BMSTAT_INTERRUPT 0x04
139#define ATA_BMSTAT_MASK 0x07
140#define ATA_BMSTAT_DMA_MASTER 0x20
141#define ATA_BMSTAT_DMA_SLAVE 0x40
142#define ATA_BMSTAT_DMA_SIMPLEX 0x80
143
144#define ATA_BMDTP_PORT 0x04
145
146/* structure for holding DMA address data */
147struct ata_dmaentry {
148 u_int32_t base;
149 u_int32_t count;
150};
151
152/* structure describing an ATA device */
153struct ata_softc {
154 struct device *dev; /* device handle */
155 int channel; /* channel on this controller */
156 struct resource *r_io; /* io addr resource handle */
157 struct resource *r_altio; /* altio addr resource handle */
158 struct resource *r_bmio; /* bmio addr resource handle */
159 struct resource *r_irq; /* interrupt of this channel */
160 void *ih; /* interrupt handle */
161 int (*intr_func)(struct ata_softc *); /* interrupt function */
162 u_int32_t chiptype; /* pciid of controller chip */
163 u_int32_t alignment; /* dma engine min alignment */
164 char *dev_name[2]; /* name of device */
165 struct ata_params *dev_param[2]; /* ptr to devices params */
166 void *dev_softc[2]; /* ptr to devices softc's */
167 int mode[2]; /* transfer mode for devices */
168 int flags; /* controller flags */
169#define ATA_DMA_ACTIVE 0x01
170#define ATA_ATAPI_DMA_RO 0x02
171#define ATA_USE_16BIT 0x04
172#define ATA_NO_SLAVE 0x08
173#define ATA_QUEUED 0x10
174
175 int devices; /* what is present */
176#define ATA_ATA_MASTER 0x01
177#define ATA_ATA_SLAVE 0x02
178#define ATA_ATAPI_MASTER 0x04
179#define ATA_ATAPI_SLAVE 0x08
180
181 u_int8_t status; /* last controller status */
182 u_int8_t error; /* last controller error */
183 int active; /* active processing request */
184#define ATA_IDLE 0x0000
185#define ATA_IMMEDIATE 0x0001
186#define ATA_WAIT_INTR 0x0002
187#define ATA_WAIT_READY 0x0004
188#define ATA_ACTIVE 0x0008
189#define ATA_ACTIVE_ATA 0x0010
190#define ATA_ACTIVE_ATAPI 0x0020
191#define ATA_CONTROL 0x0040
192
193 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
194 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
195 void *running; /* currently running request */
196};
197
198/* externs */
199extern devclass_t ata_devclass;
200
201/* public prototypes */
202int ata_probe(device_t);
203int ata_attach(device_t);
204int ata_detach(device_t);
205int ata_resume(device_t);
206
207void ata_start(struct ata_softc *);
208void ata_reset(struct ata_softc *);
209int ata_reinit(struct ata_softc *);
210int ata_wait(struct ata_softc *, int, u_int8_t);
211int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
212int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
213void ata_set_name(struct ata_softc *, int, char *);
214void ata_free_name(struct ata_softc *, int);
215int ata_get_lun(u_int32_t *);
216int ata_test_lun(u_int32_t *, int);
217void ata_free_lun(u_int32_t *, int);
218char *ata_mode2str(int);
219int ata_pio2mode(int);
220int ata_pmode(struct ata_params *);
221int ata_wmode(struct ata_params *);
222int ata_umode(struct ata_params *);
223int ata_find_dev(device_t, u_int32_t, u_int32_t);
224
225void *ata_dmaalloc(struct ata_softc *, int);
226void ata_dmainit(struct ata_softc *, int, int, int, int);
227int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
228void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
229int ata_dmastatus(struct ata_softc *);
230int ata_dmadone(struct ata_softc *);
231
232/* macros to hide busspace uglyness */
233#define ATA_INB(res, offset) \
234 bus_space_read_1(rman_get_bustag((res)), \
235 rman_get_bushandle((res)), (offset))
236#define ATA_INW(res, offset) \
237 bus_space_read_2(rman_get_bustag((res)), \
238 rman_get_bushandle((res)), (offset))
239#define ATA_INL(res, offset) \
240 bus_space_read_4(rman_get_bustag((res)), \
241 rman_get_bushandle((res)), (offset))
242#define ATA_INSW(res, offset, addr, count) \
243 bus_space_read_multi_2(rman_get_bustag((res)), \
244 rman_get_bushandle((res)), \
245 (offset), (addr), (count))
246#define ATA_INSL(res, offset, addr, count) \
247 bus_space_read_multi_4(rman_get_bustag((res)), \
248 rman_get_bushandle((res)), \
249 (offset), (addr), (count))
250#define ATA_OUTB(res, offset, value) \
251 bus_space_write_1(rman_get_bustag((res)), \
252 rman_get_bushandle((res)), (offset), (value))
253#define ATA_OUTW(res, offset, value) \
254 bus_space_write_2(rman_get_bustag((res)), \
255 rman_get_bushandle((res)), (offset), (value))
256#define ATA_OUTL(res, offset, value) \
257 bus_space_write_4(rman_get_bustag((res)), \
258 rman_get_bushandle((res)), (offset), (value))
259#define ATA_OUTSW(res, offset, addr, count) \
260 bus_space_write_multi_2(rman_get_bustag((res)), \
261 rman_get_bushandle((res)), \
262 (offset), (addr), (count))
263#define ATA_OUTSL(res, offset, addr, count) \
264 bus_space_write_multi_4(rman_get_bustag((res)), \
265 rman_get_bushandle((res)), \
266 (offset), (addr), (count))
| 78#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
79#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
80#define ATA_C_SETFEATURES 0xef /* features command */
81#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
82#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
83#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
84#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
85#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
86#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
87#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
88#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
89#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
90
91#define ATA_STATUS 0x07 /* status register */
92#define ATA_S_ERROR 0x01 /* error */
93#define ATA_S_INDEX 0x02 /* index */
94#define ATA_S_CORR 0x04 /* data corrected */
95#define ATA_S_DRQ 0x08 /* data request */
96#define ATA_S_DSC 0x10 /* drive seek completed */
97#define ATA_S_SERVICE 0x10 /* drive needs service */
98#define ATA_S_DWF 0x20 /* drive write fault */
99#define ATA_S_DMA 0x20 /* DMA ready */
100#define ATA_S_READY 0x40 /* drive ready */
101#define ATA_S_BUSY 0x80 /* busy */
102
103#define ATA_ALTSTAT 0x00 /* alternate status register */
104#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
105#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
106#define ATA_A_IDS 0x02 /* disable interrupts */
107#define ATA_A_RESET 0x04 /* RESET controller */
108#define ATA_A_4BIT 0x08 /* 4 head bits */
109
110/* misc defines */
111#define ATA_PRIMARY 0x1f0
112#define ATA_SECONDARY 0x170
113#define ATA_MASTER 0x00
114#define ATA_SLAVE 0x10
115#define ATA_IOSIZE 0x08
116#define ATA_ALTIOSIZE 0x01
117#define ATA_BMIOSIZE 0x08
118#define ATA_OP_FINISHED 0x00
119#define ATA_OP_CONTINUES 0x01
120#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
121#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
122
123#define ATA_IOADDR_RID 0
124#define ATA_ALTADDR_RID 1
125#define ATA_BMADDR_RID 2
126#define ATA_IRQ_RID 0
127
128/* busmaster DMA related defines */
129#define ATA_DMA_ENTRIES 256
130#define ATA_DMA_EOT 0x80000000
131
132#define ATA_BMCMD_PORT 0x00
133#define ATA_BMCMD_START_STOP 0x01
134#define ATA_BMCMD_WRITE_READ 0x08
135
136#define ATA_BMSTAT_PORT 0x02
137#define ATA_BMSTAT_ACTIVE 0x01
138#define ATA_BMSTAT_ERROR 0x02
139#define ATA_BMSTAT_INTERRUPT 0x04
140#define ATA_BMSTAT_MASK 0x07
141#define ATA_BMSTAT_DMA_MASTER 0x20
142#define ATA_BMSTAT_DMA_SLAVE 0x40
143#define ATA_BMSTAT_DMA_SIMPLEX 0x80
144
145#define ATA_BMDTP_PORT 0x04
146
147/* structure for holding DMA address data */
148struct ata_dmaentry {
149 u_int32_t base;
150 u_int32_t count;
151};
152
153/* structure describing an ATA device */
154struct ata_softc {
155 struct device *dev; /* device handle */
156 int channel; /* channel on this controller */
157 struct resource *r_io; /* io addr resource handle */
158 struct resource *r_altio; /* altio addr resource handle */
159 struct resource *r_bmio; /* bmio addr resource handle */
160 struct resource *r_irq; /* interrupt of this channel */
161 void *ih; /* interrupt handle */
162 int (*intr_func)(struct ata_softc *); /* interrupt function */
163 u_int32_t chiptype; /* pciid of controller chip */
164 u_int32_t alignment; /* dma engine min alignment */
165 char *dev_name[2]; /* name of device */
166 struct ata_params *dev_param[2]; /* ptr to devices params */
167 void *dev_softc[2]; /* ptr to devices softc's */
168 int mode[2]; /* transfer mode for devices */
169 int flags; /* controller flags */
170#define ATA_DMA_ACTIVE 0x01
171#define ATA_ATAPI_DMA_RO 0x02
172#define ATA_USE_16BIT 0x04
173#define ATA_NO_SLAVE 0x08
174#define ATA_QUEUED 0x10
175
176 int devices; /* what is present */
177#define ATA_ATA_MASTER 0x01
178#define ATA_ATA_SLAVE 0x02
179#define ATA_ATAPI_MASTER 0x04
180#define ATA_ATAPI_SLAVE 0x08
181
182 u_int8_t status; /* last controller status */
183 u_int8_t error; /* last controller error */
184 int active; /* active processing request */
185#define ATA_IDLE 0x0000
186#define ATA_IMMEDIATE 0x0001
187#define ATA_WAIT_INTR 0x0002
188#define ATA_WAIT_READY 0x0004
189#define ATA_ACTIVE 0x0008
190#define ATA_ACTIVE_ATA 0x0010
191#define ATA_ACTIVE_ATAPI 0x0020
192#define ATA_CONTROL 0x0040
193
194 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
195 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
196 void *running; /* currently running request */
197};
198
199/* externs */
200extern devclass_t ata_devclass;
201
202/* public prototypes */
203int ata_probe(device_t);
204int ata_attach(device_t);
205int ata_detach(device_t);
206int ata_resume(device_t);
207
208void ata_start(struct ata_softc *);
209void ata_reset(struct ata_softc *);
210int ata_reinit(struct ata_softc *);
211int ata_wait(struct ata_softc *, int, u_int8_t);
212int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
213int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
214void ata_set_name(struct ata_softc *, int, char *);
215void ata_free_name(struct ata_softc *, int);
216int ata_get_lun(u_int32_t *);
217int ata_test_lun(u_int32_t *, int);
218void ata_free_lun(u_int32_t *, int);
219char *ata_mode2str(int);
220int ata_pio2mode(int);
221int ata_pmode(struct ata_params *);
222int ata_wmode(struct ata_params *);
223int ata_umode(struct ata_params *);
224int ata_find_dev(device_t, u_int32_t, u_int32_t);
225
226void *ata_dmaalloc(struct ata_softc *, int);
227void ata_dmainit(struct ata_softc *, int, int, int, int);
228int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
229void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
230int ata_dmastatus(struct ata_softc *);
231int ata_dmadone(struct ata_softc *);
232
233/* macros to hide busspace uglyness */
234#define ATA_INB(res, offset) \
235 bus_space_read_1(rman_get_bustag((res)), \
236 rman_get_bushandle((res)), (offset))
237#define ATA_INW(res, offset) \
238 bus_space_read_2(rman_get_bustag((res)), \
239 rman_get_bushandle((res)), (offset))
240#define ATA_INL(res, offset) \
241 bus_space_read_4(rman_get_bustag((res)), \
242 rman_get_bushandle((res)), (offset))
243#define ATA_INSW(res, offset, addr, count) \
244 bus_space_read_multi_2(rman_get_bustag((res)), \
245 rman_get_bushandle((res)), \
246 (offset), (addr), (count))
247#define ATA_INSL(res, offset, addr, count) \
248 bus_space_read_multi_4(rman_get_bustag((res)), \
249 rman_get_bushandle((res)), \
250 (offset), (addr), (count))
251#define ATA_OUTB(res, offset, value) \
252 bus_space_write_1(rman_get_bustag((res)), \
253 rman_get_bushandle((res)), (offset), (value))
254#define ATA_OUTW(res, offset, value) \
255 bus_space_write_2(rman_get_bustag((res)), \
256 rman_get_bushandle((res)), (offset), (value))
257#define ATA_OUTL(res, offset, value) \
258 bus_space_write_4(rman_get_bustag((res)), \
259 rman_get_bushandle((res)), (offset), (value))
260#define ATA_OUTSW(res, offset, addr, count) \
261 bus_space_write_multi_2(rman_get_bustag((res)), \
262 rman_get_bushandle((res)), \
263 (offset), (addr), (count))
264#define ATA_OUTSL(res, offset, addr, count) \
265 bus_space_write_multi_4(rman_get_bustag((res)), \
266 rman_get_bushandle((res)), \
267 (offset), (addr), (count))
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