1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 74250 2001-03-14 12:05:44Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 74302 2001-03-15 15:36:25Z sos $
|
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_NOP 0x00 /* NOP command */
62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
65#define ATA_C_READ 0x20 /* read command */
66#define ATA_C_WRITE 0x30 /* write command */
67#define ATA_C_PACKET_CMD 0xa0 /* packet command */
68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
69#define ATA_C_SERVICE 0xa2 /* service command */
70#define ATA_C_READ_MUL 0xc4 /* read multi command */
71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
77#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
78#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
79#define ATA_C_SETFEATURES 0xef /* features command */
80#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
81#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
82#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
83#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
84#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
85#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
86#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
87#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
88#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89
90#define ATA_STATUS 0x07 /* status register */
91#define ATA_S_ERROR 0x01 /* error */
92#define ATA_S_INDEX 0x02 /* index */
93#define ATA_S_CORR 0x04 /* data corrected */
94#define ATA_S_DRQ 0x08 /* data request */
95#define ATA_S_DSC 0x10 /* drive seek completed */
96#define ATA_S_SERVICE 0x10 /* drive needs service */
97#define ATA_S_DWF 0x20 /* drive write fault */
98#define ATA_S_DMA 0x20 /* DMA ready */
99#define ATA_S_READY 0x40 /* drive ready */
100#define ATA_S_BUSY 0x80 /* busy */
101
102#define ATA_ALTSTAT 0x00 /* alternate status register */
103#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
104#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
105#define ATA_A_IDS 0x02 /* disable interrupts */
106#define ATA_A_RESET 0x04 /* RESET controller */
107#define ATA_A_4BIT 0x08 /* 4 head bits */
108
109/* misc defines */
110#define ATA_PRIMARY 0x1f0
111#define ATA_SECONDARY 0x170
112#define ATA_MASTER 0x00
113#define ATA_SLAVE 0x10
114#define ATA_IOSIZE 0x08
115#define ATA_ALTIOSIZE 0x01
116#define ATA_BMIOSIZE 0x08
117#define ATA_OP_FINISHED 0x00
118#define ATA_OP_CONTINUES 0x01
119#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
120#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
121
122#define ATA_IOADDR_RID 0
123#define ATA_ALTADDR_RID 1
124#define ATA_BMADDR_RID 2
125#define ATA_IRQ_RID 0
126
127/* busmaster DMA related defines */
128#define ATA_DMA_ENTRIES 256
129#define ATA_DMA_EOT 0x80000000
130
131#define ATA_BMCMD_PORT 0x00
132#define ATA_BMCMD_START_STOP 0x01
133#define ATA_BMCMD_WRITE_READ 0x08
134
135#define ATA_BMSTAT_PORT 0x02
136#define ATA_BMSTAT_ACTIVE 0x01
137#define ATA_BMSTAT_ERROR 0x02
138#define ATA_BMSTAT_INTERRUPT 0x04
139#define ATA_BMSTAT_MASK 0x07
140#define ATA_BMSTAT_DMA_MASTER 0x20
141#define ATA_BMSTAT_DMA_SLAVE 0x40
142#define ATA_BMSTAT_DMA_SIMPLEX 0x80
143
144#define ATA_BMDTP_PORT 0x04
145
146/* structure for holding DMA address data */
147struct ata_dmaentry {
148 u_int32_t base;
149 u_int32_t count;
150};
151
| 29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_NOP 0x00 /* NOP command */
62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
65#define ATA_C_READ 0x20 /* read command */
66#define ATA_C_WRITE 0x30 /* write command */
67#define ATA_C_PACKET_CMD 0xa0 /* packet command */
68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
69#define ATA_C_SERVICE 0xa2 /* service command */
70#define ATA_C_READ_MUL 0xc4 /* read multi command */
71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
77#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
78#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
79#define ATA_C_SETFEATURES 0xef /* features command */
80#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
81#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
82#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
83#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
84#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
85#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
86#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
87#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
88#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89
90#define ATA_STATUS 0x07 /* status register */
91#define ATA_S_ERROR 0x01 /* error */
92#define ATA_S_INDEX 0x02 /* index */
93#define ATA_S_CORR 0x04 /* data corrected */
94#define ATA_S_DRQ 0x08 /* data request */
95#define ATA_S_DSC 0x10 /* drive seek completed */
96#define ATA_S_SERVICE 0x10 /* drive needs service */
97#define ATA_S_DWF 0x20 /* drive write fault */
98#define ATA_S_DMA 0x20 /* DMA ready */
99#define ATA_S_READY 0x40 /* drive ready */
100#define ATA_S_BUSY 0x80 /* busy */
101
102#define ATA_ALTSTAT 0x00 /* alternate status register */
103#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
104#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
105#define ATA_A_IDS 0x02 /* disable interrupts */
106#define ATA_A_RESET 0x04 /* RESET controller */
107#define ATA_A_4BIT 0x08 /* 4 head bits */
108
109/* misc defines */
110#define ATA_PRIMARY 0x1f0
111#define ATA_SECONDARY 0x170
112#define ATA_MASTER 0x00
113#define ATA_SLAVE 0x10
114#define ATA_IOSIZE 0x08
115#define ATA_ALTIOSIZE 0x01
116#define ATA_BMIOSIZE 0x08
117#define ATA_OP_FINISHED 0x00
118#define ATA_OP_CONTINUES 0x01
119#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
120#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
121
122#define ATA_IOADDR_RID 0
123#define ATA_ALTADDR_RID 1
124#define ATA_BMADDR_RID 2
125#define ATA_IRQ_RID 0
126
127/* busmaster DMA related defines */
128#define ATA_DMA_ENTRIES 256
129#define ATA_DMA_EOT 0x80000000
130
131#define ATA_BMCMD_PORT 0x00
132#define ATA_BMCMD_START_STOP 0x01
133#define ATA_BMCMD_WRITE_READ 0x08
134
135#define ATA_BMSTAT_PORT 0x02
136#define ATA_BMSTAT_ACTIVE 0x01
137#define ATA_BMSTAT_ERROR 0x02
138#define ATA_BMSTAT_INTERRUPT 0x04
139#define ATA_BMSTAT_MASK 0x07
140#define ATA_BMSTAT_DMA_MASTER 0x20
141#define ATA_BMSTAT_DMA_SLAVE 0x40
142#define ATA_BMSTAT_DMA_SIMPLEX 0x80
143
144#define ATA_BMDTP_PORT 0x04
145
146/* structure for holding DMA address data */
147struct ata_dmaentry {
148 u_int32_t base;
149 u_int32_t count;
150};
151
|
152/* ATA/ATAPI device parameter information */
153struct ata_params {
154 u_int8_t cmdsize :2; /* packet command size */
155#define ATAPI_PSIZE_12 0 /* 12 bytes */
156#define ATAPI_PSIZE_16 1 /* 16 bytes */
157
158 u_int8_t :3;
159 u_int8_t drqtype :2; /* DRQ type */
160#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
161#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
162#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
163
164 u_int8_t removable :1; /* device is removable */
165 u_int8_t device_type :5; /* device type */
166#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
167#define ATAPI_TYPE_TAPE 1 /* streaming tape */
168#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
169#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
170
171 u_int8_t :1;
172 u_int8_t proto :2; /* command protocol */
173#define ATAPI_PROTO_ATAPI 2
174
175 u_int16_t cylinders; /* number of cylinders */
176 u_int16_t reserved2;
177 u_int16_t heads; /* # heads */
178 u_int16_t unfbytespertrk; /* # unformatted bytes/track */
179 u_int16_t unfbytes; /* # unformatted bytes/sector */
180 u_int16_t sectors; /* # sectors/track */
181 u_int16_t vendorunique0[3];
182 u_int8_t serial[20]; /* serial number */
183 u_int16_t buffertype; /* buffer type */
184#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
185#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
186#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
187
188 u_int16_t buffersize; /* buf size, 512-byte units */
189 u_int16_t necc; /* ecc bytes appended */
190 u_int8_t revision[8]; /* firmware revision */
191 u_int8_t model[40]; /* model name */
192 u_int8_t nsecperint; /* sectors per interrupt */
193 u_int8_t vendorunique1;
194 u_int16_t usedmovsd; /* double word read/write? */
195
196 u_int8_t vendorcap; /* vendor capabilities */
197 u_int8_t dmaflag :1; /* DMA supported - always 1 */
198 u_int8_t lbaflag :1; /* LBA supported - always 1 */
199 u_int8_t iordydis :1; /* IORDY may be disabled */
200 u_int8_t iordyflag :1; /* IORDY supported */
201 u_int8_t softreset :1; /* needs softreset when busy */
202 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
203 u_int8_t queueing :1; /* supports queuing overlap */
204 u_int8_t idmaflag :1; /* interleaved DMA supported */
205 u_int16_t capvalidate; /* validation for above */
206
207 u_int8_t vendorunique3;
208 u_int8_t opiomode; /* PIO modes 0-2 */
209 u_int8_t vendorunique4;
210 u_int8_t odmamode; /* old DMA modes, not ATA-3 */
211
212 u_int16_t atavalid; /* fields valid */
213#define ATA_FLAG_54_58 1 /* words 54-58 valid */
214#define ATA_FLAG_64_70 2 /* words 64-70 valid */
215#define ATA_FLAG_88 4 /* word 88 valid */
216
217 u_int16_t currcyls;
218 u_int16_t currheads;
219 u_int16_t currsectors;
220 u_int16_t currsize0;
221 u_int16_t currsize1;
222 u_int8_t currmultsect;
223 u_int8_t multsectvalid;
224 u_int32_t lbasize;
225
226 u_int16_t sdmamodes; /* singleword DMA modes */
227 u_int16_t wdmamodes; /* multiword DMA modes */
228 u_int16_t apiomodes; /* advanced PIO modes */
229
230 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
231 u_int16_t mwdmarec; /* rec. M/W DMA time ns */
232 u_int16_t pioblind; /* min. PIO cycle w/o flow */
233 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
234
235 u_int16_t reserved69;
236 u_int16_t reserved70;
237 u_int16_t rlsovlap; /* rel time (us) for overlap */
238 u_int16_t rlsservice; /* rel time (us) for service */
239 u_int16_t reserved73;
240 u_int16_t reserved74;
241 u_int16_t queuelen:5;
242 u_int16_t :11;
243 u_int16_t reserved76;
244 u_int16_t reserved77;
245 u_int16_t reserved78;
246 u_int16_t reserved79;
247 u_int16_t versmajor;
248 u_int16_t versminor;
249 u_int16_t featsupp1; /* 82 */
250 u_int16_t supmicrocode:1;
251 u_int16_t supqueued:1;
252 u_int16_t supcfa:1;
253 u_int16_t supapm:1;
254 u_int16_t suprmsn:1;
255 u_int16_t :11;
256 u_int16_t featsupp3; /* 84 */
257 u_int16_t featenab1; /* 85 */
258 u_int16_t enabmicrocode:1;
259 u_int16_t enabqueued:1;
260 u_int16_t enabcfa:1;
261 u_int16_t enabapm:1;
262 u_int16_t enabrmsn:1;
263 u_int16_t :11;
264 u_int16_t featenab3; /* 87 */
265 u_int16_t udmamodes; /* UltraDMA modes */
266 u_int16_t erasetime;
267 u_int16_t enherasetime;
268 u_int16_t apmlevel;
269 u_int16_t masterpasswdrev;
270 u_int16_t masterhwres :8;
271 u_int16_t slavehwres :5;
272 u_int16_t cblid :1;
273 u_int16_t reserved93_1415 :2;
274 u_int16_t reserved94[32];
275 u_int16_t rmvstat;
276 u_int16_t securstat;
277 u_int16_t reserved129[30];
278 u_int16_t cfapwrmode;
279 u_int16_t reserved161[84];
280 u_int16_t integrity;
281};
282
| |
283/* structure describing an ATA device */
284struct ata_softc {
285 struct device *dev; /* device handle */
286 int channel; /* channel on this controller */
287 struct resource *r_io; /* io addr resource handle */
288 struct resource *r_altio; /* altio addr resource handle */
289 struct resource *r_bmio; /* bmio addr resource handle */
290 struct resource *r_irq; /* interrupt of this channel */
291 void *ih; /* interrupt handle */
292 int (*intr_func)(struct ata_softc *); /* interrupt function */
293 u_int32_t chiptype; /* pciid of controller chip */
294 u_int32_t alignment; /* dma engine min alignment */
| 152/* structure describing an ATA device */
153struct ata_softc {
154 struct device *dev; /* device handle */
155 int channel; /* channel on this controller */
156 struct resource *r_io; /* io addr resource handle */
157 struct resource *r_altio; /* altio addr resource handle */
158 struct resource *r_bmio; /* bmio addr resource handle */
159 struct resource *r_irq; /* interrupt of this channel */
160 void *ih; /* interrupt handle */
161 int (*intr_func)(struct ata_softc *); /* interrupt function */
162 u_int32_t chiptype; /* pciid of controller chip */
163 u_int32_t alignment; /* dma engine min alignment */
|
| 164 char *dev_name[2]; /* name of device */
|
295 struct ata_params *dev_param[2]; /* ptr to devices params */
296 void *dev_softc[2]; /* ptr to devices softc's */
297 int mode[2]; /* transfer mode for devices */
| 165 struct ata_params *dev_param[2]; /* ptr to devices params */
166 void *dev_softc[2]; /* ptr to devices softc's */
167 int mode[2]; /* transfer mode for devices */
|
298#define ATA_PIO 0x00
299#define ATA_PIO0 0x08
300#define ATA_PIO1 0x09
301#define ATA_PIO2 0x0a
302#define ATA_PIO3 0x0b
303#define ATA_PIO4 0x0c
304#define ATA_DMA 0x10
305#define ATA_WDMA2 0x22
306#define ATA_UDMA2 0x42
307#define ATA_UDMA4 0x44
308#define ATA_UDMA5 0x45
309
| |
310 int flags; /* controller flags */
311#define ATA_DMA_ACTIVE 0x01
312#define ATA_ATAPI_DMA_RO 0x02
313#define ATA_USE_16BIT 0x04
314#define ATA_NO_SLAVE 0x08
315#define ATA_QUEUED 0x10
316
317 int devices; /* what is present */
318#define ATA_ATA_MASTER 0x01
319#define ATA_ATA_SLAVE 0x02
320#define ATA_ATAPI_MASTER 0x04
321#define ATA_ATAPI_SLAVE 0x08
322
323 u_int8_t status; /* last controller status */
324 u_int8_t error; /* last controller error */
325 int active; /* active processing request */
326#define ATA_IDLE 0x0000
327#define ATA_IMMEDIATE 0x0001
328#define ATA_WAIT_INTR 0x0002
329#define ATA_WAIT_READY 0x0004
330#define ATA_ACTIVE 0x0008
331#define ATA_ACTIVE_ATA 0x0010
332#define ATA_ACTIVE_ATAPI 0x0020
333#define ATA_REINITING 0x0040
334
335 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
336 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
337 void *running; /* currently running request */
338};
339
340/* externs */
341extern devclass_t ata_devclass;
342
343/* public prototypes */
344int ata_probe(device_t);
345int ata_attach(device_t);
346int ata_detach(device_t);
347int ata_resume(device_t);
348
349void ata_start(struct ata_softc *);
350void ata_reset(struct ata_softc *);
351int ata_reinit(struct ata_softc *);
352int ata_wait(struct ata_softc *, int, u_int8_t);
353int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
354int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
| 168 int flags; /* controller flags */
169#define ATA_DMA_ACTIVE 0x01
170#define ATA_ATAPI_DMA_RO 0x02
171#define ATA_USE_16BIT 0x04
172#define ATA_NO_SLAVE 0x08
173#define ATA_QUEUED 0x10
174
175 int devices; /* what is present */
176#define ATA_ATA_MASTER 0x01
177#define ATA_ATA_SLAVE 0x02
178#define ATA_ATAPI_MASTER 0x04
179#define ATA_ATAPI_SLAVE 0x08
180
181 u_int8_t status; /* last controller status */
182 u_int8_t error; /* last controller error */
183 int active; /* active processing request */
184#define ATA_IDLE 0x0000
185#define ATA_IMMEDIATE 0x0001
186#define ATA_WAIT_INTR 0x0002
187#define ATA_WAIT_READY 0x0004
188#define ATA_ACTIVE 0x0008
189#define ATA_ACTIVE_ATA 0x0010
190#define ATA_ACTIVE_ATAPI 0x0020
191#define ATA_REINITING 0x0040
192
193 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
194 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
195 void *running; /* currently running request */
196};
197
198/* externs */
199extern devclass_t ata_devclass;
200
201/* public prototypes */
202int ata_probe(device_t);
203int ata_attach(device_t);
204int ata_detach(device_t);
205int ata_resume(device_t);
206
207void ata_start(struct ata_softc *);
208void ata_reset(struct ata_softc *);
209int ata_reinit(struct ata_softc *);
210int ata_wait(struct ata_softc *, int, u_int8_t);
211int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
212int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
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| 213void ata_set_name(struct ata_softc *, int, char *);
214void ata_free_name(struct ata_softc *, int);
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355int ata_get_lun(u_int32_t *);
356int ata_test_lun(u_int32_t *, int);
357void ata_free_lun(u_int32_t *, int);
358char *ata_mode2str(int);
359int ata_pio2mode(int);
360int ata_pmode(struct ata_params *);
361int ata_wmode(struct ata_params *);
362int ata_umode(struct ata_params *);
363int ata_find_dev(device_t, u_int32_t, u_int32_t);
364
365void *ata_dmaalloc(struct ata_softc *, int);
366void ata_dmainit(struct ata_softc *, int, int, int, int);
367int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
368void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
369int ata_dmastatus(struct ata_softc *);
370int ata_dmadone(struct ata_softc *);
371
372/* macros to hide busspace uglyness */
373#define ATA_INB(res, offset) \
374 bus_space_read_1(rman_get_bustag((res)), \
375 rman_get_bushandle((res)), (offset))
376#define ATA_INW(res, offset) \
377 bus_space_read_2(rman_get_bustag((res)), \
378 rman_get_bushandle((res)), (offset))
379#define ATA_INL(res, offset) \
380 bus_space_read_4(rman_get_bustag((res)), \
381 rman_get_bushandle((res)), (offset))
382#define ATA_INSW(res, offset, addr, count) \
383 bus_space_read_multi_2(rman_get_bustag((res)), \
384 rman_get_bushandle((res)), \
385 (offset), (addr), (count))
386#define ATA_INSL(res, offset, addr, count) \
387 bus_space_read_multi_4(rman_get_bustag((res)), \
388 rman_get_bushandle((res)), \
389 (offset), (addr), (count))
390#define ATA_OUTB(res, offset, value) \
391 bus_space_write_1(rman_get_bustag((res)), \
392 rman_get_bushandle((res)), (offset), (value))
393#define ATA_OUTW(res, offset, value) \
394 bus_space_write_2(rman_get_bustag((res)), \
395 rman_get_bushandle((res)), (offset), (value))
396#define ATA_OUTL(res, offset, value) \
397 bus_space_write_4(rman_get_bustag((res)), \
398 rman_get_bushandle((res)), (offset), (value))
399#define ATA_OUTSW(res, offset, addr, count) \
400 bus_space_write_multi_2(rman_get_bustag((res)), \
401 rman_get_bushandle((res)), \
402 (offset), (addr), (count))
403#define ATA_OUTSL(res, offset, addr, count) \
404 bus_space_write_multi_4(rman_get_bustag((res)), \
405 rman_get_bushandle((res)), \
406 (offset), (addr), (count))
| 215int ata_get_lun(u_int32_t *);
216int ata_test_lun(u_int32_t *, int);
217void ata_free_lun(u_int32_t *, int);
218char *ata_mode2str(int);
219int ata_pio2mode(int);
220int ata_pmode(struct ata_params *);
221int ata_wmode(struct ata_params *);
222int ata_umode(struct ata_params *);
223int ata_find_dev(device_t, u_int32_t, u_int32_t);
224
225void *ata_dmaalloc(struct ata_softc *, int);
226void ata_dmainit(struct ata_softc *, int, int, int, int);
227int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
228void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
229int ata_dmastatus(struct ata_softc *);
230int ata_dmadone(struct ata_softc *);
231
232/* macros to hide busspace uglyness */
233#define ATA_INB(res, offset) \
234 bus_space_read_1(rman_get_bustag((res)), \
235 rman_get_bushandle((res)), (offset))
236#define ATA_INW(res, offset) \
237 bus_space_read_2(rman_get_bustag((res)), \
238 rman_get_bushandle((res)), (offset))
239#define ATA_INL(res, offset) \
240 bus_space_read_4(rman_get_bustag((res)), \
241 rman_get_bushandle((res)), (offset))
242#define ATA_INSW(res, offset, addr, count) \
243 bus_space_read_multi_2(rman_get_bustag((res)), \
244 rman_get_bushandle((res)), \
245 (offset), (addr), (count))
246#define ATA_INSL(res, offset, addr, count) \
247 bus_space_read_multi_4(rman_get_bustag((res)), \
248 rman_get_bushandle((res)), \
249 (offset), (addr), (count))
250#define ATA_OUTB(res, offset, value) \
251 bus_space_write_1(rman_get_bustag((res)), \
252 rman_get_bushandle((res)), (offset), (value))
253#define ATA_OUTW(res, offset, value) \
254 bus_space_write_2(rman_get_bustag((res)), \
255 rman_get_bushandle((res)), (offset), (value))
256#define ATA_OUTL(res, offset, value) \
257 bus_space_write_4(rman_get_bustag((res)), \
258 rman_get_bushandle((res)), (offset), (value))
259#define ATA_OUTSW(res, offset, addr, count) \
260 bus_space_write_multi_2(rman_get_bustag((res)), \
261 rman_get_bushandle((res)), \
262 (offset), (addr), (count))
263#define ATA_OUTSL(res, offset, addr, count) \
264 bus_space_write_multi_4(rman_get_bustag((res)), \
265 rman_get_bushandle((res)), \
266 (offset), (addr), (count))
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