1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999,2000 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 66326 2000-09-24 18:19:43Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 67058 2000-10-13 11:21:27Z sos $
|
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_NOP 0x00 /* NOP command */
62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
65#define ATA_C_READ 0x20 /* read command */
66#define ATA_C_WRITE 0x30 /* write command */
67#define ATA_C_PACKET_CMD 0xa0 /* packet command */
68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
69#define ATA_C_SERVICE 0xa2 /* service command */
70#define ATA_C_READ_MUL 0xc4 /* read multi command */
71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
77#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
78#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
79#define ATA_C_SETFEATURES 0xef /* features command */
80#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
81#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
82#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
83#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
84#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
85#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
86#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
87#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
88#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89
90#define ATA_STATUS 0x07 /* status register */
91#define ATA_S_ERROR 0x01 /* error */
92#define ATA_S_INDEX 0x02 /* index */
93#define ATA_S_CORR 0x04 /* data corrected */
94#define ATA_S_DRQ 0x08 /* data request */
95#define ATA_S_DSC 0x10 /* drive seek completed */
96#define ATA_S_SERVICE 0x10 /* drive needs service */
97#define ATA_S_DWF 0x20 /* drive write fault */
98#define ATA_S_DMA 0x20 /* DMA ready */
99#define ATA_S_READY 0x40 /* drive ready */
100#define ATA_S_BUSY 0x80 /* busy */
101
102#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
103#define ATA_ALTIOSIZE 0x01 /* alternate registers size */
104#define ATA_A_IDS 0x02 /* disable interrupts */
105#define ATA_A_RESET 0x04 /* RESET controller */
106#define ATA_A_4BIT 0x08 /* 4 head bits */
107
108/* misc defines */
109#define ATA_MASTER 0x00
110#define ATA_SLAVE 0x10
111#define ATA_IOSIZE 0x08
112#define ATA_OP_FINISHED 0x00
113#define ATA_OP_CONTINUES 0x01
| 29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
34#define ATA_E_NM 0x02 /* no media */
35#define ATA_E_ABORT 0x04 /* command aborted */
36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_NOP 0x00 /* NOP command */
62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
65#define ATA_C_READ 0x20 /* read command */
66#define ATA_C_WRITE 0x30 /* write command */
67#define ATA_C_PACKET_CMD 0xa0 /* packet command */
68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
69#define ATA_C_SERVICE 0xa2 /* service command */
70#define ATA_C_READ_MUL 0xc4 /* read multi command */
71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
77#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
78#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
79#define ATA_C_SETFEATURES 0xef /* features command */
80#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
81#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
82#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
83#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
84#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
85#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
86#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
87#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
88#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
89
90#define ATA_STATUS 0x07 /* status register */
91#define ATA_S_ERROR 0x01 /* error */
92#define ATA_S_INDEX 0x02 /* index */
93#define ATA_S_CORR 0x04 /* data corrected */
94#define ATA_S_DRQ 0x08 /* data request */
95#define ATA_S_DSC 0x10 /* drive seek completed */
96#define ATA_S_SERVICE 0x10 /* drive needs service */
97#define ATA_S_DWF 0x20 /* drive write fault */
98#define ATA_S_DMA 0x20 /* DMA ready */
99#define ATA_S_READY 0x40 /* drive ready */
100#define ATA_S_BUSY 0x80 /* busy */
101
102#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
103#define ATA_ALTIOSIZE 0x01 /* alternate registers size */
104#define ATA_A_IDS 0x02 /* disable interrupts */
105#define ATA_A_RESET 0x04 /* RESET controller */
106#define ATA_A_4BIT 0x08 /* 4 head bits */
107
108/* misc defines */
109#define ATA_MASTER 0x00
110#define ATA_SLAVE 0x10
111#define ATA_IOSIZE 0x08
112#define ATA_OP_FINISHED 0x00
113#define ATA_OP_CONTINUES 0x01
|
114#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
115#define ATA_PARAM(scp, unit) (scp->dev_param[ATA_DEV(unit)])
| 114#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
115#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
|
116
117/* busmaster DMA related defines */
118#define ATA_BM_OFFSET1 0x08
119#define ATA_DMA_ENTRIES 256
120#define ATA_DMA_EOT 0x80000000
121
122#define ATA_BMCMD_PORT 0x00
123#define ATA_BMCMD_START_STOP 0x01
124#define ATA_BMCMD_WRITE_READ 0x08
125
126#define ATA_BMSTAT_PORT 0x02
127#define ATA_BMSTAT_ACTIVE 0x01
128#define ATA_BMSTAT_ERROR 0x02
129#define ATA_BMSTAT_INTERRUPT 0x04
130#define ATA_BMSTAT_MASK 0x07
131#define ATA_BMSTAT_DMA_MASTER 0x20
132#define ATA_BMSTAT_DMA_SLAVE 0x40
133#define ATA_BMSTAT_DMA_SIMPLEX 0x80
134
135#define ATA_BMDTP_PORT 0x04
136
137#define ATA_BMIOSIZE 0x20
138
139/* structure for holding DMA address data */
140struct ata_dmaentry {
141 u_int32_t base;
142 u_int32_t count;
143};
144
145/* ATA/ATAPI device parameter information */
146struct ata_params {
147 u_int8_t cmdsize :2; /* packet command size */
148#define ATAPI_PSIZE_12 0 /* 12 bytes */
149#define ATAPI_PSIZE_16 1 /* 16 bytes */
150
151 u_int8_t :3;
152 u_int8_t drqtype :2; /* DRQ type */
153#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
154#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
155#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
156
157 u_int8_t removable :1; /* device is removable */
158 u_int8_t device_type :5; /* device type */
159#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
160#define ATAPI_TYPE_TAPE 1 /* streaming tape */
161#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
162#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
163
164 u_int8_t :1;
165 u_int8_t proto :2; /* command protocol */
166#define ATAPI_PROTO_ATAPI 2
167
168 u_int16_t cylinders; /* number of cylinders */
169 u_int16_t reserved2;
170 u_int16_t heads; /* # heads */
171 u_int16_t unfbytespertrk; /* # unformatted bytes/track */
172 u_int16_t unfbytes; /* # unformatted bytes/sector */
173 u_int16_t sectors; /* # sectors/track */
174 u_int16_t vendorunique0[3];
175 u_int8_t serial[20]; /* serial number */
176 u_int16_t buffertype; /* buffer type */
177#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
178#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
179#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
180
181 u_int16_t buffersize; /* buf size, 512-byte units */
182 u_int16_t necc; /* ecc bytes appended */
183 u_int8_t revision[8]; /* firmware revision */
184 u_int8_t model[40]; /* model name */
185 u_int8_t nsecperint; /* sectors per interrupt */
186 u_int8_t vendorunique1;
187 u_int16_t usedmovsd; /* double word read/write? */
188
189 u_int8_t vendorcap; /* vendor capabilities */
190 u_int8_t dmaflag :1; /* DMA supported - always 1 */
191 u_int8_t lbaflag :1; /* LBA supported - always 1 */
192 u_int8_t iordydis :1; /* IORDY may be disabled */
193 u_int8_t iordyflag :1; /* IORDY supported */
194 u_int8_t softreset :1; /* needs softreset when busy */
195 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
196 u_int8_t queueing :1; /* supports queuing overlap */
197 u_int8_t idmaflag :1; /* interleaved DMA supported */
198 u_int16_t capvalidate; /* validation for above */
199
200 u_int8_t vendorunique3;
201 u_int8_t opiomode; /* PIO modes 0-2 */
202 u_int8_t vendorunique4;
203 u_int8_t odmamode; /* old DMA modes, not ATA-3 */
204
205 u_int16_t atavalid; /* fields valid */
206#define ATA_FLAG_54_58 1 /* words 54-58 valid */
207#define ATA_FLAG_64_70 2 /* words 64-70 valid */
208#define ATA_FLAG_88 4 /* word 88 valid */
209
210 u_int16_t currcyls;
211 u_int16_t currheads;
212 u_int16_t currsectors;
213 u_int16_t currsize0;
214 u_int16_t currsize1;
215 u_int8_t currmultsect;
216 u_int8_t multsectvalid;
217 u_int32_t lbasize;
218
219 u_int16_t sdmamodes; /* singleword DMA modes */
220 u_int16_t wdmamodes; /* multiword DMA modes */
221 u_int16_t apiomodes; /* advanced PIO modes */
222
223 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
224 u_int16_t mwdmarec; /* rec. M/W DMA time ns */
225 u_int16_t pioblind; /* min. PIO cycle w/o flow */
226 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
227
228 u_int16_t reserved69;
229 u_int16_t reserved70;
230 u_int16_t rlsovlap; /* rel time (us) for overlap */
231 u_int16_t rlsservice; /* rel time (us) for service */
232 u_int16_t reserved73;
233 u_int16_t reserved74;
234 u_int16_t queuelen:5;
235 u_int16_t :11;
236 u_int16_t reserved76;
237 u_int16_t reserved77;
238 u_int16_t reserved78;
239 u_int16_t reserved79;
240 u_int16_t versmajor;
241 u_int16_t versminor;
242 u_int16_t featsupp1; /* 82 */
243 u_int16_t supmicrocode:1;
244 u_int16_t supqueued:1;
245 u_int16_t supcfa:1;
246 u_int16_t supapm:1;
247 u_int16_t suprmsn:1;
248 u_int16_t :11;
249 u_int16_t featsupp3; /* 84 */
250 u_int16_t featenab1; /* 85 */
251 u_int16_t enabmicrocode:1;
252 u_int16_t enabqueued:1;
253 u_int16_t enabcfa:1;
254 u_int16_t enabapm:1;
255 u_int16_t enabrmsn:1;
256 u_int16_t :11;
257 u_int16_t featenab3; /* 87 */
258 u_int16_t udmamodes; /* UltraDMA modes */
259 u_int16_t erasetime;
260 u_int16_t enherasetime;
261 u_int16_t apmlevel;
262 u_int16_t masterpasswdrev;
263 u_int16_t masterhwres :8;
264 u_int16_t slavehwres :5;
265 u_int16_t cblid :1;
266 u_int16_t reserved93_1415 :2;
267 u_int16_t reserved94[32];
268 u_int16_t rmvstat;
269 u_int16_t securstat;
270 u_int16_t reserved129[30];
271 u_int16_t cfapwrmode;
272 u_int16_t reserved161[84];
273 u_int16_t integrity;
274};
275
276/* structure describing an ATA device */
277struct ata_softc {
278 struct device *dev; /* device handle */
| 116
117/* busmaster DMA related defines */
118#define ATA_BM_OFFSET1 0x08
119#define ATA_DMA_ENTRIES 256
120#define ATA_DMA_EOT 0x80000000
121
122#define ATA_BMCMD_PORT 0x00
123#define ATA_BMCMD_START_STOP 0x01
124#define ATA_BMCMD_WRITE_READ 0x08
125
126#define ATA_BMSTAT_PORT 0x02
127#define ATA_BMSTAT_ACTIVE 0x01
128#define ATA_BMSTAT_ERROR 0x02
129#define ATA_BMSTAT_INTERRUPT 0x04
130#define ATA_BMSTAT_MASK 0x07
131#define ATA_BMSTAT_DMA_MASTER 0x20
132#define ATA_BMSTAT_DMA_SLAVE 0x40
133#define ATA_BMSTAT_DMA_SIMPLEX 0x80
134
135#define ATA_BMDTP_PORT 0x04
136
137#define ATA_BMIOSIZE 0x20
138
139/* structure for holding DMA address data */
140struct ata_dmaentry {
141 u_int32_t base;
142 u_int32_t count;
143};
144
145/* ATA/ATAPI device parameter information */
146struct ata_params {
147 u_int8_t cmdsize :2; /* packet command size */
148#define ATAPI_PSIZE_12 0 /* 12 bytes */
149#define ATAPI_PSIZE_16 1 /* 16 bytes */
150
151 u_int8_t :3;
152 u_int8_t drqtype :2; /* DRQ type */
153#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
154#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
155#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
156
157 u_int8_t removable :1; /* device is removable */
158 u_int8_t device_type :5; /* device type */
159#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
160#define ATAPI_TYPE_TAPE 1 /* streaming tape */
161#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
162#define ATAPI_TYPE_OPTICAL 7 /* optical disk */
163
164 u_int8_t :1;
165 u_int8_t proto :2; /* command protocol */
166#define ATAPI_PROTO_ATAPI 2
167
168 u_int16_t cylinders; /* number of cylinders */
169 u_int16_t reserved2;
170 u_int16_t heads; /* # heads */
171 u_int16_t unfbytespertrk; /* # unformatted bytes/track */
172 u_int16_t unfbytes; /* # unformatted bytes/sector */
173 u_int16_t sectors; /* # sectors/track */
174 u_int16_t vendorunique0[3];
175 u_int8_t serial[20]; /* serial number */
176 u_int16_t buffertype; /* buffer type */
177#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
178#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
179#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
180
181 u_int16_t buffersize; /* buf size, 512-byte units */
182 u_int16_t necc; /* ecc bytes appended */
183 u_int8_t revision[8]; /* firmware revision */
184 u_int8_t model[40]; /* model name */
185 u_int8_t nsecperint; /* sectors per interrupt */
186 u_int8_t vendorunique1;
187 u_int16_t usedmovsd; /* double word read/write? */
188
189 u_int8_t vendorcap; /* vendor capabilities */
190 u_int8_t dmaflag :1; /* DMA supported - always 1 */
191 u_int8_t lbaflag :1; /* LBA supported - always 1 */
192 u_int8_t iordydis :1; /* IORDY may be disabled */
193 u_int8_t iordyflag :1; /* IORDY supported */
194 u_int8_t softreset :1; /* needs softreset when busy */
195 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
196 u_int8_t queueing :1; /* supports queuing overlap */
197 u_int8_t idmaflag :1; /* interleaved DMA supported */
198 u_int16_t capvalidate; /* validation for above */
199
200 u_int8_t vendorunique3;
201 u_int8_t opiomode; /* PIO modes 0-2 */
202 u_int8_t vendorunique4;
203 u_int8_t odmamode; /* old DMA modes, not ATA-3 */
204
205 u_int16_t atavalid; /* fields valid */
206#define ATA_FLAG_54_58 1 /* words 54-58 valid */
207#define ATA_FLAG_64_70 2 /* words 64-70 valid */
208#define ATA_FLAG_88 4 /* word 88 valid */
209
210 u_int16_t currcyls;
211 u_int16_t currheads;
212 u_int16_t currsectors;
213 u_int16_t currsize0;
214 u_int16_t currsize1;
215 u_int8_t currmultsect;
216 u_int8_t multsectvalid;
217 u_int32_t lbasize;
218
219 u_int16_t sdmamodes; /* singleword DMA modes */
220 u_int16_t wdmamodes; /* multiword DMA modes */
221 u_int16_t apiomodes; /* advanced PIO modes */
222
223 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */
224 u_int16_t mwdmarec; /* rec. M/W DMA time ns */
225 u_int16_t pioblind; /* min. PIO cycle w/o flow */
226 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */
227
228 u_int16_t reserved69;
229 u_int16_t reserved70;
230 u_int16_t rlsovlap; /* rel time (us) for overlap */
231 u_int16_t rlsservice; /* rel time (us) for service */
232 u_int16_t reserved73;
233 u_int16_t reserved74;
234 u_int16_t queuelen:5;
235 u_int16_t :11;
236 u_int16_t reserved76;
237 u_int16_t reserved77;
238 u_int16_t reserved78;
239 u_int16_t reserved79;
240 u_int16_t versmajor;
241 u_int16_t versminor;
242 u_int16_t featsupp1; /* 82 */
243 u_int16_t supmicrocode:1;
244 u_int16_t supqueued:1;
245 u_int16_t supcfa:1;
246 u_int16_t supapm:1;
247 u_int16_t suprmsn:1;
248 u_int16_t :11;
249 u_int16_t featsupp3; /* 84 */
250 u_int16_t featenab1; /* 85 */
251 u_int16_t enabmicrocode:1;
252 u_int16_t enabqueued:1;
253 u_int16_t enabcfa:1;
254 u_int16_t enabapm:1;
255 u_int16_t enabrmsn:1;
256 u_int16_t :11;
257 u_int16_t featenab3; /* 87 */
258 u_int16_t udmamodes; /* UltraDMA modes */
259 u_int16_t erasetime;
260 u_int16_t enherasetime;
261 u_int16_t apmlevel;
262 u_int16_t masterpasswdrev;
263 u_int16_t masterhwres :8;
264 u_int16_t slavehwres :5;
265 u_int16_t cblid :1;
266 u_int16_t reserved93_1415 :2;
267 u_int16_t reserved94[32];
268 u_int16_t rmvstat;
269 u_int16_t securstat;
270 u_int16_t reserved129[30];
271 u_int16_t cfapwrmode;
272 u_int16_t reserved161[84];
273 u_int16_t integrity;
274};
275
276/* structure describing an ATA device */
277struct ata_softc {
278 struct device *dev; /* device handle */
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279 int unit; /* unit on this controller */
| 279 int channel; /* channel on this controller */
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280 struct resource *r_io; /* io addr resource handle */
281 struct resource *r_altio; /* altio addr resource handle */
282 struct resource *r_bmio; /* bmio addr resource handle */
283 struct resource *r_irq; /* interrupt of this channel */
284 void *ih; /* interrupt handle */
285 u_int32_t ioaddr; /* physical port addr */
286 u_int32_t altioaddr; /* physical alt port addr */
287 u_int32_t bmaddr; /* physical bus master port */
288 u_int32_t chiptype; /* pciid of controller chip */
289 u_int32_t alignment; /* dma engine min alignment */
290 struct ata_params *dev_param[2]; /* ptr to devices params */
291 void *dev_softc[2]; /* ptr to devices softc's */
292 int mode[2]; /* transfer mode for devices */
293#define ATA_PIO 0x00
294#define ATA_PIO0 0x08
295#define ATA_PIO1 0x09
296#define ATA_PIO2 0x0a
297#define ATA_PIO3 0x0b
298#define ATA_PIO4 0x0c
299#define ATA_DMA 0x10
300#define ATA_WDMA2 0x22
301#define ATA_UDMA2 0x42
302#define ATA_UDMA4 0x44
303#define ATA_UDMA5 0x45
304
305 int flags; /* controller flags */
306#define ATA_DMA_ACTIVE 0x01
307#define ATA_ATAPI_DMA_RO 0x02
308#define ATA_USE_16BIT 0x04
309#define ATA_ATTACHED 0x08
310#define ATA_QUEUED 0x10
| 280 struct resource *r_io; /* io addr resource handle */
281 struct resource *r_altio; /* altio addr resource handle */
282 struct resource *r_bmio; /* bmio addr resource handle */
283 struct resource *r_irq; /* interrupt of this channel */
284 void *ih; /* interrupt handle */
285 u_int32_t ioaddr; /* physical port addr */
286 u_int32_t altioaddr; /* physical alt port addr */
287 u_int32_t bmaddr; /* physical bus master port */
288 u_int32_t chiptype; /* pciid of controller chip */
289 u_int32_t alignment; /* dma engine min alignment */
290 struct ata_params *dev_param[2]; /* ptr to devices params */
291 void *dev_softc[2]; /* ptr to devices softc's */
292 int mode[2]; /* transfer mode for devices */
293#define ATA_PIO 0x00
294#define ATA_PIO0 0x08
295#define ATA_PIO1 0x09
296#define ATA_PIO2 0x0a
297#define ATA_PIO3 0x0b
298#define ATA_PIO4 0x0c
299#define ATA_DMA 0x10
300#define ATA_WDMA2 0x22
301#define ATA_UDMA2 0x42
302#define ATA_UDMA4 0x44
303#define ATA_UDMA5 0x45
304
305 int flags; /* controller flags */
306#define ATA_DMA_ACTIVE 0x01
307#define ATA_ATAPI_DMA_RO 0x02
308#define ATA_USE_16BIT 0x04
309#define ATA_ATTACHED 0x08
310#define ATA_QUEUED 0x10
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| 311#define ATA_RAID 0x20
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311
312 int devices; /* what is present */
313#define ATA_ATA_MASTER 0x01
314#define ATA_ATA_SLAVE 0x02
315#define ATA_ATAPI_MASTER 0x04
316#define ATA_ATAPI_SLAVE 0x08
317
318 u_int8_t status; /* last controller status */
319 u_int8_t error; /* last controller error */
320 int active; /* active processing request */
321#define ATA_IDLE 0x0
322#define ATA_IMMEDIATE 0x1
323#define ATA_WAIT_INTR 0x2
324#define ATA_WAIT_READY 0x3
325#define ATA_ACTIVE 0x4
326#define ATA_ACTIVE_ATA 0x5
327#define ATA_ACTIVE_ATAPI 0x6
328#define ATA_REINITING 0x7
329
330 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
331 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
332 void *running; /* currently running request */
333};
334
| 312
313 int devices; /* what is present */
314#define ATA_ATA_MASTER 0x01
315#define ATA_ATA_SLAVE 0x02
316#define ATA_ATAPI_MASTER 0x04
317#define ATA_ATAPI_SLAVE 0x08
318
319 u_int8_t status; /* last controller status */
320 u_int8_t error; /* last controller error */
321 int active; /* active processing request */
322#define ATA_IDLE 0x0
323#define ATA_IMMEDIATE 0x1
324#define ATA_WAIT_INTR 0x2
325#define ATA_WAIT_READY 0x3
326#define ATA_ACTIVE 0x4
327#define ATA_ACTIVE_ATA 0x5
328#define ATA_ACTIVE_ATAPI 0x6
329#define ATA_REINITING 0x7
330
331 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
332 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
333 void *running; /* currently running request */
334};
335
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335/* To convert unit numbers to devices */
| 336/* externs */
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336extern devclass_t ata_devclass;
337
338/* public prototypes */
339void ata_start(struct ata_softc *);
340void ata_reset(struct ata_softc *, int *);
341int ata_reinit(struct ata_softc *);
342int ata_wait(struct ata_softc *, int, u_int8_t);
343int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
344int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
345int ata_get_lun(u_int32_t *);
346void ata_free_lun(u_int32_t *, int);
347char *ata_mode2str(int);
348int ata_pio2mode(int);
349int ata_pmode(struct ata_params *);
350int ata_wmode(struct ata_params *);
351int ata_umode(struct ata_params *);
352#if NPCI > 0
353int ata_find_dev(device_t, u_int32_t, u_int32_t);
354#endif
355
356void *ata_dmaalloc(struct ata_softc *, int);
357void ata_dmainit(struct ata_softc *, int, int, int, int);
358int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
359void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
360int ata_dmastatus(struct ata_softc *);
361int ata_dmadone(struct ata_softc *);
| 337extern devclass_t ata_devclass;
338
339/* public prototypes */
340void ata_start(struct ata_softc *);
341void ata_reset(struct ata_softc *, int *);
342int ata_reinit(struct ata_softc *);
343int ata_wait(struct ata_softc *, int, u_int8_t);
344int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int);
345int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
346int ata_get_lun(u_int32_t *);
347void ata_free_lun(u_int32_t *, int);
348char *ata_mode2str(int);
349int ata_pio2mode(int);
350int ata_pmode(struct ata_params *);
351int ata_wmode(struct ata_params *);
352int ata_umode(struct ata_params *);
353#if NPCI > 0
354int ata_find_dev(device_t, u_int32_t, u_int32_t);
355#endif
356
357void *ata_dmaalloc(struct ata_softc *, int);
358void ata_dmainit(struct ata_softc *, int, int, int, int);
359int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
360void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
361int ata_dmastatus(struct ata_softc *);
362int ata_dmadone(struct ata_softc *);
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