1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
| 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 64307 2000-08-06 19:51:58Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 66070 2000-09-19 11:08:39Z sos $
|
29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ 37#define ATA_E_IDNF 0x10 /* ID not found */ 38#define ATA_E_MC 0x20 /* media changed */ 39#define ATA_E_UNC 0x40 /* uncorrectable data */ 40#define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42#define ATA_FEATURE 0x01 /* (W) feature register */ 43#define ATA_F_DMA 0x01 /* enable DMA */ 44#define ATA_F_OVL 0x02 /* enable overlap */ 45 46#define ATA_COUNT 0x02 /* (W) sector count */ 47#define ATA_IREASON 0x02 /* (R) interrupt reason */ 48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49#define ATA_I_IN 0x02 /* read (1) | write (0) */ 50#define ATA_I_RELEASE 0x04 /* released bus (1) */ 51#define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53#define ATA_SECTOR 0x03 /* sector # */ 54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57#define ATA_D_LBA 0x40 /* use LBA adressing */ 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ 37#define ATA_E_IDNF 0x10 /* ID not found */ 38#define ATA_E_MC 0x20 /* media changed */ 39#define ATA_E_UNC 0x40 /* uncorrectable data */ 40#define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42#define ATA_FEATURE 0x01 /* (W) feature register */ 43#define ATA_F_DMA 0x01 /* enable DMA */ 44#define ATA_F_OVL 0x02 /* enable overlap */ 45 46#define ATA_COUNT 0x02 /* (W) sector count */ 47#define ATA_IREASON 0x02 /* (R) interrupt reason */ 48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49#define ATA_I_IN 0x02 /* read (1) | write (0) */ 50#define ATA_I_RELEASE 0x04 /* released bus (1) */ 51#define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53#define ATA_SECTOR 0x03 /* sector # */ 54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57#define ATA_D_LBA 0x40 /* use LBA adressing */ 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */
|
| 61#define ATA_C_NOP 0x00 /* NOP command */ 62#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */ 63#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
|
61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 62#define ATA_C_READ 0x20 /* read command */ 63#define ATA_C_WRITE 0x30 /* write command */ 64#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
| 64#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 65#define ATA_C_READ 0x20 /* read command */ 66#define ATA_C_WRITE 0x30 /* write command */ 67#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 68#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
|
| 69#define ATA_C_SERVICE 0xa2 /* service command */
|
66#define ATA_C_READ_MUL 0xc4 /* read multi command */ 67#define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
| 70#define ATA_C_READ_MUL 0xc4 /* read multi command */ 71#define ATA_C_WRITE_MUL 0xc5 /* write multi command */ 72#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
|
| 73#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
|
69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
| 74#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 75#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
|
| 76#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
|
71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 72#define ATA_C_SETFEATURES 0xef /* features command */ 73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
| 77#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 78#define ATA_C_SETFEATURES 0xef /* features command */ 79#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
|
74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
| |
75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
| 80#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
|
| 81#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */ 82#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 83#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */ 84#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
|
76 77#define ATA_STATUS 0x07 /* status register */ 78#define ATA_S_ERROR 0x01 /* error */ 79#define ATA_S_INDEX 0x02 /* index */ 80#define ATA_S_CORR 0x04 /* data corrected */ 81#define ATA_S_DRQ 0x08 /* data request */ 82#define ATA_S_DSC 0x10 /* drive seek completed */ 83#define ATA_S_SERVICE 0x10 /* drive needs service */ 84#define ATA_S_DWF 0x20 /* drive write fault */ 85#define ATA_S_DMA 0x20 /* DMA ready */ 86#define ATA_S_READY 0x40 /* drive ready */ 87#define ATA_S_BUSY 0x80 /* busy */ 88
| 85 86#define ATA_STATUS 0x07 /* status register */ 87#define ATA_S_ERROR 0x01 /* error */ 88#define ATA_S_INDEX 0x02 /* index */ 89#define ATA_S_CORR 0x04 /* data corrected */ 90#define ATA_S_DRQ 0x08 /* data request */ 91#define ATA_S_DSC 0x10 /* drive seek completed */ 92#define ATA_S_SERVICE 0x10 /* drive needs service */ 93#define ATA_S_DWF 0x20 /* drive write fault */ 94#define ATA_S_DMA 0x20 /* DMA ready */ 95#define ATA_S_READY 0x40 /* drive ready */ 96#define ATA_S_BUSY 0x80 /* busy */ 97
|
89#define ATA_ALTPORT 0x206 /* alternate status register */ 90#define ATA_ALTPORT_PCCARD 0x8 /* ditto on PCCARD devices */
| 98#define ATA_ALTSTAT 0x02 /* alternate status register */ 99#define ATA_ALTCTRL 0X02 /* alternate device control */
|
91#define ATA_A_IDS 0x02 /* disable interrupts */ 92#define ATA_A_RESET 0x04 /* RESET controller */ 93#define ATA_A_4BIT 0x08 /* 4 head bits */ 94
| 100#define ATA_A_IDS 0x02 /* disable interrupts */ 101#define ATA_A_RESET 0x04 /* RESET controller */ 102#define ATA_A_4BIT 0x08 /* 4 head bits */ 103
|
95#define ATA_ALTIOSIZE 0x01
| 104#define ATA_ALTPORT 0x204 /* alternate registers offset */ 105#define ATA_ALTIOSIZE 0x01 /* alternate registers size */
|
96 97/* misc defines */ 98#define ATA_MASTER 0x00 99#define ATA_SLAVE 0x10 100#define ATA_IOSIZE 0x08 101#define ATA_OP_FINISHED 0x00 102#define ATA_OP_CONTINUES 0x01 103#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
| 106 107/* misc defines */ 108#define ATA_MASTER 0x00 109#define ATA_SLAVE 0x10 110#define ATA_IOSIZE 0x08 111#define ATA_OP_FINISHED 0x00 112#define ATA_OP_CONTINUES 0x01 113#define ATA_DEV(unit) ((unit == ATA_MASTER) ? 0 : 1)
|
104#define ATA_PARAM(scp, unit) scp->dev_param[ATA_DEV(unit)]
| 114#define ATA_PARAM(scp, unit) (scp->dev_param[ATA_DEV(unit)])
|
105
| 115
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106
| |
107/* busmaster DMA related defines */ 108#define ATA_BM_OFFSET1 0x08 109#define ATA_DMA_ENTRIES 256 110#define ATA_DMA_EOT 0x80000000 111 112#define ATA_BMCMD_PORT 0x00 113#define ATA_BMCMD_START_STOP 0x01 114#define ATA_BMCMD_WRITE_READ 0x08 115 116#define ATA_BMSTAT_PORT 0x02 117#define ATA_BMSTAT_ACTIVE 0x01 118#define ATA_BMSTAT_ERROR 0x02 119#define ATA_BMSTAT_INTERRUPT 0x04 120#define ATA_BMSTAT_MASK 0x07 121#define ATA_BMSTAT_DMA_MASTER 0x20 122#define ATA_BMSTAT_DMA_SLAVE 0x40 123#define ATA_BMSTAT_DMA_SIMPLEX 0x80 124 125#define ATA_BMDTP_PORT 0x04 126 127#define ATA_BMIOSIZE 0x20 128 129/* structure for holding DMA address data */ 130struct ata_dmaentry { 131 u_int32_t base; 132 u_int32_t count; 133}; 134 135/* ATA/ATAPI device parameter information */ 136struct ata_params { 137 u_int8_t cmdsize :2; /* packet command size */ 138#define ATAPI_PSIZE_12 0 /* 12 bytes */ 139#define ATAPI_PSIZE_16 1 /* 16 bytes */ 140 141 u_int8_t :3; 142 u_int8_t drqtype :2; /* DRQ type */ 143#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 144#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 145#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 146 147 u_int8_t removable :1; /* device is removable */ 148 u_int8_t device_type :5; /* device type */ 149#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 150#define ATAPI_TYPE_TAPE 1 /* streaming tape */ 151#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 152#define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 153 154 u_int8_t :1; 155 u_int8_t proto :2; /* command protocol */ 156#define ATAPI_PROTO_ATAPI 2 157 158 u_int16_t cylinders; /* number of cylinders */
| 116/* busmaster DMA related defines */ 117#define ATA_BM_OFFSET1 0x08 118#define ATA_DMA_ENTRIES 256 119#define ATA_DMA_EOT 0x80000000 120 121#define ATA_BMCMD_PORT 0x00 122#define ATA_BMCMD_START_STOP 0x01 123#define ATA_BMCMD_WRITE_READ 0x08 124 125#define ATA_BMSTAT_PORT 0x02 126#define ATA_BMSTAT_ACTIVE 0x01 127#define ATA_BMSTAT_ERROR 0x02 128#define ATA_BMSTAT_INTERRUPT 0x04 129#define ATA_BMSTAT_MASK 0x07 130#define ATA_BMSTAT_DMA_MASTER 0x20 131#define ATA_BMSTAT_DMA_SLAVE 0x40 132#define ATA_BMSTAT_DMA_SIMPLEX 0x80 133 134#define ATA_BMDTP_PORT 0x04 135 136#define ATA_BMIOSIZE 0x20 137 138/* structure for holding DMA address data */ 139struct ata_dmaentry { 140 u_int32_t base; 141 u_int32_t count; 142}; 143 144/* ATA/ATAPI device parameter information */ 145struct ata_params { 146 u_int8_t cmdsize :2; /* packet command size */ 147#define ATAPI_PSIZE_12 0 /* 12 bytes */ 148#define ATAPI_PSIZE_16 1 /* 16 bytes */ 149 150 u_int8_t :3; 151 u_int8_t drqtype :2; /* DRQ type */ 152#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 153#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 154#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 155 156 u_int8_t removable :1; /* device is removable */ 157 u_int8_t device_type :5; /* device type */ 158#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 159#define ATAPI_TYPE_TAPE 1 /* streaming tape */ 160#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 161#define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 162 163 u_int8_t :1; 164 u_int8_t proto :2; /* command protocol */ 165#define ATAPI_PROTO_ATAPI 2 166 167 u_int16_t cylinders; /* number of cylinders */
|
159 int16_t reserved2;
| 168 u_int16_t reserved2;
|
160 u_int16_t heads; /* # heads */
| 169 u_int16_t heads; /* # heads */
|
161 int16_t unfbytespertrk; /* # unformatted bytes/track */ 162 int16_t unfbytes; /* # unformatted bytes/sector */
| 170 u_int16_t unfbytespertrk; /* # unformatted bytes/track */ 171 u_int16_t unfbytes; /* # unformatted bytes/sector */
|
163 u_int16_t sectors; /* # sectors/track */
| 172 u_int16_t sectors; /* # sectors/track */
|
164 int16_t vendorunique0[3]; 165 int8_t serial[20]; /* serial number */ 166 int16_t buffertype; /* buffer type */
| 173 u_int16_t vendorunique0[3]; 174 u_int8_t serial[20]; /* serial number */ 175 u_int16_t buffertype; /* buffer type */
|
167#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 168#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 169#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 170
| 176#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 177#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 178#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 179
|
171 int16_t buffersize; /* buf size, 512-byte units */ 172 int16_t necc; /* ecc bytes appended */ 173 int8_t revision[8]; /* firmware revision */ 174 int8_t model[40]; /* model name */ 175 int8_t nsecperint; /* sectors per interrupt */ 176 int8_t vendorunique1; 177 int16_t usedmovsd; /* double word read/write? */
| 180 u_int16_t buffersize; /* buf size, 512-byte units */ 181 u_int16_t necc; /* ecc bytes appended */ 182 u_int8_t revision[8]; /* firmware revision */ 183 u_int8_t model[40]; /* model name */ 184 u_int8_t nsecperint; /* sectors per interrupt */ 185 u_int8_t vendorunique1; 186 u_int16_t usedmovsd; /* double word read/write? */
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178 179 u_int8_t vendorcap; /* vendor capabilities */ 180 u_int8_t dmaflag :1; /* DMA supported - always 1 */ 181 u_int8_t lbaflag :1; /* LBA supported - always 1 */ 182 u_int8_t iordydis :1; /* IORDY may be disabled */ 183 u_int8_t iordyflag :1; /* IORDY supported */ 184 u_int8_t softreset :1; /* needs softreset when busy */ 185 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
| 187 188 u_int8_t vendorcap; /* vendor capabilities */ 189 u_int8_t dmaflag :1; /* DMA supported - always 1 */ 190 u_int8_t lbaflag :1; /* LBA supported - always 1 */ 191 u_int8_t iordydis :1; /* IORDY may be disabled */ 192 u_int8_t iordyflag :1; /* IORDY supported */ 193 u_int8_t softreset :1; /* needs softreset when busy */ 194 u_int8_t stdby_ovlap :1; /* standby/overlap supported */
|
186 u_int8_t queuing :1; /* supports queuing overlap */
| 195 u_int8_t queueing :1; /* supports queuing overlap */
|
187 u_int8_t idmaflag :1; /* interleaved DMA supported */
| 196 u_int8_t idmaflag :1; /* interleaved DMA supported */
|
188 int16_t capvalidate; /* validation for above */
| 197 u_int16_t capvalidate; /* validation for above */
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189
| 198
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190 int8_t vendorunique3; 191 int8_t opiomode; /* PIO modes 0-2 */ 192 int8_t vendorunique4; 193 int8_t odmamode; /* old DMA modes, not ATA-3 */
| 199 u_int8_t vendorunique3; 200 u_int8_t opiomode; /* PIO modes 0-2 */ 201 u_int8_t vendorunique4; 202 u_int8_t odmamode; /* old DMA modes, not ATA-3 */
|
194
| 203
|
195 int16_t atavalid; /* fields valid */
| 204 u_int16_t atavalid; /* fields valid */
|
196#define ATA_FLAG_54_58 1 /* words 54-58 valid */ 197#define ATA_FLAG_64_70 2 /* words 64-70 valid */ 198#define ATA_FLAG_88 4 /* word 88 valid */ 199
| 205#define ATA_FLAG_54_58 1 /* words 54-58 valid */ 206#define ATA_FLAG_64_70 2 /* words 64-70 valid */ 207#define ATA_FLAG_88 4 /* word 88 valid */ 208
|
200 int16_t currcyls; 201 int16_t currheads; 202 int16_t currsectors; 203 int16_t currsize0; 204 int16_t currsize1; 205 int8_t currmultsect; 206 int8_t multsectvalid; 207 int32_t lbasize;
| 209 u_int16_t currcyls; 210 u_int16_t currheads; 211 u_int16_t currsectors; 212 u_int16_t currsize0; 213 u_int16_t currsize1; 214 u_int8_t currmultsect; 215 u_int8_t multsectvalid; 216 u_int32_t lbasize;
|
208
| 217
|
209 int16_t sdmamodes; /* singleword DMA modes */ 210 int16_t wdmamodes; /* multiword DMA modes */ 211 int16_t apiomodes; /* advanced PIO modes */
| 218 u_int16_t sdmamodes; /* singleword DMA modes */ 219 u_int16_t wdmamodes; /* multiword DMA modes */ 220 u_int16_t apiomodes; /* advanced PIO modes */
|
212 213 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 214 u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 215 u_int16_t pioblind; /* min. PIO cycle w/o flow */ 216 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 217
| 221 222 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 223 u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 224 u_int16_t pioblind; /* min. PIO cycle w/o flow */ 225 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 226
|
218 int16_t reserved69; 219 int16_t reserved70;
| 227 u_int16_t reserved69; 228 u_int16_t reserved70;
|
220 u_int16_t rlsovlap; /* rel time (us) for overlap */ 221 u_int16_t rlsservice; /* rel time (us) for service */
| 229 u_int16_t rlsovlap; /* rel time (us) for overlap */ 230 u_int16_t rlsservice; /* rel time (us) for service */
|
222 int16_t reserved73; 223 int16_t reserved74; 224 int16_t queuelen; 225 int16_t reserved76; 226 int16_t reserved77; 227 int16_t reserved78; 228 int16_t reserved79; 229 int16_t versmajor; 230 int16_t versminor; 231 int16_t featsupp1; 232 int16_t featsupp2; 233 int16_t featsupp3; 234 int16_t featenab1; 235 int16_t featenab2; 236 int16_t featenab3; 237 int16_t udmamodes; /* UltraDMA modes */ 238 int16_t erasetime; 239 int16_t enherasetime; 240 int16_t apmlevel; 241 int16_t masterpasswdrev;
| 231 u_int16_t reserved73; 232 u_int16_t reserved74; 233 u_int16_t queuelen:5; 234 u_int16_t :11; 235 u_int16_t reserved76; 236 u_int16_t reserved77; 237 u_int16_t reserved78; 238 u_int16_t reserved79; 239 u_int16_t versmajor; 240 u_int16_t versminor; 241 u_int16_t featsupp1; /* 82 */ 242 u_int16_t supmicrocode:1; 243 u_int16_t supqueued:1; 244 u_int16_t supcfa:1; 245 u_int16_t supapm:1; 246 u_int16_t suprmsn:1; 247 u_int16_t :11; 248 u_int16_t featsupp3; /* 84 */ 249 u_int16_t featenab1; /* 85 */ 250 u_int16_t enabmicrocode:1; 251 u_int16_t enabqueued:1; 252 u_int16_t enabcfa:1; 253 u_int16_t enabapm:1; 254 u_int16_t enabrmsn:1; 255 u_int16_t :11; 256 u_int16_t featenab3; /* 87 */ 257 u_int16_t udmamodes; /* UltraDMA modes */ 258 u_int16_t erasetime; 259 u_int16_t enherasetime; 260 u_int16_t apmlevel; 261 u_int16_t masterpasswdrev;
|
242 u_int16_t masterhwres :8; 243 u_int16_t slavehwres :5; 244 u_int16_t cblid :1; 245 u_int16_t reserved93_1415 :2;
| 262 u_int16_t masterhwres :8; 263 u_int16_t slavehwres :5; 264 u_int16_t cblid :1; 265 u_int16_t reserved93_1415 :2;
|
246 int16_t reserved94[32]; 247 int16_t rmvstat; 248 int16_t securstat; 249 int16_t reserved129[30]; 250 int16_t cfapwrmode; 251 int16_t reserved161[84]; 252 int16_t integrity;
| 266 u_int16_t reserved94[32]; 267 u_int16_t rmvstat; 268 u_int16_t securstat; 269 u_int16_t reserved129[30]; 270 u_int16_t cfapwrmode; 271 u_int16_t reserved161[84]; 272 u_int16_t integrity;
|
253}; 254 255/* structure describing an ATA device */ 256struct ata_softc { 257 struct device *dev; /* device handle */
| 273}; 274 275/* structure describing an ATA device */ 276struct ata_softc { 277 struct device *dev; /* device handle */
|
258 int32_t unit; /* unit on this controller */
| 278 int unit; /* unit on this controller */
|
259 struct resource *r_io; /* io addr resource handle */ 260 struct resource *r_altio; /* altio addr resource handle */ 261 struct resource *r_bmio; /* bmio addr resource handle */ 262 struct resource *r_irq; /* interrupt of this channel */ 263 void *ih; /* interrupt handle */
| 279 struct resource *r_io; /* io addr resource handle */ 280 struct resource *r_altio; /* altio addr resource handle */ 281 struct resource *r_bmio; /* bmio addr resource handle */ 282 struct resource *r_irq; /* interrupt of this channel */ 283 void *ih; /* interrupt handle */
|
264 int32_t ioaddr; /* physical port addr */ 265 int32_t altioaddr; /* physical alt port addr */ 266 int32_t bmaddr; /* physical bus master port */ 267 int32_t chiptype; /* pciid of controller chip */
| 284 u_int32_t ioaddr; /* physical port addr */ 285 u_int32_t altioaddr; /* physical alt port addr */ 286 u_int32_t bmaddr; /* physical bus master port */ 287 u_int32_t chiptype; /* pciid of controller chip */ 288 u_int32_t alignment; /* dma engine min alignment */
|
268 struct ata_params *dev_param[2]; /* ptr to devices params */ 269 void *dev_softc[2]; /* ptr to devices softc's */
| 289 struct ata_params *dev_param[2]; /* ptr to devices params */ 290 void *dev_softc[2]; /* ptr to devices softc's */
|
270 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 271 int32_t mode[2]; /* transfer mode for devices */
| 291 int mode[2]; /* transfer mode for devices */
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272#define ATA_PIO 0x00 273#define ATA_PIO0 0x08 274#define ATA_PIO1 0x09 275#define ATA_PIO2 0x0a 276#define ATA_PIO3 0x0b 277#define ATA_PIO4 0x0c 278#define ATA_DMA 0x10 279#define ATA_WDMA2 0x22 280#define ATA_UDMA2 0x42 281#define ATA_UDMA4 0x44 282#define ATA_UDMA5 0x45 283
| 292#define ATA_PIO 0x00 293#define ATA_PIO0 0x08 294#define ATA_PIO1 0x09 295#define ATA_PIO2 0x0a 296#define ATA_PIO3 0x0b 297#define ATA_PIO4 0x0c 298#define ATA_DMA 0x10 299#define ATA_WDMA2 0x22 300#define ATA_UDMA2 0x42 301#define ATA_UDMA4 0x44 302#define ATA_UDMA5 0x45 303
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284 int32_t flags; /* controller flags */
| 304 int flags; /* controller flags */
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285#define ATA_DMA_ACTIVE 0x01 286#define ATA_ATAPI_DMA_RO 0x02 287#define ATA_USE_16BIT 0x04 288#define ATA_ATTACHED 0x08
| 305#define ATA_DMA_ACTIVE 0x01 306#define ATA_ATAPI_DMA_RO 0x02 307#define ATA_USE_16BIT 0x04 308#define ATA_ATTACHED 0x08
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| 309#define ATA_QUEUED 0x10
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289
| 310
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290 int32_t devices; /* what is present */
| 311 int devices; /* what is present */
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291#define ATA_ATA_MASTER 0x01 292#define ATA_ATA_SLAVE 0x02 293#define ATA_ATAPI_MASTER 0x04 294#define ATA_ATAPI_SLAVE 0x08 295 296 u_int8_t status; /* last controller status */ 297 u_int8_t error; /* last controller error */
| 312#define ATA_ATA_MASTER 0x01 313#define ATA_ATA_SLAVE 0x02 314#define ATA_ATAPI_MASTER 0x04 315#define ATA_ATAPI_SLAVE 0x08 316 317 u_int8_t status; /* last controller status */ 318 u_int8_t error; /* last controller error */
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298 int32_t active; /* active processing request */
| 319 int active; /* active processing request */
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299#define ATA_IDLE 0x0 300#define ATA_IMMEDIATE 0x1 301#define ATA_WAIT_INTR 0x2 302#define ATA_WAIT_READY 0x3 303#define ATA_ACTIVE 0x4 304#define ATA_ACTIVE_ATA 0x5 305#define ATA_ACTIVE_ATAPI 0x6 306#define ATA_REINITING 0x7 307 308 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 309 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 310 void *running; /* currently running request */ 311}; 312 313/* To convert unit numbers to devices */ 314extern devclass_t ata_devclass; 315 316/* public prototypes */ 317void ata_start(struct ata_softc *);
| 320#define ATA_IDLE 0x0 321#define ATA_IMMEDIATE 0x1 322#define ATA_WAIT_INTR 0x2 323#define ATA_WAIT_READY 0x3 324#define ATA_ACTIVE 0x4 325#define ATA_ACTIVE_ATA 0x5 326#define ATA_ACTIVE_ATAPI 0x6 327#define ATA_REINITING 0x7 328 329 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 330 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 331 void *running; /* currently running request */ 332}; 333 334/* To convert unit numbers to devices */ 335extern devclass_t ata_devclass; 336 337/* public prototypes */ 338void ata_start(struct ata_softc *);
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318void ata_reset(struct ata_softc *, int32_t *); 319int32_t ata_reinit(struct ata_softc *); 320int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 321int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 322int ata_printf(struct ata_softc *, int32_t, const char *, ...) __printflike(3, 4);
| 339void ata_reset(struct ata_softc *, int *); 340int ata_reinit(struct ata_softc *); 341int ata_wait(struct ata_softc *, int, u_int8_t); 342int ata_command(struct ata_softc *, int, u_int8_t, u_int16_t, u_int8_t, u_int8_t, u_int8_t, u_int8_t, int); 343int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
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323int ata_get_lun(u_int32_t *); 324void ata_free_lun(u_int32_t *, int);
| 344int ata_get_lun(u_int32_t *); 345void ata_free_lun(u_int32_t *, int);
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325int8_t *ata_mode2str(int32_t); 326int8_t ata_pio2mode(int32_t);
| 346char *ata_mode2str(int); 347int ata_pio2mode(int);
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327int ata_pmode(struct ata_params *); 328int ata_wmode(struct ata_params *); 329int ata_umode(struct ata_params *); 330#if NPCI > 0
| 348int ata_pmode(struct ata_params *); 349int ata_wmode(struct ata_params *); 350int ata_umode(struct ata_params *); 351#if NPCI > 0
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331int32_t ata_find_dev(device_t, int32_t, int32_t);
| 352int ata_find_dev(device_t, u_int32_t, u_int32_t);
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332#endif 333
| 353#endif 354
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334void ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 335int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); 336void ata_dmastart(struct ata_softc *); 337int32_t ata_dmastatus(struct ata_softc *); 338int32_t ata_dmadone(struct ata_softc *);
| 355void *ata_dmaalloc(struct ata_softc *, int); 356void ata_dmainit(struct ata_softc *, int, int, int, int); 357int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int); 358void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int); 359int ata_dmastatus(struct ata_softc *); 360int ata_dmadone(struct ata_softc *);
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