1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
| 1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 *
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28 * $FreeBSD: head/sys/dev/ata/ata-all.h 55333 2000-01-03 10:26:59Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 56138 2000-01-17 02:04:19Z sos $
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29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ 37#define ATA_E_IDNF 0x10 /* ID not found */ 38#define ATA_E_MC 0x20 /* media changed */ 39#define ATA_E_UNC 0x40 /* uncorrectable data */ 40#define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42#define ATA_FEATURE 0x01 /* (W) feature register */ 43#define ATA_F_DMA 0x01 /* enable DMA */ 44#define ATA_F_OVL 0x02 /* enable overlap */ 45 46#define ATA_COUNT 0x02 /* (W) sector count */ 47#define ATA_IREASON 0x02 /* (R) interrupt reason */ 48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49#define ATA_I_IN 0x02 /* read (1) | write (0) */ 50#define ATA_I_RELEASE 0x04 /* released bus (1) */ 51#define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53#define ATA_SECTOR 0x03 /* sector # */ 54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57#define ATA_D_LBA 0x40 /* use LBA adressing */ 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */ 61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 62#define ATA_C_READ 0x20 /* read command */ 63#define ATA_C_WRITE 0x30 /* write command */ 64#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 66#define ATA_C_READ_MULTI 0xc4 /* read multi command */ 67#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */ 68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 72#define ATA_C_SETFEATURES 0xef /* features command */ 73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 76 77#define ATA_STATUS 0x07 /* status register */ 78#define ATA_S_ERROR 0x01 /* error */ 79#define ATA_S_INDEX 0x02 /* index */ 80#define ATA_S_CORR 0x04 /* data corrected */ 81#define ATA_S_DRQ 0x08 /* data request */ 82#define ATA_S_DSC 0x10 /* drive seek completed */ 83#define ATA_S_SERVICE 0x10 /* drive needs service */ 84#define ATA_S_DWF 0x20 /* drive write fault */ 85#define ATA_S_DMA 0x20 /* DMA ready */ 86#define ATA_S_READY 0x40 /* drive ready */ 87#define ATA_S_BUSY 0x80 /* busy */ 88 89#define ATA_ALTPORT 0x206 /* alternate Status register */ 90#define ATA_A_IDS 0x02 /* disable interrupts */ 91#define ATA_A_RESET 0x04 /* RESET controller */ 92#define ATA_A_4BIT 0x08 /* 4 head bits */ 93 94/* misc defines */ 95#define ATA_MASTER 0x00 96#define ATA_SLAVE 0x10 97#define ATA_IOSIZE 0x08 98#define ATA_OP_FINISHED 0x00 99#define ATA_OP_CONTINUES 0x01 100 101/* busmaster DMA related defines */ 102#define ATA_BM_OFFSET1 0x08 103#define ATA_DMA_ENTRIES 256 104#define ATA_DMA_EOT 0x80000000 105 106#define ATA_BMCMD_PORT 0x00 107#define ATA_BMCMD_START_STOP 0x01 108#define ATA_BMCMD_WRITE_READ 0x08 109 110#define ATA_BMSTAT_PORT 0x02 111#define ATA_BMSTAT_ACTIVE 0x01 112#define ATA_BMSTAT_ERROR 0x02 113#define ATA_BMSTAT_INTERRUPT 0x04 114#define ATA_BMSTAT_MASK 0x07 115#define ATA_BMSTAT_DMA_MASTER 0x20 116#define ATA_BMSTAT_DMA_SLAVE 0x40 117#define ATA_BMSTAT_DMA_SIMPLEX 0x80 118 119#define ATA_BMDTP_PORT 0x04 120 121/* structure for holding DMA address data */ 122struct ata_dmaentry { 123 u_int32_t base; 124 u_int32_t count; 125}; 126 127/* structure describing an ATA device */ 128struct ata_softc { 129 int32_t unit; /* unit on this controller */ 130 int32_t lun; /* logical unit # */ 131 struct device *dev; /* device handle */ 132 int32_t ioaddr; /* port addr */ 133 int32_t altioaddr; /* alternate port addr */ 134 int32_t bmaddr; /* bus master DMA port */ 135 int32_t chiptype; /* pciid of controller chip */ 136 void *dev_softc[2]; /* ptr to devices softc's */ 137 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 138 int32_t mode[2]; /* transfer mode for devices */ 139#define ATA_PIO0 0x08 140#define ATA_PIO1 0x09 141#define ATA_PIO2 0x0a 142#define ATA_PIO3 0x0b 143#define ATA_PIO4 0x0c 144#define ATA_WDMA2 0x22 145#define ATA_UDMA2 0x42 146#define ATA_UDMA4 0x44 147 148 int32_t flags; /* controller flags */ 149#define ATA_DMA_ACTIVE 0x01 150#define ATA_ATAPI_DMA_RO 0x02
| 29 */ 30 31/* ATA register defines */ 32#define ATA_DATA 0x00 /* data register */ 33#define ATA_ERROR 0x01 /* (R) error register */ 34#define ATA_E_NM 0x02 /* no media */ 35#define ATA_E_ABORT 0x04 /* command aborted */ 36#define ATA_E_MCR 0x08 /* media change request */ 37#define ATA_E_IDNF 0x10 /* ID not found */ 38#define ATA_E_MC 0x20 /* media changed */ 39#define ATA_E_UNC 0x40 /* uncorrectable data */ 40#define ATA_E_ICRC 0x80 /* UDMA crc error */ 41 42#define ATA_FEATURE 0x01 /* (W) feature register */ 43#define ATA_F_DMA 0x01 /* enable DMA */ 44#define ATA_F_OVL 0x02 /* enable overlap */ 45 46#define ATA_COUNT 0x02 /* (W) sector count */ 47#define ATA_IREASON 0x02 /* (R) interrupt reason */ 48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 49#define ATA_I_IN 0x02 /* read (1) | write (0) */ 50#define ATA_I_RELEASE 0x04 /* released bus (1) */ 51#define ATA_I_TAGMASK 0xf8 /* tag mask */ 52 53#define ATA_SECTOR 0x03 /* sector # */ 54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */ 55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */ 56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ 57#define ATA_D_LBA 0x40 /* use LBA adressing */ 58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 59 60#define ATA_CMD 0x07 /* command register */ 61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */ 62#define ATA_C_READ 0x20 /* read command */ 63#define ATA_C_WRITE 0x30 /* write command */ 64#define ATA_C_PACKET_CMD 0xa0 /* packet command */ 65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/ 66#define ATA_C_READ_MULTI 0xc4 /* read multi command */ 67#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */ 68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */ 69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */ 70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */ 71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */ 72#define ATA_C_SETFEATURES 0xef /* features command */ 73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */ 74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */ 75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */ 76 77#define ATA_STATUS 0x07 /* status register */ 78#define ATA_S_ERROR 0x01 /* error */ 79#define ATA_S_INDEX 0x02 /* index */ 80#define ATA_S_CORR 0x04 /* data corrected */ 81#define ATA_S_DRQ 0x08 /* data request */ 82#define ATA_S_DSC 0x10 /* drive seek completed */ 83#define ATA_S_SERVICE 0x10 /* drive needs service */ 84#define ATA_S_DWF 0x20 /* drive write fault */ 85#define ATA_S_DMA 0x20 /* DMA ready */ 86#define ATA_S_READY 0x40 /* drive ready */ 87#define ATA_S_BUSY 0x80 /* busy */ 88 89#define ATA_ALTPORT 0x206 /* alternate Status register */ 90#define ATA_A_IDS 0x02 /* disable interrupts */ 91#define ATA_A_RESET 0x04 /* RESET controller */ 92#define ATA_A_4BIT 0x08 /* 4 head bits */ 93 94/* misc defines */ 95#define ATA_MASTER 0x00 96#define ATA_SLAVE 0x10 97#define ATA_IOSIZE 0x08 98#define ATA_OP_FINISHED 0x00 99#define ATA_OP_CONTINUES 0x01 100 101/* busmaster DMA related defines */ 102#define ATA_BM_OFFSET1 0x08 103#define ATA_DMA_ENTRIES 256 104#define ATA_DMA_EOT 0x80000000 105 106#define ATA_BMCMD_PORT 0x00 107#define ATA_BMCMD_START_STOP 0x01 108#define ATA_BMCMD_WRITE_READ 0x08 109 110#define ATA_BMSTAT_PORT 0x02 111#define ATA_BMSTAT_ACTIVE 0x01 112#define ATA_BMSTAT_ERROR 0x02 113#define ATA_BMSTAT_INTERRUPT 0x04 114#define ATA_BMSTAT_MASK 0x07 115#define ATA_BMSTAT_DMA_MASTER 0x20 116#define ATA_BMSTAT_DMA_SLAVE 0x40 117#define ATA_BMSTAT_DMA_SIMPLEX 0x80 118 119#define ATA_BMDTP_PORT 0x04 120 121/* structure for holding DMA address data */ 122struct ata_dmaentry { 123 u_int32_t base; 124 u_int32_t count; 125}; 126 127/* structure describing an ATA device */ 128struct ata_softc { 129 int32_t unit; /* unit on this controller */ 130 int32_t lun; /* logical unit # */ 131 struct device *dev; /* device handle */ 132 int32_t ioaddr; /* port addr */ 133 int32_t altioaddr; /* alternate port addr */ 134 int32_t bmaddr; /* bus master DMA port */ 135 int32_t chiptype; /* pciid of controller chip */ 136 void *dev_softc[2]; /* ptr to devices softc's */ 137 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */ 138 int32_t mode[2]; /* transfer mode for devices */ 139#define ATA_PIO0 0x08 140#define ATA_PIO1 0x09 141#define ATA_PIO2 0x0a 142#define ATA_PIO3 0x0b 143#define ATA_PIO4 0x0c 144#define ATA_WDMA2 0x22 145#define ATA_UDMA2 0x42 146#define ATA_UDMA4 0x44 147 148 int32_t flags; /* controller flags */ 149#define ATA_DMA_ACTIVE 0x01 150#define ATA_ATAPI_DMA_RO 0x02
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| 151#define ATA_USE_16BIT 0x04
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151 152 int32_t devices; /* what is present */ 153#define ATA_ATA_MASTER 0x01 154#define ATA_ATA_SLAVE 0x02 155#define ATA_ATAPI_MASTER 0x04 156#define ATA_ATAPI_SLAVE 0x08 157 158 u_int8_t status; /* last controller status */ 159 u_int8_t error; /* last controller error */ 160 int32_t active; /* active processing request */ 161#define ATA_IDLE 0x0 162#define ATA_IMMEDIATE 0x0 163#define ATA_WAIT_INTR 0x1 164#define ATA_WAIT_READY 0x2 165#define ATA_ACTIVE_ATA 0x3 166#define ATA_ACTIVE_ATAPI 0x4 167#define ATA_REINITING 0x5 168 169 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 170 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 171 void *running; /* currently running request */ 172#if NAPM > 0 173 struct apmhook resume_hook; /* hook for apm */ 174#endif 175 176}; 177 178/* array to hold all ata softc's */ 179extern struct ata_softc *atadevices[]; 180#define MAXATA 16 181 182/* public prototypes */ 183void ata_start(struct ata_softc *); 184void ata_reset(struct ata_softc *, int32_t *); 185int32_t ata_reinit(struct ata_softc *); 186int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 187int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 188int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 189int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); 190void ata_dmastart(struct ata_softc *); 191int32_t ata_dmastatus(struct ata_softc *); 192int32_t ata_dmadone(struct ata_softc *); 193int8_t *ata_mode2str(int32_t); 194int8_t ata_pio2mode(int32_t); 195void bswap(int8_t *, int32_t); 196void btrim(int8_t *, int32_t); 197void bpack(int8_t *, int8_t *, int32_t); 198int32_t ata_find_dev(device_t, int32_t);
| 152 153 int32_t devices; /* what is present */ 154#define ATA_ATA_MASTER 0x01 155#define ATA_ATA_SLAVE 0x02 156#define ATA_ATAPI_MASTER 0x04 157#define ATA_ATAPI_SLAVE 0x08 158 159 u_int8_t status; /* last controller status */ 160 u_int8_t error; /* last controller error */ 161 int32_t active; /* active processing request */ 162#define ATA_IDLE 0x0 163#define ATA_IMMEDIATE 0x0 164#define ATA_WAIT_INTR 0x1 165#define ATA_WAIT_READY 0x2 166#define ATA_ACTIVE_ATA 0x3 167#define ATA_ACTIVE_ATAPI 0x4 168#define ATA_REINITING 0x5 169 170 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */ 171 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */ 172 void *running; /* currently running request */ 173#if NAPM > 0 174 struct apmhook resume_hook; /* hook for apm */ 175#endif 176 177}; 178 179/* array to hold all ata softc's */ 180extern struct ata_softc *atadevices[]; 181#define MAXATA 16 182 183/* public prototypes */ 184void ata_start(struct ata_softc *); 185void ata_reset(struct ata_softc *, int32_t *); 186int32_t ata_reinit(struct ata_softc *); 187int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t); 188int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t); 189int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t); 190int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t); 191void ata_dmastart(struct ata_softc *); 192int32_t ata_dmastatus(struct ata_softc *); 193int32_t ata_dmadone(struct ata_softc *); 194int8_t *ata_mode2str(int32_t); 195int8_t ata_pio2mode(int32_t); 196void bswap(int8_t *, int32_t); 197void btrim(int8_t *, int32_t); 198void bpack(int8_t *, int8_t *, int32_t); 199int32_t ata_find_dev(device_t, int32_t);
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