1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
| 1/*-
2 * Copyright (c) 1998,1999 S�ren Schmidt
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
|
28 * $FreeBSD: head/sys/dev/ata/ata-all.h 53029 1999-11-08 21:36:00Z sos $
| 28 * $FreeBSD: head/sys/dev/ata/ata-all.h 53681 1999-11-24 21:40:05Z sos $
|
29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
| 29 */
30
31/* ATA register defines */
32#define ATA_DATA 0x00 /* data register */
33#define ATA_ERROR 0x01 /* (R) error register */
|
| 34#define ATA_E_NM 0x02 /* no media */
|
34#define ATA_E_ABORT 0x04 /* command aborted */
| 35#define ATA_E_ABORT 0x04 /* command aborted */
|
| 36#define ATA_E_MCR 0x08 /* media change request */
37#define ATA_E_IDNF 0x10 /* ID not found */
38#define ATA_E_MC 0x20 /* media changed */
39#define ATA_E_UNC 0x40 /* uncorrectable data */
40#define ATA_E_ICRC 0x80 /* UDMA crc error */
|
35
36#define ATA_FEATURE 0x01 /* (W) feature register */
37#define ATA_F_DMA 0x01 /* enable DMA */
38#define ATA_F_OVL 0x02 /* enable overlap */
39
40#define ATA_COUNT 0x02 /* (W) sector count */
41#define ATA_IREASON 0x02 /* (R) interrupt reason */
42#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
43#define ATA_I_IN 0x02 /* read (1) | write (0) */
44#define ATA_I_RELEASE 0x04 /* released bus (1) */
45#define ATA_I_TAGMASK 0xf8 /* tag mask */
46
47#define ATA_SECTOR 0x03 /* sector # */
48#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
49#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
50#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
51#define ATA_D_LBA 0x40 /* use LBA adressing */
52#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
53
54#define ATA_CMD 0x07 /* command register */
55#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
56#define ATA_C_READ 0x20 /* read command */
57#define ATA_C_WRITE 0x30 /* write command */
58#define ATA_C_PACKET_CMD 0xa0 /* packet command */
59#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
60#define ATA_C_READ_MULTI 0xc4 /* read multi command */
61#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
62#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
63#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
64#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
65#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
66#define ATA_C_SETFEATURES 0xef /* features command */
67#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
68#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
69#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
70
71#define ATA_STATUS 0x07 /* status register */
72#define ATA_S_ERROR 0x01 /* error */
73#define ATA_S_INDEX 0x02 /* index */
74#define ATA_S_CORR 0x04 /* data corrected */
75#define ATA_S_DRQ 0x08 /* data request */
76#define ATA_S_DSC 0x10 /* drive seek completed */
77#define ATA_S_SERVICE 0x10 /* drive needs service */
78#define ATA_S_DWF 0x20 /* drive write fault */
79#define ATA_S_DMA 0x20 /* DMA ready */
80#define ATA_S_READY 0x40 /* drive ready */
81#define ATA_S_BUSY 0x80 /* busy */
82
83#define ATA_ALTPORT 0x206 /* alternate Status register */
84#define ATA_A_IDS 0x02 /* disable interrupts */
85#define ATA_A_RESET 0x04 /* RESET controller */
86#define ATA_A_4BIT 0x08 /* 4 head bits */
87
88/* misc defines */
89#define ATA_MASTER 0x00
90#define ATA_SLAVE 0x10
91#define ATA_IOSIZE 0x08
92#define ATA_OP_FINISHED 0x00
93#define ATA_OP_CONTINUES 0x01
94
95/* busmaster DMA related defines */
96#define ATA_BM_OFFSET1 0x08
97#define ATA_DMA_ENTRIES 256
98#define ATA_DMA_EOT 0x80000000
99
100#define ATA_BMCMD_PORT 0x00
101#define ATA_BMCMD_START_STOP 0x01
102#define ATA_BMCMD_WRITE_READ 0x08
103
104#define ATA_BMSTAT_PORT 0x02
105#define ATA_BMSTAT_ACTIVE 0x01
106#define ATA_BMSTAT_ERROR 0x02
107#define ATA_BMSTAT_INTERRUPT 0x04
108#define ATA_BMSTAT_MASK 0x07
109#define ATA_BMSTAT_DMA_MASTER 0x20
110#define ATA_BMSTAT_DMA_SLAVE 0x40
111#define ATA_BMSTAT_DMA_SIMPLEX 0x80
112
113#define ATA_BMDTP_PORT 0x04
114
115/* structure for holding DMA address data */
116struct ata_dmaentry {
117 u_int32_t base;
118 u_int32_t count;
119};
120
121/* ATA device DMA access modes */
122#define ATA_WDMA2 0x22
123#define ATA_UDMA2 0x42
124#define ATA_UDMA3 0x43
125#define ATA_UDMA4 0x44
126
127/* structure describing an ATA device */
128struct ata_softc {
129 int32_t unit; /* unit on this controller */
130 int32_t lun; /* logical unit # */
131 struct device *dev; /* device handle */
132 int32_t ioaddr; /* port addr */
133 int32_t altioaddr; /* alternate port addr */
134 int32_t bmaddr; /* bus master DMA port */
135 void *dev_softc[2]; /* ptr to devices softc's */
136 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
137 int32_t mode[2]; /* transfer mode for devices */
138#define ATA_MODE_PIO 0x00
139#define ATA_MODE_WDMA2 0x01
140#define ATA_MODE_UDMA2 0x02
141#define ATA_MODE_UDMA3 0x04
142#define ATA_MODE_UDMA4 0x08
143
144 int32_t flags; /* controller flags */
145#define ATA_DMA_ACTIVE 0x01
146#define ATA_ATAPI_DMA_RO 0x02
147
148 int32_t devices; /* what is present */
149#define ATA_ATA_MASTER 0x01
150#define ATA_ATA_SLAVE 0x02
151#define ATA_ATAPI_MASTER 0x04
152#define ATA_ATAPI_SLAVE 0x08
153
154 u_int8_t status; /* last controller status */
155 u_int8_t error; /* last controller error */
156 int32_t active; /* active processing request */
157#define ATA_IDLE 0x0
158#define ATA_IMMEDIATE 0x0
159#define ATA_WAIT_INTR 0x1
160#define ATA_WAIT_READY 0x2
161#define ATA_ACTIVE_ATA 0x3
162#define ATA_ACTIVE_ATAPI 0x4
163#define ATA_REINITING 0x5
164
165 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
166 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
167 void *running; /* currently running request */
168#if NAPM > 0
169 struct apmhook resume_hook; /* hook for apm */
170#endif
171
172};
173
174/* array to hold all ata softc's */
175extern struct ata_softc *atadevices[];
176#define MAXATA 16
177
178/* public prototypes */
179void ata_start(struct ata_softc *);
180void ata_reset(struct ata_softc *, int32_t *);
181int32_t ata_reinit(struct ata_softc *);
182int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
183int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
184int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
185int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
186void ata_dmastart(struct ata_softc *);
187int32_t ata_dmastatus(struct ata_softc *);
188int32_t ata_dmadone(struct ata_softc *);
189int8_t *ata_mode2str(int32_t);
190void bswap(int8_t *, int32_t);
191void btrim(int8_t *, int32_t);
192void bpack(int8_t *, int8_t *, int32_t);
| 41
42#define ATA_FEATURE 0x01 /* (W) feature register */
43#define ATA_F_DMA 0x01 /* enable DMA */
44#define ATA_F_OVL 0x02 /* enable overlap */
45
46#define ATA_COUNT 0x02 /* (W) sector count */
47#define ATA_IREASON 0x02 /* (R) interrupt reason */
48#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
49#define ATA_I_IN 0x02 /* read (1) | write (0) */
50#define ATA_I_RELEASE 0x04 /* released bus (1) */
51#define ATA_I_TAGMASK 0xf8 /* tag mask */
52
53#define ATA_SECTOR 0x03 /* sector # */
54#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
55#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
56#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
57#define ATA_D_LBA 0x40 /* use LBA adressing */
58#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
59
60#define ATA_CMD 0x07 /* command register */
61#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
62#define ATA_C_READ 0x20 /* read command */
63#define ATA_C_WRITE 0x30 /* write command */
64#define ATA_C_PACKET_CMD 0xa0 /* packet command */
65#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
66#define ATA_C_READ_MULTI 0xc4 /* read multi command */
67#define ATA_C_WRITE_MULTI 0xc5 /* write multi command */
68#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
69#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
70#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
71#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
72#define ATA_C_SETFEATURES 0xef /* features command */
73#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
74#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
75#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
76
77#define ATA_STATUS 0x07 /* status register */
78#define ATA_S_ERROR 0x01 /* error */
79#define ATA_S_INDEX 0x02 /* index */
80#define ATA_S_CORR 0x04 /* data corrected */
81#define ATA_S_DRQ 0x08 /* data request */
82#define ATA_S_DSC 0x10 /* drive seek completed */
83#define ATA_S_SERVICE 0x10 /* drive needs service */
84#define ATA_S_DWF 0x20 /* drive write fault */
85#define ATA_S_DMA 0x20 /* DMA ready */
86#define ATA_S_READY 0x40 /* drive ready */
87#define ATA_S_BUSY 0x80 /* busy */
88
89#define ATA_ALTPORT 0x206 /* alternate Status register */
90#define ATA_A_IDS 0x02 /* disable interrupts */
91#define ATA_A_RESET 0x04 /* RESET controller */
92#define ATA_A_4BIT 0x08 /* 4 head bits */
93
94/* misc defines */
95#define ATA_MASTER 0x00
96#define ATA_SLAVE 0x10
97#define ATA_IOSIZE 0x08
98#define ATA_OP_FINISHED 0x00
99#define ATA_OP_CONTINUES 0x01
100
101/* busmaster DMA related defines */
102#define ATA_BM_OFFSET1 0x08
103#define ATA_DMA_ENTRIES 256
104#define ATA_DMA_EOT 0x80000000
105
106#define ATA_BMCMD_PORT 0x00
107#define ATA_BMCMD_START_STOP 0x01
108#define ATA_BMCMD_WRITE_READ 0x08
109
110#define ATA_BMSTAT_PORT 0x02
111#define ATA_BMSTAT_ACTIVE 0x01
112#define ATA_BMSTAT_ERROR 0x02
113#define ATA_BMSTAT_INTERRUPT 0x04
114#define ATA_BMSTAT_MASK 0x07
115#define ATA_BMSTAT_DMA_MASTER 0x20
116#define ATA_BMSTAT_DMA_SLAVE 0x40
117#define ATA_BMSTAT_DMA_SIMPLEX 0x80
118
119#define ATA_BMDTP_PORT 0x04
120
121/* structure for holding DMA address data */
122struct ata_dmaentry {
123 u_int32_t base;
124 u_int32_t count;
125};
126
127/* ATA device DMA access modes */
128#define ATA_WDMA2 0x22
129#define ATA_UDMA2 0x42
130#define ATA_UDMA3 0x43
131#define ATA_UDMA4 0x44
132
133/* structure describing an ATA device */
134struct ata_softc {
135 int32_t unit; /* unit on this controller */
136 int32_t lun; /* logical unit # */
137 struct device *dev; /* device handle */
138 int32_t ioaddr; /* port addr */
139 int32_t altioaddr; /* alternate port addr */
140 int32_t bmaddr; /* bus master DMA port */
141 void *dev_softc[2]; /* ptr to devices softc's */
142 struct ata_dmaentry *dmatab[2]; /* DMA transfer tables */
143 int32_t mode[2]; /* transfer mode for devices */
144#define ATA_MODE_PIO 0x00
145#define ATA_MODE_WDMA2 0x01
146#define ATA_MODE_UDMA2 0x02
147#define ATA_MODE_UDMA3 0x04
148#define ATA_MODE_UDMA4 0x08
149
150 int32_t flags; /* controller flags */
151#define ATA_DMA_ACTIVE 0x01
152#define ATA_ATAPI_DMA_RO 0x02
153
154 int32_t devices; /* what is present */
155#define ATA_ATA_MASTER 0x01
156#define ATA_ATA_SLAVE 0x02
157#define ATA_ATAPI_MASTER 0x04
158#define ATA_ATAPI_SLAVE 0x08
159
160 u_int8_t status; /* last controller status */
161 u_int8_t error; /* last controller error */
162 int32_t active; /* active processing request */
163#define ATA_IDLE 0x0
164#define ATA_IMMEDIATE 0x0
165#define ATA_WAIT_INTR 0x1
166#define ATA_WAIT_READY 0x2
167#define ATA_ACTIVE_ATA 0x3
168#define ATA_ACTIVE_ATAPI 0x4
169#define ATA_REINITING 0x5
170
171 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
172 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
173 void *running; /* currently running request */
174#if NAPM > 0
175 struct apmhook resume_hook; /* hook for apm */
176#endif
177
178};
179
180/* array to hold all ata softc's */
181extern struct ata_softc *atadevices[];
182#define MAXATA 16
183
184/* public prototypes */
185void ata_start(struct ata_softc *);
186void ata_reset(struct ata_softc *, int32_t *);
187int32_t ata_reinit(struct ata_softc *);
188int32_t ata_wait(struct ata_softc *, int32_t, u_int8_t);
189int32_t ata_command(struct ata_softc *, int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, u_int32_t, int32_t);
190int32_t ata_dmainit(struct ata_softc *, int32_t, int32_t, int32_t, int32_t);
191int32_t ata_dmasetup(struct ata_softc *, int32_t, int8_t *, int32_t, int32_t);
192void ata_dmastart(struct ata_softc *);
193int32_t ata_dmastatus(struct ata_softc *);
194int32_t ata_dmadone(struct ata_softc *);
195int8_t *ata_mode2str(int32_t);
196void bswap(int8_t *, int32_t);
197void btrim(int8_t *, int32_t);
198void bpack(int8_t *, int8_t *, int32_t);
|